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-rw-r--r--chipset_enable.c70
-rw-r--r--flash.h8
-rw-r--r--ichspi.c14
-rw-r--r--internal.c40
-rw-r--r--sb600spi.c22
5 files changed, 93 insertions, 61 deletions
diff --git a/chipset_enable.c b/chipset_enable.c
index d9e82ec..15e5df4 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -215,7 +215,7 @@ static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n",
- *(uint16_t *) (spibar + 0x6c));
+ mmio_readw(spibar + 0x6c));
flashbus = BUS_TYPE_VIA_SPI;
ich_init_opcodes();
@@ -245,14 +245,14 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
/* Map RCBA to virtual memory */
rcrb = physmap("ICH RCRB", tmp, 0x4000);
- gcs = *(volatile uint32_t *)(rcrb + 0x3410);
+ gcs = mmio_readl(rcrb + 0x3410);
printf_debug("GCS = 0x%x: ", gcs);
printf_debug("BIOS Interface Lock-Down: %sabled, ",
(gcs & 0x1) ? "en" : "dis");
bbs = (gcs >> 10) & 0x3;
printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
- buc = *(volatile uint8_t *)(rcrb + 0x3414);
+ buc = mmio_readb(rcrb + 0x3414);
printf_debug("Top Swap : %s\n",
(buc & 1) ? "enabled (A16 inverted)" : "not enabled");
@@ -292,44 +292,44 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
switch (flashbus) {
case BUS_TYPE_ICH7_SPI:
printf_debug("0x00: 0x%04x (SPIS)\n",
- *(uint16_t *) (spibar + 0));
+ mmio_readw(spibar + 0));
printf_debug("0x02: 0x%04x (SPIC)\n",
- *(uint16_t *) (spibar + 2));
+ mmio_readw(spibar + 2));
printf_debug("0x04: 0x%08x (SPIA)\n",
- *(uint32_t *) (spibar + 4));
+ mmio_readl(spibar + 4));
for (i = 0; i < 8; i++) {
int offs;
offs = 8 + (i * 8);
printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs,
- *(uint32_t *) (spibar + offs), i);
+ mmio_readl(spibar + offs), i);
printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
- *(uint32_t *) (spibar + offs + 4), i);
+ mmio_readl(spibar + offs + 4), i);
}
printf_debug("0x50: 0x%08x (BBAR)\n",
- *(uint32_t *) (spibar + 0x50));
+ mmio_readl(spibar + 0x50));
printf_debug("0x54: 0x%04x (PREOP)\n",
- *(uint16_t *) (spibar + 0x54));
+ mmio_readw(spibar + 0x54));
printf_debug("0x56: 0x%04x (OPTYPE)\n",
- *(uint16_t *) (spibar + 0x56));
+ mmio_readw(spibar + 0x56));
printf_debug("0x58: 0x%08x (OPMENU)\n",
- *(uint32_t *) (spibar + 0x58));
+ mmio_readl(spibar + 0x58));
printf_debug("0x5c: 0x%08x (OPMENU+4)\n",
- *(uint32_t *) (spibar + 0x5c));
+ mmio_readl(spibar + 0x5c));
for (i = 0; i < 4; i++) {
int offs;
offs = 0x60 + (i * 4);
printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs,
- *(uint32_t *) (spibar + offs), i);
+ mmio_readl(spibar + offs), i);
}
printf_debug("\n");
- if ((*(uint16_t *) spibar) & (1 << 15)) {
+ if (mmio_readw(spibar) & (1 << 15)) {
printf("WARNING: SPI Configuration Lockdown activated.\n");
ichspi_lock = 1;
}
ich_init_opcodes();
break;
case BUS_TYPE_ICH9_SPI:
- tmp2 = *(uint16_t *) (spibar + 4);
+ tmp2 = mmio_readw(spibar + 4);
printf_debug("0x04: 0x%04x (HSFS)\n", tmp2);
printf_debug("FLOCKDN %i, ", (tmp2 >> 15 & 1));
printf_debug("FDV %i, ", (tmp2 >> 14) & 1);
@@ -340,7 +340,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
printf_debug("FCERR %i, ", (tmp2 >> 1) & 1);
printf_debug("FDONE %i\n", (tmp2 >> 0) & 1);
- tmp = *(uint32_t *) (spibar + 0x50);
+ tmp = mmio_readl(spibar + 0x50);
printf_debug("0x50: 0x%08x (FRAP)\n", tmp);
printf_debug("BMWAG %i, ", (tmp >> 24) & 0xff);
printf_debug("BMRAG %i, ", (tmp >> 16) & 0xff);
@@ -348,39 +348,39 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
printf_debug("BRRA %i\n", (tmp >> 0) & 0xff);
printf_debug("0x54: 0x%08x (FREG0)\n",
- *(uint32_t *) (spibar + 0x54));
+ mmio_readl(spibar + 0x54));
printf_debug("0x58: 0x%08x (FREG1)\n",
- *(uint32_t *) (spibar + 0x58));
+ mmio_readl(spibar + 0x58));
printf_debug("0x5C: 0x%08x (FREG2)\n",
- *(uint32_t *) (spibar + 0x5C));
+ mmio_readl(spibar + 0x5C));
printf_debug("0x60: 0x%08x (FREG3)\n",
- *(uint32_t *) (spibar + 0x60));
+ mmio_readl(spibar + 0x60));
printf_debug("0x64: 0x%08x (FREG4)\n",
- *(uint32_t *) (spibar + 0x64));
+ mmio_readl(spibar + 0x64));
printf_debug("0x74: 0x%08x (PR0)\n",
- *(uint32_t *) (spibar + 0x74));
+ mmio_readl(spibar + 0x74));
printf_debug("0x78: 0x%08x (PR1)\n",
- *(uint32_t *) (spibar + 0x78));
+ mmio_readl(spibar + 0x78));
printf_debug("0x7C: 0x%08x (PR2)\n",
- *(uint32_t *) (spibar + 0x7C));
+ mmio_readl(spibar + 0x7C));
printf_debug("0x80: 0x%08x (PR3)\n",
- *(uint32_t *) (spibar + 0x80));
+ mmio_readl(spibar + 0x80));
printf_debug("0x84: 0x%08x (PR4)\n",
- *(uint32_t *) (spibar + 0x84));
+ mmio_readl(spibar + 0x84));
printf_debug("0x90: 0x%08x (SSFS, SSFC)\n",
- *(uint32_t *) (spibar + 0x90));
+ mmio_readl(spibar + 0x90));
printf_debug("0x94: 0x%04x (PREOP)\n",
- *(uint16_t *) (spibar + 0x94));
+ mmio_readw(spibar + 0x94));
printf_debug("0x96: 0x%04x (OPTYPE)\n",
- *(uint16_t *) (spibar + 0x96));
+ mmio_readw(spibar + 0x96));
printf_debug("0x98: 0x%08x (OPMENU)\n",
- *(uint32_t *) (spibar + 0x98));
+ mmio_readl(spibar + 0x98));
printf_debug("0x9C: 0x%08x (OPMENU+4)\n",
- *(uint32_t *) (spibar + 0x9C));
+ mmio_readl(spibar + 0x9C));
printf_debug("0xA0: 0x%08x (BBAR)\n",
- *(uint32_t *) (spibar + 0xA0));
+ mmio_readl(spibar + 0xA0));
printf_debug("0xB0: 0x%08x (FDOC)\n",
- *(uint32_t *) (spibar + 0xB0));
+ mmio_readl(spibar + 0xB0));
if (tmp2 & (1 << 15)) {
printf("WARNING: SPI Configuration Lockdown activated.\n");
ichspi_lock = 1;
@@ -897,7 +897,7 @@ static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
* BOOTCS region (PARx[31:29] = 100b)e
*/
for (i = 0x88; i <= 0xc4; i += 4) {
- parx = *(volatile uint32_t *)(mmcr + i);
+ parx = mmio_readl(mmcr + i);
if ((parx >> 29) == 4) {
bootcs_found = 1;
break; /* BOOTCS found */
diff --git a/flash.h b/flash.h
index f6bdab0..d172ac1 100644
--- a/flash.h
+++ b/flash.h
@@ -621,6 +621,12 @@ void internal_chip_writel(uint32_t val, chipaddr addr);
uint8_t internal_chip_readb(const chipaddr addr);
uint16_t internal_chip_readw(const chipaddr addr);
uint32_t internal_chip_readl(const chipaddr addr);
+void mmio_writeb(uint8_t val, void *addr);
+void mmio_writew(uint16_t val, void *addr);
+void mmio_writel(uint32_t val, void *addr);
+uint8_t mmio_readb(void *addr);
+uint16_t mmio_readw(void *addr);
+uint32_t mmio_readl(void *addr);
void fallback_chip_writew(uint16_t val, chipaddr addr);
void fallback_chip_writel(uint32_t val, chipaddr addr);
uint16_t fallback_chip_readw(const chipaddr addr);
@@ -731,7 +737,7 @@ int sb600_spi_command(unsigned int writecnt, unsigned int readcnt,
int sb600_spi_read(struct flashchip *flash, uint8_t *buf);
int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf);
uint8_t sb600_read_status_register(void);
-extern uint8_t volatile *sb600_spibar;
+extern uint8_t *sb600_spibar;
/* jedec.c */
uint8_t oddparity(uint8_t val);
diff --git a/ichspi.c b/ichspi.c
index 4ddf2ad..5ae5f7d 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -129,21 +129,17 @@ static OPCODES *curopcodes = NULL;
/* HW access functions */
static uint32_t REGREAD32(int X)
{
- volatile uint32_t regval;
- regval = *(volatile uint32_t *)((uint8_t *) spibar + X);
- return regval;
+ return mmio_readl(spibar + X);
}
static uint16_t REGREAD16(int X)
{
- volatile uint16_t regval;
- regval = *(volatile uint16_t *)((uint8_t *) spibar + X);
- return regval;
+ return mmio_readw(spibar + X);
}
-#define REGWRITE32(X,Y) (*(uint32_t *)((uint8_t *)spibar+X)=Y)
-#define REGWRITE16(X,Y) (*(uint16_t *)((uint8_t *)spibar+X)=Y)
-#define REGWRITE8(X,Y) (*(uint8_t *)((uint8_t *)spibar+X)=Y)
+#define REGWRITE32(X,Y) mmio_writel(Y, spibar+X)
+#define REGWRITE16(X,Y) mmio_writew(Y, spibar+X)
+#define REGWRITE8(X,Y) mmio_writeb(Y, spibar+X)
/* Common SPI functions */
static int find_opcode(OPCODES *op, uint8_t opcode);
diff --git a/internal.c b/internal.c
index a9829a8..d2a9ae2 100644
--- a/internal.c
+++ b/internal.c
@@ -137,31 +137,61 @@ int internal_shutdown(void)
void internal_chip_writeb(uint8_t val, chipaddr addr)
{
- *(volatile uint8_t *) addr = val;
+ mmio_writeb(val, (void *) addr);
}
void internal_chip_writew(uint16_t val, chipaddr addr)
{
- *(volatile uint16_t *) addr = val;
+ mmio_writew(val, (void *) addr);
}
void internal_chip_writel(uint32_t val, chipaddr addr)
{
- *(volatile uint32_t *) addr = val;
+ mmio_writel(val, (void *) addr);
}
uint8_t internal_chip_readb(const chipaddr addr)
{
- return *(volatile uint8_t *) addr;
+ return mmio_readb((void *) addr);
}
uint16_t internal_chip_readw(const chipaddr addr)
{
- return *(volatile uint16_t *) addr;
+ return mmio_readw((void *) addr);
}
uint32_t internal_chip_readl(const chipaddr addr)
{
+ return mmio_readl((void *) addr);
+}
+
+void mmio_writeb(uint8_t val, void *addr)
+{
+ *(volatile uint8_t *) addr = val;
+}
+
+void mmio_writew(uint16_t val, void *addr)
+{
+ *(volatile uint16_t *) addr = val;
+}
+
+void mmio_writel(uint32_t val, void *addr)
+{
+ *(volatile uint32_t *) addr = val;
+}
+
+uint8_t mmio_readb(void *addr)
+{
+ return *(volatile uint8_t *) addr;
+}
+
+uint16_t mmio_readw(void *addr)
+{
+ return *(volatile uint16_t *) addr;
+}
+
+uint32_t mmio_readl(void *addr)
+{
return *(volatile uint32_t *) addr;
}
diff --git a/sb600spi.c b/sb600spi.c
index eaf92d2..03e1ab8 100644
--- a/sb600spi.c
+++ b/sb600spi.c
@@ -37,7 +37,7 @@ typedef struct _spi_controller {
} sb600_spi_controller;
sb600_spi_controller *spi_bar = NULL;
-uint8_t volatile *sb600_spibar;
+uint8_t *sb600_spibar;
int sb600_spi_read(struct flashchip *flash, uint8_t *buf)
{
@@ -91,17 +91,17 @@ int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf)
void reset_internal_fifo_pointer(void)
{
- sb600_spibar[2] |= 0x10;
+ mmio_writeb(mmio_readb(sb600_spibar + 2) | 0x10, sb600_spibar + 2);
- while (sb600_spibar[0xD] & 0x7)
+ while (mmio_readb(sb600_spibar + 0xD) & 0x7)
printf("reset\n");
}
void execute_command(void)
{
- sb600_spibar[2] |= 1;
+ mmio_writeb(mmio_readb(sb600_spibar + 2) | 1, sb600_spibar + 2);
- while (sb600_spibar[2] & 1)
+ while (mmio_readb(sb600_spibar + 2) & 1)
;
}
@@ -131,8 +131,8 @@ int sb600_spi_command(unsigned int writecnt, unsigned int readcnt,
return 1;
}
- sb600_spibar[0] = cmd;
- sb600_spibar[1] = readcnt << 4 | (writecnt);
+ mmio_writeb(cmd, sb600_spibar + 0);
+ mmio_writeb(readcnt << 4 | (writecnt), sb600_spibar + 1);
/* Before we use the FIFO, reset it first. */
reset_internal_fifo_pointer();
@@ -140,7 +140,7 @@ int sb600_spi_command(unsigned int writecnt, unsigned int readcnt,
/* Send the write byte to FIFO. */
for (count = 0; count < writecnt; count++, writearr++) {
printf_debug(" [%x]", *writearr);
- sb600_spibar[0xC] = *writearr;
+ mmio_writeb(*writearr, sb600_spibar + 0xC);
}
printf_debug("\n");
@@ -160,13 +160,13 @@ int sb600_spi_command(unsigned int writecnt, unsigned int readcnt,
reset_internal_fifo_pointer();
for (count = 0; count < writecnt; count++) {
- cmd = sb600_spibar[0xC]; /* Skip the byte we send. */
+ cmd = mmio_readb(sb600_spibar + 0xC); /* Skip the byte we send. */
printf_debug("[ %2x]", cmd);
}
- printf_debug("The FIFO pointer 6 is %d.\n", sb600_spibar[0xd] & 0x07);
+ printf_debug("The FIFO pointer 6 is %d.\n", mmio_readb(sb600_spibar + 0xd) & 0x07);
for (count = 0; count < readcnt; count++, readarr++) {
- *readarr = sb600_spibar[0xC];
+ *readarr = mmio_readb(sb600_spibar + 0xC);
printf_debug("[%02x]", *readarr);
}
printf_debug("\n");
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