path: root/nicintel_spi.c
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authorCarl-Daniel Hailfinger <>2010-09-15 00:13:02 +0000
committerCarl-Daniel Hailfinger <>2010-09-15 00:13:02 +0000
commitec489e4ec65ec416a6c41ded6d5eae0b6ebd7103 (patch)
tree096c8eb5101ada5ba8b098baf30060a20f471512 /nicintel_spi.c
parent9a87c5d6ad41f7c1512ad9f2a2f0ee60213fbef0 (diff)
Honor ICH SPI address window for reads
ICH SPI has the ability to restrict SPI read/write accesses to a given address range. The low end of the range is configurable by the BIOS (and by flashrom if the BIOS didn't lock down the flash interface), the high end of the range is 0xffffff (2^24-1). This patch checks for an address range restriction and uses the low end of the allowed range as base for SPI reads. A similar workaround for REMS/RES opcodes has been committed in r500. This fixes read on the Intel D945GCLF mainboard where the stock BIOS enforces a restricted address range. Please note that writes need the same fix, but for architectural reasons that fix will be merged once partial write is available. Corresponding to flashrom svn r1170. Signed-off-by: Carl-Daniel Hailfinger <> Tested by David Hendricks on the Intel D945GCLF mainboard, results at Acked-by: David Hendricks <>
Diffstat (limited to 'nicintel_spi.c')
0 files changed, 0 insertions, 0 deletions
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