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authorCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2010-09-15 00:17:37 +0000
committerCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2010-09-15 00:17:37 +0000
commit2822888c810eaf2d68271f4dac4a0ad639221fd3 (patch)
treea6e81bc8cf557252479496bc3a655c1981b6303e /nicintel_spi.c
parentec489e4ec65ec416a6c41ded6d5eae0b6ebd7103 (diff)
downloadast2050-flashrom-2822888c810eaf2d68271f4dac4a0ad639221fd3.zip
ast2050-flashrom-2822888c810eaf2d68271f4dac4a0ad639221fd3.tar.gz
SPI bitbanging: request/release bus
SPI bitbanging on devices which speak SPI natively has a dual-use problem: We need to shut down normal SPI operations to do the bitbanging ourselves. Once we're done, it makes a lot of sense to reenable "normal" SPI operations again. Add request_bus/release_bus functions to struct bitbang_spi_master. Add a bitbang shutdown function (not used yet). Change MCP SPI and Intel NIC SPI to use the new request/release bus infrastructure. Cosmetic changes to a few error messages (80 column limit). There are multiple possible strategies for bus request/release: - Request at the start of a SPI command, release immediately afterwards. - Request at the start of a SPI multicommand, release once all commands of the multicommand are done. - Request on programmer init, release on shutdown. Each strategy has its own advantages. For now, we will stay with the first strategy which worked fine so far. Corresponding to flashrom svn r1171. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Diffstat (limited to 'nicintel_spi.c')
-rw-r--r--nicintel_spi.c12
1 files changed, 2 insertions, 10 deletions
diff --git a/nicintel_spi.c b/nicintel_spi.c
index d09facc..75dc423 100644
--- a/nicintel_spi.c
+++ b/nicintel_spi.c
@@ -91,20 +91,10 @@ static void nicintel_bitbang_set_cs(int val)
{
uint32_t tmp;
- /*
- * Requesting and releasing the SPI bus is handled in here to allow
- * the chipset to use its own SPI engine for native reads.
- */
- if (val == 0)
- nicintel_request_spibus();
-
tmp = pci_mmio_readl(nicintel_spibar + FLA);
tmp &= ~(1 << FL_CS);
tmp |= (val << FL_CS);
pci_mmio_writel(tmp, nicintel_spibar + FLA);
-
- if (val == 1)
- nicintel_release_spibus();
}
static void nicintel_bitbang_set_sck(int val)
@@ -142,6 +132,8 @@ static const struct bitbang_spi_master bitbang_spi_master_nicintel = {
.set_sck = nicintel_bitbang_set_sck,
.set_mosi = nicintel_bitbang_set_mosi,
.get_miso = nicintel_bitbang_get_miso,
+ .request_bus = nicintel_request_spibus,
+ .release_bus = nicintel_release_spibus,
};
int nicintel_spi_init(void)
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