path: root/it87spi.c
diff options
authorCarl-Daniel Hailfinger <>2009-07-10 21:08:55 +0000
committerCarl-Daniel Hailfinger <>2009-07-10 21:08:55 +0000
commitd0478299b1d714a7001f19fb2cafeb257698a2c0 (patch)
tree4cd9e2881c6f02f26270149770210e6d1aa742cd /it87spi.c
parent8ef7dce29aead4f17000e2c14b39f0723adc3953 (diff)
Add SPI multicommand infrastructure
Some SPI opcodes need to be sent in direct succession after each other without any chip deselect happening in between. A prominent example is WREN (Write Enable) directly before PP (Page Program). Intel calls the first opcode in such a row "preopcode". Right now, we ignore the direct succession requirement completely and it works pretty well because most onboard SPI masters have a timing or heuristics which make the problem disappear. The FT2232 SPI flasher is different. Since it is an external flasher, timing is very different to what we can expect from onboard flashers and this leads to failure at slow speeds. This patch allows any function to submit multiple SPI commands in a stream to any flasher. Support in the individual flashers isn't implemented yet, so there is one generic function which passes the each command in the stream one-by-one to the command functions of the selected SPI flash driver. Tested-by: Jakob Bornecrantz <> Corresponding to flashrom svn r645. Signed-off-by: Carl-Daniel Hailfinger <> Acked-by: Jakob Bornecrantz <>
Diffstat (limited to 'it87spi.c')
1 files changed, 1 insertions, 1 deletions
diff --git a/it87spi.c b/it87spi.c
index 67dfd2b..f062f4d 100644
--- a/it87spi.c
+++ b/it87spi.c
@@ -141,7 +141,7 @@ int it87xx_probe_spi_flash(const char *name)
* commands with the address in inverse wire order. That's why the register
* ordering in case 4 and 5 may seem strange.
-int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt,
+int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt,
const unsigned char *writearr, unsigned char *readarr)
uint8_t busy, writeenc;
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