summaryrefslogtreecommitdiffstats
path: root/flashrom.8.tmpl
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-09-14 23:37:01 +0000
committerStefan Tauner <stefan.tauner@alumni.tuwien.ac.at>2013-09-14 23:37:01 +0000
commit88ee040ab98a1ffa0c7d8faf6aac1187500e4974 (patch)
treee322dec9da0fd698ac6bb71c2f0ea2c461df5e5e /flashrom.8.tmpl
parent78cd0875a266b106004f786116fbc3d920fe2303 (diff)
downloadast2050-flashrom-88ee040ab98a1ffa0c7d8faf6aac1187500e4974.zip
ast2050-flashrom-88ee040ab98a1ffa0c7d8faf6aac1187500e4974.tar.gz
Enable fwh_idsel parameter for C-ICH and ICH2/3/4/5 chipsets
Register locations are different from ICH6, but otherwise appear to have identical bit specifications and defaults. Corresponding to flashrom svn r1748. Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Diffstat (limited to 'flashrom.8.tmpl')
-rw-r--r--flashrom.8.tmpl2
1 files changed, 1 insertions, 1 deletions
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl
index 9f8af03..b507a97 100644
--- a/flashrom.8.tmpl
+++ b/flashrom.8.tmpl
@@ -397,7 +397,7 @@ syntax. If this leads to erase or write accesses to the flash it would most
probably bring it into an inconsistent and unbootable state and we will not
provide any support in such a case.
.sp
-If you have an Intel chipset with an ICH6 or later southbridge and if you want
+If you have an Intel chipset with an ICH2 or later southbridge and if you want
to set specific IDSEL values for a non-default flash chip or an embedded
controller (EC), you can use the
.sp
OpenPOWER on IntegriCloud