path: root/flashrom.8.tmpl
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authorStefan Tauner <>2014-05-16 21:39:48 +0000
committerStefan Tauner <>2014-05-16 21:39:48 +0000
commit21071b00e35e0e20861c8b9337675c19c8459983 (patch)
tree9dd1c7b6bf85ac1d675cd7f6e41876503bb5495d /flashrom.8.tmpl
parent31402ee6872ce2880f7fe98dc933e5bc73e8613c (diff)
sbxxx: Add spispeed parameter
Allow to set the SPI clock frequency on AMD chipsets with a programmer parameter. If the parameter is given (and matches a possible value), the SPI clock is set temporarily. Both registers are restored on programmer shutdown. Example: ./flashrom -p internal:spispeed="33 MHz" -V Possible values for spispeed are "16.5 MHz", "22 MHz", "33 MHz", "66 MHz", "100 MHZ" and "800 kHz" depending on the chipset generation. Corresponding to flashrom svn r1795. Signed-off-by: Stefan Tauner <> Acked-by: Stefan Tauner <>
Diffstat (limited to 'flashrom.8.tmpl')
1 files changed, 21 insertions, 0 deletions
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl
index 8d46ffe..fb18c04 100644
--- a/flashrom.8.tmpl
+++ b/flashrom.8.tmpl
@@ -357,6 +357,27 @@ syntax. The user is responsible for supplying a suitable image or leaving out th
a layout file. This limitation might be removed in the future when we understand the details better and have
received enough feedback from users. Please report the outcome if you had to use this option to write a chip.
+An optional
+.B spispeed
+parameter specifies the frequency of the SPI bus where applicable (i.e.\& SB600 or later with an SPI flash chip
+directly attached to the chipset).
+Syntax is
+.B " flashrom \-p internal:spispeed=frequency"
+.B frequency
+can be
+.BR "'16.5\ MHz'" ", " "'22\ MHz'" ", " "'33\ MHz'" ", " "'66\ MHz'" ", " "'100\ MHZ'" ", or " "'800\ kHz'" "."
+Support of individual frequencies depends on the generation of the chipset:
+* SB6xx, SB7xx, SP5xxx: from 16.5 MHz up to and including 33 MHz
+* SB8xx, SB9xx, Hudson: from 16.5 MHz up to and including 66 MHz
+* Yangtze (with SPI 100 engine as found in Kabini and Tamesh): all of them
+The default is to use 16.5 MHz and disable Fast Reads.
.B Intel chipsets
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