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authorStefan Tauner <stefan.tauner@alumni.tuwien.ac.at>2012-12-29 15:04:12 +0000
committerStefan Tauner <stefan.tauner@alumni.tuwien.ac.at>2012-12-29 15:04:12 +0000
commit54aaa4ae2bb4026ae7acbf3e0aafe8542aaff2a4 (patch)
treeb394950b3bd52b2490e1da77a1c497516d6bfd06 /flashchips.h
parent9530a02212bd48aca32752250c4e2ec91e24d3b6 (diff)
downloadast2050-flashrom-54aaa4ae2bb4026ae7acbf3e0aafe8542aaff2a4.zip
ast2050-flashrom-54aaa4ae2bb4026ae7acbf3e0aafe8542aaff2a4.tar.gz
Add support for Intel S33 series flash chips
This includes: Bottom boot block: * 16Mb/2MB: QB25F160S33B8, QB25F016S33B8, QH25F160S33B8, QH25F016S33B8 * 32Mb/4MB: QB25F320S33B8, QH25F320S33B8 * 64Mb/8MB: QB25F640S33B8, QH25F640S33B8 Top boot block: * 16Mb/2MB: QB25F160S33T8, QB25F016S33T8, QH25F160S33T8, QH25F016S33T8 * 32Mb/4MB: QB25F320S33T8, QH25F320S33T8 * 64Mb/8MB: QB25F640S33T8, QH25F640S33T8 At least some seem to be marketed by other vendors (too?) but also with Intel's vendor ID. Besides a 0xC7 chip erase and a 0xD8 uniform 64kB block erase they support also erasing the top/bottom 8 8kB blocks with opcode 0x40. But since this command fails for all addresses outside those ranges, it is not easily implemented with flashrom's current code base and hence left out. Corresponding to flashrom svn r1636. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Diffstat (limited to 'flashchips.h')
-rw-r--r--flashchips.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/flashchips.h b/flashchips.h
index f10fbae..073f4eb 100644
--- a/flashchips.h
+++ b/flashchips.h
@@ -364,6 +364,12 @@
#define INTEL_28F008B3B 0xD3 /* 28F008B3-B */
#define INTEL_28F004B3T 0xD4 /* 28F004B3-T */
#define INTEL_28F004B3B 0xD5 /* 28F004B3-B */
+#define INTEL_25F160S33B8 0x8911 /* Same as 25F016S33B8 */
+#define INTEL_25F320S33B8 0x8912
+#define INTEL_25F640S33B8 0x8913
+#define INTEL_25F160S33T8 0x8915 /* Same as 25F016S33T8 */
+#define INTEL_25F320S33T8 0x8916
+#define INTEL_25F640S33T8 0x8917
#define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */
#define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */
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