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authorJason Wang <Qingpei.Wang@amd.com>2008-11-28 21:36:51 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2008-11-28 21:36:51 +0000
commita3f04be761d45aed2f6113eb2a6d08679370f546 (patch)
treeb1e437eb9e184676bc4ca62472bfb103ca4d2196 /flash.h
parent7f30022fb0fb62a484514e50d5b3f15157a5885d (diff)
downloadast2050-flashrom-a3f04be761d45aed2f6113eb2a6d08679370f546.zip
ast2050-flashrom-a3f04be761d45aed2f6113eb2a6d08679370f546.tar.gz
Add support for the AMD/ATI SB600 southbridge SPI functionality
This has been tested by Uwe Hermann on an RS690/SB600 board. Corresponding to flashrom svn r351 and coreboot v2 svn r3779. Signed-off-by: Jason Wang <Qingpei.Wang@amd.com> Reviewed-by: Joe Bao <zheng.bao@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Diffstat (limited to 'flash.h')
-rw-r--r--flash.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/flash.h b/flash.h
index d1e417f..cbc2e48 100644
--- a/flash.h
+++ b/flash.h
@@ -414,6 +414,7 @@ typedef enum {
BUS_TYPE_ICH7_SPI,
BUS_TYPE_ICH9_SPI,
BUS_TYPE_IT87XX_SPI,
+ BUS_TYPE_SB600_SPI,
BUS_TYPE_VIA_SPI
} flashbus_t;
@@ -497,6 +498,14 @@ int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt,
int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf);
int it8716f_spi_chip_write(struct flashchip *flash, uint8_t *buf);
+/* sb600spi.c */
+int sb600_spi_command(unsigned int writecnt, unsigned int readcnt,
+ const unsigned char *writearr, unsigned char *readarr);
+int sb600_spi_read(struct flashchip *flash, uint8_t *buf);
+int sb600_spi_write(struct flashchip *flash, uint8_t *buf);
+uint8_t sb600_read_status_register(void);
+extern uint8_t volatile *sb600_spibar;
+
/* jedec.c */
uint8_t oddparity(uint8_t val);
void toggle_ready_jedec(volatile uint8_t *dst);
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