summaryrefslogtreecommitdiffstats
path: root/chipset_enable.c
diff options
context:
space:
mode:
authorFENG yu ning <fengyuning1984@gmail.com>2008-12-15 02:32:11 +0000
committerPeter Stuge <peter@stuge.se>2008-12-15 02:32:11 +0000
commitf041e9b5865c9b5544905d163b47d2387732c634 (patch)
tree7e43780959ba8b54ea09bc0711ef3e31bc989df7 /chipset_enable.c
parent7de8639b29c4988ccf7ee110fc5ba6e7e66986f8 (diff)
downloadast2050-flashrom-f041e9b5865c9b5544905d163b47d2387732c634.zip
ast2050-flashrom-f041e9b5865c9b5544905d163b47d2387732c634.tar.gz
Various ichspi.c refinements
* add a generic preop-opcode-pair table. * rename ich_check_opcodes to ich_init_opcodes. * let ich_init_opcodes do not need to access flashchip structure: . move the definition of struct preop_opcode_pair to a better place . remove preop_opcode_pairs from 'struct flashchip' . modify ich_init_opcodes and generate_opcodes so that they do not access the flashchip structure * call ich_init_opcodes during chipset enable. Now OPCODES generation mechanism works. * fix a coding style mistake. Corresponding to flashrom svn r367 and coreboot v2 svn r3814. Signed-off-by: FENG yu ning <fengyuning1984@gmail.com> Acked-by: Peter Stuge <peter@stuge.se>
Diffstat (limited to 'chipset_enable.c')
-rw-r--r--chipset_enable.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/chipset_enable.c b/chipset_enable.c
index d2ae212..b5af401 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -339,6 +339,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
printf("WARNING: SPI Configuration Lockdown activated.\n");
ichspi_lock = 1;
}
+ ich_init_opcodes();
break;
case BUS_TYPE_ICH9_SPI:
tmp2 = *(uint16_t *) (spibar + 0);
OpenPOWER on IntegriCloud