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authorZheng Bao <zheng.bao@amd.com>2009-05-04 22:33:50 +0000
committerCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2009-05-04 22:33:50 +0000
commit284a60065d2c1b76467cbf3fb2ca1c2ef58141a5 (patch)
treee1a8f45410e4aae386d1a03103ff841fb8c70b0c /chipset_enable.c
parent98aa032c1684c02f7767c45b0c316959a5b2aa0f (diff)
downloadast2050-flashrom-284a60065d2c1b76467cbf3fb2ca1c2ef58141a5.zip
ast2050-flashrom-284a60065d2c1b76467cbf3fb2ca1c2ef58141a5.tar.gz
Force enabling SPI mode for SB600 is a bad idea and leads to hangs
Only access LPC ROM if we boot via LPC ROM. Only access SPI ROM if we boot via SPI ROM. The code to force enable SPI is commented out in case someone wants to reenable it for a particular board with LPC and SPI flash. Corresponding to flashrom svn r459. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Diffstat (limited to 'chipset_enable.c')
-rw-r--r--chipset_enable.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/chipset_enable.c b/chipset_enable.c
index 21864af..0395df6 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -680,8 +680,16 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name)
flashbus = BUS_TYPE_SB600_SPI;
/* Enable SPI ROM in SB600 PM register. */
+ /* If we enable SPI ROM here, we have to disable it after we leave.
+ * But how can we know which ROM we are going to handle? So we have
+ * to trade off. We only access LPC ROM if we boot via LPC ROM. And
+ * only SPI ROM if we boot via SPI ROM. If you want to do it crossly,
+ * you have to use the code below.
+ */
+ /*
OUTB(0x8f, 0xcd6);
OUTB(0x0e, 0xcd7);
+ */
return 0;
}
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