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authorCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2009-05-31 17:57:34 +0000
committerCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2009-05-31 17:57:34 +0000
commit1dfe0ff1745118406f2ca0d03340dd346cc39770 (patch)
tree8b0f6db0abbbd38355b6ddf8feadb7b06a4e9bab /chipset_enable.c
parentebd7b8393906876d4b450d8b83a9b748d43c64b4 (diff)
downloadast2050-flashrom-1dfe0ff1745118406f2ca0d03340dd346cc39770.zip
ast2050-flashrom-1dfe0ff1745118406f2ca0d03340dd346cc39770.tar.gz
Add bus type annotation to struct flashchips
Right now, the annotation only differentiates between SPI and non-SPI. Anyone who knows more about a specific flash chip should feel free to update it. The existing flashbus variable was abused to denote the SPI controller type. Use an aptly named variable for that purpose. Once this patch is merged, the chipset/programmer init functions can set supported flash chip types and flashrom can automatically select only matching probe/read/erase/write functions. A side benefit of that will be the elimination of the Winbond W29EE011 vs. AMIC A49LF040A conflict. Corresponding to flashrom svn r556. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Diffstat (limited to 'chipset_enable.c')
-rw-r--r--chipset_enable.c19
1 files changed, 9 insertions, 10 deletions
diff --git a/chipset_enable.c b/chipset_enable.c
index 8fbbe86..5436493 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -42,8 +42,7 @@ unsigned long flashbase = 0;
* Eventually, this will become an array when multiple flash support works.
*/
-flashbus_t flashbus = BUS_TYPE_LPC;
-void *spibar = NULL;
+enum chipbustype buses_supported = CHIP_BUSTYPE_UNKNOWN;
extern int ichspi_lock;
@@ -218,7 +217,7 @@ static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n",
mmio_readw(spibar + 0x6c));
- flashbus = BUS_TYPE_VIA_SPI;
+ spi_controller = SPI_CONTROLLER_VIA;
ich_init_opcodes();
return 0;
@@ -269,17 +268,17 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
switch (ich_generation) {
case 7:
- flashbus = BUS_TYPE_ICH7_SPI;
+ spi_controller = SPI_CONTROLLER_ICH7;
spibar_offset = 0x3020;
break;
case 8:
- flashbus = BUS_TYPE_ICH9_SPI;
+ spi_controller = SPI_CONTROLLER_ICH9;
spibar_offset = 0x3020;
break;
case 9:
case 10:
default: /* Future version might behave the same */
- flashbus = BUS_TYPE_ICH9_SPI;
+ spi_controller = SPI_CONTROLLER_ICH9;
spibar_offset = 0x3800;
break;
}
@@ -290,8 +289,8 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
/* Assign Virtual Address */
spibar = rcrb + spibar_offset;
- switch (flashbus) {
- case BUS_TYPE_ICH7_SPI:
+ switch (spi_controller) {
+ case SPI_CONTROLLER_ICH7:
printf_debug("0x00: 0x%04x (SPIS)\n",
mmio_readw(spibar + 0));
printf_debug("0x02: 0x%04x (SPIC)\n",
@@ -329,7 +328,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
}
ich_init_opcodes();
break;
- case BUS_TYPE_ICH9_SPI:
+ case SPI_CONTROLLER_ICH9:
tmp2 = mmio_readw(spibar + 4);
printf_debug("0x04: 0x%04x (HSFS)\n", tmp2);
printf_debug("FLOCKDN %i, ", (tmp2 >> 15 & 1));
@@ -729,7 +728,7 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name)
}
if (has_spi)
- flashbus = BUS_TYPE_SB600_SPI;
+ spi_controller = SPI_CONTROLLER_SB600;
/* Read ROM strap override register. */
OUTB(0x8f, 0xcd6);
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