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authorUwe Hermann <uwe@hermann-uwe.de>2009-04-11 13:59:00 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2009-04-11 13:59:00 +0000
commitd42009c4aebda9fc09844b46226a1e7f23c68c7f (patch)
tree466f616746a8f6a3b2d421903a0b286897ab7a1f
parenta822bd00437937676b094d03dffadae23983bbaf (diff)
downloadast2050-flashrom-d42009c4aebda9fc09844b46226a1e7f23c68c7f.zip
ast2050-flashrom-d42009c4aebda9fc09844b46226a1e7f23c68c7f.tar.gz
Mention a few more flash chip packages in README/manpage
Corresponding to flashrom svn r427 and coreboot v2 svn r4092. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
-rw-r--r--README5
-rw-r--r--flashrom.89
2 files changed, 8 insertions, 6 deletions
diff --git a/README b/README
index a4eee49..2d26877 100644
--- a/README
+++ b/README
@@ -5,8 +5,9 @@ Flashrom README
Flashrom is a utility for reading, writing, and erasing flash ROM chips.
It's often used to flash BIOS/coreboot/firmware images.
-It supports a wide range of DIP32, PLCC32, DIP8, and TSOP chips, which use
-various protocols such as LPC, FWH, parallel flash, or SPI.
+It supports a wide range of DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, and
+TSOP40 chips, which use various protocols such as LPC, FWH, parallel flash,
+or SPI.
(see http://coreboot.org for details on coreboot)
diff --git a/flashrom.8 b/flashrom.8
index d732e1a..cf6f5fd 100644
--- a/flashrom.8
+++ b/flashrom.8
@@ -1,6 +1,6 @@
-.TH FLASHROM 8 "January 5, 2009"
+.TH FLASHROM 8 "April 11, 2009"
.SH NAME
-flashrom \- utility for reading, writing, and erasing BIOS/ROM/flash chips
+flashrom \- read, write, and erase BIOS/ROM/flash chips
.SH SYNOPSIS
.B flashrom \fR[\fB\-rwvEVfLhR\fR] [\fB\-c\fR chipname] [\fB\-s\fR exclude_start] [\fB\-e\fR exclude_end]
[\fB-m\fR vendor:part] [\fB-l\fR file.layout] [\fB-i\fR image_name] [file]
@@ -9,8 +9,9 @@ flashrom \- utility for reading, writing, and erasing BIOS/ROM/flash chips
is a utility for reading, writing, and erasing flash ROM chips.
It's often used to flash BIOS/coreboot/firmware images.
.PP
-It supports a wide range of DIP32, PLCC32, DIP8, and TSOP chips, which use
-various protocols such as LPC, FWH, parallel flash, or SPI.
+It supports a wide range of DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, and
+TSOP40 chips, which use various protocols such as LPC, FWH, parallel flash,
+or SPI.
.PP
(see
.B http://coreboot.org
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