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authorMichael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>2010-04-03 10:27:08 +0000
committerMichael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>2010-04-03 10:27:08 +0000
commitad0010a67a9d9fdfe03164bec8d10607b882cec2 (patch)
treed94bd51665ece058ae418dd66f3bdffce0c202c5
parent253101e69e217e02802b6f7de453cb6b209f1dfa (diff)
downloadast2050-flashrom-ad0010a67a9d9fdfe03164bec8d10607b882cec2.zip
ast2050-flashrom-ad0010a67a9d9fdfe03164bec8d10607b882cec2.tar.gz
Intel 28F004/28F400 support
Remove blockwise write for i82802ab chips. It will be reintroduced in post-0.9.2 in a generic way. This is needed to fix FWH-like chips with non-uniform sectors. These are: Intel 28F001 Sharp LHF00L04 ST M50FW002 ST M50LPW116 Corresponding to flashrom svn r991. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
-rw-r--r--82802ab.c54
-rw-r--r--flash.h2
-rw-r--r--flashchips.c110
-rw-r--r--flashchips.h4
4 files changed, 133 insertions, 37 deletions
diff --git a/82802ab.c b/82802ab.c
index aa7e45e..c9d1a75 100644
--- a/82802ab.c
+++ b/82802ab.c
@@ -48,6 +48,7 @@ int probe_82802ab(struct flashchip *flash)
chipaddr bios = flash->virtual_memory;
uint8_t id1, id2;
uint8_t flashcontent1, flashcontent2;
+ int shifted = (flash->feature_bits & FEATURE_ADDR_SHIFTED) != 0;
/* Reset to get a clean state */
chip_writeb(0xFF, bios);
@@ -57,8 +58,8 @@ int probe_82802ab(struct flashchip *flash)
chip_writeb(0x90, bios);
programmer_delay(10);
- id1 = chip_readb(bios);
- id2 = chip_readb(bios + 0x01);
+ id1 = chip_readb(bios + (0x00 << shifted));
+ id2 = chip_readb(bios + (0x01 << shifted));
/* Leave ID mode */
chip_writeb(0xFF, bios);
@@ -71,8 +72,8 @@ int probe_82802ab(struct flashchip *flash)
msg_cdbg(", id1 parity violation");
/* Read the product ID location again. We should now see normal flash contents. */
- flashcontent1 = chip_readb(bios);
- flashcontent2 = chip_readb(bios + 0x01);
+ flashcontent1 = chip_readb(bios + (0x00 << shifted));
+ flashcontent2 = chip_readb(bios + (0x01 << shifted));
if (id1 == flashcontent1)
msg_cdbg(", id1 is normal flash content");
@@ -178,44 +179,25 @@ void write_page_82802ab(chipaddr bios, uint8_t *src,
int write_82802ab(struct flashchip *flash, uint8_t *buf)
{
int i;
- int total_size = flash->total_size * 1024;
- int page_size = flash->page_size;
chipaddr bios = flash->virtual_memory;
- uint8_t *tmpbuf = malloc(page_size);
- if (!tmpbuf) {
- msg_cerr("Could not allocate memory!\n");
- exit(1);
+ if (erase_flash(flash)) {
+ msg_cerr("ERASE FAILED!\n");
+ return -1;
}
- msg_cinfo("Programming page: \n");
- for (i = 0; i < total_size / page_size; i++) {
- msg_cinfo("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
- msg_cinfo("%04d at address: 0x%08x", i, i * page_size);
-
- /* Auto Skip Blocks, which already contain the desired data
- * Faster, because we only write, what has changed
- * More secure, because blocks, which are excluded
- * (with the exclude or layout feature)
- * or not erased and rewritten; their data is retained also in
- * sudden power off situations
- */
- chip_readn(tmpbuf, bios + i * page_size, page_size);
- if (!memcmp((void *)(buf + i * page_size), tmpbuf, page_size)) {
- msg_cdbg("SKIPPED\n");
- continue;
- }
- /* erase block by block and write block by block; this is the most secure way */
- if (erase_block_82802ab(flash, i * page_size, page_size)) {
- msg_cerr("ERASE FAILED!\n");
- return -1;
- }
- write_page_82802ab(bios, buf + i * page_size,
- bios + i * page_size, page_size);
+ msg_cinfo("Programming at: ");
+ for (i = 0; i < flash->total_size; i++) {
+ if ((i & 0x3) == 0)
+ msg_cinfo("address: 0x%08lx", (unsigned long)i * 1024);
+
+ write_page_82802ab(bios, buf + i * 1024, bios + i * 1024, 1024);
+
+ if ((i & 0x3) == 0)
+ msg_cinfo("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
}
- msg_cinfo("DONE!\n");
- free(tmpbuf);
+ msg_cinfo("DONE!\n");
return 0;
}
diff --git a/flash.h b/flash.h
index aee95a3..0a74363 100644
--- a/flash.h
+++ b/flash.h
@@ -166,7 +166,7 @@ enum chipbustype {
#define FEATURE_ADDR_MASK (3 << 2)
#define FEATURE_ADDR_2AA (1 << 2)
#define FEATURE_ADDR_AAA (2 << 2)
-#define FEATURE_ADDR_SHIFTED 0
+#define FEATURE_ADDR_SHIFTED (1 << 5)
struct flashchip {
const char *vendor;
diff --git a/flashchips.c b/flashchips.c
index 4f9cea7..2e0552d 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -2385,6 +2385,116 @@ struct flashchip flashchips[] = {
{
.vendor = "Intel",
+ .name = "28F004BV/BE-B",
+ .bustype = CHIP_BUSTYPE_PARALLEL,
+ .manufacture_id = INTEL_ID,
+ .model_id = P28F004BB,
+ .total_size = 512,
+ .page_size = 128 * 1024, /* maximal block size */
+ .tested = TEST_UNTESTED,
+ .probe = probe_82802ab,
+ .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */
+ .block_erasers =
+ {
+ {
+ .eraseblocks = {
+ {16 * 1024, 1},
+ {8 * 1024, 2},
+ {96 * 1024, 1},
+ {128 * 1024, 3},
+ },
+ .block_erase = erase_block_82802ab,
+ },
+ },
+ .write = write_82802ab,
+ .read = read_memmapped,
+ },
+
+ {
+ .vendor = "Intel",
+ .name = "28F004BV/BE-T",
+ .bustype = CHIP_BUSTYPE_PARALLEL,
+ .manufacture_id = INTEL_ID,
+ .model_id = P28F004BT,
+ .total_size = 512,
+ .page_size = 128 * 1024, /* maximal block size */
+ .tested = TEST_UNTESTED,
+ .probe = probe_82802ab,
+ .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */
+ .block_erasers =
+ {
+ {
+ .eraseblocks = {
+ {128 * 1024, 3},
+ {96 * 1024, 1},
+ {8 * 1024, 2},
+ {16 * 1024, 1},
+ },
+ .block_erase = erase_block_82802ab,
+ },
+ },
+ .write = write_82802ab,
+ .read = read_memmapped,
+ },
+
+ {
+ .vendor = "Intel",
+ .name = "28F400BV/CV/CE-B",
+ .bustype = CHIP_BUSTYPE_PARALLEL,
+ .manufacture_id = INTEL_ID,
+ .model_id = P28F400BB,
+ .total_size = 512,
+ .page_size = 128 * 1024, /* maximal block size */
+ .feature_bits = FEATURE_ADDR_SHIFTED,
+ .tested = TEST_UNTESTED,
+ .probe = probe_82802ab,
+ .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */
+ .block_erasers =
+ {
+ {
+ .eraseblocks = {
+ {16 * 1024, 1},
+ {8 * 1024, 2},
+ {96 * 1024, 1},
+ {128 * 1024, 3},
+ },
+ .block_erase = erase_block_82802ab,
+ },
+ },
+ .write = write_82802ab,
+ .read = read_memmapped,
+ },
+
+ {
+ .vendor = "Intel",
+ .name = "28F400BV/CV/CE-T",
+ .bustype = CHIP_BUSTYPE_PARALLEL,
+ .manufacture_id = INTEL_ID,
+ .model_id = P28F400BT,
+ .total_size = 512,
+ .page_size = 128 * 1024, /* maximal block size */
+ .feature_bits = FEATURE_ADDR_SHIFTED,
+ .tested = TEST_UNTESTED,
+ .probe = probe_82802ab,
+ .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */
+ .block_erasers =
+ {
+ {
+ .eraseblocks = {
+ {128 * 1024, 3},
+ {96 * 1024, 1},
+ {8 * 1024, 2},
+ {16 * 1024, 1},
+ },
+ .block_erase = erase_block_82802ab,
+ },
+ },
+ .write = write_82802ab,
+ .read = read_memmapped,
+ },
+
+ {
+ .vendor = "Intel",
.name = "82802AB",
.bustype = CHIP_BUSTYPE_FWH,
.manufacture_id = INTEL_ID,
diff --git a/flashchips.h b/flashchips.h
index 4337e52..b6c2e8b 100644
--- a/flashchips.h
+++ b/flashchips.h
@@ -259,6 +259,10 @@
#define E_28F016S5 0xAA
#define P28F001BXT 0x94 /* 28F001BX-T */
#define P28F001BXB 0x95 /* 28F001BX-B */
+#define P28F004BT 0x78 /* 28F004BV/BE-T */
+#define P28F004BB 0x79 /* 28F004BV/BE-B */
+#define P28F400BT 0x70 /* 28F400BV/CV/CE-T */
+#define P28F400BB 0x71 /* 28F400BV/CV/CE-B */
#define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */
#define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */
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