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| author | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2009-05-09 07:24:23 +0000 |
|---|---|---|
| committer | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2009-05-09 07:24:23 +0000 |
| commit | 4c24ad4bdfcd6a2453b550f1964da9617a33d97e (patch) | |
| tree | df21b780203e38bc19e7024f9a80bc6c24eb854f | |
| parent | 8d49701bcbd9f86e9283ef8df3082c78afddbbab (diff) | |
| download | ast2050-flashrom-4c24ad4bdfcd6a2453b550f1964da9617a33d97e.zip ast2050-flashrom-4c24ad4bdfcd6a2453b550f1964da9617a33d97e.tar.gz | |
Trim default ICH SPI delay from 1000 to 10 microseconds
Since many commands take around 10 microseconds to complete, it is
totally pointless to wait for 1000 microseconds before checking the
status again.
This patch is tested and reduced write time on ICH7 with SST25VF080B
from over one hour to 62 seconds.
Thanks to Ali Nadalizadeh for testing!
Corresponding to flashrom svn r487.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
| -rw-r--r-- | ichspi.c | 8 |
1 files changed, 4 insertions, 4 deletions
@@ -458,9 +458,9 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, REGWRITE16(ICH7_REG_SPIC, temp16); /* wait for cycle complete */ - timeout = 1000 * 60; // 60s is a looong timeout. + timeout = 100 * 1000 * 60; // 60s is a looong timeout. while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) { - myusec_delay(1000); + myusec_delay(10); } if (!timeout) { printf_debug("timeout\n"); @@ -575,9 +575,9 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, REGWRITE32(ICH9_REG_SSFS, temp32); /*wait for cycle complete */ - timeout = 1000 * 60; // 60s is a looong timeout. + timeout = 100 * 1000 * 60; // 60s is a looong timeout. while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) { - myusec_delay(1000); + myusec_delay(10); } if (!timeout) { printf_debug("timeout\n"); |
