1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
|
/* $OpenBSD: locore.S,v 1.18 1998/09/15 10:58:53 pefo Exp $ */
/*-
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Digital Equipment Corporation and Ralph Campbell.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* Copyright (C) 1989 Digital Equipment Corporation.
* Permission to use, copy, modify, and distribute this software and
* its documentation for any purpose and without fee is hereby granted,
* provided that the above copyright notice appears in all copies.
* Digital Equipment Corporation makes no representations about the
* suitability of this software for any purpose. It is provided "as is"
* without express or implied warranty.
*
* from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/loMem.s,
* v 1.1 89/07/11 17:55:04 nelson Exp SPRITE (DECWRL)
* from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsm.s,
* v 9.2 90/01/29 18:00:39 shirriff Exp SPRITE (DECWRL)
* from: Header: /sprite/src/kernel/vm/ds3100.md/vmPmaxAsm.s,
* v 1.1 89/07/10 14:27:41 nelson Exp SPRITE (DECWRL)
*
* from: @(#)locore.s 8.5 (Berkeley) 1/4/94
* JNPR: support.S,v 1.5.2.2 2007/08/29 10:03:49 girish
* $FreeBSD$
*/
/*
* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Jonathan R. Stone for
* the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Contains code that is the first executed at boot time plus
* assembly language support routines.
*/
#include "opt_cputype.h"
#include "opt_ddb.h"
#include <sys/errno.h>
#include <machine/asm.h>
#include <machine/cpu.h>
#include <machine/regnum.h>
#include <machine/cpuregs.h>
#include "assym.s"
.set noreorder # Noreorder is default style!
/*
* Primitives
*/
.text
/*
* See if access to addr with a len type instruction causes a machine check.
* len is length of access (1=byte, 2=short, 4=int)
*
* badaddr(addr, len)
* char *addr;
* int len;
*/
LEAF(badaddr)
PTR_LA v0, baderr
GET_CPU_PCPU(v1)
PTR_L v1, PC_CURPCB(v1)
bne a1, 1, 2f
PTR_S v0, U_PCB_ONFAULT(v1)
b 5f
lbu v0, (a0)
2:
bne a1, 2, 4f
nop
b 5f
lhu v0, (a0)
4:
lw v0, (a0)
5:
PTR_S zero, U_PCB_ONFAULT(v1)
j ra
move v0, zero # made it w/o errors
baderr:
j ra
li v0, 1 # trap sends us here
END(badaddr)
/*
* int copystr(void *kfaddr, void *kdaddr, size_t maxlen, size_t *lencopied)
* Copy a NIL-terminated string, at most maxlen characters long. Return the
* number of characters copied (including the NIL) in *lencopied. If the
* string is too long, return ENAMETOOLONG; else return 0.
*/
LEAF(copystr)
move t0, a2
beq a2, zero, 4f
1:
lbu v0, 0(a0)
PTR_SUBU a2, a2, 1
beq v0, zero, 2f
sb v0, 0(a1) # each byte until NIL
PTR_ADDU a0, a0, 1
bne a2, zero, 1b # less than maxlen
PTR_ADDU a1, a1, 1
4:
li v0, ENAMETOOLONG # run out of space
2:
beq a3, zero, 3f # return num. of copied bytes
PTR_SUBU a2, t0, a2 # if the 4th arg was non-NULL
PTR_S a2, 0(a3)
3:
j ra # v0 is 0 or ENAMETOOLONG
nop
END(copystr)
/*
* fillw(pat, addr, count)
*/
LEAF(fillw)
1:
PTR_ADDU a2, a2, -1
sh a0, 0(a1)
bne a2,zero, 1b
PTR_ADDU a1, a1, 2
jr ra
nop
END(fillw)
/*
* Optimized memory zero code.
* mem_zero_page(addr);
*/
LEAF(mem_zero_page)
li v0, PAGE_SIZE
1:
PTR_SUBU v0, 8
sd zero, 0(a0)
bne zero, v0, 1b
PTR_ADDU a0, 8
jr ra
nop
END(mem_zero_page)
/*
* Block I/O routines mainly used by I/O drivers.
*
* Args as: a0 = port
* a1 = memory address
* a2 = count
*/
LEAF(insb)
beq a2, zero, 2f
PTR_ADDU a2, a1
1:
lbu v0, 0(a0)
PTR_ADDU a1, 1
bne a1, a2, 1b
sb v0, -1(a1)
2:
jr ra
nop
END(insb)
LEAF(insw)
beq a2, zero, 2f
PTR_ADDU a2, a2
PTR_ADDU a2, a1
1:
lhu v0, 0(a0)
PTR_ADDU a1, 2
bne a1, a2, 1b
sh v0, -2(a1)
2:
jr ra
nop
END(insw)
LEAF(insl)
beq a2, zero, 2f
sll a2, 2
PTR_ADDU a2, a1
1:
lw v0, 0(a0)
PTR_ADDU a1, 4
bne a1, a2, 1b
sw v0, -4(a1)
2:
jr ra
nop
END(insl)
LEAF(outsb)
beq a2, zero, 2f
PTR_ADDU a2, a1
1:
lbu v0, 0(a1)
PTR_ADDU a1, 1
bne a1, a2, 1b
sb v0, 0(a0)
2:
jr ra
nop
END(outsb)
LEAF(outsw)
beq a2, zero, 2f
addu a2, a2
li v0, 1
and v0, a1
bne v0, zero, 3f # arghh, unaligned.
addu a2, a1
1:
lhu v0, 0(a1)
addiu a1, 2
bne a1, a2, 1b
sh v0, 0(a0)
2:
jr ra
nop
3:
LWHI v0, 0(a1)
LWLO v0, 3(a1)
addiu a1, 2
bne a1, a2, 3b
sh v0, 0(a0)
jr ra
nop
END(outsw)
LEAF(outsl)
beq a2, zero, 2f
sll a2, 2
li v0, 3
and v0, a1
bne v0, zero, 3f # arghh, unaligned.
addu a2, a1
1:
lw v0, 0(a1)
addiu a1, 4
bne a1, a2, 1b
sw v0, 0(a0)
2:
jr ra
nop
3:
LWHI v0, 0(a1)
LWLO v0, 3(a1)
addiu a1, 4
bne a1, a2, 3b
sw v0, 0(a0)
jr ra
nop
END(outsl)
/*
* Copy a null terminated string from the user address space into
* the kernel address space.
*
* copyinstr(fromaddr, toaddr, maxlength, &lencopied)
* caddr_t fromaddr;
* caddr_t toaddr;
* u_int maxlength;
* u_int *lencopied;
*/
NON_LEAF(copyinstr, CALLFRAME_SIZ, ra)
PTR_SUBU sp, sp, CALLFRAME_SIZ
.mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
PTR_LA v0, copyerr
blt a0, zero, _C_LABEL(copyerr) # make sure address is in user space
REG_S ra, CALLFRAME_RA(sp)
GET_CPU_PCPU(v1)
PTR_L v1, PC_CURPCB(v1)
jal _C_LABEL(copystr)
PTR_S v0, U_PCB_ONFAULT(v1)
REG_L ra, CALLFRAME_RA(sp)
GET_CPU_PCPU(v1)
PTR_L v1, PC_CURPCB(v1)
PTR_S zero, U_PCB_ONFAULT(v1)
j ra
PTR_ADDU sp, sp, CALLFRAME_SIZ
END(copyinstr)
/*
* Copy a null terminated string from the kernel address space into
* the user address space.
*
* copyoutstr(fromaddr, toaddr, maxlength, &lencopied)
* caddr_t fromaddr;
* caddr_t toaddr;
* u_int maxlength;
* u_int *lencopied;
*/
NON_LEAF(copyoutstr, CALLFRAME_SIZ, ra)
PTR_SUBU sp, sp, CALLFRAME_SIZ
.mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
PTR_LA v0, copyerr
blt a1, zero, _C_LABEL(copyerr) # make sure address is in user space
REG_S ra, CALLFRAME_RA(sp)
GET_CPU_PCPU(v1)
PTR_L v1, PC_CURPCB(v1)
jal _C_LABEL(copystr)
PTR_S v0, U_PCB_ONFAULT(v1)
REG_L ra, CALLFRAME_RA(sp)
GET_CPU_PCPU(v1)
PTR_L v1, PC_CURPCB(v1)
PTR_S zero, U_PCB_ONFAULT(v1)
j ra
PTR_ADDU sp, sp, CALLFRAME_SIZ
END(copyoutstr)
/*
* Copy specified amount of data from user space into the kernel
* copyin(from, to, len)
* caddr_t *from; (user source address)
* caddr_t *to; (kernel destination address)
* unsigned len;
*/
NON_LEAF(copyin, CALLFRAME_SIZ, ra)
PTR_SUBU sp, sp, CALLFRAME_SIZ
.mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
PTR_LA v0, copyerr
blt a0, zero, _C_LABEL(copyerr) # make sure address is in user space
REG_S ra, CALLFRAME_RA(sp)
GET_CPU_PCPU(v1)
PTR_L v1, PC_CURPCB(v1)
jal _C_LABEL(bcopy)
PTR_S v0, U_PCB_ONFAULT(v1)
REG_L ra, CALLFRAME_RA(sp)
GET_CPU_PCPU(v1)
PTR_L v1, PC_CURPCB(v1) # bcopy modified v1, so reload
PTR_S zero, U_PCB_ONFAULT(v1)
PTR_ADDU sp, sp, CALLFRAME_SIZ
j ra
move v0, zero
END(copyin)
/*
* Copy specified amount of data from kernel to the user space
* copyout(from, to, len)
* caddr_t *from; (kernel source address)
* caddr_t *to; (user destination address)
* unsigned len;
*/
NON_LEAF(copyout, CALLFRAME_SIZ, ra)
PTR_SUBU sp, sp, CALLFRAME_SIZ
.mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
PTR_LA v0, copyerr
blt a1, zero, _C_LABEL(copyerr) # make sure address is in user space
REG_S ra, CALLFRAME_RA(sp)
GET_CPU_PCPU(v1)
PTR_L v1, PC_CURPCB(v1)
jal _C_LABEL(bcopy)
PTR_S v0, U_PCB_ONFAULT(v1)
REG_L ra, CALLFRAME_RA(sp)
GET_CPU_PCPU(v1)
PTR_L v1, PC_CURPCB(v1) # bcopy modified v1, so reload
PTR_S zero, U_PCB_ONFAULT(v1)
PTR_ADDU sp, sp, CALLFRAME_SIZ
j ra
move v0, zero
END(copyout)
LEAF(copyerr)
REG_L ra, CALLFRAME_RA(sp)
PTR_ADDU sp, sp, CALLFRAME_SIZ
j ra
li v0, EFAULT # return error
END(copyerr)
/*
* {fu,su},{ibyte,isword,iword}, fetch or store a byte, short or word to
* user text space.
* {fu,su},{byte,sword,word}, fetch or store a byte, short or word to
* user data space.
*/
#ifdef __mips_n64
LEAF(fuword64)
ALEAF(fuword)
ALEAF(fuiword)
PTR_LA v0, fswberr
blt a0, zero, fswberr # make sure address is in user space
nop
GET_CPU_PCPU(v1)
PTR_L v1, PC_CURPCB(v1)
PTR_S v0, U_PCB_ONFAULT(v1)
ld v0, 0(a0) # fetch word
j ra
PTR_S zero, U_PCB_ONFAULT(v1)
END(fuword64)
#endif
LEAF(fuword32)
#ifndef __mips_n64
ALEAF(fuword)
ALEAF(fuiword)
#endif
PTR_LA v0, fswberr
blt a0, zero, fswberr # make sure address is in user space
nop
GET_CPU_PCPU(v1)
PTR_L v1, PC_CURPCB(v1)
PTR_S v0, U_PCB_ONFAULT(v1)
lw v0, 0(a0) # fetch word
j ra
PTR_S zero, U_PCB_ONFAULT(v1)
END(fuword32)
LEAF(fusword)
ALEAF(fuisword)
PTR_LA v0, fswberr
blt a0, zero, fswberr # make sure address is in user space
nop
GET_CPU_PCPU(v1)
PTR_L v1, PC_CURPCB(v1)
PTR_S v0, U_PCB_ONFAULT(v1)
lhu v0, 0(a0) # fetch short
j ra
PTR_S zero, U_PCB_ONFAULT(v1)
END(fusword)
LEAF(fubyte)
ALEAF(fuibyte)
PTR_LA v0, fswberr
blt a0, zero, fswberr # make sure address is in user space
nop
GET_CPU_PCPU(v1)
PTR_L v1, PC_CURPCB(v1)
PTR_S v0, U_PCB_ONFAULT(v1)
lbu v0, 0(a0) # fetch byte
j ra
PTR_S zero, U_PCB_ONFAULT(v1)
END(fubyte)
LEAF(suword32)
#ifndef __mips_n64
XLEAF(suword)
#endif
PTR_LA v0, fswberr
blt a0, zero, fswberr # make sure address is in user space
nop
GET_CPU_PCPU(v1)
PTR_L v1, PC_CURPCB(v1)
PTR_S v0, U_PCB_ONFAULT(v1)
sw a1, 0(a0) # store word
PTR_S zero, U_PCB_ONFAULT(v1)
j ra
move v0, zero
END(suword32)
#ifdef __mips_n64
LEAF(suword64)
XLEAF(suword)
PTR_LA v0, fswberr
blt a0, zero, fswberr # make sure address is in user space
nop
GET_CPU_PCPU(v1)
PTR_L v1, PC_CURPCB(v1)
PTR_S v0, U_PCB_ONFAULT(v1)
sd a1, 0(a0) # store word
PTR_S zero, U_PCB_ONFAULT(v1)
j ra
move v0, zero
END(suword64)
#endif
/*
* casuword(9)
* <v0>u_long casuword(<a0>u_long *p, <a1>u_long oldval, <a2>u_long newval)
*/
/*
* casuword32(9)
* <v0>uint32_t casuword(<a0>uint32_t *p, <a1>uint32_t oldval,
* <a2>uint32_t newval)
*/
LEAF(casuword32)
#ifndef __mips_n64
XLEAF(casuword)
#endif
PTR_LA v0, fswberr
blt a0, zero, fswberr # make sure address is in user space
nop
GET_CPU_PCPU(v1)
PTR_L v1, PC_CURPCB(v1)
PTR_S v0, U_PCB_ONFAULT(v1)
1:
move t0, a2
ll v0, 0(a0)
bne a1, v0, 2f
nop
sc t0, 0(a0) # store word
beqz t0, 1b
nop
j 3f
nop
2:
li v0, -1
3:
PTR_S zero, U_PCB_ONFAULT(v1)
jr ra
nop
END(casuword32)
#ifdef __mips_n64
LEAF(casuword64)
XLEAF(casuword)
PTR_LA v0, fswberr
blt a0, zero, fswberr # make sure address is in user space
nop
GET_CPU_PCPU(v1)
PTR_L v1, PC_CURPCB(v1)
PTR_S v0, U_PCB_ONFAULT(v1)
1:
move t0, a2
lld v0, 0(a0)
bne a1, v0, 2f
nop
scd t0, 0(a0) # store double word
beqz t0, 1b
nop
j 3f
nop
2:
li v0, -1
3:
PTR_S zero, U_PCB_ONFAULT(v1)
jr ra
nop
END(casuword64)
#endif
#if 0
/* unused in FreeBSD */
/*
* Have to flush instruction cache afterwards.
*/
LEAF(suiword)
PTR_LA v0, fswberr
blt a0, zero, fswberr # make sure address is in user space
nop
GET_CPU_PCPU(v1)
PTR_L v1, PC_CURPCB(v1)
PTR_S v0, U_PCB_ONFAULT(v1)
sw a1, 0(a0) # store word
PTR_S zero, U_PCB_ONFAULT(v1)
j _C_LABEL(Mips_SyncICache) # FlushICache sets v0 = 0. (Ugly)
li a1, 4 # size of word
END(suiword)
#endif
/*
* Will have to flush the instruction cache if byte merging is done in hardware.
*/
LEAF(susword)
ALEAF(suisword)
PTR_LA v0, fswberr
blt a0, zero, fswberr # make sure address is in user space
nop
GET_CPU_PCPU(v1)
PTR_L v1, PC_CURPCB(v1)
PTR_S v0, U_PCB_ONFAULT(v1)
sh a1, 0(a0) # store short
PTR_S zero, U_PCB_ONFAULT(v1)
j ra
move v0, zero
END(susword)
LEAF(subyte)
ALEAF(suibyte)
PTR_LA v0, fswberr
blt a0, zero, fswberr # make sure address is in user space
nop
GET_CPU_PCPU(v1)
PTR_L v1, PC_CURPCB(v1)
PTR_S v0, U_PCB_ONFAULT(v1)
sb a1, 0(a0) # store byte
PTR_S zero, U_PCB_ONFAULT(v1)
j ra
move v0, zero
END(subyte)
LEAF(fswberr)
j ra
li v0, -1
END(fswberr)
/*
* fuswintr and suswintr are just like fusword and susword except that if
* the page is not in memory or would cause a trap, then we return an error.
* The important thing is to prevent sleep() and switch().
*/
LEAF(fuswintr)
PTR_LA v0, fswintrberr
blt a0, zero, fswintrberr # make sure address is in user space
nop
GET_CPU_PCPU(v1)
PTR_L v1, PC_CURPCB(v1)
PTR_S v0, U_PCB_ONFAULT(v1)
lhu v0, 0(a0) # fetch short
j ra
PTR_S zero, U_PCB_ONFAULT(v1)
END(fuswintr)
LEAF(suswintr)
PTR_LA v0, fswintrberr
blt a0, zero, fswintrberr # make sure address is in user space
nop
GET_CPU_PCPU(v1)
PTR_L v1, PC_CURPCB(v1)
PTR_S v0, U_PCB_ONFAULT(v1)
sh a1, 0(a0) # store short
PTR_S zero, U_PCB_ONFAULT(v1)
j ra
move v0, zero
END(suswintr)
LEAF(fswintrberr)
j ra
li v0, -1
END(fswintrberr)
/*
* memcpy(to, from, len)
* {ov}bcopy(from, to, len)
*/
LEAF(memcpy)
.set noreorder
move v0, a0 # swap from and to
move a0, a1
move a1, v0
ALEAF(bcopy)
ALEAF(ovbcopy)
.set noreorder
PTR_ADDU t0, a0, a2 # t0 = end of s1 region
sltu t1, a1, t0
sltu t2, a0, a1
and t1, t1, t2 # t1 = true if from < to < (from+len)
beq t1, zero, forward # non overlapping, do forward copy
slt t2, a2, 12 # check for small copy
ble a2, zero, 2f
PTR_ADDU t1, a1, a2 # t1 = end of to region
1:
lb v1, -1(t0) # copy bytes backwards,
PTR_SUBU t0, t0, 1 # doesnt happen often so do slow way
PTR_SUBU t1, t1, 1
bne t0, a0, 1b
sb v1, 0(t1)
2:
j ra
nop
forward:
bne t2, zero, smallcpy # do a small bcopy
xor v1, a0, a1 # compare low two bits of addresses
and v1, v1, 3
PTR_SUBU a3, zero, a1 # compute # bytes to word align address
beq v1, zero, aligned # addresses can be word aligned
and a3, a3, 3
beq a3, zero, 1f
PTR_SUBU a2, a2, a3 # subtract from remaining count
LWHI v1, 0(a0) # get next 4 bytes (unaligned)
LWLO v1, 3(a0)
PTR_ADDU a0, a0, a3
SWHI v1, 0(a1) # store 1, 2, or 3 bytes to align a1
PTR_ADDU a1, a1, a3
1:
and v1, a2, 3 # compute number of words left
PTR_SUBU a3, a2, v1
move a2, v1
PTR_ADDU a3, a3, a0 # compute ending address
2:
LWHI v1, 0(a0) # copy words a0 unaligned, a1 aligned
LWLO v1, 3(a0)
PTR_ADDU a0, a0, 4
sw v1, 0(a1)
PTR_ADDU a1, a1, 4
bne a0, a3, 2b
nop # We have to do this mmu-bug.
b smallcpy
nop
aligned:
beq a3, zero, 1f
PTR_SUBU a2, a2, a3 # subtract from remaining count
LWHI v1, 0(a0) # copy 1, 2, or 3 bytes to align
PTR_ADDU a0, a0, a3
SWHI v1, 0(a1)
PTR_ADDU a1, a1, a3
1:
and v1, a2, 3 # compute number of whole words left
PTR_SUBU a3, a2, v1
move a2, v1
PTR_ADDU a3, a3, a0 # compute ending address
2:
lw v1, 0(a0) # copy words
PTR_ADDU a0, a0, 4
sw v1, 0(a1)
bne a0, a3, 2b
PTR_ADDU a1, a1, 4
smallcpy:
ble a2, zero, 2f
PTR_ADDU a3, a2, a0 # compute ending address
1:
lbu v1, 0(a0) # copy bytes
PTR_ADDU a0, a0, 1
sb v1, 0(a1)
bne a0, a3, 1b
PTR_ADDU a1, a1, 1 # MMU BUG ? can not do -1(a1) at 0x80000000!!
2:
j ra
nop
END(memcpy)
/*
* memset(void *s1, int c, int len)
* NetBSD: memset.S,v 1.3 2001/10/16 15:40:53 uch Exp
*/
LEAF(memset)
.set noreorder
blt a2, 12, memsetsmallclr # small amount to clear?
move v0, a0 # save s1 for result
sll t1, a1, 8 # compute c << 8 in t1
or t1, t1, a1 # compute c << 8 | c in 11
sll t2, t1, 16 # shift that left 16
or t1, t2, t1 # or together
PTR_SUBU t0, zero, a0 # compute # bytes to word align address
and t0, t0, 3
beq t0, zero, 1f # skip if word aligned
PTR_SUBU a2, a2, t0 # subtract from remaining count
SWHI t1, 0(a0) # store 1, 2, or 3 bytes to align
PTR_ADDU a0, a0, t0
1:
and v1, a2, 3 # compute number of whole words left
PTR_SUBU t0, a2, v1
PTR_SUBU a2, a2, t0
PTR_ADDU t0, t0, a0 # compute ending address
2:
PTR_ADDU a0, a0, 4 # clear words
#ifdef MIPS3_5900
nop
nop
nop
nop
#endif
bne a0, t0, 2b # unrolling loop does not help
sw t1, -4(a0) # since we are limited by memory speed
memsetsmallclr:
ble a2, zero, 2f
PTR_ADDU t0, a2, a0 # compute ending address
1:
PTR_ADDU a0, a0, 1 # clear bytes
#ifdef MIPS3_5900
nop
nop
nop
nop
#endif
bne a0, t0, 1b
sb a1, -1(a0)
2:
j ra
nop
.set reorder
END(memset)
/*
* bzero(s1, n)
*/
LEAF(bzero)
ALEAF(blkclr)
.set noreorder
blt a1, 12, smallclr # small amount to clear?
PTR_SUBU a3, zero, a0 # compute # bytes to word align address
and a3, a3, 3
beq a3, zero, 1f # skip if word aligned
PTR_SUBU a1, a1, a3 # subtract from remaining count
SWHI zero, 0(a0) # clear 1, 2, or 3 bytes to align
PTR_ADDU a0, a0, a3
1:
and v0, a1, 3 # compute number of words left
PTR_SUBU a3, a1, v0
move a1, v0
PTR_ADDU a3, a3, a0 # compute ending address
2:
PTR_ADDU a0, a0, 4 # clear words
bne a0, a3, 2b # unrolling loop does not help
sw zero, -4(a0) # since we are limited by memory speed
smallclr:
ble a1, zero, 2f
PTR_ADDU a3, a1, a0 # compute ending address
1:
PTR_ADDU a0, a0, 1 # clear bytes
bne a0, a3, 1b
sb zero, -1(a0)
2:
j ra
nop
END(bzero)
/*
* bcmp(s1, s2, n)
*/
LEAF(bcmp)
.set noreorder
blt a2, 16, smallcmp # is it worth any trouble?
xor v0, a0, a1 # compare low two bits of addresses
and v0, v0, 3
PTR_SUBU a3, zero, a1 # compute # bytes to word align address
bne v0, zero, unalignedcmp # not possible to align addresses
and a3, a3, 3
beq a3, zero, 1f
PTR_SUBU a2, a2, a3 # subtract from remaining count
move v0, v1 # init v0,v1 so unmodified bytes match
LWHI v0, 0(a0) # read 1, 2, or 3 bytes
LWHI v1, 0(a1)
PTR_ADDU a1, a1, a3
bne v0, v1, nomatch
PTR_ADDU a0, a0, a3
1:
and a3, a2, ~3 # compute number of whole words left
PTR_SUBU a2, a2, a3 # which has to be >= (16-3) & ~3
PTR_ADDU a3, a3, a0 # compute ending address
2:
lw v0, 0(a0) # compare words
lw v1, 0(a1)
PTR_ADDU a0, a0, 4
bne v0, v1, nomatch
PTR_ADDU a1, a1, 4
bne a0, a3, 2b
nop
b smallcmp # finish remainder
nop
unalignedcmp:
beq a3, zero, 2f
PTR_SUBU a2, a2, a3 # subtract from remaining count
PTR_ADDU a3, a3, a0 # compute ending address
1:
lbu v0, 0(a0) # compare bytes until a1 word aligned
lbu v1, 0(a1)
PTR_ADDU a0, a0, 1
bne v0, v1, nomatch
PTR_ADDU a1, a1, 1
bne a0, a3, 1b
nop
2:
and a3, a2, ~3 # compute number of whole words left
PTR_SUBU a2, a2, a3 # which has to be >= (16-3) & ~3
PTR_ADDU a3, a3, a0 # compute ending address
3:
LWHI v0, 0(a0) # compare words a0 unaligned, a1 aligned
LWLO v0, 3(a0)
lw v1, 0(a1)
PTR_ADDU a0, a0, 4
bne v0, v1, nomatch
PTR_ADDU a1, a1, 4
bne a0, a3, 3b
nop
smallcmp:
ble a2, zero, match
PTR_ADDU a3, a2, a0 # compute ending address
1:
lbu v0, 0(a0)
lbu v1, 0(a1)
PTR_ADDU a0, a0, 1
bne v0, v1, nomatch
PTR_ADDU a1, a1, 1
bne a0, a3, 1b
nop
match:
j ra
move v0, zero
nomatch:
j ra
li v0, 1
END(bcmp)
/*
* bit = ffs(value)
*/
LEAF(ffs)
.set noreorder
beq a0, zero, 2f
move v0, zero
1:
and v1, a0, 1 # bit set?
addu v0, v0, 1
beq v1, zero, 1b # no, continue
srl a0, a0, 1
2:
j ra
nop
END(ffs)
LEAF(get_current_fp)
j ra
move v0, s8
END(get_current_fp)
LEAF(loadandclear)
.set noreorder
1:
ll v0, 0(a0)
move t0, zero
sc t0, 0(a0)
beq t0, zero, 1b
nop
j ra
nop
END(loadandclear)
#if 0
/*
* u_int32_t atomic_cmpset_32(u_int32_t *p, u_int32_t cmpval, u_int32_t newval)
* Atomically compare the value stored at p with cmpval
* and if the two values are equal, update value *p with
* newval. Return zero if compare failed, non-zero otherwise
*
*/
LEAF(atomic_cmpset_32)
.set noreorder
1:
ll t0, 0(a0)
move v0, zero
bne t0, a1, 2f
move t1, a2
sc t1, 0(a0)
beq t1, zero, 1b
or v0, v0, 1
2:
j ra
nop
END(atomic_cmpset_32)
/**
* u_int32_t
* atomic_readandclear_32(u_int32_t *a)
* {
* u_int32_t retval;
* retval = *a;
* *a = 0;
* }
*/
LEAF(atomic_readandclear_32)
.set noreorder
1:
ll t0, 0(a0)
move t1, zero
move v0, t0
sc t1, 0(a0)
beq t1, zero, 1b
nop
j ra
nop
END(atomic_readandclear_32)
/**
* void
* atomic_set_32(u_int32_t *a, u_int32_t b)
* {
* *a |= b;
* }
*/
LEAF(atomic_set_32)
.set noreorder
1:
ll t0, 0(a0)
or t0, t0, a1
sc t0, 0(a0)
beq t0, zero, 1b
nop
j ra
nop
END(atomic_set_32)
/**
* void
* atomic_add_32(uint32_t *a, uint32_t b)
* {
* *a += b;
* }
*/
LEAF(atomic_add_32)
.set noreorder
srl a0, a0, 2 # round down address to be 32-bit aligned
sll a0, a0, 2
1:
ll t0, 0(a0)
addu t0, t0, a1
sc t0, 0(a0)
beq t0, zero, 1b
nop
j ra
nop
END(atomic_add_32)
/**
* void
* atomic_clear_32(u_int32_t *a, u_int32_t b)
* {
* *a &= ~b;
* }
*/
LEAF(atomic_clear_32)
.set noreorder
srl a0, a0, 2 # round down address to be 32-bit aligned
sll a0, a0, 2
nor a1, zero, a1
1:
ll t0, 0(a0)
and t0, t0, a1 # t1 has the new lower 16 bits
sc t0, 0(a0)
beq t0, zero, 1b
nop
j ra
nop
END(atomic_clear_32)
/**
* void
* atomic_subtract_32(uint16_t *a, uint16_t b)
* {
* *a -= b;
* }
*/
LEAF(atomic_subtract_32)
.set noreorder
srl a0, a0, 2 # round down address to be 32-bit aligned
sll a0, a0, 2
1:
ll t0, 0(a0)
subu t0, t0, a1
sc t0, 0(a0)
beq t0, zero, 1b
nop
j ra
nop
END(atomic_subtract_32)
#endif
/**
* void
* atomic_set_16(u_int16_t *a, u_int16_t b)
* {
* *a |= b;
* }
*/
LEAF(atomic_set_16)
.set noreorder
srl a0, a0, 2 # round down address to be 32-bit aligned
sll a0, a0, 2
andi a1, a1, 0xffff
1:
ll t0, 0(a0)
or t0, t0, a1
sc t0, 0(a0)
beq t0, zero, 1b
nop
j ra
nop
END(atomic_set_16)
/**
* void
* atomic_clear_16(u_int16_t *a, u_int16_t b)
* {
* *a &= ~b;
* }
*/
LEAF(atomic_clear_16)
.set noreorder
srl a0, a0, 2 # round down address to be 32-bit aligned
sll a0, a0, 2
nor a1, zero, a1
1:
ll t0, 0(a0)
move t1, t0
andi t1, t1, 0xffff # t1 has the original lower 16 bits
and t1, t1, a1 # t1 has the new lower 16 bits
srl t0, t0, 16 # preserve original top 16 bits
sll t0, t0, 16
or t0, t0, t1
sc t0, 0(a0)
beq t0, zero, 1b
nop
j ra
nop
END(atomic_clear_16)
/**
* void
* atomic_subtract_16(uint16_t *a, uint16_t b)
* {
* *a -= b;
* }
*/
LEAF(atomic_subtract_16)
.set noreorder
srl a0, a0, 2 # round down address to be 32-bit aligned
sll a0, a0, 2
1:
ll t0, 0(a0)
move t1, t0
andi t1, t1, 0xffff # t1 has the original lower 16 bits
subu t1, t1, a1
andi t1, t1, 0xffff # t1 has the new lower 16 bits
srl t0, t0, 16 # preserve original top 16 bits
sll t0, t0, 16
or t0, t0, t1
sc t0, 0(a0)
beq t0, zero, 1b
nop
j ra
nop
END(atomic_subtract_16)
/**
* void
* atomic_add_16(uint16_t *a, uint16_t b)
* {
* *a += b;
* }
*/
LEAF(atomic_add_16)
.set noreorder
srl a0, a0, 2 # round down address to be 32-bit aligned
sll a0, a0, 2
1:
ll t0, 0(a0)
move t1, t0
andi t1, t1, 0xffff # t1 has the original lower 16 bits
addu t1, t1, a1
andi t1, t1, 0xffff # t1 has the new lower 16 bits
srl t0, t0, 16 # preserve original top 16 bits
sll t0, t0, 16
or t0, t0, t1
sc t0, 0(a0)
beq t0, zero, 1b
nop
j ra
nop
END(atomic_add_16)
/**
* void
* atomic_add_8(uint8_t *a, uint8_t b)
* {
* *a += b;
* }
*/
LEAF(atomic_add_8)
.set noreorder
srl a0, a0, 2 # round down address to be 32-bit aligned
sll a0, a0, 2
1:
ll t0, 0(a0)
move t1, t0
andi t1, t1, 0xff # t1 has the original lower 8 bits
addu t1, t1, a1
andi t1, t1, 0xff # t1 has the new lower 8 bits
srl t0, t0, 8 # preserve original top 24 bits
sll t0, t0, 8
or t0, t0, t1
sc t0, 0(a0)
beq t0, zero, 1b
nop
j ra
nop
END(atomic_add_8)
/**
* void
* atomic_subtract_8(uint8_t *a, uint8_t b)
* {
* *a += b;
* }
*/
LEAF(atomic_subtract_8)
.set noreorder
srl a0, a0, 2 # round down address to be 32-bit aligned
sll a0, a0, 2
1:
ll t0, 0(a0)
move t1, t0
andi t1, t1, 0xff # t1 has the original lower 8 bits
subu t1, t1, a1
andi t1, t1, 0xff # t1 has the new lower 8 bits
srl t0, t0, 8 # preserve original top 24 bits
sll t0, t0, 8
or t0, t0, t1
sc t0, 0(a0)
beq t0, zero, 1b
nop
j ra
nop
END(atomic_subtract_8)
/*
* atomic 64-bit register read/write assembly language support routines.
*/
.set noreorder # Noreorder is default style!
#if !defined(__mips_n64) && !defined(__mips_n32)
/*
* I don't know if these routines have the right number of
* NOPs in it for all processors. XXX
*
* Maybe it would be better to just leave this undefined in that case.
*/
LEAF(atomic_store_64)
mfc0 t1, MIPS_COP_0_STATUS
and t2, t1, ~MIPS_SR_INT_IE
mtc0 t2, MIPS_COP_0_STATUS
nop
nop
nop
nop
ld t0, (a1)
nop
nop
sd t0, (a0)
nop
nop
mtc0 t1,MIPS_COP_0_STATUS
nop
nop
nop
nop
j ra
nop
END(atomic_store_64)
LEAF(atomic_load_64)
mfc0 t1, MIPS_COP_0_STATUS
and t2, t1, ~MIPS_SR_INT_IE
mtc0 t2, MIPS_COP_0_STATUS
nop
nop
nop
nop
ld t0, (a0)
nop
nop
sd t0, (a1)
nop
nop
mtc0 t1,MIPS_COP_0_STATUS
nop
nop
nop
nop
j ra
nop
END(atomic_load_64)
#endif
#if defined(DDB) || defined(DEBUG)
LEAF(kdbpeek)
PTR_LA v1, ddberr
and v0, a0, 3 # unaligned ?
GET_CPU_PCPU(t1)
PTR_L t1, PC_CURPCB(t1)
bne v0, zero, 1f
PTR_S v1, U_PCB_ONFAULT(t1)
lw v0, (a0)
jr ra
PTR_S zero, U_PCB_ONFAULT(t1)
1:
LWHI v0, 0(a0)
LWLO v0, 3(a0)
jr ra
PTR_S zero, U_PCB_ONFAULT(t1)
END(kdbpeek)
LEAF(kdbpeekd)
PTR_LA v1, ddberr
and v0, a0, 3 # unaligned ?
GET_CPU_PCPU(t1)
PTR_L t1, PC_CURPCB(t1)
bne v0, zero, 1f
PTR_S v1, U_PCB_ONFAULT(t1)
ld v0, (a0)
jr ra
PTR_S zero, U_PCB_ONFAULT(t1)
1:
REG_LHI v0, 0(a0)
REG_LLO v0, 7(a0)
jr ra
PTR_S zero, U_PCB_ONFAULT(t1)
END(kdbpeekd)
ddberr:
jr ra
nop
#if defined(DDB)
LEAF(kdbpoke)
PTR_LA v1, ddberr
and v0, a0, 3 # unaligned ?
GET_CPU_PCPU(t1)
PTR_L t1, PC_CURPCB(t1)
bne v0, zero, 1f
PTR_S v1, U_PCB_ONFAULT(t1)
sw a1, (a0)
jr ra
PTR_S zero, U_PCB_ONFAULT(t1)
1:
SWHI a1, 0(a0)
SWLO a1, 3(a0)
jr ra
PTR_S zero, U_PCB_ONFAULT(t1)
END(kdbpoke)
.data
.globl esym
esym: .word 0
#endif /* DDB */
#endif /* DDB || DEBUG */
.text
LEAF(breakpoint)
break MIPS_BREAK_SOVER_VAL
jr ra
nop
END(breakpoint)
LEAF(setjmp)
mfc0 v0, MIPS_COP_0_STATUS # Later the "real" spl value!
REG_S s0, (SZREG * PREG_S0)(a0)
REG_S s1, (SZREG * PREG_S1)(a0)
REG_S s2, (SZREG * PREG_S2)(a0)
REG_S s3, (SZREG * PREG_S3)(a0)
REG_S s4, (SZREG * PREG_S4)(a0)
REG_S s5, (SZREG * PREG_S5)(a0)
REG_S s6, (SZREG * PREG_S6)(a0)
REG_S s7, (SZREG * PREG_S7)(a0)
REG_S s8, (SZREG * PREG_S8)(a0)
REG_S sp, (SZREG * PREG_SP)(a0)
REG_S ra, (SZREG * PREG_RA)(a0)
REG_S v0, (SZREG * PREG_SR)(a0)
jr ra
li v0, 0 # setjmp return
END(setjmp)
LEAF(longjmp)
REG_L v0, (SZREG * PREG_SR)(a0)
REG_L ra, (SZREG * PREG_RA)(a0)
REG_L s0, (SZREG * PREG_S0)(a0)
REG_L s1, (SZREG * PREG_S1)(a0)
REG_L s2, (SZREG * PREG_S2)(a0)
REG_L s3, (SZREG * PREG_S3)(a0)
REG_L s4, (SZREG * PREG_S4)(a0)
REG_L s5, (SZREG * PREG_S5)(a0)
REG_L s6, (SZREG * PREG_S6)(a0)
REG_L s7, (SZREG * PREG_S7)(a0)
REG_L s8, (SZREG * PREG_S8)(a0)
REG_L sp, (SZREG * PREG_SP)(a0)
mtc0 v0, MIPS_COP_0_STATUS # Later the "real" spl value!
ITLBNOPFIX
jr ra
li v0, 1 # longjmp return
END(longjmp)
LEAF(fusufault)
GET_CPU_PCPU(t0)
lw t0, PC_CURTHREAD(t0)
lw t0, TD_PCB(t0)
li v0, -1
j ra
END(fusufault)
/* Define a new md function 'casuptr'. This atomically compares and sets
a pointer that is in user space. It will be used as the basic primitive
for a kernel supported user space lock implementation. */
LEAF(casuptr)
PTR_LI t0, VM_MAXUSER_ADDRESS /* verify address validity */
blt a0, t0, fusufault /* trap faults */
nop
GET_CPU_PCPU(t1)
lw t1, PC_CURTHREAD(t1)
lw t1, TD_PCB(t1)
PTR_LA t2, fusufault
PTR_S t2, U_PCB_ONFAULT(t1)
1:
ll v0, 0(a0) /* try to load the old value */
beq v0, a1, 2f /* compare */
move t0, a2 /* setup value to write */
sc t0, 0(a0) /* write if address still locked */
beq t0, zero, 1b /* if it failed, spin */
2:
PTR_S zero, U_PCB_ONFAULT(t1) /* clean up */
j ra
END(casuptr)
#ifdef CPU_CNMIPS
/*
* void octeon_enable_shadow(void)
* turns on access to CC and CCRes
*/
LEAF(octeon_enable_shadow)
li t1, 0x0000000f
mtc0 t1, MIPS_COP_0_INFO
jr ra
nop
END(octeon_enable_shadow)
LEAF(octeon_get_shadow)
mfc0 v0, MIPS_COP_0_INFO
jr ra
nop
END(octeon_get_shadow)
/*
* octeon_set_control(addr, uint32_t val)
*/
LEAF(octeon_set_control)
.set push
or t1, a1, zero
/* dmfc0 a1, 9, 7*/
.word 0x40254807
sd a1, 0(a0)
or a1, t1, zero
/* dmtc0 a1, 9, 7*/
.word 0x40a54807
jr ra
nop
.set pop
END(octeon_set_control)
/*
* octeon_get_control(addr)
*/
LEAF(octeon_get_control)
.set push
.set mips64r2
/* dmfc0 a1, 9, 7 */
.word 0x40254807
sd a1, 0(a0)
jr ra
nop
.set pop
END(octeon_get_control)
#endif
LEAF(mips3_ld)
.set push
.set noreorder
.set mips64
#if defined(__mips_o32)
mfc0 t0, MIPS_COP_0_STATUS # turn off interrupts
and t1, t0, ~(MIPS_SR_INT_IE)
mtc0 t1, MIPS_COP_0_STATUS
COP0_SYNC
nop
nop
nop
ld v0, 0(a0)
#if _BYTE_ORDER == _BIG_ENDIAN
dsll v1, v0, 32
dsra v1, v1, 32 # low word in v1
dsra v0, v0, 32 # high word in v0
#else
dsra v1, v0, 32 # high word in v1
dsll v0, v0, 32
dsra v0, v0, 32 # low word in v0
#endif
mtc0 t0, MIPS_COP_0_STATUS # restore intr status.
COP0_SYNC
nop
#else /* !__mips_o32 */
ld v0, 0(a0)
#endif /* !__mips_o32 */
jr ra
nop
.set pop
END(mips3_ld)
LEAF(mips3_sd)
.set push
.set mips64
.set noreorder
#if defined(__mips_o32)
mfc0 t0, MIPS_COP_0_STATUS # turn off interrupts
and t1, t0, ~(MIPS_SR_INT_IE)
mtc0 t1, MIPS_COP_0_STATUS
COP0_SYNC
nop
nop
nop
# NOTE: a1 is padding!
#if _BYTE_ORDER == _BIG_ENDIAN
dsll a2, a2, 32 # high word in a2
dsll a3, a3, 32 # low word in a3
dsrl a3, a3, 32
#else
dsll a2, a2, 32 # low word in a2
dsrl a2, a2, 32
dsll a3, a3, 32 # high word in a3
#endif
or a1, a2, a3
sd a1, 0(a0)
mtc0 t0, MIPS_COP_0_STATUS # restore intr status.
COP0_SYNC
nop
#else /* !__mips_o32 */
sd a1, 0(a0)
#endif /* !__mips_o32 */
jr ra
nop
.set pop
END(mips3_sd)
|