1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
|
/*-
* Copyright (c) 1998 Doug Rabson
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_CPUFUNC_H_
#define _MACHINE_CPUFUNC_H_
#ifdef _KERNEL
#include <sys/types.h>
#include <machine/ia64_cpu.h>
#include <machine/vmparam.h>
struct thread;
#ifdef __GNUC__
static __inline void
breakpoint(void)
{
__asm __volatile("break 0x80100"); /* XXX use linux value */
}
#endif
extern u_int64_t ia64_port_base;
static __inline volatile void *
ia64_port_address(u_int port)
{
return (volatile void *)(ia64_port_base
| ((port >> 2) << 12)
| (port & ((1 << 12) - 1)));
}
static __inline volatile void *
ia64_memory_address(u_int64_t addr)
{
return (volatile void *) IA64_PHYS_TO_RR6(addr);
}
static __inline u_int8_t
inb(u_int port)
{
volatile u_int8_t *p = ia64_port_address(port);
u_int8_t v = *p;
ia64_mf_a();
ia64_mf();
return v;
}
static __inline u_int16_t
inw(u_int port)
{
volatile u_int16_t *p = ia64_port_address(port);
u_int16_t v = *p;
ia64_mf_a();
ia64_mf();
return v;
}
static __inline u_int32_t
inl(u_int port)
{
volatile u_int32_t *p = ia64_port_address(port);
u_int32_t v = *p;
ia64_mf_a();
ia64_mf();
return v;
}
static __inline void
insb(u_int port, void *addr, size_t count)
{
u_int8_t *p = addr;
while (count--)
*p++ = inb(port);
}
static __inline void
insw(u_int port, void *addr, size_t count)
{
u_int16_t *p = addr;
while (count--)
*p++ = inw(port);
}
static __inline void
insl(u_int port, void *addr, size_t count)
{
u_int32_t *p = addr;
while (count--)
*p++ = inl(port);
}
static __inline void
outb(u_int port, u_int8_t data)
{
volatile u_int8_t *p = ia64_port_address(port);
*p = data;
ia64_mf_a();
ia64_mf();
}
static __inline void
outw(u_int port, u_int16_t data)
{
volatile u_int16_t *p = ia64_port_address(port);
*p = data;
ia64_mf_a();
ia64_mf();
}
static __inline void
outl(u_int port, u_int32_t data)
{
volatile u_int32_t *p = ia64_port_address(port);
*p = data;
ia64_mf_a();
ia64_mf();
}
static __inline void
outsb(u_int port, const void *addr, size_t count)
{
const u_int8_t *p = addr;
while (count--)
outb(port, *p++);
}
static __inline void
outsw(u_int port, const void *addr, size_t count)
{
const u_int16_t *p = addr;
while (count--)
outw(port, *p++);
}
static __inline void
outsl(u_int port, const void *addr, size_t count)
{
const u_int32_t *p = addr;
while (count--)
outl(port, *p++);
}
static __inline u_int8_t
readb(u_int addr)
{
volatile u_int8_t *p = ia64_memory_address(addr);
u_int8_t v = *p;
ia64_mf_a();
ia64_mf();
return v;
}
static __inline u_int16_t
readw(u_int addr)
{
volatile u_int16_t *p = ia64_memory_address(addr);
u_int16_t v = *p;
ia64_mf_a();
ia64_mf();
return v;
}
static __inline u_int32_t
readl(u_int addr)
{
volatile u_int32_t *p = ia64_memory_address(addr);
u_int32_t v = *p;
ia64_mf_a();
ia64_mf();
return v;
}
static __inline void
writeb(u_int addr, u_int8_t data)
{
volatile u_int8_t *p = ia64_memory_address(addr);
*p = data;
ia64_mf_a();
ia64_mf();
}
static __inline void
writew(u_int addr, u_int16_t data)
{
volatile u_int16_t *p = ia64_memory_address(addr);
*p = data;
ia64_mf_a();
ia64_mf();
}
static __inline void
writel(u_int addr, u_int32_t data)
{
volatile u_int32_t *p = ia64_memory_address(addr);
*p = data;
ia64_mf_a();
ia64_mf();
}
static __inline void
memcpy_fromio(u_int8_t *addr, size_t ofs, size_t count)
{
volatile u_int8_t *p = ia64_memory_address(ofs);
while (count--)
*addr++ = *p++;
}
static __inline void
memcpy_io(size_t dst, size_t src, size_t count)
{
volatile u_int8_t *dp = ia64_memory_address(dst);
volatile u_int8_t *sp = ia64_memory_address(src);
while (count--)
*dp++ = *sp++;
}
static __inline void
memcpy_toio(size_t ofs, u_int8_t *addr, size_t count)
{
volatile u_int8_t *p = ia64_memory_address(ofs);
while (count--)
*p++ = *addr++;
}
static __inline void
memset_io(size_t ofs, u_int8_t value, size_t count)
{
volatile u_int8_t *p = ia64_memory_address(ofs);
while (count--)
*p++ = value;
}
static __inline void
memsetw(u_int16_t *addr, int val, size_t size)
{
while (size--)
*addr++ = val;
}
static __inline void
memsetw_io(size_t ofs, u_int16_t value, size_t count)
{
volatile u_int16_t *p = ia64_memory_address(ofs);
while (count--)
*p++ = value;
}
static __inline void
disable_intr(void)
{
__asm __volatile ("rsm psr.i;;");
}
static __inline void
enable_intr(void)
{
__asm __volatile (";; ssm psr.i;; srlz.d");
}
static __inline register_t
intr_disable(void)
{
register_t psr;
__asm __volatile ("mov %0=psr;;" : "=r" (psr));
disable_intr();
return (psr);
}
static __inline void
intr_restore(critical_t psr)
{
__asm __volatile ("mov psr.l=%0;; srlz.d" :: "r" (psr));
}
#endif /* _KERNEL */
#endif /* !_MACHINE_CPUFUNC_H_ */
|