1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
|
/*
* Copyright (c) 1998 Martijn Plak. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
* 4. Altered versions must be plainly marked as such, and must not be
* misrepresented as being the original software and/or documentation.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*---------------------------------------------------------------------------
*
* isdn4bsd layer1 driver for Dynalink IS64PH isdn TA
* ==================================================
*
* $Id: i4b_dynalink.c,v 1.8 1998/12/17 04:55:38 hm Exp $
*
* last edit-date: [Thu Dec 17 05:50:39 1998]
*
* written by Martijn Plak <tigrfhur@xs4all.nl>
*
* -mp 11 jun 1998 first try, code borrowed from Creatix driver
* -mp 18 jun 1998 cleaned up code
* -hm FreeBSD PnP
* -mp 17 dec 1998 made it compile again
*
*---------------------------------------------------------------------------*/
/* NOTES:
This driver was written for the Dynalink IS64PH ISDN TA, based on two
Siemens chips (HSCX 21525 and ISAC 2186). It is sold in the Netherlands.
model numbers found on (my) card:
IS64PH, TAS100H-N, P/N:89590555, TA200S100045521
chips:
Siemens PSB 21525N, HSCX TE V2.1
Siemens PSB 2186N, ISAC-S TE V1.1
95MS14, PNP
plug-and-play info:
device id "ASU1688"
vendor id 0x88167506
serial 0x00000044
i/o port 4 byte alignment, 4 bytes requested,
10 bit i/o decoding, 0x100-0x3f8 (?)
irq 3,4,5,9,10,11,12,15, high true, edge sensitive
At the moment I'm writing this Dynalink is replacing this card with
one based on a single Siemens chip (IPAC). It will apparently be sold
under the same model name.
This driver might also work for Asuscom cards.
*/
#ifdef __FreeBSD__
#include "isic.h"
#include "opt_i4b.h"
#include "pnp.h"
#else
#define NISIC 1
#define NPNP 1
#endif
#if (NISIC > 0) && (NPNP > 0) && defined(DYNALINK)
/* HEADERS
*/
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/systm.h>
#include <sys/mbuf.h>
#include <sys/socket.h>
#include <net/if.h>
#ifdef __FreeBSD__
#if __FreeBSD__ >= 3
#include <sys/ioccom.h>
#else
#include <sys/ioctl.h>
#endif
#include <machine/clock.h>
#include <i386/isa/isa_device.h>
#include <i386/isa/pnp.h>
#else
#include <machine/bus.h>
#include <sys/device.h>
#endif
#ifdef __FreeBSD__
#include <machine/i4b_debug.h>
#include <machine/i4b_ioctl.h>
#else
#include <i4b/i4b_debug.h>
#include <i4b/i4b_ioctl.h>
#endif
#include <i4b/include/i4b_global.h>
#include <i4b/include/i4b_l1l2.h>
#include <i4b/include/i4b_mbuf.h>
#include <i4b/layer1/i4b_l1.h>
#include <i4b/layer1/i4b_isac.h>
#include <i4b/layer1/i4b_hscx.h>
#ifdef __FreeBSD__
static void dynalink_read_fifo(void *buf, const void *base, size_t len);
static void dynalink_write_fifo(void *base, const void *buf, size_t len);
static void dynalink_write_reg(u_char *base, u_int offset, u_int v);
static u_char dynalink_read_reg(u_char *base, u_int offset);
extern struct isa_driver isicdriver;
#else
static void dynalink_read_fifo(struct isic_softc *sc, int what, void *buf, size_t size);
static void dynalink_write_fifo(struct isic_softc *sc, int what, const void *buf, size_t size);
static void dynalink_write_reg(struct isic_softc *sc, int what, bus_size_t offs, u_int8_t data);
static u_int8_t dynalink_read_reg(struct isic_softc *sc, int what, bus_size_t offs);
void isic_attach_Dyn(struct isic_softc *sc);
#endif
/* io address mapping */
#define ISAC 0
#define HSCX 1
#define ADDR 2
/* ADDR bits */
#define ADDRMASK 0x7F
#define RESET 0x80
/* HSCX register offsets */
#define HSCXA 0x00
#define HSCXB 0x40
#ifdef __FreeBSD__
/* base address juggling */
#define HSCXB_HACK 0x400
#define IOBASE(addr) (((int)addr)&0x3FC)
#define IOADDR(addr) (((int)addr)&0x3FF)
#define IS_HSCXB_HACK(addr) ((((int)addr)&HSCXB_HACK)?HSCXB:HSCXA)
/* ISIC probe and attach
*/
int
isic_probe_Dyn(struct isa_device *dev, unsigned int iobase2)
{
struct isic_softc *sc = &isic_sc[dev->id_unit];
if(dev->id_unit >= ISIC_MAXUNIT)
{
printf("isic%d: Error, unit %d >= ISIC_MAXUNIT for Dynalink IS64PH.\n",
dev->id_unit, dev->id_unit);
return(0);
}
sc->sc_unit = dev->id_unit;
/* check IRQ validity */
switch(ffs(dev->id_irq) - 1)
{
case 3:
case 4:
case 5:
case 9:
case 10:
case 11:
case 12:
case 15:
break;
default:
printf("isic%d: Error, invalid IRQ [%d] specified for Dynalink IS64PH.\n",
dev->id_unit, ffs(dev->id_irq)-1);
return(0);
break;
}
sc->sc_irq = dev->id_irq;
/* check if memory addr specified */
if(dev->id_maddr)
{
printf("isic%d: Error, mem addr 0x%lx specified for Dynalink IS64PH.\n",
dev->id_unit, (u_long)dev->id_maddr);
return (0);
}
dev->id_msize = 0;
/* check if we got an iobase */
if ( (dev->id_iobase < 0x100) ||
(dev->id_iobase > 0x3f8) ||
(dev->id_iobase & 3) )
{
printf("isic%d: Error, invalid iobase 0x%x specified for Dynalink!\n", dev->id_unit, dev->id_iobase);
return(0);
}
sc->sc_port = dev->id_iobase;
/* setup access routines */
sc->clearirq = NULL;
sc->readreg = dynalink_read_reg;
sc->writereg = dynalink_write_reg;
sc->readfifo = dynalink_read_fifo;
sc->writefifo = dynalink_write_fifo;
/* setup card type */
sc->sc_cardtyp = CARD_TYPEP_DYNALINK;
/* setup IOM bus type */
sc->sc_bustyp = BUS_TYPE_IOM2;
sc->sc_ipac = 0;
sc->sc_bfifolen = HSCX_FIFO_LEN;
/* setup ISAC and HSCX base addr */
ISAC_BASE = (caddr_t) sc->sc_port;
HSCX_A_BASE = (caddr_t) sc->sc_port + 1;
HSCX_B_BASE = (caddr_t) sc->sc_port + 1 + HSCXB_HACK;
/* Read HSCX A/B VSTR. Expected value is 0x05 (V2.1). */
if( ((HSCX_READ(0, H_VSTR) & 0xf) != 0x5) ||
((HSCX_READ(1, H_VSTR) & 0xf) != 0x5) )
{
printf("isic%d: HSCX VSTR test failed for Dynalink\n",
dev->id_unit);
printf("isic%d: HSC0: VSTR: %#x\n",
dev->id_unit, HSCX_READ(0, H_VSTR));
printf("isic%d: HSC1: VSTR: %#x\n",
dev->id_unit, HSCX_READ(1, H_VSTR));
return (0);
}
return (1);
}
int
isic_attach_Dyn(struct isa_device *dev, unsigned int iobase2)
{
outb((dev->id_iobase)+ADDR, RESET);
DELAY(SEC_DELAY / 10);
outb((dev->id_iobase)+ADDR, 0);
DELAY(SEC_DELAY / 10);
return(1);
}
#else
void isic_attach_Dyn(struct isic_softc *sc)
{
/* setup access routines */
sc->clearirq = NULL;
sc->readreg = dynalink_read_reg;
sc->writereg = dynalink_write_reg;
sc->readfifo = dynalink_read_fifo;
sc->writefifo = dynalink_write_fifo;
/* setup card type */
sc->sc_cardtyp = CARD_TYPEP_DYNALINK;
/* setup IOM bus type */
sc->sc_bustyp = BUS_TYPE_IOM2;
sc->sc_ipac = 0;
sc->sc_bfifolen = HSCX_FIFO_LEN;
/* Read HSCX A/B VSTR. Expected value is 0x05 (V2.1). */
if( ((HSCX_READ(0, H_VSTR) & 0xf) != 0x5) || ((HSCX_READ(1, H_VSTR) & 0xf) != 0x5) )
{
printf("%s: HSCX VSTR test failed for Dynalink PnP\n",
sc->sc_dev.dv_xname);
printf("%s: HSC0: VSTR: %#x\n",
sc->sc_dev.dv_xname, HSCX_READ(0, H_VSTR));
printf("%s: HSC1: VSTR: %#x\n",
sc->sc_dev.dv_xname, HSCX_READ(1, H_VSTR));
return;
}
bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, ADDR, RESET);
DELAY(SEC_DELAY / 10);
bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, ADDR, 0);
DELAY(SEC_DELAY / 10);
}
#endif /* ISIC>0 && NPNP>0 && defined(DYNALINK) */
/* LOW-LEVEL DEVICE ACCESS
NOTE: The isdn4bsd code expects the two HSCX channels at different
base addresses. I'm faking this, and remap them to the same address
in the low-level routines. Search for HSCXB_HACK and IS_HSCXB_HACK.
REM: this is only true for the FreeBSD version of I4B!
*/
#ifdef __FreeBSD__
static void
dynalink_read_fifo(void *buf, const void *base, size_t len)
{
outb(IOBASE(base)+ADDR, 0+IS_HSCXB_HACK(base));
insb(IOADDR(base), (u_char *)buf, (u_int)len);
}
#else
static void
dynalink_read_fifo(struct isic_softc *sc, int what, void *buf, size_t size)
{
bus_space_tag_t t = sc->sc_maps[0].t;
bus_space_handle_t h = sc->sc_maps[0].h;
switch (what) {
case ISIC_WHAT_ISAC:
bus_space_write_1(t, h, ADDR, 0);
bus_space_read_multi_1(t, h, ISAC, buf, size);
break;
case ISIC_WHAT_HSCXA:
bus_space_write_1(t, h, ADDR, HSCXA);
bus_space_read_multi_1(t, h, HSCX, buf, size);
break;
case ISIC_WHAT_HSCXB:
bus_space_write_1(t, h, ADDR, HSCXB);
bus_space_read_multi_1(t, h, HSCX, buf, size);
break;
}
}
#endif
#ifdef __FreeBSD__
static void
dynalink_write_fifo(void *base, const void *buf, size_t len)
{
outb(IOBASE(base)+ADDR, 0+IS_HSCXB_HACK(base));
outsb(IOADDR(base), (u_char *)buf, (u_int)len);
}
#else
static void dynalink_write_fifo(struct isic_softc *sc, int what, const void *buf, size_t size)
{
bus_space_tag_t t = sc->sc_maps[0].t;
bus_space_handle_t h = sc->sc_maps[0].h;
switch (what) {
case ISIC_WHAT_ISAC:
bus_space_write_1(t, h, ADDR, 0);
bus_space_write_multi_1(t, h, ISAC, (u_int8_t*)buf, size);
break;
case ISIC_WHAT_HSCXA:
bus_space_write_1(t, h, ADDR, HSCXA);
bus_space_write_multi_1(t, h, HSCX, (u_int8_t*)buf, size);
break;
case ISIC_WHAT_HSCXB:
bus_space_write_1(t, h, ADDR, HSCXB);
bus_space_write_multi_1(t, h, HSCX, (u_int8_t*)buf, size);
break;
}
}
#endif
#ifdef __FreeBSD__
static void
dynalink_write_reg(u_char *base, u_int offset, u_int v)
{
outb(IOBASE(base)+ADDR, (offset+IS_HSCXB_HACK(base))&ADDRMASK);
outb(IOADDR(base), (u_char)v);
}
#else
static void dynalink_write_reg(struct isic_softc *sc, int what, bus_size_t offs, u_int8_t data)
{
bus_space_tag_t t = sc->sc_maps[0].t;
bus_space_handle_t h = sc->sc_maps[0].h;
switch (what) {
case ISIC_WHAT_ISAC:
bus_space_write_1(t, h, ADDR, offs);
bus_space_write_1(t, h, ISAC, data);
break;
case ISIC_WHAT_HSCXA:
bus_space_write_1(t, h, ADDR, HSCXA+offs);
bus_space_write_1(t, h, HSCX, data);
break;
case ISIC_WHAT_HSCXB:
bus_space_write_1(t, h, ADDR, HSCXB+offs);
bus_space_write_1(t, h, HSCX, data);
break;
}
}
#endif
#ifdef __FreeBSD__
static u_char
dynalink_read_reg(u_char *base, u_int offset)
{
outb(IOBASE(base)+ADDR, (offset+IS_HSCXB_HACK(base))&ADDRMASK);
return (inb(IOADDR(base)));
}
#else
static u_int8_t dynalink_read_reg(struct isic_softc *sc, int what, bus_size_t offs)
{
bus_space_tag_t t = sc->sc_maps[0].t;
bus_space_handle_t h = sc->sc_maps[0].h;
switch (what) {
case ISIC_WHAT_ISAC:
bus_space_write_1(t, h, ADDR, offs);
return bus_space_read_1(t, h, ISAC);
case ISIC_WHAT_HSCXA:
bus_space_write_1(t, h, ADDR, HSCXA+offs);
return bus_space_read_1(t, h, HSCX);
case ISIC_WHAT_HSCXB:
bus_space_write_1(t, h, ADDR, HSCXB+offs);
return bus_space_read_1(t, h, HSCX);
}
return 0;
}
#endif
#endif /* (NISIC > 0) && (NPNP > 0) && defined(DYNALINK) */
|