1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
|
/*-
* Copyright (c) 2013 Cedric GROSS <cg@cgross.info>
* Copyright (c) 2011 Intel Corporation
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
*/
#ifndef __IF_IWN_CHIP_CFG_H__
#define __IF_IWN_CHIP_CFG_H__
/* ==========================================================================
* NIC PARAMETERS
*
* ==========================================================================
*/
/*
* Flags for managing calibration result. See calib_need
* in iwn_base_params struct
*
* These are bitmasks that determine which indexes in the calibcmd
* array are pushed up.
*/
#define IWN_FLG_NEED_PHY_CALIB_DC (1<<0)
#define IWN_FLG_NEED_PHY_CALIB_LO (1<<1)
#define IWN_FLG_NEED_PHY_CALIB_TX_IQ (1<<2)
#define IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC (1<<3)
#define IWN_FLG_NEED_PHY_CALIB_BASE_BAND (1<<4)
/*
* These aren't (yet) included in the calibcmd array, but
* are used as flags for which calibrations to use.
*
* XXX I think they should be named differently and
* stuffed in a different member in the config struct!
*/
#define IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET (1<<5)
#define IWN_FLG_NEED_PHY_CALIB_CRYSTAL (1<<6)
#define IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2 (1<<7)
/*
* Each chip has a different threshold for PLCP errors that should trigger a
* retune.
*/
#define IWN_PLCP_ERR_DEFAULT_THRESHOLD 50
#define IWN_PLCP_ERR_LONG_THRESHOLD 100
#define IWN_PLCP_ERR_EXT_LONG_THRESHOLD 200
/*
* Define some parameters for managing different NIC.
* Refer to linux specific file like iwl-xxxx.c to determine correct value
* for NIC.
*
* @max_ll_items: max number of OTP blocks
* @shadow_ram_support: shadow support for OTP memory
* @shadow_reg_enable: HW shadhow register bit
* @no_idle_support: do not support idle mode
* @advanced_bt_coexist : Advanced BT management
* @bt_session_2 : NIC need a new struct for configure BT coexistence. Needed
* only if advanced_bt_coexist is true
* @bt_sco_disable :
* @additional_nic_config: For 6005 series
* @iq_invert : ? But need it for N 2000 series
* @regulatory_bands : XXX
* @enhanced_TX_power : EEPROM Has advanced TX power options. Set 'True'
* if update_enhanced_txpower = iwl_eeprom_enhanced_txpower.
* See iwl-agn-devices.c file to determine that(enhanced_txpower)
* @need_temp_offset_calib : Need to compute some temp offset for calibration.
* @calib_need : Use IWN_FLG_NEED_PHY_CALIB_* flags to specify which
* calibration data ucode need. See calib_init_cfg in iwl-xxxx.c
* linux kernel file
* @support_hostap: Define IEEE80211_C_HOSTAP for ic_caps
* @no_multi_vaps: See iwn_vap_create
* @additional_gp_drv_bit : Specific bit to defined during nic_config
* @bt_mode: BT configuration mode
*/
enum bt_mode_enum {
IWN_BT_NONE,
IWN_BT_SIMPLE,
IWN_BT_ADVANCED
};
struct iwn_base_params {
uint32_t pll_cfg_val;
const uint16_t max_ll_items;
#define IWN_OTP_MAX_LL_ITEMS_1000 (3) /* OTP blocks for 1000 */
#define IWN_OTP_MAX_LL_ITEMS_6x00 (4) /* OTP blocks for 6x00 */
#define IWN_OTP_MAX_LL_ITEMS_6x50 (7) /* OTP blocks for 6x50 */
#define IWN_OTP_MAX_LL_ITEMS_2x00 (4) /* OTP blocks for 2x00 */
const bool shadow_ram_support;
const bool shadow_reg_enable;
const bool bt_session_2;
const bool bt_sco_disable;
const bool additional_nic_config;
const uint32_t *regulatory_bands;
const bool enhanced_TX_power;
const uint16_t calib_need;
const bool support_hostap;
const bool no_multi_vaps;
uint8_t additional_gp_drv_bit;
enum bt_mode_enum bt_mode;
uint32_t plcp_err_threshold;
};
static const struct iwn_base_params iwn5000_base_params = {
.pll_cfg_val = IWN_ANA_PLL_INIT, /* pll_cfg_val; */
.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00, /* max_ll_items */
.shadow_ram_support = false, /* shadow_ram_support */
.shadow_reg_enable = false, /* shadow_reg_enable */
.bt_session_2 = false, /* bt_session_2 */
.bt_sco_disable = true, /* bt_sco_disable */
.additional_nic_config = false, /* additional_nic_config */
.regulatory_bands = iwn5000_regulatory_bands, /* regulatory_bands */
.enhanced_TX_power = false, /* enhanced_TX_power */
.calib_need =
( IWN_FLG_NEED_PHY_CALIB_LO
| IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC
| IWN_FLG_NEED_PHY_CALIB_TX_IQ
| IWN_FLG_NEED_PHY_CALIB_BASE_BAND ),
.support_hostap = false, /* support_hostap */
.no_multi_vaps = true, /* no_multi_vaps */
.additional_gp_drv_bit = IWN_GP_DRIVER_NONE, /* additional_gp_drv_bit */
.bt_mode = IWN_BT_NONE, /* bt_mode */
.plcp_err_threshold = IWN_PLCP_ERR_LONG_THRESHOLD,
};
/*
* 4965 support
*/
static const struct iwn_base_params iwn4965_base_params = {
.pll_cfg_val = 0, /* pll_cfg_val; */
.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00, /* max_ll_items - ignored for 4965 */
.shadow_ram_support = true, /* shadow_ram_support */
.shadow_reg_enable = false, /* shadow_reg_enable */
.bt_session_2 = false, /* bt_session_2 XXX unknown? */
.bt_sco_disable = true, /* bt_sco_disable XXX unknown? */
.additional_nic_config = false, /* additional_nic_config - not for 4965 */
.regulatory_bands = iwn5000_regulatory_bands, /* regulatory_bands */
.enhanced_TX_power = false, /* enhanced_TX_power - not for 4965 */
.calib_need =
(IWN_FLG_NEED_PHY_CALIB_DC
| IWN_FLG_NEED_PHY_CALIB_LO
| IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC
| IWN_FLG_NEED_PHY_CALIB_TX_IQ
| IWN_FLG_NEED_PHY_CALIB_BASE_BAND ),
.support_hostap = false, /* support_hostap - XXX should work on fixing! */
.no_multi_vaps = true, /* no_multi_vaps - XXX should work on fixing! */
.additional_gp_drv_bit = IWN_GP_DRIVER_NONE, /* additional_gp_drv_bit */
.bt_mode = IWN_BT_SIMPLE, /* bt_mode */
.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
};
static const struct iwn_base_params iwn2000_base_params = {
.pll_cfg_val = 0,
.max_ll_items = IWN_OTP_MAX_LL_ITEMS_2x00,
.shadow_ram_support = true,
.shadow_reg_enable = false,
.bt_session_2 = false,
.bt_sco_disable = true,
.additional_nic_config = false,
.regulatory_bands = iwn2030_regulatory_bands,
.enhanced_TX_power = true,
.calib_need =
(IWN_FLG_NEED_PHY_CALIB_DC
| IWN_FLG_NEED_PHY_CALIB_LO
| IWN_FLG_NEED_PHY_CALIB_TX_IQ
| IWN_FLG_NEED_PHY_CALIB_BASE_BAND
| IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2 ),
.support_hostap = true,
.no_multi_vaps = false,
.additional_gp_drv_bit = IWN_GP_DRIVER_REG_BIT_RADIO_IQ_INVERT,
.bt_mode = IWN_BT_NONE,
.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
};
static const struct iwn_base_params iwn2030_base_params = {
.pll_cfg_val = 0,
.max_ll_items = IWN_OTP_MAX_LL_ITEMS_2x00,
.shadow_ram_support = true,
.shadow_reg_enable = false, /* XXX check? */
.bt_session_2 = true,
.bt_sco_disable = true,
.additional_nic_config = false,
.regulatory_bands = iwn2030_regulatory_bands,
.enhanced_TX_power = true,
.calib_need =
(IWN_FLG_NEED_PHY_CALIB_DC
| IWN_FLG_NEED_PHY_CALIB_LO
| IWN_FLG_NEED_PHY_CALIB_TX_IQ
| IWN_FLG_NEED_PHY_CALIB_BASE_BAND
| IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2 ),
.support_hostap = true,
.no_multi_vaps = false,
.additional_gp_drv_bit = IWN_GP_DRIVER_REG_BIT_RADIO_IQ_INVERT,
.bt_mode = IWN_BT_ADVANCED,
.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
};
static const struct iwn_base_params iwn1000_base_params = {
.pll_cfg_val = IWN_ANA_PLL_INIT,
.max_ll_items = IWN_OTP_MAX_LL_ITEMS_1000,
.shadow_ram_support = false,
.shadow_reg_enable = false, /* XXX check? */
.bt_session_2 = false,
.bt_sco_disable = false,
.additional_nic_config = false,
.regulatory_bands = iwn5000_regulatory_bands,
.enhanced_TX_power = false,
.calib_need =
( IWN_FLG_NEED_PHY_CALIB_LO
| IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC
| IWN_FLG_NEED_PHY_CALIB_TX_IQ
| IWN_FLG_NEED_PHY_CALIB_BASE_BAND
),
.support_hostap = false,
.no_multi_vaps = true,
.additional_gp_drv_bit = IWN_GP_DRIVER_NONE,
/* XXX 1000 - no BT */
.bt_mode = IWN_BT_SIMPLE,
.plcp_err_threshold = IWN_PLCP_ERR_EXT_LONG_THRESHOLD,
};
static const struct iwn_base_params iwn_6000_base_params = {
.pll_cfg_val = 0,
.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00,
.shadow_ram_support = true,
.shadow_reg_enable = true,
.bt_session_2 = false,
.bt_sco_disable = false,
.additional_nic_config = false,
.regulatory_bands = iwn6000_regulatory_bands,
.enhanced_TX_power = true,
.calib_need =
(IWN_FLG_NEED_PHY_CALIB_DC
| IWN_FLG_NEED_PHY_CALIB_LO
| IWN_FLG_NEED_PHY_CALIB_TX_IQ
| IWN_FLG_NEED_PHY_CALIB_BASE_BAND ),
.support_hostap = false,
.no_multi_vaps = true,
.additional_gp_drv_bit = IWN_GP_DRIVER_NONE,
.bt_mode = IWN_BT_SIMPLE,
.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
};
static const struct iwn_base_params iwn_6000i_base_params = {
.pll_cfg_val = 0,
.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00,
.shadow_ram_support = true,
.shadow_reg_enable = true,
.bt_session_2 = false,
.bt_sco_disable = true,
.additional_nic_config = false,
.regulatory_bands = iwn6000_regulatory_bands,
.enhanced_TX_power = true,
.calib_need =
(IWN_FLG_NEED_PHY_CALIB_DC
| IWN_FLG_NEED_PHY_CALIB_LO
| IWN_FLG_NEED_PHY_CALIB_TX_IQ
| IWN_FLG_NEED_PHY_CALIB_BASE_BAND ),
.support_hostap = false,
.no_multi_vaps = true,
.additional_gp_drv_bit = IWN_GP_DRIVER_NONE,
.bt_mode = IWN_BT_SIMPLE,
.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
};
static const struct iwn_base_params iwn_6000g2_base_params = {
.pll_cfg_val = 0,
.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00,
.shadow_ram_support = true,
.shadow_reg_enable = true,
.bt_session_2 = false,
.bt_sco_disable = true,
.additional_nic_config = false,
.regulatory_bands = iwn6000_regulatory_bands,
.enhanced_TX_power = true,
.calib_need =
(IWN_FLG_NEED_PHY_CALIB_DC
| IWN_FLG_NEED_PHY_CALIB_LO
| IWN_FLG_NEED_PHY_CALIB_TX_IQ
| IWN_FLG_NEED_PHY_CALIB_BASE_BAND
| IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET ),
.support_hostap = false,
.no_multi_vaps = true,
.additional_gp_drv_bit = 0,
.bt_mode = IWN_BT_SIMPLE,
.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
};
static const struct iwn_base_params iwn_6050_base_params = {
.pll_cfg_val = 0,
.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x50,
.shadow_ram_support = true,
.shadow_reg_enable = true,
.bt_session_2 = false,
.bt_sco_disable = true,
.additional_nic_config = true,
.regulatory_bands = iwn6000_regulatory_bands,
.enhanced_TX_power = true,
.calib_need =
(IWN_FLG_NEED_PHY_CALIB_LO
| IWN_FLG_NEED_PHY_CALIB_TX_IQ
| IWN_FLG_NEED_PHY_CALIB_BASE_BAND ),
.support_hostap = false,
.no_multi_vaps = true,
.additional_gp_drv_bit = IWN_GP_DRIVER_NONE,
.bt_mode = IWN_BT_SIMPLE,
.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
};
static const struct iwn_base_params iwn_6150_base_params = {
.pll_cfg_val = 0,
.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x50,
.shadow_ram_support = true,
.shadow_reg_enable = true,
.bt_session_2 = false,
.bt_sco_disable = true,
.additional_nic_config = true,
.regulatory_bands = iwn6000_regulatory_bands,
.enhanced_TX_power = true,
.calib_need =
(IWN_FLG_NEED_PHY_CALIB_LO
| IWN_FLG_NEED_PHY_CALIB_TX_IQ
| IWN_FLG_NEED_PHY_CALIB_BASE_BAND),
.support_hostap = false,
.no_multi_vaps = true,
.additional_gp_drv_bit = IWN_GP_DRIVER_6050_1X2,
.bt_mode = IWN_BT_SIMPLE,
.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
};
/* IWL_DEVICE_6035 & IWL_DEVICE_6030 */
static const struct iwn_base_params iwn_6000g2b_base_params = {
.pll_cfg_val = 0,
.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00,
.shadow_ram_support = true,
.shadow_reg_enable = true,
.bt_session_2 = false,
.bt_sco_disable = true,
.additional_nic_config = false,
.regulatory_bands = iwn6000_regulatory_bands,
.enhanced_TX_power = true,
.calib_need =
(IWN_FLG_NEED_PHY_CALIB_DC
| IWN_FLG_NEED_PHY_CALIB_LO
| IWN_FLG_NEED_PHY_CALIB_TX_IQ
| IWN_FLG_NEED_PHY_CALIB_BASE_BAND
| IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET ),
.support_hostap = false,
.no_multi_vaps = true,
.additional_gp_drv_bit = IWN_GP_DRIVER_NONE,
.bt_mode = IWN_BT_ADVANCED,
.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
};
/*
* 6235 series NICs.
*/
static const struct iwn_base_params iwn_6235_base_params = {
.pll_cfg_val = 0,
.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00,
.shadow_ram_support = true,
.shadow_reg_enable = true,
.bt_session_2 = false,
.bt_sco_disable = true,
.additional_nic_config = true,
.regulatory_bands = iwn6000_regulatory_bands,
.enhanced_TX_power = true,
.calib_need =
(IWN_FLG_NEED_PHY_CALIB_DC
| IWN_FLG_NEED_PHY_CALIB_LO
| IWN_FLG_NEED_PHY_CALIB_TX_IQ
| IWN_FLG_NEED_PHY_CALIB_BASE_BAND
| IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET ),
.support_hostap = false,
.no_multi_vaps = true,
/* XXX 1x2? This NIC is 2x2, right? */
.additional_gp_drv_bit = IWN_GP_DRIVER_6050_1X2,
.bt_mode = IWN_BT_ADVANCED,
.plcp_err_threshold = IWN_PLCP_ERR_DEFAULT_THRESHOLD,
};
static const struct iwn_base_params iwn_5x50_base_params = {
.pll_cfg_val = IWN_ANA_PLL_INIT,
.max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00,
.shadow_ram_support = true,
.shadow_reg_enable = false,
.bt_session_2 = false,
.bt_sco_disable = true,
.additional_nic_config = false,
.regulatory_bands = iwn5000_regulatory_bands,
.enhanced_TX_power =false,
.calib_need =
(IWN_FLG_NEED_PHY_CALIB_DC
| IWN_FLG_NEED_PHY_CALIB_LO
| IWN_FLG_NEED_PHY_CALIB_TX_IQ
| IWN_FLG_NEED_PHY_CALIB_BASE_BAND ),
.support_hostap = false,
.no_multi_vaps = true,
.additional_gp_drv_bit = IWN_GP_DRIVER_NONE,
.bt_mode = IWN_BT_SIMPLE,
.plcp_err_threshold = IWN_PLCP_ERR_LONG_THRESHOLD,
};
#endif /* __IF_IWN_CHIP_CFG_H__ */
|
