1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
|
/*-
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
* The full GNU General Public License is included in this distribution
* in the file called LICENSE.GPL.
*
* BSD LICENSE
*
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _SCIC_SDS_PCI_H_
#define _SCIC_SDS_PCI_H_
/**
* @file
*
* @brief This file contains the prototypes/macros utilized in writing
* out PCI data for the SCI core.
*/
#ifdef __cplusplus
extern "C" {
#endif // __cplusplus
#include <dev/isci/scil/sci_types.h>
#define PATSBURG_SMU_BAR 0
#define PATSBURG_SCU_BAR 1
#define PATSBURG_IO_SPACE_BAR0 2
#define PATSBURG_IO_SPACE_BAR1 3
#define SCIC_SDS_PCI_REVISION_A0 0
#define SCIC_SDS_PCI_REVISION_A2 2
#define SCIC_SDS_PCI_REVISION_B0 4
#define SCIC_SDS_PCI_REVISION_C0 5
#define SCIC_SDS_PCI_REVISION_C1 6
enum SCU_CONTROLLER_PCI_REVISION_CODE
{
SCU_PBG_HBA_REV_A0 = SCIC_SDS_PCI_REVISION_A0,
SCU_PBG_HBA_REV_A2 = SCIC_SDS_PCI_REVISION_A2,
SCU_PBG_HBA_REV_B0 = SCIC_SDS_PCI_REVISION_B0,
SCU_PBG_HBA_REV_C0 = SCIC_SDS_PCI_REVISION_C0,
SCU_PBG_HBA_REV_C1 = SCIC_SDS_PCI_REVISION_C1
};
struct SCIC_SDS_CONTROLLER;
void scic_sds_pci_bar_initialization(
struct SCIC_SDS_CONTROLLER * this_controller
);
#if !defined(ENABLE_PCI_IO_SPACE_ACCESS) || defined(ARLINGTON_BUILD)
#define scic_sds_pci_read_smu_dword scic_cb_pci_read_dword
#define scic_sds_pci_write_smu_dword scic_cb_pci_write_dword
#define scic_sds_pci_read_scu_dword scic_cb_pci_read_dword
#define scic_sds_pci_write_scu_dword scic_cb_pci_write_dword
#else // !defined(ENABLE_PCI_IO_SPACE_ACCESS)
// These two registers form the Data/Index pair equivalent in the
// SCU. They are only used for access registers in BAR 1, not BAR 0.
#define SCU_MMR_ADDRESS_WINDOW_OFFSET 0xA0
#define SCU_MMR_DATA_WINDOW_OFFSET 0xA4
U32 scic_sds_pci_read_smu_dword(
SCI_CONTROLLER_HANDLE_T controller,
void * address
);
void scic_sds_pci_write_smu_dword(
SCI_CONTROLLER_HANDLE_T controller,
void * address,
U32 write_value
);
U32 scic_sds_pci_read_scu_dword(
SCI_CONTROLLER_HANDLE_T controller,
void * address
);
void scic_sds_pci_write_scu_dword(
SCI_CONTROLLER_HANDLE_T controller,
void * address,
U32 write_value
);
#endif // !defined(ENABLE_PCI_IO_SPACE_ACCESS)
#ifdef __cplusplus
}
#endif // __cplusplus
#endif // _SCIC_SDS_PCI_H_
|
