1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
|
/*
* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
*/
#include "opt_ah.h"
#include "ah.h"
#include "ah_internal.h"
#include "ah_devid.h"
#ifdef AH_DEBUG
#include "ah_desc.h" /* NB: for HAL_PHYERR* */
#endif
#include "ar5212/ar5212.h"
#include "ar5212/ar5212reg.h"
#include "ar5212/ar5212phy.h"
#define AR_NUM_GPIO 6 /* 6 GPIO pins */
#define AR_GPIOD_MASK 0x0000002F /* GPIO data reg r/w mask */
/*
* Configure GPIO Output lines
*/
HAL_BOOL
ar5212GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)
{
HALASSERT(gpio < AR_NUM_GPIO);
/*
* NB: AR_GPIOCR_CR_A(pin) is all 1's so there's no need
* to clear the field before or'ing in the new value.
*/
OS_REG_WRITE(ah, AR_GPIOCR,
OS_REG_READ(ah, AR_GPIOCR) | AR_GPIOCR_CR_A(gpio));
return AH_TRUE;
}
/*
* Configure GPIO Input lines
*/
HAL_BOOL
ar5212GpioCfgInput(struct ath_hal *ah, uint32_t gpio)
{
HALASSERT(gpio < AR_NUM_GPIO);
OS_REG_WRITE(ah, AR_GPIOCR,
(OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_CR_A(gpio))
| AR_GPIOCR_CR_N(gpio));
return AH_TRUE;
}
/*
* Once configured for I/O - set output lines
*/
HAL_BOOL
ar5212GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)
{
uint32_t reg;
HALASSERT(gpio < AR_NUM_GPIO);
reg = OS_REG_READ(ah, AR_GPIODO);
reg &= ~(1 << gpio);
reg |= (val&1) << gpio;
OS_REG_WRITE(ah, AR_GPIODO, reg);
return AH_TRUE;
}
/*
* Once configured for I/O - get input lines
*/
uint32_t
ar5212GpioGet(struct ath_hal *ah, uint32_t gpio)
{
if (gpio < AR_NUM_GPIO) {
uint32_t val = OS_REG_READ(ah, AR_GPIODI);
val = ((val & AR_GPIOD_MASK) >> gpio) & 0x1;
return val;
} else {
return 0xffffffff;
}
}
/*
* Set the GPIO Interrupt
*/
void
ar5212GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)
{
uint32_t val;
/* XXX bounds check gpio */
val = OS_REG_READ(ah, AR_GPIOCR);
val &= ~(AR_GPIOCR_CR_A(gpio) |
AR_GPIOCR_INT_MASK | AR_GPIOCR_INT_ENA | AR_GPIOCR_INT_SEL);
val |= AR_GPIOCR_CR_N(gpio) | AR_GPIOCR_INT(gpio) | AR_GPIOCR_INT_ENA;
if (ilevel)
val |= AR_GPIOCR_INT_SELH; /* interrupt on pin high */
else
val |= AR_GPIOCR_INT_SELL; /* interrupt on pin low */
/* Don't need to change anything for low level interrupt. */
OS_REG_WRITE(ah, AR_GPIOCR, val);
/* Change the interrupt mask. */
(void) ar5212SetInterrupts(ah, AH5212(ah)->ah_maskReg | HAL_INT_GPIO);
}
|
