1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136
4137
4138
4139
4140
4141
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159
4160
4161
4162
4163
4164
4165
4166
4167
4168
4169
4170
4171
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193
4194
4195
4196
4197
4198
4199
4200
4201
4202
4203
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228
4229
4230
4231
4232
4233
4234
4235
4236
4237
4238
4239
4240
4241
4242
4243
4244
4245
4246
4247
4248
4249
4250
4251
4252
4253
4254
4255
4256
4257
4258
4259
4260
4261
4262
4263
4264
4265
4266
4267
4268
4269
4270
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282
4283
4284
4285
4286
4287
4288
4289
4290
4291
4292
4293
4294
4295
4296
4297
4298
4299
4300
4301
4302
4303
4304
4305
4306
4307
4308
4309
4310
4311
4312
4313
4314
4315
4316
4317
4318
4319
4320
4321
4322
4323
4324
4325
4326
4327
4328
4329
4330
4331
4332
4333
4334
4335
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
4346
4347
4348
4349
4350
4351
4352
4353
4354
4355
4356
4357
4358
4359
4360
4361
4362
4363
4364
4365
4366
4367
4368
4369
4370
4371
4372
|
/* $FreeBSD$ */
/*
* Copyright (c) 1996-2000 Distributed Processing Technology Corporation
* Copyright (c) 2000 Adaptec Corporation
* All rights reserved.
*
* TERMS AND CONDITIONS OF USE
*
* Redistribution and use in source form, with or without modification, are
* permitted provided that redistributions of source code must retain the
* above copyright notice, this list of conditions and the following disclaimer.
*
* This software is provided `as is' by Adaptec and any express or implied
* warranties, including, but not limited to, the implied warranties of
* merchantability and fitness for a particular purpose, are disclaimed. In no
* event shall Adaptec be liable for any direct, indirect, incidental, special,
* exemplary or consequential damages (including, but not limited to,
* procurement of substitute goods or services; loss of use, data, or profits;
* or business interruptions) however caused and on any theory of liability,
* whether in contract, strict liability, or tort (including negligence or
* otherwise) arising in any way out of the use of this driver software, even
* if advised of the possibility of such damage.
*
* SCSI I2O host adapter driver
*
* V1.03 2000/07/12 Mark_Salyzyn@adaptec.com
* - The controller is not actually an ASR (Adaptec SCSI RAID)
* series that is visible, it's more of an internal code name.
* remove any visible references within reason for now.
* - bus_ptr->LUN was not correctly zeroed when initially
* allocated causing a possible panic of the operating system
* during boot.
* V1.02 2000/06/26 Mark_Salyzyn@adaptec.com
* - Code always fails for ASR_getTid affecting performance.
* - initiated a set of changes that resulted from a formal
* code inspection by Mark_Salyzyn@adaptec.com,
* George_Dake@adaptec.com, Jeff_Zeak@adaptec.com,
* Martin_Wilson@adaptec.com and Vincent_Trandoan@adaptec.com.
* Their findings were focussed on the LCT & TID handler, and
* all resulting changes were to improve code readability,
* consistency or have a positive effect on performance.
* V1.01 2000/06/14 Mark_Salyzyn@adaptec.com
* - Passthrough returned an incorrect error.
* - Passthrough did not migrate the intrinsic scsi layer wakeup
* on command completion.
* - generate control device nodes using make_dev and delete_dev.
* - Performance affected by TID caching reallocing.
* - Made suggested changes by Justin_Gibbs@adaptec.com
* - use splcam instead of splbio.
* - use cam_imask instead of bio_imask.
* - use u_int8_t instead of u_char.
* - use u_int16_t instead of u_short.
* - use u_int32_t instead of u_long where appropriate.
* - use 64 bit context handler instead of 32 bit.
* - create_ccb should only allocate the worst case
* requirements for the driver since CAM may evolve
* making union ccb much larger than needed here.
* renamed create_ccb to asr_alloc_ccb.
* - go nutz justifying all debug prints as macros
* defined at the top and remove unsightly ifdefs.
* - INLINE STATIC viewed as confusing. Historically
* utilized to affect code performance and debug
* issues in OS, Compiler or OEM specific situations.
* V1.00 2000/05/31 Mark_Salyzyn@adaptec.com
* - Ported from FreeBSD 2.2.X DPT I2O driver.
* changed struct scsi_xfer to union ccb/struct ccb_hdr
* changed variable name xs to ccb
* changed struct scsi_link to struct cam_path
* changed struct scsibus_data to struct cam_sim
* stopped using fordriver for holding on to the TID
* use proprietary packet creation instead of scsi_inquire
* CAM layer sends synchronize commands.
*/
#define ASR_VERSION 1
#define ASR_REVISION '0'
#define ASR_SUBREVISION '3'
#define ASR_MONTH 7
#define ASR_DAY 12
#define ASR_YEAR 2000 - 1980
/*
* Debug macros to resude the unsightly ifdefs
*/
#if (defined(DEBUG_ASR) || defined(DEBUG_ASR_USR_CMD) || defined(DEBUG_ASR_CMD))
# define debug_asr_message(message) \
{ \
u_int32_t * pointer = (u_int32_t *)message; \
u_int32_t length = I2O_MESSAGE_FRAME_getMessageSize(message);\
u_int32_t counter = 0; \
\
while (length--) { \
printf ("%08lx%c", (u_long)*(pointer++), \
(((++counter & 7) == 0) || (length == 0)) \
? '\n' \
: ' '); \
} \
}
#endif /* DEBUG_ASR || DEBUG_ASR_USR_CMD || DEBUG_ASR_CMD */
#if (defined(DEBUG_ASR))
/* Breaks on none STDC based compilers :-( */
# define debug_asr_printf(fmt,args...) printf(fmt, ##args)
# define debug_asr_dump_message(message) debug_asr_message(message)
# define debug_asr_print_path(ccb) xpt_print_path(ccb->ccb_h.path);
/* None fatal version of the ASSERT macro */
# if (defined(__STDC__))
# define ASSERT(phrase) if(!(phrase))printf(#phrase " at line %d file %s\n",__LINE__,__FILE__)
# else
# define ASSERT(phrase) if(!(phrase))printf("phrase" " at line %d file %s\n",__LINE__,__FILE__)
# endif
#else /* DEBUG_ASR */
# define debug_asr_printf(fmt,args...)
# define debug_asr_dump_message(message)
# define debug_asr_print_path(ccb)
# define ASSERT(x)
#endif /* DEBUG_ASR */
/*
* If DEBUG_ASR_CMD is defined:
* 0 - Display incoming SCSI commands
* 1 - add in a quick character before queueing.
* 2 - add in outgoing message frames.
*/
#if (defined(DEBUG_ASR_CMD))
# define debug_asr_cmd_printf(fmt,args...) printf(fmt,##args)
# define debug_asr_dump_ccb(ccb) \
{ \
u_int8_t * cp = (unsigned char *)&(ccb->csio.cdb_io); \
int len = ccb->csio.cdb_len; \
\
while (len) { \
debug_asr_cmd_printf (" %02x", *(cp++)); \
--len; \
} \
}
# if (DEBUG_ASR_CMD > 0)
# define debug_asr_cmd1_printf debug_asr_cmd_printf
# else
# define debug_asr_cmd1_printf(fmt,args...)
# endif
# if (DEBUG_ASR_CMD > 1)
# define debug_asr_cmd2_printf debug_asr_cmd_printf
# define debug_asr_cmd2_dump_message(message) debug_asr_message(message)
# else
# define debug_asr_cmd2_printf(fmt,args...)
# define debug_asr_cmd2_dump_message(message)
# endif
#else /* DEBUG_ASR_CMD */
# define debug_asr_cmd_printf(fmt,args...)
# define debug_asr_cmd_dump_ccb(ccb)
# define debug_asr_cmd1_printf(fmt,args...)
# define debug_asr_cmd2_printf(fmt,args...)
# define debug_asr_cmd2_dump_message(message)
#endif /* DEBUG_ASR_CMD */
#if (defined(DEBUG_ASR_USR_CMD))
# define debug_usr_cmd_printf(fmt,args...) printf(fmt,##args)
# define debug_usr_cmd_dump_message(message) debug_usr_message(message)
#else /* DEBUG_ASR_USR_CMD */
# define debug_usr_cmd_printf(fmt,args...)
# define debug_usr_cmd_dump_message(message)
#endif /* DEBUG_ASR_USR_CMD */
#define dsDescription_size 46 /* Snug as a bug in a rug */
#include "dev/asr/dptsig.h"
static dpt_sig_S ASR_sig = {
{ 'd', 'P', 't', 'S', 'i', 'G'}, SIG_VERSION, PROC_INTEL,
PROC_386 | PROC_486 | PROC_PENTIUM | PROC_SEXIUM, FT_HBADRVR, 0,
OEM_DPT, OS_FREE_BSD, CAP_ABOVE16MB, DEV_ALL,
ADF_ALL_SC5,
0, 0, ASR_VERSION, ASR_REVISION, ASR_SUBREVISION,
ASR_MONTH, ASR_DAY, ASR_YEAR,
/* 01234567890123456789012345678901234567890123456789 < 50 chars */
"Adaptec FreeBSD 4.0.0 Unix SCSI I2O HBA Driver"
/* ^^^^^ asr_attach alters these to match OS */
};
#include <sys/param.h> /* TRUE=1 and FALSE=0 defined here */
#include <sys/kernel.h>
#include <sys/systm.h>
#include <sys/malloc.h>
#include <sys/conf.h>
#include <sys/disklabel.h>
#include <sys/bus.h>
#include <machine/resource.h>
#include <machine/bus.h>
#include <sys/rman.h>
#include <sys/stat.h>
#include <cam/cam.h>
#include <cam/cam_ccb.h>
#include <cam/cam_sim.h>
#include <cam/cam_xpt_sim.h>
#include <cam/cam_xpt_periph.h>
#include <cam/scsi/scsi_all.h>
#include <cam/scsi/scsi_message.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <machine/cputypes.h>
#include <i386/include/vmparam.h>
#include <pci/pcivar.h>
#include <pci/pcireg.h>
#define STATIC static
#define INLINE
#if (defined(DEBUG_ASR) && (DEBUG_ASR > 0))
# undef STATIC
# define STATIC
# undef INLINE
# define INLINE
#endif
#define IN
#define OUT
#define INOUT
#define osdSwap4(x) ((u_long)ntohl((u_long)(x)))
#define KVTOPHYS(x) vtophys(x)
#include "dev/asr/dptalign.h"
#include "dev/asr/i2oexec.h"
#include "dev/asr/i2obscsi.h"
#include "dev/asr/i2odpt.h"
#include "dev/asr/i2oadptr.h"
#include "opt_asr.h"
#include "dev/asr/sys_info.h"
/* Configuration Definitions */
#define SG_SIZE 58 /* Scatter Gather list Size */
#define MAX_TARGET_ID 126 /* Maximum Target ID supported */
#define MAX_LUN 255 /* Maximum LUN Supported */
#define MAX_CHANNEL 7 /* Maximum Channel # Supported by driver */
#define MAX_INBOUND 2000 /* Max CCBs, Also Max Queue Size */
#define MAX_OUTBOUND 256 /* Maximum outbound frames/adapter */
#define MAX_INBOUND_SIZE 512 /* Maximum inbound frame size */
#define MAX_MAP 4194304L /* Maximum mapping size of IOP */
/**************************************************************************
** ASR Host Adapter structure - One Structure For Each Host Adapter That **
** Is Configured Into The System. The Structure Supplies Configuration **
** Information, Status Info, Queue Info And An Active CCB List Pointer. **
***************************************************************************/
/* I2O register set */
typedef struct {
U8 Address[0x30];
volatile U32 Status;
volatile U32 Mask;
# define Mask_InterruptsDisabled 0x08
U32 x[2];
volatile U32 ToFIFO; /* In Bound FIFO */
volatile U32 FromFIFO; /* Out Bound FIFO */
} i2oRegs_t;
/*
* A MIX of performance and space considerations for TID lookups
*/
typedef u_int16_t tid_t;
typedef struct {
u_int32_t size; /* up to MAX_LUN */
tid_t TID[1];
} lun2tid_t;
typedef struct {
u_int32_t size; /* up to MAX_TARGET */
lun2tid_t * LUN[1];
} target2lun_t;
/*
* To ensure that we only allocate and use the worst case ccb here, lets
* make our own local ccb union. If asr_alloc_ccb is utilized for another
* ccb type, ensure that you add the additional structures into our local
* ccb union. To ensure strict type checking, we will utilize the local
* ccb definition wherever possible.
*/
union asr_ccb {
struct ccb_hdr ccb_h; /* For convenience */
struct ccb_scsiio csio;
struct ccb_setasync csa;
};
typedef struct Asr_softc {
u_int16_t ha_irq;
void * ha_Base; /* base port for each board */
u_int8_t * volatile ha_blinkLED;
i2oRegs_t * ha_Virt; /* Base address of adapter */
I2O_IOP_ENTRY ha_SystemTable;
LIST_HEAD(,ccb_hdr) ha_ccb; /* ccbs in use */
struct cam_path * ha_path[MAX_CHANNEL+1];
struct cam_sim * ha_sim[MAX_CHANNEL+1];
#if __FreeBSD_version >= 400000
struct resource * ha_mem_res;
struct resource * ha_irq_res;
void * ha_intr;
#endif
u_int8_t ha_adapter_target[MAX_CHANNEL+1];
PI2O_LCT ha_LCT; /* Complete list of devices */
# define le_type IdentityTag[0]
# define I2O_BSA 0x20
# define I2O_FCA 0x40
# define I2O_SCSI 0x00
# define I2O_PORT 0x80
# define I2O_UNKNOWN 0x7F
# define le_bus IdentityTag[1]
# define le_target IdentityTag[2]
# define le_lun IdentityTag[3]
target2lun_t * ha_targets[MAX_CHANNEL+1];
PI2O_SCSI_ERROR_REPLY_MESSAGE_FRAME ha_Msgs;
u_long ha_Msgs_Phys;
u_int16_t ha_Msgs_Count;
/* Configuration information */
/* The target id maximums we take */
u_int8_t ha_MaxBus; /* Maximum bus */
u_int8_t ha_MaxId; /* Maximum target ID */
u_int8_t ha_MaxLun; /* Maximum target LUN */
u_int8_t ha_SgSize; /* Max SG elements */
u_int8_t ha_pciBusNum;
u_int8_t ha_pciDeviceNum;
u_int16_t ha_QueueSize; /* Max outstanding commands */
/* Links into other parents and HBAs */
struct Asr_softc * ha_next; /* HBA list */
#ifdef ASR_MEASURE_PERFORMANCE
#define MAX_TIMEQ_SIZE 256 // assumes MAX 256 scsi commands sent
asr_perf_t ha_performance;
u_int32_t ha_submitted_ccbs_count;
// Queueing macros for a circular queue
#define TIMEQ_FREE_LIST_EMPTY(head, tail) (-1 == (head) && -1 == (tail))
#define TIMEQ_FREE_LIST_FULL(head, tail) ((((tail) + 1) % MAX_TIMEQ_SIZE) == (head))
#define ENQ_TIMEQ_FREE_LIST(item, Q, head, tail) \
if (!TIMEQ_FREE_LIST_FULL((head), (tail))) { \
if TIMEQ_FREE_LIST_EMPTY((head),(tail)) { \
(head) = (tail) = 0; \
} \
else (tail) = ((tail) + 1) % MAX_TIMEQ_SIZE; \
Q[(tail)] = (item); \
} \
else { \
debug_asr_printf("asr: Enqueueing when TimeQ Free List is full... This should not happen!\n"); \
}
#define DEQ_TIMEQ_FREE_LIST(item, Q, head, tail) \
if (!TIMEQ_FREE_LIST_EMPTY((head), (tail))) { \
item = Q[(head)]; \
if ((head) == (tail)) { (head) = (tail) = -1; } \
else (head) = ((head) + 1) % MAX_TIMEQ_SIZE; \
} \
else { \
(item) = -1; \
debug_asr_printf("asr: Dequeueing when TimeQ Free List is empty... This should not happen!\n"); \
}
// Circular queue of time stamps
struct timeval ha_timeQ[MAX_TIMEQ_SIZE];
u_int32_t ha_timeQFreeList[MAX_TIMEQ_SIZE];
int ha_timeQFreeHead;
int ha_timeQFreeTail;
#endif
} Asr_softc_t;
STATIC Asr_softc_t * Asr_softc;
/*
* Prototypes of the routines we have in this object.
*/
/* Externally callable routines */
#if __FreeBSD_version >= 400000
#define PROBE_ARGS IN device_t tag
#define PROBE_RET int
#define PROBE_SET() u_long id = (pci_get_device(tag)<<16)|pci_get_vendor(tag)
#define PROBE_RETURN(retval) if(retval){device_set_desc(tag,retval);return(0);}else{return(ENXIO);}
#define ATTACH_ARGS IN device_t tag
#define ATTACH_RET int
#define ATTACH_SET() int unit = device_get_unit(tag)
#define ATTACH_RETURN(retval) return(retval)
#else
#define PROBE_ARGS IN pcici_t tag, IN pcidi_t id
#define PROBE_RET const char *
#define PROBE_SET()
#define PROBE_RETURN(retval) return(retval)
#define ATTACH_ARGS IN pcici_t tag, IN int unit
#define ATTACH_RET void
#define ATTACH_SET()
#define ATTACH_RETURN(retval) return
#endif
/* I2O HDM interface */
STATIC PROBE_RET asr_probe __P((PROBE_ARGS));
STATIC ATTACH_RET asr_attach __P((ATTACH_ARGS));
/* DOMINO placeholder */
STATIC PROBE_RET domino_probe __P((PROBE_ARGS));
STATIC ATTACH_RET domino_attach __P((ATTACH_ARGS));
/* MODE0 adapter placeholder */
STATIC PROBE_RET mode0_probe __P((PROBE_ARGS));
STATIC ATTACH_RET mode0_attach __P((ATTACH_ARGS));
STATIC Asr_softc_t * ASR_get_sc __P((
IN dev_t dev));
STATIC int asr_ioctl __P((
IN dev_t dev,
IN u_long cmd,
INOUT caddr_t data,
int flag,
struct proc * proc));
STATIC int asr_open __P((
IN dev_t dev,
int32_t flags,
int32_t ifmt,
IN struct proc * proc));
STATIC int asr_close __P((
dev_t dev,
int flags,
int ifmt,
struct proc * proc));
STATIC int asr_intr __P((
IN Asr_softc_t * sc));
STATIC void asr_timeout __P((
INOUT void * arg));
STATIC int ASR_init __P((
IN Asr_softc_t * sc));
STATIC INLINE int ASR_acquireLct __P((
INOUT Asr_softc_t * sc));
STATIC INLINE int ASR_acquireHrt __P((
INOUT Asr_softc_t * sc));
STATIC void asr_action __P((
IN struct cam_sim * sim,
IN union ccb * ccb));
STATIC void asr_async __P((
void * callback_arg,
u_int32_t code,
struct cam_path * path,
void * arg));
STATIC void asr_poll __P((
IN struct cam_sim * sim));
/*
* Here is the auto-probe structure used to nest our tests appropriately
* during the startup phase of the operating system.
*/
#if __FreeBSD_version >= 400000
STATIC device_method_t asr_methods[] = {
DEVMETHOD(device_probe, asr_probe),
DEVMETHOD(device_attach, asr_attach),
{ 0, 0 }
};
STATIC driver_t asr_driver = {
"asr",
asr_methods,
sizeof(Asr_softc_t)
};
STATIC devclass_t asr_devclass;
DRIVER_MODULE(asr, pci, asr_driver, asr_devclass, 0, 0);
STATIC device_method_t domino_methods[] = {
DEVMETHOD(device_probe, domino_probe),
DEVMETHOD(device_attach, domino_attach),
{ 0, 0 }
};
STATIC driver_t domino_driver = {
"domino",
domino_methods,
0
};
STATIC devclass_t domino_devclass;
DRIVER_MODULE(domino, pci, domino_driver, domino_devclass, 0, 0);
STATIC device_method_t mode0_methods[] = {
DEVMETHOD(device_probe, mode0_probe),
DEVMETHOD(device_attach, mode0_attach),
{ 0, 0 }
};
STATIC driver_t mode0_driver = {
"mode0",
mode0_methods,
0
};
STATIC devclass_t mode0_devclass;
DRIVER_MODULE(mode0, pci, mode0_driver, mode0_devclass, 0, 0);
#else
STATIC u_long asr_pcicount = 0;
STATIC struct pci_device asr_pcidev = {
"asr",
asr_probe,
asr_attach,
&asr_pcicount,
NULL
};
DATA_SET (asr_pciset, asr_pcidev);
STATIC u_long domino_pcicount = 0;
STATIC struct pci_device domino_pcidev = {
"domino",
domino_probe,
domino_attach,
&domino_pcicount,
NULL
};
DATA_SET (domino_pciset, domino_pcidev);
STATIC u_long mode0_pcicount = 0;
STATIC struct pci_device mode0_pcidev = {
"mode0",
mode0_probe,
mode0_attach,
&mode0_pcicount,
NULL
};
DATA_SET (mode0_pciset, mode0_pcidev);
#endif
/*
* devsw for asr hba driver
*
* only ioctl is used. the sd driver provides all other access.
*/
#define CDEV_MAJOR 154 /* prefered default character major */
STATIC struct cdevsw asr_cdevsw = {
asr_open, /* open */
asr_close, /* close */
noread, /* read */
nowrite, /* write */
asr_ioctl, /* ioctl */
nopoll, /* poll */
nommap, /* mmap */
nostrategy, /* strategy */
"asr", /* name */
CDEV_MAJOR, /* maj */
nodump, /* dump */
nopsize, /* psize */
0, /* flags */
-1 /* bmaj */
};
#ifdef ASR_MEASURE_PERFORMANCE
STATIC u_int32_t asr_time_delta __P((IN struct timeval start,
IN struct timeval end));
#endif
/*
* Initialize the dynamic cdevsw hooks.
*/
STATIC void
asr_drvinit (
void * unused)
{
static int asr_devsw_installed = 0;
if (asr_devsw_installed) {
return;
}
asr_devsw_installed++;
/*
* Find a free spot (the report during driver load used by
* osd layer in engine to generate the controlling nodes).
*/
while ((asr_cdevsw.d_maj < NUMCDEVSW)
&& (devsw(makedev(asr_cdevsw.d_maj,0)) != (struct cdevsw *)NULL)) {
++asr_cdevsw.d_maj;
}
if (asr_cdevsw.d_maj >= NUMCDEVSW) for (
asr_cdevsw.d_maj = 0;
(asr_cdevsw.d_maj < CDEV_MAJOR)
&& (devsw(makedev(asr_cdevsw.d_maj,0)) != (struct cdevsw *)NULL);
++asr_cdevsw.d_maj);
/*
* Come to papa
*/
cdevsw_add(&asr_cdevsw);
/*
* delete any nodes that would attach to the primary adapter,
* let the adapter scans add them.
*/
destroy_dev(makedev(asr_cdevsw.d_maj,0));
} /* asr_drvinit */
/* Must initialize before CAM layer picks up our HBA driver */
SYSINIT(asrdev,SI_SUB_DRIVERS,SI_ORDER_MIDDLE+CDEV_MAJOR,asr_drvinit,NULL)
/* I2O support routines */
#define defAlignLong(STRUCT,NAME) char NAME[sizeof(STRUCT)]
#define getAlignLong(STRUCT,NAME) ((STRUCT *)(NAME))
/*
* Fill message with default.
*/
STATIC PI2O_MESSAGE_FRAME
ASR_fillMessage (
IN char * Message,
IN u_int16_t size)
{
OUT PI2O_MESSAGE_FRAME Message_Ptr;
Message_Ptr = getAlignLong(I2O_MESSAGE_FRAME, Message);
bzero ((void *)Message_Ptr, size);
I2O_MESSAGE_FRAME_setVersionOffset(Message_Ptr, I2O_VERSION_11);
I2O_MESSAGE_FRAME_setMessageSize(Message_Ptr,
(size + sizeof(U32) - 1) >> 2);
I2O_MESSAGE_FRAME_setInitiatorAddress (Message_Ptr, 1);
return (Message_Ptr);
} /* ASR_fillMessage */
#define EMPTY_QUEUE ((U32)-1L)
STATIC INLINE U32
ASR_getMessage(
IN i2oRegs_t * virt)
{
OUT U32 MessageOffset;
if ((MessageOffset = virt->ToFIFO) == EMPTY_QUEUE) {
MessageOffset = virt->ToFIFO;
}
return (MessageOffset);
} /* ASR_getMessage */
/* Issue a polled command */
STATIC U32
ASR_initiateCp (
INOUT i2oRegs_t * virt,
IN PI2O_MESSAGE_FRAME Message)
{
OUT U32 Mask = -1L;
U32 MessageOffset;
u_int Delay = 1500;
/*
* ASR_initiateCp is only used for synchronous commands and will
* be made more resiliant to adapter delays since commands like
* resetIOP can cause the adapter to be deaf for a little time.
*/
while (((MessageOffset = ASR_getMessage(virt)) == EMPTY_QUEUE)
&& (--Delay != 0)) {
DELAY (10000);
}
if (MessageOffset != EMPTY_QUEUE) {
bcopy (Message, virt->Address + MessageOffset,
I2O_MESSAGE_FRAME_getMessageSize(Message) << 2);
/*
* Disable the Interrupts
*/
virt->Mask = (Mask = virt->Mask) | Mask_InterruptsDisabled;
virt->ToFIFO = MessageOffset;
}
return (Mask);
} /* ASR_initiateCp */
/*
* Reset the adapter.
*/
STATIC U32
ASR_resetIOP (
INOUT i2oRegs_t * virt)
{
struct resetMessage {
I2O_EXEC_IOP_RESET_MESSAGE M;
U32 R;
};
defAlignLong(struct resetMessage,Message);
PI2O_EXEC_IOP_RESET_MESSAGE Message_Ptr;
OUT U32 * volatile Reply_Ptr;
U32 Old;
/*
* Build up our copy of the Message.
*/
Message_Ptr = (PI2O_EXEC_IOP_RESET_MESSAGE)ASR_fillMessage(Message,
sizeof(I2O_EXEC_IOP_RESET_MESSAGE));
I2O_EXEC_IOP_RESET_MESSAGE_setFunction(Message_Ptr, I2O_EXEC_IOP_RESET);
/*
* Reset the Reply Status
*/
*(Reply_Ptr = (U32 *)((char *)Message_Ptr
+ sizeof(I2O_EXEC_IOP_RESET_MESSAGE))) = 0;
I2O_EXEC_IOP_RESET_MESSAGE_setStatusWordLowAddress(Message_Ptr,
KVTOPHYS((void *)Reply_Ptr));
/*
* Send the Message out
*/
if ((Old = ASR_initiateCp (virt, (PI2O_MESSAGE_FRAME)Message_Ptr)) != (U32)-1L) {
/*
* Wait for a response (Poll), timeouts are dangerous if
* the card is truly responsive. We assume response in 2s.
*/
u_int8_t Delay = 200;
while ((*Reply_Ptr == 0) && (--Delay != 0)) {
DELAY (10000);
}
/*
* Re-enable the interrupts.
*/
virt->Mask = Old;
ASSERT (*Reply_Ptr);
return (*Reply_Ptr);
}
ASSERT (Old != (U32)-1L);
return (0);
} /* ASR_resetIOP */
/*
* Get the curent state of the adapter
*/
STATIC INLINE PI2O_EXEC_STATUS_GET_REPLY
ASR_getStatus (
INOUT i2oRegs_t * virt,
OUT PI2O_EXEC_STATUS_GET_REPLY buffer)
{
defAlignLong(I2O_EXEC_STATUS_GET_MESSAGE,Message);
PI2O_EXEC_STATUS_GET_MESSAGE Message_Ptr;
U32 Old;
/*
* Build up our copy of the Message.
*/
Message_Ptr = (PI2O_EXEC_STATUS_GET_MESSAGE)ASR_fillMessage(Message,
sizeof(I2O_EXEC_STATUS_GET_MESSAGE));
I2O_EXEC_STATUS_GET_MESSAGE_setFunction(Message_Ptr,
I2O_EXEC_STATUS_GET);
I2O_EXEC_STATUS_GET_MESSAGE_setReplyBufferAddressLow(Message_Ptr,
KVTOPHYS((void *)buffer));
/* This one is a Byte Count */
I2O_EXEC_STATUS_GET_MESSAGE_setReplyBufferLength(Message_Ptr,
sizeof(I2O_EXEC_STATUS_GET_REPLY));
/*
* Reset the Reply Status
*/
bzero ((void *)buffer, sizeof(I2O_EXEC_STATUS_GET_REPLY));
/*
* Send the Message out
*/
if ((Old = ASR_initiateCp (virt, (PI2O_MESSAGE_FRAME)Message_Ptr)) != (U32)-1L) {
/*
* Wait for a response (Poll), timeouts are dangerous if
* the card is truly responsive. We assume response in 50ms.
*/
u_int8_t Delay = 50;
while (*((U8 * volatile)&buffer->SyncByte) == 0) {
if (--Delay == 0) {
buffer = (PI2O_EXEC_STATUS_GET_REPLY)NULL;
break;
}
DELAY (1000);
}
/*
* Re-enable the interrupts.
*/
virt->Mask = Old;
return (buffer);
}
return ((PI2O_EXEC_STATUS_GET_REPLY)NULL);
} /* ASR_getStatus */
/*
* Check if the device is a SCSI I2O HBA, and add it to the list.
*/
/*
* Probe for ASR controller. If we find it, we will use it.
* virtual adapters.
*/
STATIC PROBE_RET
asr_probe(PROBE_ARGS)
{
PROBE_SET();
if (id == 0xA5011044) {
PROBE_RETURN ("Adaptec Caching SCSI RAID");
}
PROBE_RETURN (NULL);
} /* asr_probe */
/*
* Probe/Attach for DOMINO chipset.
*/
STATIC PROBE_RET
domino_probe(PROBE_ARGS)
{
PROBE_SET();
if (id == 0x10121044) {
PROBE_RETURN ("Adaptec Caching Memory Controller");
}
PROBE_RETURN (NULL);
} /* domino_probe */
STATIC ATTACH_RET
domino_attach (ATTACH_ARGS)
{
ATTACH_RETURN (0);
} /* domino_attach */
/*
* Probe/Attach for MODE0 adapters.
*/
STATIC PROBE_RET
mode0_probe(PROBE_ARGS)
{
PROBE_SET();
if (id == 0x908010B5) {
PROBE_RETURN ("Adaptec Mode0 3xxx");
}
#if 0 /* this would match any generic i960 -- mjs */
if (id == 0x19608086) {
PROBE_RETURN ("Adaptec Mode0 1xxx");
}
#endif
PROBE_RETURN (NULL);
} /* mode0_probe */
STATIC ATTACH_RET
mode0_attach (ATTACH_ARGS)
{
ATTACH_RETURN (0);
} /* mode0_attach */
STATIC INLINE union asr_ccb *
asr_alloc_ccb (
IN Asr_softc_t * sc)
{
OUT union asr_ccb * new_ccb;
if ((new_ccb = (union asr_ccb *)malloc(sizeof(*new_ccb),
M_DEVBUF, M_WAITOK | M_ZERO)) != (union asr_ccb *)NULL) {
new_ccb->ccb_h.pinfo.priority = 1;
new_ccb->ccb_h.pinfo.index = CAM_UNQUEUED_INDEX;
new_ccb->ccb_h.spriv_ptr0 = sc;
}
return (new_ccb);
} /* asr_alloc_ccb */
STATIC INLINE void
asr_free_ccb (
IN union asr_ccb * free_ccb)
{
free(free_ccb, M_DEVBUF);
} /* asr_free_ccb */
/*
* Print inquiry data `carefully'
*/
STATIC void
ASR_prstring (
u_int8_t * s,
int len)
{
while ((--len >= 0) && (*s) && (*s != ' ') && (*s != '-')) {
printf ("%c", *(s++));
}
} /* ASR_prstring */
/*
* Prototypes
*/
STATIC INLINE int ASR_queue __P((
IN Asr_softc_t * sc,
IN PI2O_MESSAGE_FRAME Message));
/*
* Send a message synchronously and without Interrupt to a ccb.
*/
STATIC int
ASR_queue_s (
INOUT union asr_ccb * ccb,
IN PI2O_MESSAGE_FRAME Message)
{
int s;
U32 Mask;
Asr_softc_t * sc = (Asr_softc_t *)(ccb->ccb_h.spriv_ptr0);
/*
* We do not need any (optional byteswapping) method access to
* the Initiator context field.
*/
I2O_MESSAGE_FRAME_setInitiatorContext64(Message, (long)ccb);
/* Prevent interrupt service */
s = splcam ();
sc->ha_Virt->Mask = (Mask = sc->ha_Virt->Mask)
| Mask_InterruptsDisabled;
if (ASR_queue (sc, Message) == EMPTY_QUEUE) {
ccb->ccb_h.status &= ~CAM_STATUS_MASK;
ccb->ccb_h.status |= CAM_REQUEUE_REQ;
}
/*
* Wait for this board to report a finished instruction.
*/
while (ccb->ccb_h.status == CAM_REQ_INPROG) {
(void)asr_intr (sc);
}
/* Re-enable Interrupts */
sc->ha_Virt->Mask = Mask;
splx(s);
return (ccb->ccb_h.status);
} /* ASR_queue_s */
/*
* Send a message synchronously to a Asr_softc_t
*/
STATIC int
ASR_queue_c (
IN Asr_softc_t * sc,
IN PI2O_MESSAGE_FRAME Message)
{
union asr_ccb * ccb;
OUT int status;
if ((ccb = asr_alloc_ccb (sc)) == (union asr_ccb *)NULL) {
return (CAM_REQUEUE_REQ);
}
status = ASR_queue_s (ccb, Message);
asr_free_ccb(ccb);
return (status);
} /* ASR_queue_c */
/*
* Add the specified ccb to the active queue
*/
STATIC INLINE void
ASR_ccbAdd (
IN Asr_softc_t * sc,
INOUT union asr_ccb * ccb)
{
int s;
s = splcam();
LIST_INSERT_HEAD(&(sc->ha_ccb), &(ccb->ccb_h), sim_links.le);
if (ccb->ccb_h.timeout != CAM_TIME_INFINITY) {
if (ccb->ccb_h.timeout == CAM_TIME_DEFAULT) {
/*
* RAID systems can take considerable time to
* complete some commands given the large cache
* flashes switching from write back to write thru.
*/
ccb->ccb_h.timeout = 6 * 60 * 1000;
}
ccb->ccb_h.timeout_ch = timeout(asr_timeout, (caddr_t)ccb,
(ccb->ccb_h.timeout * hz) / 1000);
}
splx(s);
} /* ASR_ccbAdd */
/*
* Remove the specified ccb from the active queue.
*/
STATIC INLINE void
ASR_ccbRemove (
IN Asr_softc_t * sc,
INOUT union asr_ccb * ccb)
{
int s;
s = splcam();
untimeout(asr_timeout, (caddr_t)ccb, ccb->ccb_h.timeout_ch);
LIST_REMOVE(&ccb->ccb_h, sim_links.le);
splx(s);
} /* ASR_ccbRemove */
/*
* Fail all the active commands, so they get re-issued by the operating
* system.
*/
STATIC INLINE void
ASR_failActiveCommands (
IN Asr_softc_t * sc)
{
struct ccb_hdr * ccb;
defAlignLong(I2O_EXEC_LCT_NOTIFY_MESSAGE,Message);
PI2O_EXEC_LCT_NOTIFY_MESSAGE Message_Ptr;
int s;
/* Send a blind LCT command to wait for the enableSys to complete */
Message_Ptr = (PI2O_EXEC_LCT_NOTIFY_MESSAGE)ASR_fillMessage(Message,
sizeof(I2O_EXEC_LCT_NOTIFY_MESSAGE) - sizeof(I2O_SG_ELEMENT));
I2O_MESSAGE_FRAME_setFunction(&(Message_Ptr->StdMessageFrame),
I2O_EXEC_LCT_NOTIFY);
I2O_EXEC_LCT_NOTIFY_MESSAGE_setClassIdentifier(Message_Ptr,
I2O_CLASS_MATCH_ANYCLASS);
(void)ASR_queue_c(sc, (PI2O_MESSAGE_FRAME)Message_Ptr);
s = splcam();
LIST_FOREACH(ccb, &(sc->ha_ccb), sim_links.le) {
ASR_ccbRemove (sc, (union asr_ccb *)ccb);
ccb->status &= ~CAM_STATUS_MASK;
ccb->status |= CAM_REQUEUE_REQ;
((struct ccb_scsiio *)ccb)->resid
= ((struct ccb_scsiio *)ccb)->dxfer_len;
if (ccb->path) {
xpt_done ((union ccb *)ccb);
} else {
wakeup ((caddr_t)ccb);
}
}
splx(s);
} /* ASR_failActiveCommands */
/*
* The following command causes the HBA to reset the specific bus
*/
STATIC INLINE void
ASR_resetBus(
IN Asr_softc_t * sc,
IN int bus)
{
defAlignLong(I2O_HBA_BUS_RESET_MESSAGE,Message);
I2O_HBA_BUS_RESET_MESSAGE * Message_Ptr;
PI2O_LCT_ENTRY Device;
Message_Ptr = (I2O_HBA_BUS_RESET_MESSAGE *)ASR_fillMessage(Message,
sizeof(I2O_HBA_BUS_RESET_MESSAGE));
I2O_MESSAGE_FRAME_setFunction(&Message_Ptr->StdMessageFrame,
I2O_HBA_BUS_RESET);
for (Device = sc->ha_LCT->LCTEntry; Device < (PI2O_LCT_ENTRY)
(((U32 *)sc->ha_LCT)+I2O_LCT_getTableSize(sc->ha_LCT));
++Device) {
if (((Device->le_type & I2O_PORT) != 0)
&& (Device->le_bus == bus)) {
I2O_MESSAGE_FRAME_setTargetAddress(
&Message_Ptr->StdMessageFrame,
I2O_LCT_ENTRY_getLocalTID(Device));
/* Asynchronous command, with no expectations */
(void)ASR_queue(sc, (PI2O_MESSAGE_FRAME)Message_Ptr);
break;
}
}
} /* ASR_resetBus */
STATIC INLINE int
ASR_getBlinkLedCode (
IN Asr_softc_t * sc)
{
if ((sc != (Asr_softc_t *)NULL)
&& (sc->ha_blinkLED != (u_int8_t *)NULL)
&& (sc->ha_blinkLED[1] == 0xBC)) {
return (sc->ha_blinkLED[0]);
}
return (0);
} /* ASR_getBlinkCode */
/*
* Determine the address of an TID lookup. Must be done at high priority
* since the address can be changed by other threads of execution.
*
* Returns NULL pointer if not indexible (but will attempt to generate
* an index if `new_entry' flag is set to TRUE).
*
* All addressible entries are to be guaranteed zero if never initialized.
*/
STATIC INLINE tid_t *
ASR_getTidAddress(
INOUT Asr_softc_t * sc,
IN int bus,
IN int target,
IN int lun,
IN int new_entry)
{
target2lun_t * bus_ptr;
lun2tid_t * target_ptr;
unsigned new_size;
/*
* Validity checking of incoming parameters. More of a bound
* expansion limit than an issue with the code dealing with the
* values.
*
* sc must be valid before it gets here, so that check could be
* dropped if speed a critical issue.
*/
if ((sc == (Asr_softc_t *)NULL)
|| (bus > MAX_CHANNEL)
|| (target > sc->ha_MaxId)
|| (lun > sc->ha_MaxLun)) {
debug_asr_printf("(%lx,%d,%d,%d) target out of range\n",
(u_long)sc, bus, target, lun);
return ((tid_t *)NULL);
}
/*
* See if there is an associated bus list.
*
* for performance, allocate in size of BUS_CHUNK chunks.
* BUS_CHUNK must be a power of two. This is to reduce
* fragmentation effects on the allocations.
*/
# define BUS_CHUNK 8
new_size = ((target + BUS_CHUNK - 1) & ~(BUS_CHUNK - 1));
if ((bus_ptr = sc->ha_targets[bus]) == (target2lun_t *)NULL) {
/*
* Allocate a new structure?
* Since one element in structure, the +1
* needed for size has been abstracted.
*/
if ((new_entry == FALSE)
|| ((sc->ha_targets[bus] = bus_ptr = (target2lun_t *)malloc (
sizeof(*bus_ptr) + (sizeof(bus_ptr->LUN) * new_size),
M_TEMP, M_WAITOK | M_ZERO))
== (target2lun_t *)NULL)) {
debug_asr_printf("failed to allocate bus list\n");
return ((tid_t *)NULL);
}
bus_ptr->size = new_size + 1;
} else if (bus_ptr->size <= new_size) {
target2lun_t * new_bus_ptr;
/*
* Reallocate a new structure?
* Since one element in structure, the +1
* needed for size has been abstracted.
*/
if ((new_entry == FALSE)
|| ((new_bus_ptr = (target2lun_t *)malloc (
sizeof(*bus_ptr) + (sizeof(bus_ptr->LUN) * new_size),
M_TEMP, M_WAITOK | M_ZERO))
== (target2lun_t *)NULL)) {
debug_asr_printf("failed to reallocate bus list\n");
return ((tid_t *)NULL);
}
/*
* Copy the whole thing, safer, simpler coding
* and not really performance critical at this point.
*/
bcopy (bus_ptr, new_bus_ptr, sizeof(*bus_ptr)
+ (sizeof(bus_ptr->LUN) * (bus_ptr->size - 1)));
sc->ha_targets[bus] = new_bus_ptr;
free (bus_ptr, M_TEMP);
bus_ptr = new_bus_ptr;
bus_ptr->size = new_size + 1;
}
/*
* We now have the bus list, lets get to the target list.
* Since most systems have only *one* lun, we do not allocate
* in chunks as above, here we allow one, then in chunk sizes.
* TARGET_CHUNK must be a power of two. This is to reduce
* fragmentation effects on the allocations.
*/
# define TARGET_CHUNK 8
if ((new_size = lun) != 0) {
new_size = ((lun + TARGET_CHUNK - 1) & ~(TARGET_CHUNK - 1));
}
if ((target_ptr = bus_ptr->LUN[target]) == (lun2tid_t *)NULL) {
/*
* Allocate a new structure?
* Since one element in structure, the +1
* needed for size has been abstracted.
*/
if ((new_entry == FALSE)
|| ((bus_ptr->LUN[target] = target_ptr = (lun2tid_t *)malloc (
sizeof(*target_ptr) + (sizeof(target_ptr->TID) * new_size),
M_TEMP, M_WAITOK | M_ZERO))
== (lun2tid_t *)NULL)) {
debug_asr_printf("failed to allocate target list\n");
return ((tid_t *)NULL);
}
target_ptr->size = new_size + 1;
} else if (target_ptr->size <= new_size) {
lun2tid_t * new_target_ptr;
/*
* Reallocate a new structure?
* Since one element in structure, the +1
* needed for size has been abstracted.
*/
if ((new_entry == FALSE)
|| ((new_target_ptr = (lun2tid_t *)malloc (
sizeof(*target_ptr) + (sizeof(target_ptr->TID) * new_size),
M_TEMP, M_WAITOK | M_ZERO))
== (lun2tid_t *)NULL)) {
debug_asr_printf("failed to reallocate target list\n");
return ((tid_t *)NULL);
}
/*
* Copy the whole thing, safer, simpler coding
* and not really performance critical at this point.
*/
bcopy (target_ptr, new_target_ptr,
sizeof(*target_ptr)
+ (sizeof(target_ptr->TID) * (target_ptr->size - 1)));
bus_ptr->LUN[target] = new_target_ptr;
free (target_ptr, M_TEMP);
target_ptr = new_target_ptr;
target_ptr->size = new_size + 1;
}
/*
* Now, acquire the TID address from the LUN indexed list.
*/
return (&(target_ptr->TID[lun]));
} /* ASR_getTidAddress */
/*
* Get a pre-existing TID relationship.
*
* If the TID was never set, return (tid_t)-1.
*
* should use mutex rather than spl.
*/
STATIC INLINE tid_t
ASR_getTid (
IN Asr_softc_t * sc,
IN int bus,
IN int target,
IN int lun)
{
tid_t * tid_ptr;
int s;
OUT tid_t retval;
s = splcam();
if (((tid_ptr = ASR_getTidAddress (sc, bus, target, lun, FALSE))
== (tid_t *)NULL)
/* (tid_t)0 or (tid_t)-1 indicate no TID */
|| (*tid_ptr == (tid_t)0)) {
splx(s);
return ((tid_t)-1);
}
retval = *tid_ptr;
splx(s);
return (retval);
} /* ASR_getTid */
/*
* Set a TID relationship.
*
* If the TID was not set, return (tid_t)-1.
*
* should use mutex rather than spl.
*/
STATIC INLINE tid_t
ASR_setTid (
INOUT Asr_softc_t * sc,
IN int bus,
IN int target,
IN int lun,
INOUT tid_t TID)
{
tid_t * tid_ptr;
int s;
if (TID != (tid_t)-1) {
if (TID == 0) {
return ((tid_t)-1);
}
s = splcam();
if ((tid_ptr = ASR_getTidAddress (sc, bus, target, lun, TRUE))
== (tid_t *)NULL) {
splx(s);
return ((tid_t)-1);
}
*tid_ptr = TID;
splx(s);
}
return (TID);
} /* ASR_setTid */
/*-------------------------------------------------------------------------*/
/* Function ASR_rescan */
/*-------------------------------------------------------------------------*/
/* The Parameters Passed To This Function Are : */
/* Asr_softc_t * : HBA miniport driver's adapter data storage. */
/* */
/* This Function Will rescan the adapter and resynchronize any data */
/* */
/* Return : 0 For OK, Error Code Otherwise */
/*-------------------------------------------------------------------------*/
STATIC INLINE int
ASR_rescan(
IN Asr_softc_t * sc)
{
int bus;
OUT int error;
/*
* Re-acquire the LCT table and synchronize us to the adapter.
*/
if ((error = ASR_acquireLct(sc)) == 0) {
error = ASR_acquireHrt(sc);
}
if (error != 0) {
return error;
}
bus = sc->ha_MaxBus;
/* Reset all existing cached TID lookups */
do {
int target;
/*
* Scan for all targets on this bus to see if they
* got affected by the rescan.
*/
for (target = 0; target <= sc->ha_MaxId; ++target) {
int lun;
for (lun = 0; lun <= sc->ha_MaxLun; ++lun) {
PI2O_LCT_ENTRY Device;
tid_t TID = (tid_t)-1;
/*
* See if the cached TID changed. Search for
* the device in our new LCT.
*/
for (Device = sc->ha_LCT->LCTEntry;
Device < (PI2O_LCT_ENTRY)(((U32 *)sc->ha_LCT)
+ I2O_LCT_getTableSize(sc->ha_LCT));
++Device) {
if ((Device->le_type != I2O_UNKNOWN)
&& (Device->le_bus == bus)
&& (Device->le_target == target)
&& (Device->le_lun == lun)
&& (I2O_LCT_ENTRY_getUserTID(Device)
== 0xFFF)) {
TID = I2O_LCT_ENTRY_getLocalTID(
Device);
break;
}
}
/*
* Indicate to the OS that the label needs
* to be recalculated, or that the specific
* open device is no longer valid (Merde)
* because the cached TID changed.
* ASR_getTid (sc, bus, target, lun) != TI
*/
/*
* We have the option of clearing the
* cached TID for it to be rescanned, or to
* set it now even if the device never got
* accessed. We chose the later since we
* currently do not use the condition that
* the TID ever got cached.
*/
ASR_setTid (sc, bus, target, lun, TID);
}
}
} while (--bus >= 0);
return (error);
} /* ASR_rescan */
/*-------------------------------------------------------------------------*/
/* Function ASR_reset */
/*-------------------------------------------------------------------------*/
/* The Parameters Passed To This Function Are : */
/* Asr_softc_t * : HBA miniport driver's adapter data storage. */
/* */
/* This Function Will reset the adapter and resynchronize any data */
/* */
/* Return : None */
/*-------------------------------------------------------------------------*/
STATIC INLINE void
ASR_reset(
IN Asr_softc_t * sc)
{
(void)ASR_resetIOP (sc->ha_Virt);
(void)ASR_init (sc);
(void)ASR_rescan (sc);
(void)ASR_failActiveCommands (sc);
} /* ASR_reset */
/*
* Device timeout handler.
*/
STATIC void
asr_timeout(
INOUT void * arg)
{
union asr_ccb * ccb = (union asr_ccb *)arg;
Asr_softc_t * sc = (Asr_softc_t *)(ccb->ccb_h.spriv_ptr0);
int s;
debug_asr_print_path(ccb);
debug_asr_printf("timed out");
/*
* Check if the adapter has locked up?
*/
if ((s = ASR_getBlinkLedCode(sc)) != 0) {
debug_asr_printf (
" due to adapter blinkled code %x\nresetting adapter\n", s);
ASR_reset (sc);
return;
}
/*
* Abort does not function on the ASR card!!! Walking away from
* the SCSI command is also *very* dangerous. A SCSI BUS reset is
* our best bet, followed by a complete adapter reset if that fails.
*/
s = splcam();
if (ccb->ccb_h.status == CAM_CMD_TIMEOUT) {
debug_asr_printf (" AGAIN\nreinitializing adapter\n");
ASR_reset (sc);
splx(s);
return;
}
debug_asr_printf ("\nresetting bus\n");
/* If the BUS reset does not take, then an adapter reset is next! */
ccb->ccb_h.status &= ~CAM_STATUS_MASK;
ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
ccb->ccb_h.timeout_ch = timeout(asr_timeout, (caddr_t)ccb,
(ccb->ccb_h.timeout * hz) / 1000);
ASR_resetBus (sc, cam_sim_bus(xpt_path_sim(ccb->ccb_h.path)));
splx(s);
} /* asr_timeout */
/*
* send a message asynchronously
*/
STATIC INLINE int
ASR_queue(
IN Asr_softc_t * sc,
IN PI2O_MESSAGE_FRAME Message)
{
OUT U32 MessageOffset;
union asr_ccb * ccb;
debug_asr_printf ("Host Command Dump:\n");
debug_asr_dump_message (Message);
/*
* Limit the number of Messages sent to this HBA. Better to sleep,
* than to hardware loop like a nut! By limiting the number of
* messages to an individual HBA here, we manage to perform all
* the processing of the message ready to drop the next one into
* the controller. We could limit the messages we are allowed to
* take, but that may have a performance hit.
*/
ccb = (union asr_ccb *)(long)
I2O_MESSAGE_FRAME_getInitiatorContext64(Message);
if (((MessageOffset = ASR_getMessage(sc->ha_Virt)) != EMPTY_QUEUE)
|| ((MessageOffset = ASR_getMessage(sc->ha_Virt)) != EMPTY_QUEUE)) {
#ifdef ASR_MEASURE_PERFORMANCE
int startTimeIndex;
if (ccb) {
++sc->ha_performance.command_count[
(int) ccb->csio.cdb_io.cdb_bytes[0]];
DEQ_TIMEQ_FREE_LIST(startTimeIndex,
sc->ha_timeQFreeList,
sc->ha_timeQFreeHead,
sc->ha_timeQFreeTail);
if (-1 != startTimeIndex) {
microtime(&sc->ha_timeQ[startTimeIndex]);
}
/* Time stamp the command before we send it out */
((PRIVATE_SCSI_SCB_EXECUTE_MESSAGE *) Message)->
PrivateMessageFrame.TransactionContext
= (I2O_TRANSACTION_CONTEXT) startTimeIndex;
++sc->ha_submitted_ccbs_count;
if (sc->ha_performance.max_submit_count
< sc->ha_submitted_ccbs_count) {
sc->ha_performance.max_submit_count
= sc->ha_submitted_ccbs_count;
}
}
#endif
bcopy (Message, sc->ha_Virt->Address + MessageOffset,
I2O_MESSAGE_FRAME_getMessageSize(Message) << 2);
if (ccb) {
ASR_ccbAdd (sc, ccb);
}
/* Post the command */
sc->ha_Virt->ToFIFO = MessageOffset;
} else {
if (ASR_getBlinkLedCode(sc)) {
ASR_reset (sc);
}
}
return (MessageOffset);
} /* ASR_queue */
/* Simple Scatter Gather elements */
#define SG(SGL,Index,Flags,Buffer,Size) \
I2O_FLAGS_COUNT_setCount( \
&(((PI2O_SG_ELEMENT)(SGL))->u.Simple[Index].FlagsCount), \
Size); \
I2O_FLAGS_COUNT_setFlags( \
&(((PI2O_SG_ELEMENT)(SGL))->u.Simple[Index].FlagsCount), \
I2O_SGL_FLAGS_SIMPLE_ADDRESS_ELEMENT | (Flags)); \
I2O_SGE_SIMPLE_ELEMENT_setPhysicalAddress( \
&(((PI2O_SG_ELEMENT)(SGL))->u.Simple[Index]), \
(Buffer == NULL) ? NULL : KVTOPHYS(Buffer))
/*
* Retrieve Parameter Group.
* Buffer must be allocated using defAlignLong macro.
*/
STATIC void *
ASR_getParams(
IN Asr_softc_t * sc,
IN tid_t TID,
IN int Group,
OUT void * Buffer,
IN unsigned BufferSize)
{
struct paramGetMessage {
I2O_UTIL_PARAMS_GET_MESSAGE M;
char F[
sizeof(I2O_SGE_SIMPLE_ELEMENT)*2 - sizeof(I2O_SG_ELEMENT)];
struct Operations {
I2O_PARAM_OPERATIONS_LIST_HEADER Header;
I2O_PARAM_OPERATION_ALL_TEMPLATE Template[1];
} O;
};
defAlignLong(struct paramGetMessage, Message);
struct Operations * Operations_Ptr;
I2O_UTIL_PARAMS_GET_MESSAGE * Message_Ptr;
struct ParamBuffer {
I2O_PARAM_RESULTS_LIST_HEADER Header;
I2O_PARAM_READ_OPERATION_RESULT Read;
char Info[1];
} * Buffer_Ptr;
Message_Ptr = (I2O_UTIL_PARAMS_GET_MESSAGE *)ASR_fillMessage(Message,
sizeof(I2O_UTIL_PARAMS_GET_MESSAGE)
+ sizeof(I2O_SGE_SIMPLE_ELEMENT)*2 - sizeof(I2O_SG_ELEMENT));
Operations_Ptr = (struct Operations *)((char *)Message_Ptr
+ sizeof(I2O_UTIL_PARAMS_GET_MESSAGE)
+ sizeof(I2O_SGE_SIMPLE_ELEMENT)*2 - sizeof(I2O_SG_ELEMENT));
bzero ((void *)Operations_Ptr, sizeof(struct Operations));
I2O_PARAM_OPERATIONS_LIST_HEADER_setOperationCount(
&(Operations_Ptr->Header), 1);
I2O_PARAM_OPERATION_ALL_TEMPLATE_setOperation(
&(Operations_Ptr->Template[0]), I2O_PARAMS_OPERATION_FIELD_GET);
I2O_PARAM_OPERATION_ALL_TEMPLATE_setFieldCount(
&(Operations_Ptr->Template[0]), 0xFFFF);
I2O_PARAM_OPERATION_ALL_TEMPLATE_setGroupNumber(
&(Operations_Ptr->Template[0]), Group);
bzero ((void *)(Buffer_Ptr = getAlignLong(struct ParamBuffer, Buffer)),
BufferSize);
I2O_MESSAGE_FRAME_setVersionOffset(&(Message_Ptr->StdMessageFrame),
I2O_VERSION_11
+ (((sizeof(I2O_UTIL_PARAMS_GET_MESSAGE) - sizeof(I2O_SG_ELEMENT))
/ sizeof(U32)) << 4));
I2O_MESSAGE_FRAME_setTargetAddress (&(Message_Ptr->StdMessageFrame),
TID);
I2O_MESSAGE_FRAME_setFunction (&(Message_Ptr->StdMessageFrame),
I2O_UTIL_PARAMS_GET);
/*
* Set up the buffers as scatter gather elements.
*/
SG(&(Message_Ptr->SGL), 0,
I2O_SGL_FLAGS_DIR | I2O_SGL_FLAGS_END_OF_BUFFER,
Operations_Ptr, sizeof(struct Operations));
SG(&(Message_Ptr->SGL), 1,
I2O_SGL_FLAGS_LAST_ELEMENT | I2O_SGL_FLAGS_END_OF_BUFFER,
Buffer_Ptr, BufferSize);
if ((ASR_queue_c(sc, (PI2O_MESSAGE_FRAME)Message_Ptr) == CAM_REQ_CMP)
&& (Buffer_Ptr->Header.ResultCount)) {
return ((void *)(Buffer_Ptr->Info));
}
return ((void *)NULL);
} /* ASR_getParams */
/*
* Acquire the LCT information.
*/
STATIC INLINE int
ASR_acquireLct (
INOUT Asr_softc_t * sc)
{
PI2O_EXEC_LCT_NOTIFY_MESSAGE Message_Ptr;
PI2O_SGE_SIMPLE_ELEMENT sg;
int MessageSizeInBytes;
caddr_t v;
int len;
I2O_LCT Table;
PI2O_LCT_ENTRY Entry;
/*
* sc value assumed valid
*/
MessageSizeInBytes = sizeof(I2O_EXEC_LCT_NOTIFY_MESSAGE)
- sizeof(I2O_SG_ELEMENT) + sizeof(I2O_SGE_SIMPLE_ELEMENT);
if ((Message_Ptr = (PI2O_EXEC_LCT_NOTIFY_MESSAGE)malloc (
MessageSizeInBytes, M_TEMP, M_WAITOK))
== (PI2O_EXEC_LCT_NOTIFY_MESSAGE)NULL) {
return (ENOMEM);
}
(void)ASR_fillMessage((char *)Message_Ptr, MessageSizeInBytes);
I2O_MESSAGE_FRAME_setVersionOffset(&(Message_Ptr->StdMessageFrame),
(I2O_VERSION_11 +
(((sizeof(I2O_EXEC_LCT_NOTIFY_MESSAGE) - sizeof(I2O_SG_ELEMENT))
/ sizeof(U32)) << 4)));
I2O_MESSAGE_FRAME_setFunction(&(Message_Ptr->StdMessageFrame),
I2O_EXEC_LCT_NOTIFY);
I2O_EXEC_LCT_NOTIFY_MESSAGE_setClassIdentifier(Message_Ptr,
I2O_CLASS_MATCH_ANYCLASS);
/*
* Call the LCT table to determine the number of device entries
* to reserve space for.
*/
SG(&(Message_Ptr->SGL), 0,
I2O_SGL_FLAGS_LAST_ELEMENT | I2O_SGL_FLAGS_END_OF_BUFFER, &Table,
sizeof(I2O_LCT));
/*
* since this code is reused in several systems, code efficiency
* is greater by using a shift operation rather than a divide by
* sizeof(u_int32_t).
*/
I2O_LCT_setTableSize(&Table,
(sizeof(I2O_LCT) - sizeof(I2O_LCT_ENTRY)) >> 2);
(void)ASR_queue_c(sc, (PI2O_MESSAGE_FRAME)Message_Ptr);
/*
* Determine the size of the LCT table.
*/
if (sc->ha_LCT) {
free (sc->ha_LCT, M_TEMP);
}
/*
* malloc only generates contiguous memory when less than a
* page is expected. We must break the request up into an SG list ...
*/
if (((len = (I2O_LCT_getTableSize(&Table) << 2)) <=
(sizeof(I2O_LCT) - sizeof(I2O_LCT_ENTRY)))
|| (len > (128 * 1024))) { /* Arbitrary */
free (Message_Ptr, M_TEMP);
return (EINVAL);
}
if ((sc->ha_LCT = (PI2O_LCT)malloc (len, M_TEMP, M_WAITOK))
== (PI2O_LCT)NULL) {
free (Message_Ptr, M_TEMP);
return (ENOMEM);
}
/*
* since this code is reused in several systems, code efficiency
* is greater by using a shift operation rather than a divide by
* sizeof(u_int32_t).
*/
I2O_LCT_setTableSize(sc->ha_LCT,
(sizeof(I2O_LCT) - sizeof(I2O_LCT_ENTRY)) >> 2);
/*
* Convert the access to the LCT table into a SG list.
*/
sg = Message_Ptr->SGL.u.Simple;
v = (caddr_t)(sc->ha_LCT);
for (;;) {
int next, base, span;
span = 0;
next = base = KVTOPHYS(v);
I2O_SGE_SIMPLE_ELEMENT_setPhysicalAddress(sg, base);
/* How far can we go contiguously */
while ((len > 0) && (base == next)) {
int size;
next = trunc_page(base) + PAGE_SIZE;
size = next - base;
if (size > len) {
size = len;
}
span += size;
v += size;
len -= size;
base = KVTOPHYS(v);
}
/* Construct the Flags */
I2O_FLAGS_COUNT_setCount(&(sg->FlagsCount), span);
{
int rw = I2O_SGL_FLAGS_SIMPLE_ADDRESS_ELEMENT;
if (len <= 0) {
rw = (I2O_SGL_FLAGS_SIMPLE_ADDRESS_ELEMENT
| I2O_SGL_FLAGS_LAST_ELEMENT
| I2O_SGL_FLAGS_END_OF_BUFFER);
}
I2O_FLAGS_COUNT_setFlags(&(sg->FlagsCount), rw);
}
if (len <= 0) {
break;
}
/*
* Incrementing requires resizing of the packet.
*/
++sg;
MessageSizeInBytes += sizeof(*sg);
I2O_MESSAGE_FRAME_setMessageSize(
&(Message_Ptr->StdMessageFrame),
I2O_MESSAGE_FRAME_getMessageSize(
&(Message_Ptr->StdMessageFrame))
+ (sizeof(*sg) / sizeof(U32)));
{
PI2O_EXEC_LCT_NOTIFY_MESSAGE NewMessage_Ptr;
if ((NewMessage_Ptr = (PI2O_EXEC_LCT_NOTIFY_MESSAGE)
malloc (MessageSizeInBytes, M_TEMP, M_WAITOK))
== (PI2O_EXEC_LCT_NOTIFY_MESSAGE)NULL) {
free (sc->ha_LCT, M_TEMP);
sc->ha_LCT = (PI2O_LCT)NULL;
free (Message_Ptr, M_TEMP);
return (ENOMEM);
}
span = ((caddr_t)sg) - (caddr_t)Message_Ptr;
bcopy ((caddr_t)Message_Ptr,
(caddr_t)NewMessage_Ptr, span);
free (Message_Ptr, M_TEMP);
sg = (PI2O_SGE_SIMPLE_ELEMENT)
(((caddr_t)NewMessage_Ptr) + span);
Message_Ptr = NewMessage_Ptr;
}
}
{ int retval;
retval = ASR_queue_c(sc, (PI2O_MESSAGE_FRAME)Message_Ptr);
free (Message_Ptr, M_TEMP);
if (retval != CAM_REQ_CMP) {
return (ENODEV);
}
}
/* If the LCT table grew, lets truncate accesses */
if (I2O_LCT_getTableSize(&Table) < I2O_LCT_getTableSize(sc->ha_LCT)) {
I2O_LCT_setTableSize(sc->ha_LCT, I2O_LCT_getTableSize(&Table));
}
for (Entry = sc->ha_LCT->LCTEntry; Entry < (PI2O_LCT_ENTRY)
(((U32 *)sc->ha_LCT)+I2O_LCT_getTableSize(sc->ha_LCT));
++Entry) {
Entry->le_type = I2O_UNKNOWN;
switch (I2O_CLASS_ID_getClass(&(Entry->ClassID))) {
case I2O_CLASS_RANDOM_BLOCK_STORAGE:
Entry->le_type = I2O_BSA;
break;
case I2O_CLASS_SCSI_PERIPHERAL:
Entry->le_type = I2O_SCSI;
break;
case I2O_CLASS_FIBRE_CHANNEL_PERIPHERAL:
Entry->le_type = I2O_FCA;
break;
case I2O_CLASS_BUS_ADAPTER_PORT:
Entry->le_type = I2O_PORT | I2O_SCSI;
/* FALLTHRU */
case I2O_CLASS_FIBRE_CHANNEL_PORT:
if (I2O_CLASS_ID_getClass(&(Entry->ClassID)) ==
I2O_CLASS_FIBRE_CHANNEL_PORT) {
Entry->le_type = I2O_PORT | I2O_FCA;
}
{ struct ControllerInfo {
I2O_PARAM_RESULTS_LIST_HEADER Header;
I2O_PARAM_READ_OPERATION_RESULT Read;
I2O_HBA_SCSI_CONTROLLER_INFO_SCALAR Info;
};
defAlignLong(struct ControllerInfo, Buffer);
PI2O_HBA_SCSI_CONTROLLER_INFO_SCALAR Info;
Entry->le_bus = 0xff;
Entry->le_target = 0xff;
Entry->le_lun = 0xff;
if ((Info = (PI2O_HBA_SCSI_CONTROLLER_INFO_SCALAR)
ASR_getParams(sc,
I2O_LCT_ENTRY_getLocalTID(Entry),
I2O_HBA_SCSI_CONTROLLER_INFO_GROUP_NO,
Buffer, sizeof(struct ControllerInfo)))
== (PI2O_HBA_SCSI_CONTROLLER_INFO_SCALAR)NULL) {
continue;
}
Entry->le_target
= I2O_HBA_SCSI_CONTROLLER_INFO_SCALAR_getInitiatorID(
Info);
Entry->le_lun = 0;
} /* FALLTHRU */
default:
continue;
}
{ struct DeviceInfo {
I2O_PARAM_RESULTS_LIST_HEADER Header;
I2O_PARAM_READ_OPERATION_RESULT Read;
I2O_DPT_DEVICE_INFO_SCALAR Info;
};
defAlignLong (struct DeviceInfo, Buffer);
PI2O_DPT_DEVICE_INFO_SCALAR Info;
Entry->le_bus = 0xff;
Entry->le_target = 0xff;
Entry->le_lun = 0xff;
if ((Info = (PI2O_DPT_DEVICE_INFO_SCALAR)
ASR_getParams(sc,
I2O_LCT_ENTRY_getLocalTID(Entry),
I2O_DPT_DEVICE_INFO_GROUP_NO,
Buffer, sizeof(struct DeviceInfo)))
== (PI2O_DPT_DEVICE_INFO_SCALAR)NULL) {
continue;
}
Entry->le_type
|= I2O_DPT_DEVICE_INFO_SCALAR_getDeviceType(Info);
Entry->le_bus
= I2O_DPT_DEVICE_INFO_SCALAR_getBus(Info);
if ((Entry->le_bus > sc->ha_MaxBus)
&& (Entry->le_bus <= MAX_CHANNEL)) {
sc->ha_MaxBus = Entry->le_bus;
}
Entry->le_target
= I2O_DPT_DEVICE_INFO_SCALAR_getIdentifier(Info);
Entry->le_lun
= I2O_DPT_DEVICE_INFO_SCALAR_getLunInfo(Info);
}
}
/*
* A zero return value indicates success.
*/
return (0);
} /* ASR_acquireLct */
/*
* Initialize a message frame.
* We assume that the CDB has already been set up, so all we do here is
* generate the Scatter Gather list.
*/
STATIC INLINE PI2O_MESSAGE_FRAME
ASR_init_message(
IN union asr_ccb * ccb,
OUT PI2O_MESSAGE_FRAME Message)
{
int next, span, base, rw;
OUT PI2O_MESSAGE_FRAME Message_Ptr;
Asr_softc_t * sc = (Asr_softc_t *)(ccb->ccb_h.spriv_ptr0);
PI2O_SGE_SIMPLE_ELEMENT sg;
caddr_t v;
vm_size_t size, len;
U32 MessageSize;
/* We only need to zero out the PRIVATE_SCSI_SCB_EXECUTE_MESSAGE */
bzero (Message_Ptr = getAlignLong(I2O_MESSAGE_FRAME, Message),
(sizeof(PRIVATE_SCSI_SCB_EXECUTE_MESSAGE) - sizeof(I2O_SG_ELEMENT)));
{
int target = ccb->ccb_h.target_id;
int lun = ccb->ccb_h.target_lun;
int bus = cam_sim_bus(xpt_path_sim(ccb->ccb_h.path));
tid_t TID;
if ((TID = ASR_getTid (sc, bus, target, lun)) == (tid_t)-1) {
PI2O_LCT_ENTRY Device;
TID = (tid_t)0;
for (Device = sc->ha_LCT->LCTEntry; Device < (PI2O_LCT_ENTRY)
(((U32 *)sc->ha_LCT)+I2O_LCT_getTableSize(sc->ha_LCT));
++Device) {
if ((Device->le_type != I2O_UNKNOWN)
&& (Device->le_bus == bus)
&& (Device->le_target == target)
&& (Device->le_lun == lun)
&& (I2O_LCT_ENTRY_getUserTID(Device) == 0xFFF)) {
TID = I2O_LCT_ENTRY_getLocalTID(Device);
ASR_setTid (sc, Device->le_bus,
Device->le_target, Device->le_lun,
TID);
break;
}
}
}
if (TID == (tid_t)0) {
return ((PI2O_MESSAGE_FRAME)NULL);
}
I2O_MESSAGE_FRAME_setTargetAddress(Message_Ptr, TID);
PRIVATE_SCSI_SCB_EXECUTE_MESSAGE_setTID(
(PPRIVATE_SCSI_SCB_EXECUTE_MESSAGE)Message_Ptr, TID);
}
I2O_MESSAGE_FRAME_setVersionOffset(Message_Ptr, I2O_VERSION_11 |
(((sizeof(PRIVATE_SCSI_SCB_EXECUTE_MESSAGE) - sizeof(I2O_SG_ELEMENT))
/ sizeof(U32)) << 4));
I2O_MESSAGE_FRAME_setMessageSize(Message_Ptr,
(sizeof(PRIVATE_SCSI_SCB_EXECUTE_MESSAGE)
- sizeof(I2O_SG_ELEMENT)) / sizeof(U32));
I2O_MESSAGE_FRAME_setInitiatorAddress (Message_Ptr, 1);
I2O_MESSAGE_FRAME_setFunction(Message_Ptr, I2O_PRIVATE_MESSAGE);
I2O_PRIVATE_MESSAGE_FRAME_setXFunctionCode (
(PI2O_PRIVATE_MESSAGE_FRAME)Message_Ptr, I2O_SCSI_SCB_EXEC);
PRIVATE_SCSI_SCB_EXECUTE_MESSAGE_setSCBFlags (
(PPRIVATE_SCSI_SCB_EXECUTE_MESSAGE)Message_Ptr,
I2O_SCB_FLAG_ENABLE_DISCONNECT
| I2O_SCB_FLAG_SIMPLE_QUEUE_TAG
| I2O_SCB_FLAG_SENSE_DATA_IN_BUFFER);
/*
* We do not need any (optional byteswapping) method access to
* the Initiator & Transaction context field.
*/
I2O_MESSAGE_FRAME_setInitiatorContext64(Message, (long)ccb);
I2O_PRIVATE_MESSAGE_FRAME_setOrganizationID(
(PI2O_PRIVATE_MESSAGE_FRAME)Message_Ptr, DPT_ORGANIZATION_ID);
/*
* copy the cdb over
*/
PRIVATE_SCSI_SCB_EXECUTE_MESSAGE_setCDBLength(
(PPRIVATE_SCSI_SCB_EXECUTE_MESSAGE)Message_Ptr, ccb->csio.cdb_len);
bcopy (&(ccb->csio.cdb_io),
((PPRIVATE_SCSI_SCB_EXECUTE_MESSAGE)Message_Ptr)->CDB, ccb->csio.cdb_len);
/*
* Given a buffer describing a transfer, set up a scatter/gather map
* in a ccb to map that SCSI transfer.
*/
rw = (ccb->ccb_h.flags & CAM_DIR_IN) ? 0 : I2O_SGL_FLAGS_DIR;
PRIVATE_SCSI_SCB_EXECUTE_MESSAGE_setSCBFlags (
(PPRIVATE_SCSI_SCB_EXECUTE_MESSAGE)Message_Ptr,
(ccb->csio.dxfer_len)
? ((rw) ? (I2O_SCB_FLAG_XFER_TO_DEVICE
| I2O_SCB_FLAG_ENABLE_DISCONNECT
| I2O_SCB_FLAG_SIMPLE_QUEUE_TAG
| I2O_SCB_FLAG_SENSE_DATA_IN_BUFFER)
: (I2O_SCB_FLAG_XFER_FROM_DEVICE
| I2O_SCB_FLAG_ENABLE_DISCONNECT
| I2O_SCB_FLAG_SIMPLE_QUEUE_TAG
| I2O_SCB_FLAG_SENSE_DATA_IN_BUFFER))
: (I2O_SCB_FLAG_ENABLE_DISCONNECT
| I2O_SCB_FLAG_SIMPLE_QUEUE_TAG
| I2O_SCB_FLAG_SENSE_DATA_IN_BUFFER));
/*
* Given a transfer described by a `data', fill in the SG list.
*/
sg = &((PPRIVATE_SCSI_SCB_EXECUTE_MESSAGE)Message_Ptr)->SGL.u.Simple[0];
len = ccb->csio.dxfer_len;
v = ccb->csio.data_ptr;
ASSERT (ccb->csio.dxfer_len >= 0);
MessageSize = I2O_MESSAGE_FRAME_getMessageSize(Message_Ptr);
PRIVATE_SCSI_SCB_EXECUTE_MESSAGE_setByteCount(
(PPRIVATE_SCSI_SCB_EXECUTE_MESSAGE)Message_Ptr, len);
while ((len > 0) && (sg < &((PPRIVATE_SCSI_SCB_EXECUTE_MESSAGE)
Message_Ptr)->SGL.u.Simple[SG_SIZE])) {
span = 0;
next = base = KVTOPHYS(v);
I2O_SGE_SIMPLE_ELEMENT_setPhysicalAddress(sg, base);
/* How far can we go contiguously */
while ((len > 0) && (base == next)) {
next = trunc_page(base) + PAGE_SIZE;
size = next - base;
if (size > len) {
size = len;
}
span += size;
v += size;
len -= size;
base = KVTOPHYS(v);
}
I2O_FLAGS_COUNT_setCount(&(sg->FlagsCount), span);
if (len == 0) {
rw |= I2O_SGL_FLAGS_LAST_ELEMENT;
}
I2O_FLAGS_COUNT_setFlags(&(sg->FlagsCount),
I2O_SGL_FLAGS_SIMPLE_ADDRESS_ELEMENT | rw);
++sg;
MessageSize += sizeof(*sg) / sizeof(U32);
}
/* We always do the request sense ... */
if ((span = ccb->csio.sense_len) == 0) {
span = sizeof(ccb->csio.sense_data);
}
SG(sg, 0, I2O_SGL_FLAGS_LAST_ELEMENT | I2O_SGL_FLAGS_END_OF_BUFFER,
&(ccb->csio.sense_data), span);
I2O_MESSAGE_FRAME_setMessageSize(Message_Ptr,
MessageSize + (sizeof(*sg) / sizeof(U32)));
return (Message_Ptr);
} /* ASR_init_message */
/*
* Reset the adapter.
*/
STATIC INLINE U32
ASR_initOutBound (
INOUT Asr_softc_t * sc)
{
struct initOutBoundMessage {
I2O_EXEC_OUTBOUND_INIT_MESSAGE M;
U32 R;
};
defAlignLong(struct initOutBoundMessage,Message);
PI2O_EXEC_OUTBOUND_INIT_MESSAGE Message_Ptr;
OUT U32 * volatile Reply_Ptr;
U32 Old;
/*
* Build up our copy of the Message.
*/
Message_Ptr = (PI2O_EXEC_OUTBOUND_INIT_MESSAGE)ASR_fillMessage(Message,
sizeof(I2O_EXEC_OUTBOUND_INIT_MESSAGE));
I2O_MESSAGE_FRAME_setFunction(&(Message_Ptr->StdMessageFrame),
I2O_EXEC_OUTBOUND_INIT);
I2O_EXEC_OUTBOUND_INIT_MESSAGE_setHostPageFrameSize(Message_Ptr, PAGE_SIZE);
I2O_EXEC_OUTBOUND_INIT_MESSAGE_setOutboundMFrameSize(Message_Ptr,
sizeof(I2O_SCSI_ERROR_REPLY_MESSAGE_FRAME));
/*
* Reset the Reply Status
*/
*(Reply_Ptr = (U32 *)((char *)Message_Ptr
+ sizeof(I2O_EXEC_OUTBOUND_INIT_MESSAGE))) = 0;
SG (&(Message_Ptr->SGL), 0, I2O_SGL_FLAGS_LAST_ELEMENT, Reply_Ptr,
sizeof(U32));
/*
* Send the Message out
*/
if ((Old = ASR_initiateCp (sc->ha_Virt, (PI2O_MESSAGE_FRAME)Message_Ptr)) != (U32)-1L) {
u_long size, addr;
/*
* Wait for a response (Poll).
*/
while (*Reply_Ptr < I2O_EXEC_OUTBOUND_INIT_REJECTED);
/*
* Re-enable the interrupts.
*/
sc->ha_Virt->Mask = Old;
/*
* Populate the outbound table.
*/
if (sc->ha_Msgs == (PI2O_SCSI_ERROR_REPLY_MESSAGE_FRAME)NULL) {
/* Allocate the reply frames */
size = sizeof(I2O_SCSI_ERROR_REPLY_MESSAGE_FRAME)
* sc->ha_Msgs_Count;
/*
* contigmalloc only works reliably at
* initialization time.
*/
if ((sc->ha_Msgs = (PI2O_SCSI_ERROR_REPLY_MESSAGE_FRAME)
contigmalloc (size, M_DEVBUF, M_WAITOK, 0ul,
0xFFFFFFFFul, (u_long)sizeof(U32), 0ul))
!= (PI2O_SCSI_ERROR_REPLY_MESSAGE_FRAME)NULL) {
(void)bzero ((char *)sc->ha_Msgs, size);
sc->ha_Msgs_Phys = KVTOPHYS(sc->ha_Msgs);
}
}
/* Initialize the outbound FIFO */
if (sc->ha_Msgs != (PI2O_SCSI_ERROR_REPLY_MESSAGE_FRAME)NULL)
for (size = sc->ha_Msgs_Count, addr = sc->ha_Msgs_Phys;
size; --size) {
sc->ha_Virt->FromFIFO = addr;
addr += sizeof(I2O_SCSI_ERROR_REPLY_MESSAGE_FRAME);
}
return (*Reply_Ptr);
}
return (0);
} /* ASR_initOutBound */
/*
* Set the system table
*/
STATIC INLINE int
ASR_setSysTab(
IN Asr_softc_t * sc)
{
PI2O_EXEC_SYS_TAB_SET_MESSAGE Message_Ptr;
PI2O_SET_SYSTAB_HEADER SystemTable;
Asr_softc_t * ha;
PI2O_SGE_SIMPLE_ELEMENT sg;
int retVal;
if ((SystemTable = (PI2O_SET_SYSTAB_HEADER)malloc (
sizeof(I2O_SET_SYSTAB_HEADER), M_TEMP, M_WAITOK | M_ZERO))
== (PI2O_SET_SYSTAB_HEADER)NULL) {
return (ENOMEM);
}
for (ha = Asr_softc; ha; ha = ha->ha_next) {
++SystemTable->NumberEntries;
}
if ((Message_Ptr = (PI2O_EXEC_SYS_TAB_SET_MESSAGE)malloc (
sizeof(I2O_EXEC_SYS_TAB_SET_MESSAGE) - sizeof(I2O_SG_ELEMENT)
+ ((3+SystemTable->NumberEntries) * sizeof(I2O_SGE_SIMPLE_ELEMENT)),
M_TEMP, M_WAITOK)) == (PI2O_EXEC_SYS_TAB_SET_MESSAGE)NULL) {
free (SystemTable, M_TEMP);
return (ENOMEM);
}
(void)ASR_fillMessage((char *)Message_Ptr,
sizeof(I2O_EXEC_SYS_TAB_SET_MESSAGE) - sizeof(I2O_SG_ELEMENT)
+ ((3+SystemTable->NumberEntries) * sizeof(I2O_SGE_SIMPLE_ELEMENT)));
I2O_MESSAGE_FRAME_setVersionOffset(&(Message_Ptr->StdMessageFrame),
(I2O_VERSION_11 +
(((sizeof(I2O_EXEC_SYS_TAB_SET_MESSAGE) - sizeof(I2O_SG_ELEMENT))
/ sizeof(U32)) << 4)));
I2O_MESSAGE_FRAME_setFunction(&(Message_Ptr->StdMessageFrame),
I2O_EXEC_SYS_TAB_SET);
/*
* Call the LCT table to determine the number of device entries
* to reserve space for.
* since this code is reused in several systems, code efficiency
* is greater by using a shift operation rather than a divide by
* sizeof(u_int32_t).
*/
sg = (PI2O_SGE_SIMPLE_ELEMENT)((char *)Message_Ptr
+ ((I2O_MESSAGE_FRAME_getVersionOffset(
&(Message_Ptr->StdMessageFrame)) & 0xF0) >> 2));
SG(sg, 0, I2O_SGL_FLAGS_DIR, SystemTable, sizeof(I2O_SET_SYSTAB_HEADER));
++sg;
for (ha = Asr_softc; ha; ha = ha->ha_next) {
SG(sg, 0,
((ha->ha_next)
? (I2O_SGL_FLAGS_DIR)
: (I2O_SGL_FLAGS_DIR | I2O_SGL_FLAGS_END_OF_BUFFER)),
&(ha->ha_SystemTable), sizeof(ha->ha_SystemTable));
++sg;
}
SG(sg, 0, I2O_SGL_FLAGS_DIR | I2O_SGL_FLAGS_END_OF_BUFFER, NULL, 0);
SG(sg, 1, I2O_SGL_FLAGS_DIR | I2O_SGL_FLAGS_LAST_ELEMENT
| I2O_SGL_FLAGS_END_OF_BUFFER, NULL, 0);
retVal = ASR_queue_c(sc, (PI2O_MESSAGE_FRAME)Message_Ptr);
free (Message_Ptr, M_TEMP);
free (SystemTable, M_TEMP);
return (retVal);
} /* ASR_setSysTab */
STATIC INLINE int
ASR_acquireHrt (
INOUT Asr_softc_t * sc)
{
defAlignLong(I2O_EXEC_HRT_GET_MESSAGE,Message);
I2O_EXEC_HRT_GET_MESSAGE * Message_Ptr;
struct {
I2O_HRT Header;
I2O_HRT_ENTRY Entry[MAX_CHANNEL];
} Hrt;
u_int8_t NumberOfEntries;
PI2O_HRT_ENTRY Entry;
bzero ((void *)&Hrt, sizeof (Hrt));
Message_Ptr = (I2O_EXEC_HRT_GET_MESSAGE *)ASR_fillMessage(Message,
sizeof(I2O_EXEC_HRT_GET_MESSAGE) - sizeof(I2O_SG_ELEMENT)
+ sizeof(I2O_SGE_SIMPLE_ELEMENT));
I2O_MESSAGE_FRAME_setVersionOffset(&(Message_Ptr->StdMessageFrame),
(I2O_VERSION_11
+ (((sizeof(I2O_EXEC_HRT_GET_MESSAGE) - sizeof(I2O_SG_ELEMENT))
/ sizeof(U32)) << 4)));
I2O_MESSAGE_FRAME_setFunction (&(Message_Ptr->StdMessageFrame),
I2O_EXEC_HRT_GET);
/*
* Set up the buffers as scatter gather elements.
*/
SG(&(Message_Ptr->SGL), 0,
I2O_SGL_FLAGS_LAST_ELEMENT | I2O_SGL_FLAGS_END_OF_BUFFER,
&Hrt, sizeof(Hrt));
if (ASR_queue_c(sc, (PI2O_MESSAGE_FRAME)Message_Ptr) != CAM_REQ_CMP) {
return (ENODEV);
}
if ((NumberOfEntries = I2O_HRT_getNumberEntries(&Hrt.Header))
> (MAX_CHANNEL + 1)) {
NumberOfEntries = MAX_CHANNEL + 1;
}
for (Entry = Hrt.Header.HRTEntry;
NumberOfEntries != 0;
++Entry, --NumberOfEntries) {
PI2O_LCT_ENTRY Device;
for (Device = sc->ha_LCT->LCTEntry; Device < (PI2O_LCT_ENTRY)
(((U32 *)sc->ha_LCT)+I2O_LCT_getTableSize(sc->ha_LCT));
++Device) {
if (I2O_LCT_ENTRY_getLocalTID(Device)
== (I2O_HRT_ENTRY_getAdapterID(Entry) & 0xFFF)) {
Device->le_bus = I2O_HRT_ENTRY_getAdapterID(
Entry) >> 16;
if ((Device->le_bus > sc->ha_MaxBus)
&& (Device->le_bus <= MAX_CHANNEL)) {
sc->ha_MaxBus = Device->le_bus;
}
}
}
}
return (0);
} /* ASR_acquireHrt */
/*
* Enable the adapter.
*/
STATIC INLINE int
ASR_enableSys (
IN Asr_softc_t * sc)
{
defAlignLong(I2O_EXEC_SYS_ENABLE_MESSAGE,Message);
PI2O_EXEC_SYS_ENABLE_MESSAGE Message_Ptr;
Message_Ptr = (PI2O_EXEC_SYS_ENABLE_MESSAGE)ASR_fillMessage(Message,
sizeof(I2O_EXEC_SYS_ENABLE_MESSAGE));
I2O_MESSAGE_FRAME_setFunction(&(Message_Ptr->StdMessageFrame),
I2O_EXEC_SYS_ENABLE);
return (ASR_queue_c(sc, (PI2O_MESSAGE_FRAME)Message_Ptr) != 0);
} /* ASR_enableSys */
/*
* Perform the stages necessary to initialize the adapter
*/
STATIC int
ASR_init(
IN Asr_softc_t * sc)
{
return ((ASR_initOutBound(sc) == 0)
|| (ASR_setSysTab(sc) != CAM_REQ_CMP)
|| (ASR_enableSys(sc) != CAM_REQ_CMP));
} /* ASR_init */
/*
* Send a Synchronize Cache command to the target device.
*/
STATIC INLINE void
ASR_sync (
IN Asr_softc_t * sc,
IN int bus,
IN int target,
IN int lun)
{
tid_t TID;
/*
* We will not synchronize the device when there are outstanding
* commands issued by the OS (this is due to a locked up device,
* as the OS normally would flush all outstanding commands before
* issuing a shutdown or an adapter reset).
*/
if ((sc != (Asr_softc_t *)NULL)
&& (LIST_FIRST(&sc->ha_ccb) != (struct ccb_hdr *)NULL)
&& ((TID = ASR_getTid (sc, bus, target, lun)) != (tid_t)-1)
&& (TID != (tid_t)0)) {
defAlignLong(PRIVATE_SCSI_SCB_EXECUTE_MESSAGE,Message);
PPRIVATE_SCSI_SCB_EXECUTE_MESSAGE Message_Ptr;
bzero (Message_Ptr
= getAlignLong(PRIVATE_SCSI_SCB_EXECUTE_MESSAGE, Message),
sizeof(PRIVATE_SCSI_SCB_EXECUTE_MESSAGE)
- sizeof(I2O_SG_ELEMENT) + sizeof(I2O_SGE_SIMPLE_ELEMENT));
I2O_MESSAGE_FRAME_setVersionOffset(
(PI2O_MESSAGE_FRAME)Message_Ptr,
I2O_VERSION_11
| (((sizeof(PRIVATE_SCSI_SCB_EXECUTE_MESSAGE)
- sizeof(I2O_SG_ELEMENT))
/ sizeof(U32)) << 4));
I2O_MESSAGE_FRAME_setMessageSize(
(PI2O_MESSAGE_FRAME)Message_Ptr,
(sizeof(PRIVATE_SCSI_SCB_EXECUTE_MESSAGE)
- sizeof(I2O_SG_ELEMENT))
/ sizeof(U32));
I2O_MESSAGE_FRAME_setInitiatorAddress (
(PI2O_MESSAGE_FRAME)Message_Ptr, 1);
I2O_MESSAGE_FRAME_setFunction(
(PI2O_MESSAGE_FRAME)Message_Ptr, I2O_PRIVATE_MESSAGE);
I2O_MESSAGE_FRAME_setTargetAddress(
(PI2O_MESSAGE_FRAME)Message_Ptr, TID);
I2O_PRIVATE_MESSAGE_FRAME_setXFunctionCode (
(PI2O_PRIVATE_MESSAGE_FRAME)Message_Ptr,
I2O_SCSI_SCB_EXEC);
PRIVATE_SCSI_SCB_EXECUTE_MESSAGE_setTID(Message_Ptr, TID);
PRIVATE_SCSI_SCB_EXECUTE_MESSAGE_setSCBFlags (Message_Ptr,
I2O_SCB_FLAG_ENABLE_DISCONNECT
| I2O_SCB_FLAG_SIMPLE_QUEUE_TAG
| I2O_SCB_FLAG_SENSE_DATA_IN_BUFFER);
I2O_PRIVATE_MESSAGE_FRAME_setOrganizationID(
(PI2O_PRIVATE_MESSAGE_FRAME)Message_Ptr,
DPT_ORGANIZATION_ID);
PRIVATE_SCSI_SCB_EXECUTE_MESSAGE_setCDBLength(Message_Ptr, 6);
Message_Ptr->CDB[0] = SYNCHRONIZE_CACHE;
Message_Ptr->CDB[1] = (lun << 5);
PRIVATE_SCSI_SCB_EXECUTE_MESSAGE_setSCBFlags (Message_Ptr,
(I2O_SCB_FLAG_XFER_FROM_DEVICE
| I2O_SCB_FLAG_ENABLE_DISCONNECT
| I2O_SCB_FLAG_SIMPLE_QUEUE_TAG
| I2O_SCB_FLAG_SENSE_DATA_IN_BUFFER));
(void)ASR_queue_c(sc, (PI2O_MESSAGE_FRAME)Message_Ptr);
}
}
STATIC INLINE void
ASR_synchronize (
IN Asr_softc_t * sc)
{
int bus, target, lun;
for (bus = 0; bus <= sc->ha_MaxBus; ++bus) {
for (target = 0; target <= sc->ha_MaxId; ++target) {
for (lun = 0; lun <= sc->ha_MaxLun; ++lun) {
ASR_sync(sc,bus,target,lun);
}
}
}
}
/*
* Reset the HBA, targets and BUS.
* Currently this resets *all* the SCSI busses.
*/
STATIC INLINE void
asr_hbareset(
IN Asr_softc_t * sc)
{
ASR_synchronize (sc);
ASR_reset (sc);
} /* asr_hbareset */
/*
* A reduced copy of the real pci_map_mem, incorporating the MAX_MAP
* limit and a reduction in error checking (in the pre 4.0 case).
*/
STATIC int
asr_pci_map_mem (
#if __FreeBSD_version >= 400000
IN device_t tag,
#else
IN pcici_t tag,
#endif
IN Asr_softc_t * sc)
{
int rid;
u_int32_t p, l;
#if __FreeBSD_version >= 400000
/*
* I2O specification says we must find first *memory* mapped BAR
*/
for (rid = PCIR_MAPS;
rid < (PCIR_MAPS + 4 * sizeof(u_int32_t));
++rid) {
p = pci_read_config(tag, rid, sizeof(p));
if ((p & 1) == 0) {
break;
}
}
/*
* Give up?
*/
if (rid >= (PCIR_MAPS + 4 * sizeof(u_int32_t))) {
rid = PCIR_MAPS;
}
p = pci_read_config(tag, rid, sizeof(p));
pci_write_config(tag, rid, -1, sizeof(p));
l = 0 - (pci_read_config(tag, rid, sizeof(l)) & ~15);
pci_write_config(tag, rid, p, sizeof(p));
if (l > MAX_MAP) {
l = MAX_MAP;
}
p &= ~15;
sc->ha_mem_res = bus_alloc_resource(tag, SYS_RES_MEMORY, &rid,
p, p + l, l, RF_ACTIVE);
if (sc->ha_mem_res == (struct resource *)NULL) {
return (0);
}
sc->ha_Base = (void *)rman_get_start(sc->ha_mem_res);
if (sc->ha_Base == (void *)NULL) {
return (0);
}
sc->ha_Virt = (i2oRegs_t *) rman_get_virtual(sc->ha_mem_res);
#else
vm_size_t psize, poffs;
/*
* I2O specification says we must find first *memory* mapped BAR
*/
for (rid = PCI_MAP_REG_START;
rid < (PCI_MAP_REG_START + 4 * sizeof(u_int32_t));
++rid) {
p = pci_conf_read (tag, rid);
if ((p & 1) == 0) {
break;
}
}
if (rid >= (PCI_MAP_REG_START + 4 * sizeof(u_int32_t))) {
rid = PCI_MAP_REG_START;
}
/*
** save old mapping, get size and type of memory
**
** type is in the lowest four bits.
** If device requires 2^n bytes, the next
** n-4 bits are read as 0.
*/
sc->ha_Base = (void *)((p = pci_conf_read (tag, rid))
& PCI_MAP_MEMORY_ADDRESS_MASK);
pci_conf_write (tag, rid, 0xfffffffful);
l = pci_conf_read (tag, rid);
pci_conf_write (tag, rid, p);
/*
** check the type
*/
if (!((l & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_32BIT_1M
&& ((u_long)sc->ha_Base & ~0xfffff) == 0)
&& ((l & PCI_MAP_MEMORY_TYPE_MASK) != PCI_MAP_MEMORY_TYPE_32BIT)) {
debug_asr_printf (
"asr_pci_map_mem failed: bad memory type=0x%x\n",
(unsigned) l);
return (0);
};
/*
** get the size.
*/
psize = -(l & PCI_MAP_MEMORY_ADDRESS_MASK);
if (psize > MAX_MAP) {
psize = MAX_MAP;
}
if ((sc->ha_Base == (void *)NULL)
|| (sc->ha_Base == (void *)PCI_MAP_MEMORY_ADDRESS_MASK)) {
debug_asr_printf ("asr_pci_map_mem: not configured by bios.\n");
return (0);
};
/*
** Truncate sc->ha_Base to page boundary.
** (Or does pmap_mapdev the job?)
*/
poffs = (u_long)sc->ha_Base - trunc_page ((u_long)sc->ha_Base);
sc->ha_Virt = (i2oRegs_t *)pmap_mapdev ((u_long)sc->ha_Base - poffs,
psize + poffs);
if (sc->ha_Virt == (i2oRegs_t *)NULL) {
return (0);
}
sc->ha_Virt = (i2oRegs_t *)((u_long)sc->ha_Virt + poffs);
#endif
return (1);
} /* asr_pci_map_mem */
/*
* A simplified copy of the real pci_map_int with additional
* registration requirements.
*/
STATIC int
asr_pci_map_int (
#if __FreeBSD_version >= 400000
IN device_t tag,
#else
IN pcici_t tag,
#endif
IN Asr_softc_t * sc)
{
#if __FreeBSD_version >= 400000
int rid = 0;
sc->ha_irq_res = bus_alloc_resource(tag, SYS_RES_IRQ, &rid,
0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
if (sc->ha_irq_res == (struct resource *)NULL) {
return (0);
}
if (bus_setup_intr(tag, sc->ha_irq_res, INTR_TYPE_CAM,
(driver_intr_t *)asr_intr, (void *)sc, &(sc->ha_intr))) {
return (0);
}
sc->ha_irq = pci_read_config(tag, PCIR_INTLINE, sizeof(char));
#else
if (!pci_map_int(tag, (pci_inthand_t *)asr_intr,
(void *)sc, &cam_imask)) {
return (0);
}
sc->ha_irq = pci_conf_read(tag, PCIR_INTLINE);
#endif
return (1);
} /* asr_pci_map_int */
/*
* Attach the devices, and virtual devices to the driver list.
*/
STATIC ATTACH_RET
asr_attach (ATTACH_ARGS)
{
Asr_softc_t * sc;
struct scsi_inquiry_data * iq;
ATTACH_SET();
if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO)) ==
(Asr_softc_t *)NULL)
{
ATTACH_RETURN(ENOMEM);
}
if (Asr_softc == (Asr_softc_t *)NULL) {
/*
* Fixup the OS revision as saved in the dptsig for the
* engine (dptioctl.h) to pick up.
*/
bcopy (osrelease, &ASR_sig.dsDescription[16], 5);
printf ("asr%d: major=%d\n", unit, asr_cdevsw.d_maj);
}
/*
* Initialize the software structure
*/
LIST_INIT(&sc->ha_ccb);
# ifdef ASR_MEASURE_PERFORMANCE
{
u_int32_t i;
// initialize free list for timeQ
sc->ha_timeQFreeHead = 0;
sc->ha_timeQFreeTail = MAX_TIMEQ_SIZE - 1;
for (i = 0; i < MAX_TIMEQ_SIZE; i++) {
sc->ha_timeQFreeList[i] = i;
}
}
# endif
/* Link us into the HA list */
{
Asr_softc_t **ha;
for (ha = &Asr_softc; *ha; ha = &((*ha)->ha_next));
*(ha) = sc;
}
{
PI2O_EXEC_STATUS_GET_REPLY status;
int size;
/*
* This is the real McCoy!
*/
if (!asr_pci_map_mem(tag, sc)) {
printf ("asr%d: could not map memory\n", unit);
ATTACH_RETURN(ENXIO);
}
/* Enable if not formerly enabled */
#if __FreeBSD_version >= 400000
pci_write_config (tag, PCIR_COMMAND,
pci_read_config (tag, PCIR_COMMAND, sizeof(char))
| PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN, sizeof(char));
/* Knowledge is power, responsibility is direct */
{
struct pci_devinfo {
STAILQ_ENTRY(pci_devinfo) pci_links;
struct resource_list resources;
pcicfgregs cfg;
} * dinfo = device_get_ivars(tag);
sc->ha_pciBusNum = dinfo->cfg.bus;
sc->ha_pciDeviceNum = (dinfo->cfg.slot << 3)
| dinfo->cfg.func;
}
#else
pci_conf_write (tag, PCIR_COMMAND,
pci_conf_read (tag, PCIR_COMMAND)
| PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
/* Knowledge is power, responsibility is direct */
switch (pci_mechanism) {
case 1:
sc->ha_pciBusNum = tag.cfg1 >> 16;
sc->ha_pciDeviceNum = tag.cfg1 >> 8;
case 2:
sc->ha_pciBusNum = tag.cfg2.forward;
sc->ha_pciDeviceNum = ((tag.cfg2.enable >> 1) & 7)
| (tag.cfg2.port >> 5);
}
#endif
/* Check if the device is there? */
if ((ASR_resetIOP(sc->ha_Virt) == 0)
|| ((status = (PI2O_EXEC_STATUS_GET_REPLY)malloc (
sizeof(I2O_EXEC_STATUS_GET_REPLY), M_TEMP, M_WAITOK))
== (PI2O_EXEC_STATUS_GET_REPLY)NULL)
|| (ASR_getStatus(sc->ha_Virt, status) == NULL)) {
printf ("asr%d: could not initialize hardware\n", unit);
ATTACH_RETURN(ENODEV); /* Get next, maybe better luck */
}
sc->ha_SystemTable.OrganizationID = status->OrganizationID;
sc->ha_SystemTable.IOP_ID = status->IOP_ID;
sc->ha_SystemTable.I2oVersion = status->I2oVersion;
sc->ha_SystemTable.IopState = status->IopState;
sc->ha_SystemTable.MessengerType = status->MessengerType;
sc->ha_SystemTable.InboundMessageFrameSize
= status->InboundMFrameSize;
sc->ha_SystemTable.MessengerInfo.InboundMessagePortAddressLow
= (U32)(sc->ha_Base) + (U32)(&(((i2oRegs_t *)NULL)->ToFIFO));
if (!asr_pci_map_int(tag, (void *)sc)) {
printf ("asr%d: could not map interrupt\n", unit);
ATTACH_RETURN(ENXIO);
}
/* Adjust the maximim inbound count */
if (((sc->ha_QueueSize
= I2O_EXEC_STATUS_GET_REPLY_getMaxInboundMFrames(status))
> MAX_INBOUND)
|| (sc->ha_QueueSize == 0)) {
sc->ha_QueueSize = MAX_INBOUND;
}
/* Adjust the maximum outbound count */
if (((sc->ha_Msgs_Count
= I2O_EXEC_STATUS_GET_REPLY_getMaxOutboundMFrames(status))
> MAX_OUTBOUND)
|| (sc->ha_Msgs_Count == 0)) {
sc->ha_Msgs_Count = MAX_OUTBOUND;
}
if (sc->ha_Msgs_Count > sc->ha_QueueSize) {
sc->ha_Msgs_Count = sc->ha_QueueSize;
}
/* Adjust the maximum SG size to adapter */
if ((size = (I2O_EXEC_STATUS_GET_REPLY_getInboundMFrameSize(
status) << 2)) > MAX_INBOUND_SIZE) {
size = MAX_INBOUND_SIZE;
}
free (status, M_TEMP);
sc->ha_SgSize = (size - sizeof(PRIVATE_SCSI_SCB_EXECUTE_MESSAGE)
+ sizeof(I2O_SG_ELEMENT)) / sizeof(I2O_SGE_SIMPLE_ELEMENT);
}
/*
* Only do a bus/HBA reset on the first time through. On this
* first time through, we do not send a flush to the devices.
*/
if (ASR_init(sc) == 0) {
struct BufferInfo {
I2O_PARAM_RESULTS_LIST_HEADER Header;
I2O_PARAM_READ_OPERATION_RESULT Read;
I2O_DPT_EXEC_IOP_BUFFERS_SCALAR Info;
};
defAlignLong (struct BufferInfo, Buffer);
PI2O_DPT_EXEC_IOP_BUFFERS_SCALAR Info;
# define FW_DEBUG_BLED_OFFSET 8
if ((Info = (PI2O_DPT_EXEC_IOP_BUFFERS_SCALAR)
ASR_getParams(sc, 0,
I2O_DPT_EXEC_IOP_BUFFERS_GROUP_NO,
Buffer, sizeof(struct BufferInfo)))
!= (PI2O_DPT_EXEC_IOP_BUFFERS_SCALAR)NULL) {
sc->ha_blinkLED = sc->ha_Virt->Address
+ I2O_DPT_EXEC_IOP_BUFFERS_SCALAR_getSerialOutputOffset(Info)
+ FW_DEBUG_BLED_OFFSET;
}
if (ASR_acquireLct(sc) == 0) {
(void)ASR_acquireHrt(sc);
}
} else {
printf ("asr%d: failed to initialize\n", unit);
ATTACH_RETURN(ENXIO);
}
/*
* Add in additional probe responses for more channels. We
* are reusing the variable `target' for a channel loop counter.
* Done here because of we need both the acquireLct and
* acquireHrt data.
*/
{ PI2O_LCT_ENTRY Device;
for (Device = sc->ha_LCT->LCTEntry; Device < (PI2O_LCT_ENTRY)
(((U32 *)sc->ha_LCT)+I2O_LCT_getTableSize(sc->ha_LCT));
++Device) {
if (Device->le_type == I2O_UNKNOWN) {
continue;
}
if (I2O_LCT_ENTRY_getUserTID(Device) == 0xFFF) {
if (Device->le_target > sc->ha_MaxId) {
sc->ha_MaxId = Device->le_target;
}
if (Device->le_lun > sc->ha_MaxLun) {
sc->ha_MaxLun = Device->le_lun;
}
}
if (((Device->le_type & I2O_PORT) != 0)
&& (Device->le_bus <= MAX_CHANNEL)) {
/* Do not increase MaxId for efficiency */
sc->ha_adapter_target[Device->le_bus]
= Device->le_target;
}
}
}
/*
* Print the HBA model number as inquired from the card.
*/
printf ("asr%d:", unit);
if ((iq = (struct scsi_inquiry_data *)malloc (
sizeof(struct scsi_inquiry_data), M_TEMP, M_WAITOK | M_ZERO))
!= (struct scsi_inquiry_data *)NULL) {
defAlignLong(PRIVATE_SCSI_SCB_EXECUTE_MESSAGE,Message);
PPRIVATE_SCSI_SCB_EXECUTE_MESSAGE Message_Ptr;
int posted = 0;
bzero (Message_Ptr
= getAlignLong(PRIVATE_SCSI_SCB_EXECUTE_MESSAGE, Message),
sizeof(PRIVATE_SCSI_SCB_EXECUTE_MESSAGE)
- sizeof(I2O_SG_ELEMENT) + sizeof(I2O_SGE_SIMPLE_ELEMENT));
I2O_MESSAGE_FRAME_setVersionOffset(
(PI2O_MESSAGE_FRAME)Message_Ptr,
I2O_VERSION_11
| (((sizeof(PRIVATE_SCSI_SCB_EXECUTE_MESSAGE)
- sizeof(I2O_SG_ELEMENT))
/ sizeof(U32)) << 4));
I2O_MESSAGE_FRAME_setMessageSize(
(PI2O_MESSAGE_FRAME)Message_Ptr,
(sizeof(PRIVATE_SCSI_SCB_EXECUTE_MESSAGE)
- sizeof(I2O_SG_ELEMENT) + sizeof(I2O_SGE_SIMPLE_ELEMENT))
/ sizeof(U32));
I2O_MESSAGE_FRAME_setInitiatorAddress (
(PI2O_MESSAGE_FRAME)Message_Ptr, 1);
I2O_MESSAGE_FRAME_setFunction(
(PI2O_MESSAGE_FRAME)Message_Ptr, I2O_PRIVATE_MESSAGE);
I2O_PRIVATE_MESSAGE_FRAME_setXFunctionCode (
(PI2O_PRIVATE_MESSAGE_FRAME)Message_Ptr,
I2O_SCSI_SCB_EXEC);
PRIVATE_SCSI_SCB_EXECUTE_MESSAGE_setSCBFlags (Message_Ptr,
I2O_SCB_FLAG_ENABLE_DISCONNECT
| I2O_SCB_FLAG_SIMPLE_QUEUE_TAG
| I2O_SCB_FLAG_SENSE_DATA_IN_BUFFER);
PRIVATE_SCSI_SCB_EXECUTE_MESSAGE_setInterpret(Message_Ptr, 1);
I2O_PRIVATE_MESSAGE_FRAME_setOrganizationID(
(PI2O_PRIVATE_MESSAGE_FRAME)Message_Ptr,
DPT_ORGANIZATION_ID);
PRIVATE_SCSI_SCB_EXECUTE_MESSAGE_setCDBLength(Message_Ptr, 6);
Message_Ptr->CDB[0] = INQUIRY;
Message_Ptr->CDB[4] = (unsigned char)sizeof(struct scsi_inquiry_data);
if (Message_Ptr->CDB[4] == 0) {
Message_Ptr->CDB[4] = 255;
}
PRIVATE_SCSI_SCB_EXECUTE_MESSAGE_setSCBFlags (Message_Ptr,
(I2O_SCB_FLAG_XFER_FROM_DEVICE
| I2O_SCB_FLAG_ENABLE_DISCONNECT
| I2O_SCB_FLAG_SIMPLE_QUEUE_TAG
| I2O_SCB_FLAG_SENSE_DATA_IN_BUFFER));
PRIVATE_SCSI_SCB_EXECUTE_MESSAGE_setByteCount(
(PPRIVATE_SCSI_SCB_EXECUTE_MESSAGE)Message_Ptr,
sizeof(struct scsi_inquiry_data));
SG(&(Message_Ptr->SGL), 0,
I2O_SGL_FLAGS_LAST_ELEMENT | I2O_SGL_FLAGS_END_OF_BUFFER,
iq, sizeof(struct scsi_inquiry_data));
(void)ASR_queue_c(sc, (PI2O_MESSAGE_FRAME)Message_Ptr);
if (iq->vendor[0] && (iq->vendor[0] != ' ')) {
printf (" ");
ASR_prstring (iq->vendor, 8);
++posted;
}
if (iq->product[0] && (iq->product[0] != ' ')) {
printf (" ");
ASR_prstring (iq->product, 16);
++posted;
}
if (iq->revision[0] && (iq->revision[0] != ' ')) {
printf (" FW Rev. ");
ASR_prstring (iq->revision, 4);
++posted;
}
free ((caddr_t)iq, M_TEMP);
if (posted) {
printf (",");
}
}
printf (" %d channel, %d CCBs, Protocol I2O\n", sc->ha_MaxBus + 1,
(sc->ha_QueueSize > MAX_INBOUND) ? MAX_INBOUND : sc->ha_QueueSize);
/*
* fill in the prototype cam_path.
*/
{
int bus;
union asr_ccb * ccb;
if ((ccb = asr_alloc_ccb (sc)) == (union asr_ccb *)NULL) {
printf ("asr%d: CAM could not be notified of asynchronous callback parameters\n", unit);
ATTACH_RETURN(ENOMEM);
}
for (bus = 0; bus <= sc->ha_MaxBus; ++bus) {
struct cam_devq * devq;
int QueueSize = sc->ha_QueueSize;
if (QueueSize > MAX_INBOUND) {
QueueSize = MAX_INBOUND;
}
/*
* Create the device queue for our SIM(s).
*/
if ((devq = cam_simq_alloc(QueueSize)) == NULL) {
continue;
}
/*
* Construct our first channel SIM entry
*/
sc->ha_sim[bus] = cam_sim_alloc(
asr_action, asr_poll, "asr", sc,
unit, 1, QueueSize, devq);
if (sc->ha_sim[bus] == NULL) {
continue;
}
if (xpt_bus_register(sc->ha_sim[bus], bus)
!= CAM_SUCCESS) {
cam_sim_free(sc->ha_sim[bus],
/*free_devq*/TRUE);
sc->ha_sim[bus] = NULL;
continue;
}
if (xpt_create_path(&(sc->ha_path[bus]), /*periph*/NULL,
cam_sim_path(sc->ha_sim[bus]), CAM_TARGET_WILDCARD,
CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
xpt_bus_deregister(
cam_sim_path(sc->ha_sim[bus]));
cam_sim_free(sc->ha_sim[bus],
/*free_devq*/TRUE);
sc->ha_sim[bus] = NULL;
continue;
}
xpt_setup_ccb(&(ccb->ccb_h),
sc->ha_path[bus], /*priority*/5);
ccb->ccb_h.func_code = XPT_SASYNC_CB;
ccb->csa.event_enable = AC_LOST_DEVICE;
ccb->csa.callback = asr_async;
ccb->csa.callback_arg = sc->ha_sim[bus];
xpt_action((union ccb *)ccb);
}
asr_free_ccb (ccb);
}
/*
* Generate the device node information
*/
(void)make_dev(&asr_cdevsw, unit, 0, 0, S_IRWXU, "rasr%d", unit);
destroy_dev(makedev(asr_cdevsw.d_maj,unit+1));
ATTACH_RETURN(0);
} /* asr_attach */
#if (!defined(UNREFERENCED_PARAMETER))
# define UNREFERENCED_PARAMETER(x) (void)(x)
#endif
STATIC void
asr_async(
void * callback_arg,
u_int32_t code,
struct cam_path * path,
void * arg)
{
UNREFERENCED_PARAMETER(callback_arg);
UNREFERENCED_PARAMETER(code);
UNREFERENCED_PARAMETER(path);
UNREFERENCED_PARAMETER(arg);
} /* asr_async */
STATIC void
asr_poll(
IN struct cam_sim *sim)
{
asr_intr(cam_sim_softc(sim));
} /* asr_poll */
STATIC void
asr_action(
IN struct cam_sim * sim,
IN union ccb * ccb)
{
struct Asr_softc * sc;
debug_asr_printf ("asr_action(%lx,%lx{%x})\n",
(u_long)sim, (u_long)ccb, ccb->ccb_h.func_code);
CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("asr_action\n"));
ccb->ccb_h.spriv_ptr0 = sc = (struct Asr_softc *)cam_sim_softc(sim);
switch (ccb->ccb_h.func_code) {
/* Common cases first */
case XPT_SCSI_IO: /* Execute the requested I/O operation */
{
struct Message {
char M[MAX_INBOUND_SIZE];
};
defAlignLong(struct Message,Message);
PI2O_MESSAGE_FRAME Message_Ptr;
if (ccb->ccb_h.status != CAM_REQ_INPROG) {
printf(
"asr%d WARNING: scsi_cmd(%x) already done on b%dt%du%d\n",
cam_sim_unit(xpt_path_sim(ccb->ccb_h.path)),
ccb->csio.cdb_io.cdb_bytes[0],
cam_sim_bus(sim),
ccb->ccb_h.target_id,
ccb->ccb_h.target_lun);
}
debug_asr_cmd_printf ("(%d,%d,%d,%d)",
cam_sim_unit(sim),
cam_sim_bus(sim),
ccb->ccb_h.target_id,
ccb->ccb_h.target_lun);
debug_asr_cmd_dump_ccb(ccb);
if ((Message_Ptr = ASR_init_message ((union asr_ccb *)ccb,
(PI2O_MESSAGE_FRAME)Message)) != (PI2O_MESSAGE_FRAME)NULL) {
debug_asr_cmd2_printf ("TID=%x:\n",
PRIVATE_SCSI_SCB_EXECUTE_MESSAGE_getTID(
(PPRIVATE_SCSI_SCB_EXECUTE_MESSAGE)Message_Ptr));
debug_asr_cmd2_dump_message(Message_Ptr);
debug_asr_cmd1_printf (" q");
if (ASR_queue (sc, Message_Ptr) == EMPTY_QUEUE) {
#ifdef ASR_MEASURE_PERFORMANCE
++sc->ha_performance.command_too_busy;
#endif
ccb->ccb_h.status &= ~CAM_STATUS_MASK;
ccb->ccb_h.status |= CAM_REQUEUE_REQ;
debug_asr_cmd_printf (" E\n");
xpt_done(ccb);
}
debug_asr_cmd_printf (" Q\n");
break;
}
/*
* We will get here if there is no valid TID for the device
* referenced in the scsi command packet.
*/
ccb->ccb_h.status &= ~CAM_STATUS_MASK;
ccb->ccb_h.status |= CAM_SEL_TIMEOUT;
debug_asr_cmd_printf (" B\n");
xpt_done(ccb);
break;
}
case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
/* Rese HBA device ... */
asr_hbareset (sc);
ccb->ccb_h.status = CAM_REQ_CMP;
xpt_done(ccb);
break;
# if (defined(REPORT_LUNS))
case REPORT_LUNS:
# endif
case XPT_ABORT: /* Abort the specified CCB */
/* XXX Implement */
ccb->ccb_h.status = CAM_REQ_INVALID;
xpt_done(ccb);
break;
case XPT_SET_TRAN_SETTINGS:
/* XXX Implement */
ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
xpt_done(ccb);
break;
case XPT_GET_TRAN_SETTINGS:
/* Get default/user set transfer settings for the target */
{
struct ccb_trans_settings *cts;
u_int target_mask;
cts = &ccb->cts;
target_mask = 0x01 << ccb->ccb_h.target_id;
if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) {
cts->flags = CCB_TRANS_DISC_ENB|CCB_TRANS_TAG_ENB;
cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
cts->sync_period = 6; /* 40MHz */
cts->sync_offset = 15;
cts->valid = CCB_TRANS_SYNC_RATE_VALID
| CCB_TRANS_SYNC_OFFSET_VALID
| CCB_TRANS_BUS_WIDTH_VALID
| CCB_TRANS_DISC_VALID
| CCB_TRANS_TQ_VALID;
ccb->ccb_h.status = CAM_REQ_CMP;
} else {
ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
}
xpt_done(ccb);
break;
}
case XPT_CALC_GEOMETRY:
{
struct ccb_calc_geometry *ccg;
u_int32_t size_mb;
u_int32_t secs_per_cylinder;
ccg = &ccb->ccg;
size_mb = ccg->volume_size
/ ((1024L * 1024L) / ccg->block_size);
if (size_mb > 4096) {
ccg->heads = 255;
ccg->secs_per_track = 63;
} else if (size_mb > 2048) {
ccg->heads = 128;
ccg->secs_per_track = 63;
} else if (size_mb > 1024) {
ccg->heads = 65;
ccg->secs_per_track = 63;
} else {
ccg->heads = 64;
ccg->secs_per_track = 32;
}
secs_per_cylinder = ccg->heads * ccg->secs_per_track;
ccg->cylinders = ccg->volume_size / secs_per_cylinder;
ccb->ccb_h.status = CAM_REQ_CMP;
xpt_done(ccb);
break;
}
case XPT_RESET_BUS: /* Reset the specified SCSI bus */
ASR_resetBus (sc, cam_sim_bus(sim));
ccb->ccb_h.status = CAM_REQ_CMP;
xpt_done(ccb);
break;
case XPT_TERM_IO: /* Terminate the I/O process */
/* XXX Implement */
ccb->ccb_h.status = CAM_REQ_INVALID;
xpt_done(ccb);
break;
case XPT_PATH_INQ: /* Path routing inquiry */
{
struct ccb_pathinq *cpi = &ccb->cpi;
cpi->version_num = 1; /* XXX??? */
cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE|PI_WIDE_16;
cpi->target_sprt = 0;
/* Not necessary to reset bus, done by HDM initialization */
cpi->hba_misc = PIM_NOBUSRESET;
cpi->hba_eng_cnt = 0;
cpi->max_target = sc->ha_MaxId;
cpi->max_lun = sc->ha_MaxLun;
cpi->initiator_id = sc->ha_adapter_target[cam_sim_bus(sim)];
cpi->bus_id = cam_sim_bus(sim);
cpi->base_transfer_speed = 3300;
strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
strncpy(cpi->hba_vid, "Adaptec", HBA_IDLEN);
strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
cpi->unit_number = cam_sim_unit(sim);
cpi->ccb_h.status = CAM_REQ_CMP;
xpt_done(ccb);
break;
}
default:
ccb->ccb_h.status = CAM_REQ_INVALID;
xpt_done(ccb);
break;
}
} /* asr_action */
#ifdef ASR_MEASURE_PERFORMANCE
#define WRITE_OP 1
#define READ_OP 2
#define min_submitR sc->ha_performance.read_by_size_min_time[index]
#define max_submitR sc->ha_performance.read_by_size_max_time[index]
#define min_submitW sc->ha_performance.write_by_size_min_time[index]
#define max_submitW sc->ha_performance.write_by_size_max_time[index]
STATIC INLINE void
asr_IObySize(
IN Asr_softc_t * sc,
IN u_int32_t submitted_time,
IN int op,
IN int index)
{
struct timeval submitted_timeval;
submitted_timeval.tv_sec = 0;
submitted_timeval.tv_usec = submitted_time;
if ( op == READ_OP ) {
++sc->ha_performance.read_by_size_count[index];
if ( submitted_time != 0xffffffff ) {
timevaladd(
&sc->ha_performance.read_by_size_total_time[index],
&submitted_timeval);
if ( (min_submitR == 0)
|| (submitted_time < min_submitR) ) {
min_submitR = submitted_time;
}
if ( submitted_time > max_submitR ) {
max_submitR = submitted_time;
}
}
} else {
++sc->ha_performance.write_by_size_count[index];
if ( submitted_time != 0xffffffff ) {
timevaladd(
&sc->ha_performance.write_by_size_total_time[index],
&submitted_timeval);
if ( (submitted_time < min_submitW)
|| (min_submitW == 0) ) {
min_submitW = submitted_time;
}
if ( submitted_time > max_submitW ) {
max_submitW = submitted_time;
}
}
}
} /* asr_IObySize */
#endif
/*
* Handle processing of current CCB as pointed to by the Status.
*/
STATIC int
asr_intr (
IN Asr_softc_t * sc)
{
OUT int processed;
#ifdef ASR_MEASURE_PERFORMANCE
struct timeval junk;
microtime(&junk);
sc->ha_performance.intr_started = junk;
#endif
for (processed = 0;
sc->ha_Virt->Status & Mask_InterruptsDisabled;
processed = 1) {
union asr_ccb * ccb;
U32 ReplyOffset;
PI2O_SCSI_ERROR_REPLY_MESSAGE_FRAME Reply;
if (((ReplyOffset = sc->ha_Virt->FromFIFO) == EMPTY_QUEUE)
&& ((ReplyOffset = sc->ha_Virt->FromFIFO) == EMPTY_QUEUE)) {
break;
}
Reply = (PI2O_SCSI_ERROR_REPLY_MESSAGE_FRAME)(ReplyOffset
- sc->ha_Msgs_Phys + (char *)(sc->ha_Msgs));
/*
* We do not need any (optional byteswapping) method access to
* the Initiator context field.
*/
ccb = (union asr_ccb *)(long)
I2O_MESSAGE_FRAME_getInitiatorContext64(
&(Reply->StdReplyFrame.StdMessageFrame));
if (I2O_MESSAGE_FRAME_getMsgFlags(
&(Reply->StdReplyFrame.StdMessageFrame))
& I2O_MESSAGE_FLAGS_FAIL) {
defAlignLong(I2O_UTIL_NOP_MESSAGE,Message);
PI2O_UTIL_NOP_MESSAGE Message_Ptr;
U32 MessageOffset;
MessageOffset = (u_long)
I2O_FAILURE_REPLY_MESSAGE_FRAME_getPreservedMFA(
(PI2O_FAILURE_REPLY_MESSAGE_FRAME)Reply);
/*
* Get the Original Message Frame's address, and get
* it's Transaction Context into our space. (Currently
* unused at original authorship, but better to be
* safe than sorry). Straight copy means that we
* need not concern ourselves with the (optional
* byteswapping) method access.
*/
Reply->StdReplyFrame.TransactionContext
= ((PI2O_SINGLE_REPLY_MESSAGE_FRAME)
(sc->ha_Virt->Address + MessageOffset))
->TransactionContext;
/*
* For 64 bit machines, we need to reconstruct the
* 64 bit context.
*/
ccb = (union asr_ccb *)(long)
I2O_MESSAGE_FRAME_getInitiatorContext64(
&(Reply->StdReplyFrame.StdMessageFrame));
/*
* Unique error code for command failure.
*/
I2O_SINGLE_REPLY_MESSAGE_FRAME_setDetailedStatusCode(
&(Reply->StdReplyFrame), (u_int16_t)-2);
/*
* Modify the message frame to contain a NOP and
* re-issue it to the controller.
*/
Message_Ptr = (PI2O_UTIL_NOP_MESSAGE)ASR_fillMessage(
Message, sizeof(I2O_UTIL_NOP_MESSAGE));
# if (I2O_UTIL_NOP != 0)
I2O_MESSAGE_FRAME_setFunction (
&(Message_Ptr->StdMessageFrame),
I2O_UTIL_NOP);
# endif
/*
* Copy the packet out to the Original Message
*/
bcopy ((caddr_t)Message_Ptr,
sc->ha_Virt->Address + MessageOffset,
sizeof(I2O_UTIL_NOP_MESSAGE));
/*
* Issue the NOP
*/
sc->ha_Virt->ToFIFO = MessageOffset;
}
/*
* Asynchronous command with no return requirements,
* and a generic handler for immunity against odd error
* returns from the adapter.
*/
if (ccb == (union asr_ccb *)NULL) {
/*
* Return Reply so that it can be used for the
* next command
*/
sc->ha_Virt->FromFIFO = ReplyOffset;
continue;
}
/* Welease Wadjah! (and stop timeouts) */
ASR_ccbRemove (sc, ccb);
switch (
I2O_SINGLE_REPLY_MESSAGE_FRAME_getDetailedStatusCode(
&(Reply->StdReplyFrame))) {
case I2O_SCSI_DSC_SUCCESS:
ccb->ccb_h.status &= ~CAM_STATUS_MASK;
ccb->ccb_h.status |= CAM_REQ_CMP;
break;
case I2O_SCSI_DSC_CHECK_CONDITION:
ccb->ccb_h.status &= ~CAM_STATUS_MASK;
ccb->ccb_h.status |= CAM_REQ_CMP|CAM_AUTOSNS_VALID;
break;
case I2O_SCSI_DSC_BUSY:
/* FALLTHRU */
case I2O_SCSI_HBA_DSC_ADAPTER_BUSY:
/* FALLTHRU */
case I2O_SCSI_HBA_DSC_SCSI_BUS_RESET:
/* FALLTHRU */
case I2O_SCSI_HBA_DSC_BUS_BUSY:
ccb->ccb_h.status &= ~CAM_STATUS_MASK;
ccb->ccb_h.status |= CAM_SCSI_BUSY;
break;
case I2O_SCSI_HBA_DSC_SELECTION_TIMEOUT:
ccb->ccb_h.status &= ~CAM_STATUS_MASK;
ccb->ccb_h.status |= CAM_SEL_TIMEOUT;
break;
case I2O_SCSI_HBA_DSC_COMMAND_TIMEOUT:
/* FALLTHRU */
case I2O_SCSI_HBA_DSC_DEVICE_NOT_PRESENT:
/* FALLTHRU */
case I2O_SCSI_HBA_DSC_LUN_INVALID:
/* FALLTHRU */
case I2O_SCSI_HBA_DSC_SCSI_TID_INVALID:
ccb->ccb_h.status &= ~CAM_STATUS_MASK;
ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
break;
case I2O_SCSI_HBA_DSC_DATA_OVERRUN:
/* FALLTHRU */
case I2O_SCSI_HBA_DSC_REQUEST_LENGTH_ERROR:
ccb->ccb_h.status &= ~CAM_STATUS_MASK;
ccb->ccb_h.status |= CAM_DATA_RUN_ERR;
break;
default:
ccb->ccb_h.status &= ~CAM_STATUS_MASK;
ccb->ccb_h.status |= CAM_REQUEUE_REQ;
break;
}
if ((ccb->csio.resid = ccb->csio.dxfer_len) != 0) {
ccb->csio.resid -=
I2O_SCSI_ERROR_REPLY_MESSAGE_FRAME_getTransferCount(
Reply);
}
#ifdef ASR_MEASURE_PERFORMANCE
{
struct timeval endTime;
u_int32_t submitted_time;
u_int32_t size;
int op_type;
int startTimeIndex;
--sc->ha_submitted_ccbs_count;
startTimeIndex
= (int)Reply->StdReplyFrame.TransactionContext;
if (-1 != startTimeIndex) {
/* Compute the time spent in device/adapter */
microtime(&endTime);
submitted_time = asr_time_delta(sc->ha_timeQ[
startTimeIndex], endTime);
/* put the startTimeIndex back on free list */
ENQ_TIMEQ_FREE_LIST(startTimeIndex,
sc->ha_timeQFreeList,
sc->ha_timeQFreeHead,
sc->ha_timeQFreeTail);
} else {
submitted_time = 0xffffffff;
}
#define maxctime sc->ha_performance.max_command_time[ccb->csio.cdb_io.cdb_bytes[0]]
#define minctime sc->ha_performance.min_command_time[ccb->csio.cdb_io.cdb_bytes[0]]
if (submitted_time != 0xffffffff) {
if ( maxctime < submitted_time ) {
maxctime = submitted_time;
}
if ( (minctime == 0)
|| (minctime > submitted_time) ) {
minctime = submitted_time;
}
if ( sc->ha_performance.max_submit_time
< submitted_time ) {
sc->ha_performance.max_submit_time
= submitted_time;
}
if ( sc->ha_performance.min_submit_time == 0
|| sc->ha_performance.min_submit_time
> submitted_time) {
sc->ha_performance.min_submit_time
= submitted_time;
}
switch ( ccb->csio.cdb_io.cdb_bytes[0] ) {
case 0xa8: /* 12-byte READ */
/* FALLTHRU */
case 0x08: /* 6-byte READ */
/* FALLTHRU */
case 0x28: /* 10-byte READ */
op_type = READ_OP;
break;
case 0x0a: /* 6-byte WRITE */
/* FALLTHRU */
case 0xaa: /* 12-byte WRITE */
/* FALLTHRU */
case 0x2a: /* 10-byte WRITE */
op_type = WRITE_OP;
break;
default:
op_type = 0;
break;
}
if ( op_type != 0 ) {
struct scsi_rw_big * cmd;
cmd = (struct scsi_rw_big *)
&(ccb->csio.cdb_io);
size = (((u_int32_t) cmd->length2 << 8)
| ((u_int32_t) cmd->length1)) << 9;
switch ( size ) {
case 512:
asr_IObySize(sc,
submitted_time, op_type,
SIZE_512);
break;
case 1024:
asr_IObySize(sc,
submitted_time, op_type,
SIZE_1K);
break;
case 2048:
asr_IObySize(sc,
submitted_time, op_type,
SIZE_2K);
break;
case 4096:
asr_IObySize(sc,
submitted_time, op_type,
SIZE_4K);
break;
case 8192:
asr_IObySize(sc,
submitted_time, op_type,
SIZE_8K);
break;
case 16384:
asr_IObySize(sc,
submitted_time, op_type,
SIZE_16K);
break;
case 32768:
asr_IObySize(sc,
submitted_time, op_type,
SIZE_32K);
break;
case 65536:
asr_IObySize(sc,
submitted_time, op_type,
SIZE_64K);
break;
default:
if ( size > (1 << 16) ) {
asr_IObySize(sc,
submitted_time,
op_type,
SIZE_BIGGER);
} else {
asr_IObySize(sc,
submitted_time,
op_type,
SIZE_OTHER);
}
break;
}
}
}
}
#endif
/* Sense data in reply packet */
if (ccb->ccb_h.status & CAM_AUTOSNS_VALID) {
u_int16_t size = I2O_SCSI_ERROR_REPLY_MESSAGE_FRAME_getAutoSenseTransferCount(Reply);
if (size) {
if (size > sizeof(ccb->csio.sense_data)) {
size = sizeof(ccb->csio.sense_data);
}
if (size > I2O_SCSI_SENSE_DATA_SZ) {
size = I2O_SCSI_SENSE_DATA_SZ;
}
if ((ccb->csio.sense_len)
&& (size > ccb->csio.sense_len)) {
size = ccb->csio.sense_len;
}
bcopy ((caddr_t)Reply->SenseData,
(caddr_t)&(ccb->csio.sense_data), size);
}
}
/*
* Return Reply so that it can be used for the next command
* since we have no more need for it now
*/
sc->ha_Virt->FromFIFO = ReplyOffset;
if (ccb->ccb_h.path) {
xpt_done ((union ccb *)ccb);
} else {
wakeup ((caddr_t)ccb);
}
}
#ifdef ASR_MEASURE_PERFORMANCE
{
u_int32_t result;
microtime(&junk);
result = asr_time_delta(sc->ha_performance.intr_started, junk);
if (result != 0xffffffff) {
if ( sc->ha_performance.max_intr_time < result ) {
sc->ha_performance.max_intr_time = result;
}
if ( (sc->ha_performance.min_intr_time == 0)
|| (sc->ha_performance.min_intr_time > result) ) {
sc->ha_performance.min_intr_time = result;
}
}
}
#endif
return (processed);
} /* asr_intr */
#undef QueueSize /* Grrrr */
#undef SG_Size /* Grrrr */
/*
* Meant to be included at the bottom of asr.c !!!
*/
/*
* Included here as hard coded. Done because other necessary include
* files utilize C++ comment structures which make them a nuisance to
* included here just to pick up these three typedefs.
*/
typedef U32 DPT_TAG_T;
typedef U32 DPT_MSG_T;
typedef U32 DPT_RTN_T;
#undef SCSI_RESET /* Conflicts with "scsi/scsiconf.h" defintion */
#include "dev/asr/osd_unix.h"
#define asr_unit(dev) minor(dev)
STATIC INLINE Asr_softc_t *
ASR_get_sc (
IN dev_t dev)
{
int unit = asr_unit(dev);
OUT Asr_softc_t * sc = Asr_softc;
while (sc && sc->ha_sim[0] && (cam_sim_unit(sc->ha_sim[0]) != unit)) {
sc = sc->ha_next;
}
return (sc);
} /* ASR_get_sc */
STATIC u_int8_t ASR_ctlr_held;
STATIC int
asr_open(
IN dev_t dev,
int32_t flags,
int32_t ifmt,
IN struct proc * proc)
{
int s;
OUT int error;
UNREFERENCED_PARAMETER(flags);
UNREFERENCED_PARAMETER(ifmt);
if (ASR_get_sc (dev) == (Asr_softc_t *)NULL) {
return (ENODEV);
}
s = splcam ();
if (ASR_ctlr_held) {
error = EBUSY;
} else if ((error = suser(proc)) == 0) {
++ASR_ctlr_held;
}
splx(s);
return (error);
} /* asr_open */
STATIC int
asr_close(
dev_t dev,
int flags,
int ifmt,
struct proc * proc)
{
UNREFERENCED_PARAMETER(dev);
UNREFERENCED_PARAMETER(flags);
UNREFERENCED_PARAMETER(ifmt);
UNREFERENCED_PARAMETER(proc);
ASR_ctlr_held = 0;
return (0);
} /* asr_close */
/*-------------------------------------------------------------------------*/
/* Function ASR_queue_i */
/*-------------------------------------------------------------------------*/
/* The Parameters Passed To This Function Are : */
/* Asr_softc_t * : HBA miniport driver's adapter data storage. */
/* PI2O_MESSAGE_FRAME : Msg Structure Pointer For This Command */
/* I2O_SCSI_ERROR_REPLY_MESSAGE_FRAME following the Msg Structure */
/* */
/* This Function Will Take The User Request Packet And Convert It To An */
/* I2O MSG And Send It Off To The Adapter. */
/* */
/* Return : 0 For OK, Error Code Otherwise */
/*-------------------------------------------------------------------------*/
STATIC INLINE int
ASR_queue_i(
IN Asr_softc_t * sc,
INOUT PI2O_MESSAGE_FRAME Packet)
{
union asr_ccb * ccb;
PI2O_SCSI_ERROR_REPLY_MESSAGE_FRAME Reply;
PI2O_MESSAGE_FRAME Message_Ptr;
PI2O_SCSI_ERROR_REPLY_MESSAGE_FRAME Reply_Ptr;
int MessageSizeInBytes;
int ReplySizeInBytes;
int error;
int s;
/* Scatter Gather buffer list */
struct ioctlSgList_S {
SLIST_ENTRY(ioctlSgList_S) link;
caddr_t UserSpace;
I2O_FLAGS_COUNT FlagsCount;
char KernelSpace[sizeof(long)];
} * elm;
/* Generates a `first' entry */
SLIST_HEAD(ioctlSgListHead_S, ioctlSgList_S) sgList;
if (ASR_getBlinkLedCode(sc)) {
debug_usr_cmd_printf ("Adapter currently in BlinkLed %x\n",
ASR_getBlinkLedCode(sc));
return (EIO);
}
/* Copy in the message into a local allocation */
if ((Message_Ptr = (PI2O_MESSAGE_FRAME)malloc (
sizeof(I2O_MESSAGE_FRAME), M_TEMP, M_WAITOK))
== (PI2O_MESSAGE_FRAME)NULL) {
debug_usr_cmd_printf (
"Failed to acquire I2O_MESSAGE_FRAME memory\n");
return (ENOMEM);
}
if ((error = copyin ((caddr_t)Packet, (caddr_t)Message_Ptr,
sizeof(I2O_MESSAGE_FRAME))) != 0) {
free (Message_Ptr, M_TEMP);
debug_usr_cmd_printf ("Can't copy in packet errno=%d\n", error);
return (error);
}
/* Acquire information to determine type of packet */
MessageSizeInBytes = (I2O_MESSAGE_FRAME_getMessageSize(Message_Ptr)<<2);
/* The offset of the reply information within the user packet */
Reply = (PI2O_SCSI_ERROR_REPLY_MESSAGE_FRAME)((char *)Packet
+ MessageSizeInBytes);
/* Check if the message is a synchronous initialization command */
s = I2O_MESSAGE_FRAME_getFunction(Message_Ptr);
free (Message_Ptr, M_TEMP);
switch (s) {
case I2O_EXEC_IOP_RESET:
{ U32 status;
status = ASR_resetIOP(sc->ha_Virt);
ReplySizeInBytes = sizeof(status);
debug_usr_cmd_printf ("resetIOP done\n");
return (copyout ((caddr_t)&status, (caddr_t)Reply,
ReplySizeInBytes));
}
case I2O_EXEC_STATUS_GET:
{ I2O_EXEC_STATUS_GET_REPLY status;
if (ASR_getStatus (sc->ha_Virt, &status)
== (PI2O_EXEC_STATUS_GET_REPLY)NULL) {
debug_usr_cmd_printf ("getStatus failed\n");
return (ENXIO);
}
ReplySizeInBytes = sizeof(status);
debug_usr_cmd_printf ("getStatus done\n");
return (copyout ((caddr_t)&status, (caddr_t)Reply,
ReplySizeInBytes));
}
case I2O_EXEC_OUTBOUND_INIT:
{ U32 status;
status = ASR_initOutBound(sc);
ReplySizeInBytes = sizeof(status);
debug_usr_cmd_printf ("intOutBound done\n");
return (copyout ((caddr_t)&status, (caddr_t)Reply,
ReplySizeInBytes));
}
}
/* Determine if the message size is valid */
if ((MessageSizeInBytes < sizeof(I2O_MESSAGE_FRAME))
|| (MAX_INBOUND_SIZE < MessageSizeInBytes)) {
debug_usr_cmd_printf ("Packet size %d incorrect\n",
MessageSizeInBytes);
return (EINVAL);
}
if ((Message_Ptr = (PI2O_MESSAGE_FRAME)malloc (MessageSizeInBytes,
M_TEMP, M_WAITOK)) == (PI2O_MESSAGE_FRAME)NULL) {
debug_usr_cmd_printf ("Failed to acquire frame[%d] memory\n",
MessageSizeInBytes);
return (ENOMEM);
}
if ((error = copyin ((caddr_t)Packet, (caddr_t)Message_Ptr,
MessageSizeInBytes)) != 0) {
free (Message_Ptr, M_TEMP);
debug_usr_cmd_printf ("Can't copy in packet[%d] errno=%d\n",
MessageSizeInBytes, error);
return (error);
}
/* Check the size of the reply frame, and start constructing */
if ((Reply_Ptr = (PI2O_SCSI_ERROR_REPLY_MESSAGE_FRAME)malloc (
sizeof(I2O_MESSAGE_FRAME), M_TEMP, M_WAITOK))
== (PI2O_SCSI_ERROR_REPLY_MESSAGE_FRAME)NULL) {
free (Message_Ptr, M_TEMP);
debug_usr_cmd_printf (
"Failed to acquire I2O_MESSAGE_FRAME memory\n");
return (ENOMEM);
}
if ((error = copyin ((caddr_t)Reply, (caddr_t)Reply_Ptr,
sizeof(I2O_MESSAGE_FRAME))) != 0) {
free (Reply_Ptr, M_TEMP);
free (Message_Ptr, M_TEMP);
debug_usr_cmd_printf (
"Failed to copy in reply frame, errno=%d\n",
error);
return (error);
}
ReplySizeInBytes = (I2O_MESSAGE_FRAME_getMessageSize(
&(Reply_Ptr->StdReplyFrame.StdMessageFrame)) << 2);
free (Reply_Ptr, M_TEMP);
if (ReplySizeInBytes < sizeof(I2O_SINGLE_REPLY_MESSAGE_FRAME)) {
free (Message_Ptr, M_TEMP);
debug_usr_cmd_printf (
"Failed to copy in reply frame[%d], errno=%d\n",
ReplySizeInBytes, error);
return (EINVAL);
}
if ((Reply_Ptr = (PI2O_SCSI_ERROR_REPLY_MESSAGE_FRAME)malloc (
((ReplySizeInBytes > sizeof(I2O_SCSI_ERROR_REPLY_MESSAGE_FRAME))
? ReplySizeInBytes
: sizeof(I2O_SCSI_ERROR_REPLY_MESSAGE_FRAME)),
M_TEMP, M_WAITOK)) == (PI2O_SCSI_ERROR_REPLY_MESSAGE_FRAME)NULL) {
free (Message_Ptr, M_TEMP);
debug_usr_cmd_printf ("Failed to acquire frame[%d] memory\n",
ReplySizeInBytes);
return (ENOMEM);
}
(void)ASR_fillMessage ((char *)Reply_Ptr, ReplySizeInBytes);
Reply_Ptr->StdReplyFrame.StdMessageFrame.InitiatorContext
= Message_Ptr->InitiatorContext;
Reply_Ptr->StdReplyFrame.TransactionContext
= ((PI2O_PRIVATE_MESSAGE_FRAME)Message_Ptr)->TransactionContext;
I2O_MESSAGE_FRAME_setMsgFlags(
&(Reply_Ptr->StdReplyFrame.StdMessageFrame),
I2O_MESSAGE_FRAME_getMsgFlags(
&(Reply_Ptr->StdReplyFrame.StdMessageFrame))
| I2O_MESSAGE_FLAGS_REPLY);
/* Check if the message is a special case command */
switch (I2O_MESSAGE_FRAME_getFunction(Message_Ptr)) {
case I2O_EXEC_SYS_TAB_SET: /* Special Case of empty Scatter Gather */
if (MessageSizeInBytes == ((I2O_MESSAGE_FRAME_getVersionOffset(
Message_Ptr) & 0xF0) >> 2)) {
free (Message_Ptr, M_TEMP);
I2O_SINGLE_REPLY_MESSAGE_FRAME_setDetailedStatusCode(
&(Reply_Ptr->StdReplyFrame), (ASR_setSysTab(sc) != CAM_REQ_CMP));
I2O_MESSAGE_FRAME_setMessageSize(
&(Reply_Ptr->StdReplyFrame.StdMessageFrame),
sizeof(I2O_SINGLE_REPLY_MESSAGE_FRAME));
error = copyout ((caddr_t)Reply_Ptr, (caddr_t)Reply,
ReplySizeInBytes);
free (Reply_Ptr, M_TEMP);
return (error);
}
}
/* Deal in the general case */
/* First allocate and optionally copy in each scatter gather element */
SLIST_INIT(&sgList);
if ((I2O_MESSAGE_FRAME_getVersionOffset(Message_Ptr) & 0xF0) != 0) {
PI2O_SGE_SIMPLE_ELEMENT sg;
/*
* since this code is reused in several systems, code
* efficiency is greater by using a shift operation rather
* than a divide by sizeof(u_int32_t).
*/
sg = (PI2O_SGE_SIMPLE_ELEMENT)((char *)Message_Ptr
+ ((I2O_MESSAGE_FRAME_getVersionOffset(Message_Ptr) & 0xF0)
>> 2));
while (sg < (PI2O_SGE_SIMPLE_ELEMENT)(((caddr_t)Message_Ptr)
+ MessageSizeInBytes)) {
caddr_t v;
int len;
if ((I2O_FLAGS_COUNT_getFlags(&(sg->FlagsCount))
& I2O_SGL_FLAGS_SIMPLE_ADDRESS_ELEMENT) == 0) {
error = EINVAL;
break;
}
len = I2O_FLAGS_COUNT_getCount(&(sg->FlagsCount));
debug_usr_cmd_printf ("SG[%d] = %x[%d]\n",
sg - (PI2O_SGE_SIMPLE_ELEMENT)((char *)Message_Ptr
+ ((I2O_MESSAGE_FRAME_getVersionOffset(
Message_Ptr) & 0xF0) >> 2)),
I2O_SGE_SIMPLE_ELEMENT_getPhysicalAddress(sg), len);
if ((elm = (struct ioctlSgList_S *)malloc (
sizeof(*elm) - sizeof(elm->KernelSpace) + len,
M_TEMP, M_WAITOK))
== (struct ioctlSgList_S *)NULL) {
debug_usr_cmd_printf (
"Failed to allocate SG[%d]\n", len);
error = ENOMEM;
break;
}
SLIST_INSERT_HEAD(&sgList, elm, link);
elm->FlagsCount = sg->FlagsCount;
elm->UserSpace = (caddr_t)
(I2O_SGE_SIMPLE_ELEMENT_getPhysicalAddress(sg));
v = elm->KernelSpace;
/* Copy in outgoing data (DIR bit could be invalid) */
if ((error = copyin (elm->UserSpace, (caddr_t)v, len))
!= 0) {
break;
}
/*
* If the buffer is not contiguous, lets
* break up the scatter/gather entries.
*/
while ((len > 0)
&& (sg < (PI2O_SGE_SIMPLE_ELEMENT)
(((caddr_t)Message_Ptr) + MAX_INBOUND_SIZE))) {
int next, base, span;
span = 0;
next = base = KVTOPHYS(v);
I2O_SGE_SIMPLE_ELEMENT_setPhysicalAddress(sg,
base);
/* How far can we go physically contiguously */
while ((len > 0) && (base == next)) {
int size;
next = trunc_page(base) + PAGE_SIZE;
size = next - base;
if (size > len) {
size = len;
}
span += size;
v += size;
len -= size;
base = KVTOPHYS(v);
}
/* Construct the Flags */
I2O_FLAGS_COUNT_setCount(&(sg->FlagsCount),
span);
{
int flags = I2O_FLAGS_COUNT_getFlags(
&(elm->FlagsCount));
/* Any remaining length? */
if (len > 0) {
flags &=
~(I2O_SGL_FLAGS_END_OF_BUFFER
| I2O_SGL_FLAGS_LAST_ELEMENT);
}
I2O_FLAGS_COUNT_setFlags(
&(sg->FlagsCount), flags);
}
debug_usr_cmd_printf ("sg[%d] = %x[%d]\n",
sg - (PI2O_SGE_SIMPLE_ELEMENT)
((char *)Message_Ptr
+ ((I2O_MESSAGE_FRAME_getVersionOffset(
Message_Ptr) & 0xF0) >> 2)),
I2O_SGE_SIMPLE_ELEMENT_getPhysicalAddress(sg),
span);
if (len <= 0) {
break;
}
/*
* Incrementing requires resizing of the
* packet, and moving up the existing SG
* elements.
*/
++sg;
MessageSizeInBytes += sizeof(*sg);
I2O_MESSAGE_FRAME_setMessageSize(Message_Ptr,
I2O_MESSAGE_FRAME_getMessageSize(Message_Ptr)
+ (sizeof(*sg) / sizeof(U32)));
{
PI2O_MESSAGE_FRAME NewMessage_Ptr;
if ((NewMessage_Ptr
= (PI2O_MESSAGE_FRAME)
malloc (MessageSizeInBytes,
M_TEMP, M_WAITOK))
== (PI2O_MESSAGE_FRAME)NULL) {
debug_usr_cmd_printf (
"Failed to acquire frame[%d] memory\n",
MessageSizeInBytes);
error = ENOMEM;
break;
}
span = ((caddr_t)sg)
- (caddr_t)Message_Ptr;
bcopy ((caddr_t)Message_Ptr,
(caddr_t)NewMessage_Ptr, span);
bcopy ((caddr_t)(sg-1),
((caddr_t)NewMessage_Ptr) + span,
MessageSizeInBytes - span);
free (Message_Ptr, M_TEMP);
sg = (PI2O_SGE_SIMPLE_ELEMENT)
(((caddr_t)NewMessage_Ptr) + span);
Message_Ptr = NewMessage_Ptr;
}
}
if ((error)
|| ((I2O_FLAGS_COUNT_getFlags(&(sg->FlagsCount))
& I2O_SGL_FLAGS_LAST_ELEMENT) != 0)) {
break;
}
++sg;
}
if (error) {
while ((elm = SLIST_FIRST(&sgList))
!= (struct ioctlSgList_S *)NULL) {
SLIST_REMOVE_HEAD(&sgList,link);
free (elm, M_TEMP);
}
free (Reply_Ptr, M_TEMP);
free (Message_Ptr, M_TEMP);
return (error);
}
}
debug_usr_cmd_printf ("Inbound: ");
debug_usr_cmd_dump_message(Message_Ptr);
/* Send the command */
if ((ccb = asr_alloc_ccb (sc)) == (union asr_ccb *)NULL) {
/* Free up in-kernel buffers */
while ((elm = SLIST_FIRST(&sgList))
!= (struct ioctlSgList_S *)NULL) {
SLIST_REMOVE_HEAD(&sgList,link);
free (elm, M_TEMP);
}
free (Reply_Ptr, M_TEMP);
free (Message_Ptr, M_TEMP);
return (ENOMEM);
}
/*
* We do not need any (optional byteswapping) method access to
* the Initiator context field.
*/
I2O_MESSAGE_FRAME_setInitiatorContext64(
(PI2O_MESSAGE_FRAME)Message_Ptr, (long)ccb);
(void)ASR_queue (sc, (PI2O_MESSAGE_FRAME)Message_Ptr);
free (Message_Ptr, M_TEMP);
/*
* Wait for the board to report a finished instruction.
*/
s = splcam();
while (ccb->ccb_h.status == CAM_REQ_INPROG) {
if (ASR_getBlinkLedCode(sc)) {
/* Reset Adapter */
printf ("asr%d: Blink LED 0x%x resetting adapter\n",
cam_sim_unit(xpt_path_sim(ccb->ccb_h.path)),
ASR_getBlinkLedCode(sc));
ASR_reset (sc);
splx(s);
/* Command Cleanup */
ASR_ccbRemove(sc, ccb);
/* Free up in-kernel buffers */
while ((elm = SLIST_FIRST(&sgList))
!= (struct ioctlSgList_S *)NULL) {
SLIST_REMOVE_HEAD(&sgList,link);
free (elm, M_TEMP);
}
free (Reply_Ptr, M_TEMP);
asr_free_ccb(ccb);
return (EIO);
}
/* Check every second for BlinkLed */
/* There is no PRICAM, but outwardly PRIBIO is functional */
tsleep((caddr_t)ccb, PRIBIO, "asr", hz);
}
splx(s);
debug_usr_cmd_printf ("Outbound: ");
debug_usr_cmd_dump_message(Reply_Ptr);
I2O_SINGLE_REPLY_MESSAGE_FRAME_setDetailedStatusCode(
&(Reply_Ptr->StdReplyFrame), (ccb->ccb_h.status != CAM_REQ_CMP));
if (ReplySizeInBytes >= (sizeof(I2O_SCSI_ERROR_REPLY_MESSAGE_FRAME)
- I2O_SCSI_SENSE_DATA_SZ - sizeof(U32))) {
I2O_SCSI_ERROR_REPLY_MESSAGE_FRAME_setTransferCount(Reply_Ptr,
ccb->csio.dxfer_len - ccb->csio.resid);
}
if ((ccb->ccb_h.status & CAM_AUTOSNS_VALID) && (ReplySizeInBytes
> (sizeof(I2O_SCSI_ERROR_REPLY_MESSAGE_FRAME)
- I2O_SCSI_SENSE_DATA_SZ))) {
int size = ReplySizeInBytes
- sizeof(I2O_SCSI_ERROR_REPLY_MESSAGE_FRAME)
- I2O_SCSI_SENSE_DATA_SZ;
if (size > sizeof(ccb->csio.sense_data)) {
size = sizeof(ccb->csio.sense_data);
}
bcopy ((caddr_t)&(ccb->csio.sense_data), (caddr_t)Reply_Ptr->SenseData,
size);
I2O_SCSI_ERROR_REPLY_MESSAGE_FRAME_setAutoSenseTransferCount(
Reply_Ptr, size);
}
/* Free up in-kernel buffers */
while ((elm = SLIST_FIRST(&sgList)) != (struct ioctlSgList_S *)NULL) {
/* Copy out as necessary */
if ((error == 0)
/* DIR bit considered `valid', error due to ignorance works */
&& ((I2O_FLAGS_COUNT_getFlags(&(elm->FlagsCount))
& I2O_SGL_FLAGS_DIR) == 0)) {
error = copyout ((caddr_t)(elm->KernelSpace),
elm->UserSpace,
I2O_FLAGS_COUNT_getCount(&(elm->FlagsCount)));
}
SLIST_REMOVE_HEAD(&sgList,link);
free (elm, M_TEMP);
}
if (error == 0) {
/* Copy reply frame to user space */
error = copyout ((caddr_t)Reply_Ptr, (caddr_t)Reply,
ReplySizeInBytes);
}
free (Reply_Ptr, M_TEMP);
asr_free_ccb(ccb);
return (error);
} /* ASR_queue_i */
/*----------------------------------------------------------------------*/
/* Function asr_ioctl */
/*----------------------------------------------------------------------*/
/* The parameters passed to this function are : */
/* dev : Device number. */
/* cmd : Ioctl Command */
/* data : User Argument Passed In. */
/* flag : Mode Parameter */
/* proc : Process Parameter */
/* */
/* This function is the user interface into this adapter driver */
/* */
/* Return : zero if OK, error code if not */
/*----------------------------------------------------------------------*/
STATIC int
asr_ioctl(
IN dev_t dev,
IN u_long cmd,
INOUT caddr_t data,
int flag,
struct proc * proc)
{
int i, j;
OUT int error = 0;
Asr_softc_t * sc = ASR_get_sc (dev);
UNREFERENCED_PARAMETER(flag);
UNREFERENCED_PARAMETER(proc);
if (sc != (Asr_softc_t *)NULL)
switch(cmd) {
case DPT_SIGNATURE:
# if (dsDescription_size != 50)
case DPT_SIGNATURE + ((50 - dsDescription_size) << 16):
# endif
if (cmd & 0xFFFF0000) {
(void)bcopy ((caddr_t)(&ASR_sig), data,
sizeof(dpt_sig_S));
return (0);
}
/* Traditional version of the ioctl interface */
case DPT_SIGNATURE & 0x0000FFFF:
return (copyout ((caddr_t)(&ASR_sig), *((caddr_t *)data),
sizeof(dpt_sig_S)));
/* Traditional version of the ioctl interface */
case DPT_CTRLINFO & 0x0000FFFF:
case DPT_CTRLINFO: {
struct {
u_int16_t length;
u_int16_t drvrHBAnum;
u_int32_t baseAddr;
u_int16_t blinkState;
u_int8_t pciBusNum;
u_int8_t pciDeviceNum;
u_int16_t hbaFlags;
u_int16_t Interrupt;
u_int32_t reserved1;
u_int32_t reserved2;
u_int32_t reserved3;
} CtlrInfo;
bzero (&CtlrInfo, sizeof(CtlrInfo));
CtlrInfo.length = sizeof(CtlrInfo) - sizeof(u_int16_t);
CtlrInfo.drvrHBAnum = asr_unit(dev);
CtlrInfo.baseAddr = (u_long)sc->ha_Base;
i = ASR_getBlinkLedCode (sc);
if (i == -1) {
i = 0;
}
CtlrInfo.blinkState = i;
CtlrInfo.pciBusNum = sc->ha_pciBusNum;
CtlrInfo.pciDeviceNum = sc->ha_pciDeviceNum;
#define FLG_OSD_PCI_VALID 0x0001
#define FLG_OSD_DMA 0x0002
#define FLG_OSD_I2O 0x0004
CtlrInfo.hbaFlags = FLG_OSD_PCI_VALID | FLG_OSD_DMA | FLG_OSD_I2O;
CtlrInfo.Interrupt = sc->ha_irq;
if (cmd & 0xFFFF0000) {
bcopy (&CtlrInfo, data, sizeof(CtlrInfo));
} else {
error = copyout (&CtlrInfo, *(caddr_t *)data, sizeof(CtlrInfo));
}
} return (error);
/* Traditional version of the ioctl interface */
case DPT_SYSINFO & 0x0000FFFF:
case DPT_SYSINFO: {
sysInfo_S Info;
caddr_t c_addr;
/* Kernel Specific ptok `hack' */
# define ptok(a) ((char *)(a) + KERNBASE)
bzero (&Info, sizeof(Info));
outb (0x70, 0x12);
i = inb(0x71);
j = i >> 4;
if (i == 0x0f) {
outb (0x70, 0x19);
j = inb (0x71);
}
Info.drive0CMOS = j;
j = i & 0x0f;
if (i == 0x0f) {
outb (0x70, 0x1a);
j = inb (0x71);
}
Info.drive1CMOS = j;
Info.numDrives = *((char *)ptok(0x475));
Info.processorFamily = ASR_sig.dsProcessorFamily;
switch (cpu) {
case CPU_386SX: case CPU_386:
Info.processorType = PROC_386; break;
case CPU_486SX: case CPU_486:
Info.processorType = PROC_486; break;
case CPU_586:
Info.processorType = PROC_PENTIUM; break;
case CPU_686:
Info.processorType = PROC_SEXIUM; break;
}
Info.osType = OS_BSDI_UNIX;
Info.osMajorVersion = osrelease[0] - '0';
Info.osMinorVersion = osrelease[2] - '0';
/* Info.osRevision = 0; */
/* Info.osSubRevision = 0; */
Info.busType = SI_PCI_BUS;
Info.flags = SI_CMOS_Valid | SI_NumDrivesValid
| SI_OSversionValid |SI_BusTypeValid;
/* Go Out And Look For SmartROM */
for(i = 0; i < 3; ++i) {
int k;
if (i == 0) {
j = 0xC8000;
} else if (i == 1) {
j = 0xD8000;
} else {
j = 0xDC000;
}
c_addr = ptok(j);
if (*((unsigned short *)c_addr) != 0xAA55) {
continue;
}
if (*((u_long *)(c_addr + 6)) != 0x202053) {
continue;
}
if (*((u_long *)(c_addr + 10)) != 0x545044) {
continue;
}
c_addr += 0x24;
for (k = 0; k < 64; ++k) {
if ((*((unsigned char *)(c_addr++)) == ' ')
&& (*((unsigned char *)(c_addr)) == 'v')) {
break;
}
}
if (k < 64) {
Info.smartROMMajorVersion
= *((unsigned char *)(c_addr += 3)) - '0';
Info.smartROMMinorVersion
= *((unsigned char *)(c_addr += 2));
Info.smartROMRevision
= *((unsigned char *)(++c_addr));
Info.flags |= SI_SmartROMverValid;
break;
}
}
if (i >= 3) {
Info.flags |= SI_NO_SmartROM;
}
/* Get The Conventional Memory Size From CMOS */
outb (0x70, 0x16);
j = inb (0x71);
j <<= 8;
outb (0x70, 0x15);
j |= inb(0x71);
Info.conventionalMemSize = j;
/* Get The Extended Memory Found At Power On From CMOS */
outb (0x70, 0x31);
j = inb (0x71);
j <<= 8;
outb (0x70, 0x30);
j |= inb(0x71);
Info.extendedMemSize = j;
Info.flags |= SI_MemorySizeValid;
# if (defined(THIS_IS_BROKEN))
/* If There Is 1 or 2 Drives Found, Set Up Drive Parameters */
if (Info.numDrives > 0) {
/*
* Get The Pointer From Int 41 For The First
* Drive Parameters
*/
j = ((unsigned)(*((unsigned short *)ptok(0x104+2))) << 4)
+ (unsigned)(*((unsigned short *)ptok(0x104+0)));
/*
* It appears that SmartROM's Int41/Int46 pointers
* use memory that gets stepped on by the kernel
* loading. We no longer have access to this
* geometry information but try anyways (!?)
*/
Info.drives[0].cylinders = *((unsigned char *)ptok(j));
++j;
Info.drives[0].cylinders += ((int)*((unsigned char *)
ptok(j))) << 8;
++j;
Info.drives[0].heads = *((unsigned char *)ptok(j));
j += 12;
Info.drives[0].sectors = *((unsigned char *)ptok(j));
Info.flags |= SI_DriveParamsValid;
if ((Info.drives[0].cylinders == 0)
|| (Info.drives[0].heads == 0)
|| (Info.drives[0].sectors == 0)) {
Info.flags &= ~SI_DriveParamsValid;
}
if (Info.numDrives > 1) {
/*
* Get The Pointer From Int 46 For The
* Second Drive Parameters
*/
j = ((unsigned)(*((unsigned short *)ptok(0x118+2))) << 4)
+ (unsigned)(*((unsigned short *)ptok(0x118+0)));
Info.drives[1].cylinders = *((unsigned char *)
ptok(j));
++j;
Info.drives[1].cylinders += ((int)
*((unsigned char *)ptok(j))) << 8;
++j;
Info.drives[1].heads = *((unsigned char *)
ptok(j));
j += 12;
Info.drives[1].sectors = *((unsigned char *)
ptok(j));
if ((Info.drives[1].cylinders == 0)
|| (Info.drives[1].heads == 0)
|| (Info.drives[1].sectors == 0)) {
Info.flags &= ~SI_DriveParamsValid;
}
}
}
# endif
/* Copy Out The Info Structure To The User */
if (cmd & 0xFFFF0000) {
bcopy (&Info, data, sizeof(Info));
} else {
error = copyout (&Info, *(caddr_t *)data, sizeof(Info));
}
return (error); }
/* Get The BlinkLED State */
case DPT_BLINKLED:
i = ASR_getBlinkLedCode (sc);
if (i == -1) {
i = 0;
}
if (cmd & 0xFFFF0000) {
bcopy ((caddr_t)(&i), data, sizeof(i));
} else {
error = copyout (&i, *(caddr_t *)data, sizeof(i));
}
break;
/* Get performance metrics */
#ifdef ASR_MEASURE_PERFORMANCE
case DPT_PERF_INFO:
bcopy((caddr_t) &sc->ha_performance, data,
sizeof(sc->ha_performance));
return (0);
#endif
/* Send an I2O command */
case I2OUSRCMD:
return (ASR_queue_i (sc, *((PI2O_MESSAGE_FRAME *)data)));
/* Reset and re-initialize the adapter */
case I2ORESETCMD:
ASR_reset (sc);
return (0);
/* Rescan the LCT table and resynchronize the information */
case I2ORESCANCMD:
return (ASR_rescan (sc));
}
return (EINVAL);
} /* asr_ioctl */
#ifdef ASR_MEASURE_PERFORMANCE
/*
* This function subtracts one timeval structure from another,
* Returning the result in usec.
* It assumes that less than 4 billion usecs passed form start to end.
* If times are sensless, 0xffffffff is returned.
*/
STATIC u_int32_t
asr_time_delta(
IN struct timeval start,
IN struct timeval end)
{
OUT u_int32_t result;
if (start.tv_sec > end.tv_sec) {
result = 0xffffffff;
}
else {
if (start.tv_sec == end.tv_sec) {
if (start.tv_usec > end.tv_usec) {
result = 0xffffffff;
} else {
return (end.tv_usec - start.tv_usec);
}
} else {
return (end.tv_sec - start.tv_sec) * 1000000 +
end.tv_usec + (1000000 - start.tv_usec);
}
}
return(result);
} /* asr_time_delta */
#endif
|