1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136
4137
4138
4139
4140
4141
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159
4160
4161
4162
4163
4164
4165
4166
4167
4168
4169
4170
4171
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193
4194
4195
4196
4197
4198
4199
4200
4201
4202
4203
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228
4229
|
/***********************license start***************
* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
* reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of Cavium Networks nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
* This Software, including technical data, may be subject to U.S. export control
* laws, including the U.S. Export Administration Act and its associated
* regulations, and may be subject to export or import regulations in other
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
***********************license end**************************************/
/**
* cvmx-sli-defs.h
*
* Configuration and status register (CSR) type definitions for
* Octeon sli.
*
* This file is auto generated. Do not edit.
*
* <hr>$Revision$<hr>
*
*/
#ifndef __CVMX_SLI_TYPEDEFS_H__
#define __CVMX_SLI_TYPEDEFS_H__
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_BIST_STATUS CVMX_SLI_BIST_STATUS_FUNC()
static inline uint64_t CVMX_SLI_BIST_STATUS_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_BIST_STATUS not supported on this chip\n");
return 0x0000000000000580ull;
}
#else
#define CVMX_SLI_BIST_STATUS (0x0000000000000580ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_SLI_CTL_PORTX(unsigned long offset)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
cvmx_warn("CVMX_SLI_CTL_PORTX(%lu) is invalid on this chip\n", offset);
return 0x0000000000000050ull + ((offset) & 1) * 16;
}
#else
#define CVMX_SLI_CTL_PORTX(offset) (0x0000000000000050ull + ((offset) & 1) * 16)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_CTL_STATUS CVMX_SLI_CTL_STATUS_FUNC()
static inline uint64_t CVMX_SLI_CTL_STATUS_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_CTL_STATUS not supported on this chip\n");
return 0x0000000000000570ull;
}
#else
#define CVMX_SLI_CTL_STATUS (0x0000000000000570ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_DATA_OUT_CNT CVMX_SLI_DATA_OUT_CNT_FUNC()
static inline uint64_t CVMX_SLI_DATA_OUT_CNT_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_DATA_OUT_CNT not supported on this chip\n");
return 0x00000000000005F0ull;
}
#else
#define CVMX_SLI_DATA_OUT_CNT (0x00000000000005F0ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_DBG_DATA CVMX_SLI_DBG_DATA_FUNC()
static inline uint64_t CVMX_SLI_DBG_DATA_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_DBG_DATA not supported on this chip\n");
return 0x0000000000000310ull;
}
#else
#define CVMX_SLI_DBG_DATA (0x0000000000000310ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_DBG_SELECT CVMX_SLI_DBG_SELECT_FUNC()
static inline uint64_t CVMX_SLI_DBG_SELECT_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_DBG_SELECT not supported on this chip\n");
return 0x0000000000000300ull;
}
#else
#define CVMX_SLI_DBG_SELECT (0x0000000000000300ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_SLI_DMAX_CNT(unsigned long offset)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
cvmx_warn("CVMX_SLI_DMAX_CNT(%lu) is invalid on this chip\n", offset);
return 0x0000000000000400ull + ((offset) & 1) * 16;
}
#else
#define CVMX_SLI_DMAX_CNT(offset) (0x0000000000000400ull + ((offset) & 1) * 16)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_SLI_DMAX_INT_LEVEL(unsigned long offset)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
cvmx_warn("CVMX_SLI_DMAX_INT_LEVEL(%lu) is invalid on this chip\n", offset);
return 0x00000000000003E0ull + ((offset) & 1) * 16;
}
#else
#define CVMX_SLI_DMAX_INT_LEVEL(offset) (0x00000000000003E0ull + ((offset) & 1) * 16)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_SLI_DMAX_TIM(unsigned long offset)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
cvmx_warn("CVMX_SLI_DMAX_TIM(%lu) is invalid on this chip\n", offset);
return 0x0000000000000420ull + ((offset) & 1) * 16;
}
#else
#define CVMX_SLI_DMAX_TIM(offset) (0x0000000000000420ull + ((offset) & 1) * 16)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_INT_ENB_CIU CVMX_SLI_INT_ENB_CIU_FUNC()
static inline uint64_t CVMX_SLI_INT_ENB_CIU_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_INT_ENB_CIU not supported on this chip\n");
return 0x0000000000003CD0ull;
}
#else
#define CVMX_SLI_INT_ENB_CIU (0x0000000000003CD0ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_SLI_INT_ENB_PORTX(unsigned long offset)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
cvmx_warn("CVMX_SLI_INT_ENB_PORTX(%lu) is invalid on this chip\n", offset);
return 0x0000000000000340ull + ((offset) & 1) * 16;
}
#else
#define CVMX_SLI_INT_ENB_PORTX(offset) (0x0000000000000340ull + ((offset) & 1) * 16)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_INT_SUM CVMX_SLI_INT_SUM_FUNC()
static inline uint64_t CVMX_SLI_INT_SUM_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_INT_SUM not supported on this chip\n");
return 0x0000000000000330ull;
}
#else
#define CVMX_SLI_INT_SUM (0x0000000000000330ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_LAST_WIN_RDATA0 CVMX_SLI_LAST_WIN_RDATA0_FUNC()
static inline uint64_t CVMX_SLI_LAST_WIN_RDATA0_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_LAST_WIN_RDATA0 not supported on this chip\n");
return 0x0000000000000600ull;
}
#else
#define CVMX_SLI_LAST_WIN_RDATA0 (0x0000000000000600ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_LAST_WIN_RDATA1 CVMX_SLI_LAST_WIN_RDATA1_FUNC()
static inline uint64_t CVMX_SLI_LAST_WIN_RDATA1_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_LAST_WIN_RDATA1 not supported on this chip\n");
return 0x0000000000000610ull;
}
#else
#define CVMX_SLI_LAST_WIN_RDATA1 (0x0000000000000610ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_MAC_CREDIT_CNT CVMX_SLI_MAC_CREDIT_CNT_FUNC()
static inline uint64_t CVMX_SLI_MAC_CREDIT_CNT_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_MAC_CREDIT_CNT not supported on this chip\n");
return 0x0000000000003D70ull;
}
#else
#define CVMX_SLI_MAC_CREDIT_CNT (0x0000000000003D70ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_MAC_NUMBER CVMX_SLI_MAC_NUMBER_FUNC()
static inline uint64_t CVMX_SLI_MAC_NUMBER_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_MAC_NUMBER not supported on this chip\n");
return 0x0000000000003E00ull;
}
#else
#define CVMX_SLI_MAC_NUMBER (0x0000000000003E00ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_MEM_ACCESS_CTL CVMX_SLI_MEM_ACCESS_CTL_FUNC()
static inline uint64_t CVMX_SLI_MEM_ACCESS_CTL_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_MEM_ACCESS_CTL not supported on this chip\n");
return 0x00000000000002F0ull;
}
#else
#define CVMX_SLI_MEM_ACCESS_CTL (0x00000000000002F0ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_SLI_MEM_ACCESS_SUBIDX(unsigned long offset)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 12) && (offset <= 27))))))
cvmx_warn("CVMX_SLI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
return 0x00000000000001A0ull + ((offset) & 31) * 16 - 16*12;
}
#else
#define CVMX_SLI_MEM_ACCESS_SUBIDX(offset) (0x00000000000001A0ull + ((offset) & 31) * 16 - 16*12)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_MSI_ENB0 CVMX_SLI_MSI_ENB0_FUNC()
static inline uint64_t CVMX_SLI_MSI_ENB0_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_MSI_ENB0 not supported on this chip\n");
return 0x0000000000003C50ull;
}
#else
#define CVMX_SLI_MSI_ENB0 (0x0000000000003C50ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_MSI_ENB1 CVMX_SLI_MSI_ENB1_FUNC()
static inline uint64_t CVMX_SLI_MSI_ENB1_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_MSI_ENB1 not supported on this chip\n");
return 0x0000000000003C60ull;
}
#else
#define CVMX_SLI_MSI_ENB1 (0x0000000000003C60ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_MSI_ENB2 CVMX_SLI_MSI_ENB2_FUNC()
static inline uint64_t CVMX_SLI_MSI_ENB2_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_MSI_ENB2 not supported on this chip\n");
return 0x0000000000003C70ull;
}
#else
#define CVMX_SLI_MSI_ENB2 (0x0000000000003C70ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_MSI_ENB3 CVMX_SLI_MSI_ENB3_FUNC()
static inline uint64_t CVMX_SLI_MSI_ENB3_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_MSI_ENB3 not supported on this chip\n");
return 0x0000000000003C80ull;
}
#else
#define CVMX_SLI_MSI_ENB3 (0x0000000000003C80ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_MSI_RCV0 CVMX_SLI_MSI_RCV0_FUNC()
static inline uint64_t CVMX_SLI_MSI_RCV0_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_MSI_RCV0 not supported on this chip\n");
return 0x0000000000003C10ull;
}
#else
#define CVMX_SLI_MSI_RCV0 (0x0000000000003C10ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_MSI_RCV1 CVMX_SLI_MSI_RCV1_FUNC()
static inline uint64_t CVMX_SLI_MSI_RCV1_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_MSI_RCV1 not supported on this chip\n");
return 0x0000000000003C20ull;
}
#else
#define CVMX_SLI_MSI_RCV1 (0x0000000000003C20ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_MSI_RCV2 CVMX_SLI_MSI_RCV2_FUNC()
static inline uint64_t CVMX_SLI_MSI_RCV2_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_MSI_RCV2 not supported on this chip\n");
return 0x0000000000003C30ull;
}
#else
#define CVMX_SLI_MSI_RCV2 (0x0000000000003C30ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_MSI_RCV3 CVMX_SLI_MSI_RCV3_FUNC()
static inline uint64_t CVMX_SLI_MSI_RCV3_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_MSI_RCV3 not supported on this chip\n");
return 0x0000000000003C40ull;
}
#else
#define CVMX_SLI_MSI_RCV3 (0x0000000000003C40ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_MSI_RD_MAP CVMX_SLI_MSI_RD_MAP_FUNC()
static inline uint64_t CVMX_SLI_MSI_RD_MAP_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_MSI_RD_MAP not supported on this chip\n");
return 0x0000000000003CA0ull;
}
#else
#define CVMX_SLI_MSI_RD_MAP (0x0000000000003CA0ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_MSI_W1C_ENB0 CVMX_SLI_MSI_W1C_ENB0_FUNC()
static inline uint64_t CVMX_SLI_MSI_W1C_ENB0_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_MSI_W1C_ENB0 not supported on this chip\n");
return 0x0000000000003CF0ull;
}
#else
#define CVMX_SLI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_MSI_W1C_ENB1 CVMX_SLI_MSI_W1C_ENB1_FUNC()
static inline uint64_t CVMX_SLI_MSI_W1C_ENB1_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_MSI_W1C_ENB1 not supported on this chip\n");
return 0x0000000000003D00ull;
}
#else
#define CVMX_SLI_MSI_W1C_ENB1 (0x0000000000003D00ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_MSI_W1C_ENB2 CVMX_SLI_MSI_W1C_ENB2_FUNC()
static inline uint64_t CVMX_SLI_MSI_W1C_ENB2_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_MSI_W1C_ENB2 not supported on this chip\n");
return 0x0000000000003D10ull;
}
#else
#define CVMX_SLI_MSI_W1C_ENB2 (0x0000000000003D10ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_MSI_W1C_ENB3 CVMX_SLI_MSI_W1C_ENB3_FUNC()
static inline uint64_t CVMX_SLI_MSI_W1C_ENB3_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_MSI_W1C_ENB3 not supported on this chip\n");
return 0x0000000000003D20ull;
}
#else
#define CVMX_SLI_MSI_W1C_ENB3 (0x0000000000003D20ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_MSI_W1S_ENB0 CVMX_SLI_MSI_W1S_ENB0_FUNC()
static inline uint64_t CVMX_SLI_MSI_W1S_ENB0_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_MSI_W1S_ENB0 not supported on this chip\n");
return 0x0000000000003D30ull;
}
#else
#define CVMX_SLI_MSI_W1S_ENB0 (0x0000000000003D30ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_MSI_W1S_ENB1 CVMX_SLI_MSI_W1S_ENB1_FUNC()
static inline uint64_t CVMX_SLI_MSI_W1S_ENB1_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_MSI_W1S_ENB1 not supported on this chip\n");
return 0x0000000000003D40ull;
}
#else
#define CVMX_SLI_MSI_W1S_ENB1 (0x0000000000003D40ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_MSI_W1S_ENB2 CVMX_SLI_MSI_W1S_ENB2_FUNC()
static inline uint64_t CVMX_SLI_MSI_W1S_ENB2_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_MSI_W1S_ENB2 not supported on this chip\n");
return 0x0000000000003D50ull;
}
#else
#define CVMX_SLI_MSI_W1S_ENB2 (0x0000000000003D50ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_MSI_W1S_ENB3 CVMX_SLI_MSI_W1S_ENB3_FUNC()
static inline uint64_t CVMX_SLI_MSI_W1S_ENB3_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_MSI_W1S_ENB3 not supported on this chip\n");
return 0x0000000000003D60ull;
}
#else
#define CVMX_SLI_MSI_W1S_ENB3 (0x0000000000003D60ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_MSI_WR_MAP CVMX_SLI_MSI_WR_MAP_FUNC()
static inline uint64_t CVMX_SLI_MSI_WR_MAP_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_MSI_WR_MAP not supported on this chip\n");
return 0x0000000000003C90ull;
}
#else
#define CVMX_SLI_MSI_WR_MAP (0x0000000000003C90ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PCIE_MSI_RCV CVMX_SLI_PCIE_MSI_RCV_FUNC()
static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PCIE_MSI_RCV not supported on this chip\n");
return 0x0000000000003CB0ull;
}
#else
#define CVMX_SLI_PCIE_MSI_RCV (0x0000000000003CB0ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PCIE_MSI_RCV_B1 CVMX_SLI_PCIE_MSI_RCV_B1_FUNC()
static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B1_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PCIE_MSI_RCV_B1 not supported on this chip\n");
return 0x0000000000000650ull;
}
#else
#define CVMX_SLI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PCIE_MSI_RCV_B2 CVMX_SLI_PCIE_MSI_RCV_B2_FUNC()
static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B2_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PCIE_MSI_RCV_B2 not supported on this chip\n");
return 0x0000000000000660ull;
}
#else
#define CVMX_SLI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PCIE_MSI_RCV_B3 CVMX_SLI_PCIE_MSI_RCV_B3_FUNC()
static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B3_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PCIE_MSI_RCV_B3 not supported on this chip\n");
return 0x0000000000000670ull;
}
#else
#define CVMX_SLI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_SLI_PKTX_CNTS(unsigned long offset)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
cvmx_warn("CVMX_SLI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
return 0x0000000000002400ull + ((offset) & 31) * 16;
}
#else
#define CVMX_SLI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_SLI_PKTX_INSTR_BADDR(unsigned long offset)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
cvmx_warn("CVMX_SLI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
return 0x0000000000002800ull + ((offset) & 31) * 16;
}
#else
#define CVMX_SLI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
cvmx_warn("CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
return 0x0000000000002C00ull + ((offset) & 31) * 16;
}
#else
#define CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
cvmx_warn("CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
return 0x0000000000003000ull + ((offset) & 31) * 16;
}
#else
#define CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_SLI_PKTX_INSTR_HEADER(unsigned long offset)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
cvmx_warn("CVMX_SLI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
return 0x0000000000003400ull + ((offset) & 31) * 16;
}
#else
#define CVMX_SLI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_SLI_PKTX_IN_BP(unsigned long offset)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
cvmx_warn("CVMX_SLI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
return 0x0000000000003800ull + ((offset) & 31) * 16;
}
#else
#define CVMX_SLI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_SLI_PKTX_OUT_SIZE(unsigned long offset)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
cvmx_warn("CVMX_SLI_PKTX_OUT_SIZE(%lu) is invalid on this chip\n", offset);
return 0x0000000000000C00ull + ((offset) & 31) * 16;
}
#else
#define CVMX_SLI_PKTX_OUT_SIZE(offset) (0x0000000000000C00ull + ((offset) & 31) * 16)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_SLI_PKTX_SLIST_BADDR(unsigned long offset)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
cvmx_warn("CVMX_SLI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
return 0x0000000000001400ull + ((offset) & 31) * 16;
}
#else
#define CVMX_SLI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
cvmx_warn("CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
return 0x0000000000001800ull + ((offset) & 31) * 16;
}
#else
#define CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
cvmx_warn("CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
return 0x0000000000001C00ull + ((offset) & 31) * 16;
}
#else
#define CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_CNT_INT CVMX_SLI_PKT_CNT_INT_FUNC()
static inline uint64_t CVMX_SLI_PKT_CNT_INT_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_CNT_INT not supported on this chip\n");
return 0x0000000000001130ull;
}
#else
#define CVMX_SLI_PKT_CNT_INT (0x0000000000001130ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_CNT_INT_ENB CVMX_SLI_PKT_CNT_INT_ENB_FUNC()
static inline uint64_t CVMX_SLI_PKT_CNT_INT_ENB_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_CNT_INT_ENB not supported on this chip\n");
return 0x0000000000001150ull;
}
#else
#define CVMX_SLI_PKT_CNT_INT_ENB (0x0000000000001150ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_CTL CVMX_SLI_PKT_CTL_FUNC()
static inline uint64_t CVMX_SLI_PKT_CTL_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_CTL not supported on this chip\n");
return 0x0000000000001220ull;
}
#else
#define CVMX_SLI_PKT_CTL (0x0000000000001220ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_DATA_OUT_ES CVMX_SLI_PKT_DATA_OUT_ES_FUNC()
static inline uint64_t CVMX_SLI_PKT_DATA_OUT_ES_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_DATA_OUT_ES not supported on this chip\n");
return 0x00000000000010B0ull;
}
#else
#define CVMX_SLI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_DATA_OUT_NS CVMX_SLI_PKT_DATA_OUT_NS_FUNC()
static inline uint64_t CVMX_SLI_PKT_DATA_OUT_NS_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_DATA_OUT_NS not supported on this chip\n");
return 0x00000000000010A0ull;
}
#else
#define CVMX_SLI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_DATA_OUT_ROR CVMX_SLI_PKT_DATA_OUT_ROR_FUNC()
static inline uint64_t CVMX_SLI_PKT_DATA_OUT_ROR_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_DATA_OUT_ROR not supported on this chip\n");
return 0x0000000000001090ull;
}
#else
#define CVMX_SLI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_DPADDR CVMX_SLI_PKT_DPADDR_FUNC()
static inline uint64_t CVMX_SLI_PKT_DPADDR_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_DPADDR not supported on this chip\n");
return 0x0000000000001080ull;
}
#else
#define CVMX_SLI_PKT_DPADDR (0x0000000000001080ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_INPUT_CONTROL CVMX_SLI_PKT_INPUT_CONTROL_FUNC()
static inline uint64_t CVMX_SLI_PKT_INPUT_CONTROL_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_INPUT_CONTROL not supported on this chip\n");
return 0x0000000000001170ull;
}
#else
#define CVMX_SLI_PKT_INPUT_CONTROL (0x0000000000001170ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_INSTR_ENB CVMX_SLI_PKT_INSTR_ENB_FUNC()
static inline uint64_t CVMX_SLI_PKT_INSTR_ENB_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_INSTR_ENB not supported on this chip\n");
return 0x0000000000001000ull;
}
#else
#define CVMX_SLI_PKT_INSTR_ENB (0x0000000000001000ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_INSTR_RD_SIZE CVMX_SLI_PKT_INSTR_RD_SIZE_FUNC()
static inline uint64_t CVMX_SLI_PKT_INSTR_RD_SIZE_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_INSTR_RD_SIZE not supported on this chip\n");
return 0x00000000000011A0ull;
}
#else
#define CVMX_SLI_PKT_INSTR_RD_SIZE (0x00000000000011A0ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_INSTR_SIZE CVMX_SLI_PKT_INSTR_SIZE_FUNC()
static inline uint64_t CVMX_SLI_PKT_INSTR_SIZE_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_INSTR_SIZE not supported on this chip\n");
return 0x0000000000001020ull;
}
#else
#define CVMX_SLI_PKT_INSTR_SIZE (0x0000000000001020ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_INT_LEVELS CVMX_SLI_PKT_INT_LEVELS_FUNC()
static inline uint64_t CVMX_SLI_PKT_INT_LEVELS_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_INT_LEVELS not supported on this chip\n");
return 0x0000000000001120ull;
}
#else
#define CVMX_SLI_PKT_INT_LEVELS (0x0000000000001120ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_IN_BP CVMX_SLI_PKT_IN_BP_FUNC()
static inline uint64_t CVMX_SLI_PKT_IN_BP_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_IN_BP not supported on this chip\n");
return 0x0000000000001210ull;
}
#else
#define CVMX_SLI_PKT_IN_BP (0x0000000000001210ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_SLI_PKT_IN_DONEX_CNTS(unsigned long offset)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31)))))
cvmx_warn("CVMX_SLI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
return 0x0000000000002000ull + ((offset) & 31) * 16;
}
#else
#define CVMX_SLI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_IN_INSTR_COUNTS CVMX_SLI_PKT_IN_INSTR_COUNTS_FUNC()
static inline uint64_t CVMX_SLI_PKT_IN_INSTR_COUNTS_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_IN_INSTR_COUNTS not supported on this chip\n");
return 0x0000000000001200ull;
}
#else
#define CVMX_SLI_PKT_IN_INSTR_COUNTS (0x0000000000001200ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_IN_PCIE_PORT CVMX_SLI_PKT_IN_PCIE_PORT_FUNC()
static inline uint64_t CVMX_SLI_PKT_IN_PCIE_PORT_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_IN_PCIE_PORT not supported on this chip\n");
return 0x00000000000011B0ull;
}
#else
#define CVMX_SLI_PKT_IN_PCIE_PORT (0x00000000000011B0ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_IPTR CVMX_SLI_PKT_IPTR_FUNC()
static inline uint64_t CVMX_SLI_PKT_IPTR_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_IPTR not supported on this chip\n");
return 0x0000000000001070ull;
}
#else
#define CVMX_SLI_PKT_IPTR (0x0000000000001070ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_OUTPUT_WMARK CVMX_SLI_PKT_OUTPUT_WMARK_FUNC()
static inline uint64_t CVMX_SLI_PKT_OUTPUT_WMARK_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_OUTPUT_WMARK not supported on this chip\n");
return 0x0000000000001180ull;
}
#else
#define CVMX_SLI_PKT_OUTPUT_WMARK (0x0000000000001180ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_OUT_BMODE CVMX_SLI_PKT_OUT_BMODE_FUNC()
static inline uint64_t CVMX_SLI_PKT_OUT_BMODE_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_OUT_BMODE not supported on this chip\n");
return 0x00000000000010D0ull;
}
#else
#define CVMX_SLI_PKT_OUT_BMODE (0x00000000000010D0ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_OUT_ENB CVMX_SLI_PKT_OUT_ENB_FUNC()
static inline uint64_t CVMX_SLI_PKT_OUT_ENB_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_OUT_ENB not supported on this chip\n");
return 0x0000000000001010ull;
}
#else
#define CVMX_SLI_PKT_OUT_ENB (0x0000000000001010ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_PCIE_PORT CVMX_SLI_PKT_PCIE_PORT_FUNC()
static inline uint64_t CVMX_SLI_PKT_PCIE_PORT_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_PCIE_PORT not supported on this chip\n");
return 0x00000000000010E0ull;
}
#else
#define CVMX_SLI_PKT_PCIE_PORT (0x00000000000010E0ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_PORT_IN_RST CVMX_SLI_PKT_PORT_IN_RST_FUNC()
static inline uint64_t CVMX_SLI_PKT_PORT_IN_RST_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_PORT_IN_RST not supported on this chip\n");
return 0x00000000000011F0ull;
}
#else
#define CVMX_SLI_PKT_PORT_IN_RST (0x00000000000011F0ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_SLIST_ES CVMX_SLI_PKT_SLIST_ES_FUNC()
static inline uint64_t CVMX_SLI_PKT_SLIST_ES_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_SLIST_ES not supported on this chip\n");
return 0x0000000000001050ull;
}
#else
#define CVMX_SLI_PKT_SLIST_ES (0x0000000000001050ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_SLIST_NS CVMX_SLI_PKT_SLIST_NS_FUNC()
static inline uint64_t CVMX_SLI_PKT_SLIST_NS_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_SLIST_NS not supported on this chip\n");
return 0x0000000000001040ull;
}
#else
#define CVMX_SLI_PKT_SLIST_NS (0x0000000000001040ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_SLIST_ROR CVMX_SLI_PKT_SLIST_ROR_FUNC()
static inline uint64_t CVMX_SLI_PKT_SLIST_ROR_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_SLIST_ROR not supported on this chip\n");
return 0x0000000000001030ull;
}
#else
#define CVMX_SLI_PKT_SLIST_ROR (0x0000000000001030ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_TIME_INT CVMX_SLI_PKT_TIME_INT_FUNC()
static inline uint64_t CVMX_SLI_PKT_TIME_INT_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_TIME_INT not supported on this chip\n");
return 0x0000000000001140ull;
}
#else
#define CVMX_SLI_PKT_TIME_INT (0x0000000000001140ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_PKT_TIME_INT_ENB CVMX_SLI_PKT_TIME_INT_ENB_FUNC()
static inline uint64_t CVMX_SLI_PKT_TIME_INT_ENB_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_PKT_TIME_INT_ENB not supported on this chip\n");
return 0x0000000000001160ull;
}
#else
#define CVMX_SLI_PKT_TIME_INT_ENB (0x0000000000001160ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_SLI_S2M_PORTX_CTL(unsigned long offset)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
cvmx_warn("CVMX_SLI_S2M_PORTX_CTL(%lu) is invalid on this chip\n", offset);
return 0x0000000000003D80ull + ((offset) & 1) * 16;
}
#else
#define CVMX_SLI_S2M_PORTX_CTL(offset) (0x0000000000003D80ull + ((offset) & 1) * 16)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_SCRATCH_1 CVMX_SLI_SCRATCH_1_FUNC()
static inline uint64_t CVMX_SLI_SCRATCH_1_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_SCRATCH_1 not supported on this chip\n");
return 0x00000000000003C0ull;
}
#else
#define CVMX_SLI_SCRATCH_1 (0x00000000000003C0ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_SCRATCH_2 CVMX_SLI_SCRATCH_2_FUNC()
static inline uint64_t CVMX_SLI_SCRATCH_2_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_SCRATCH_2 not supported on this chip\n");
return 0x00000000000003D0ull;
}
#else
#define CVMX_SLI_SCRATCH_2 (0x00000000000003D0ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_STATE1 CVMX_SLI_STATE1_FUNC()
static inline uint64_t CVMX_SLI_STATE1_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_STATE1 not supported on this chip\n");
return 0x0000000000000620ull;
}
#else
#define CVMX_SLI_STATE1 (0x0000000000000620ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_STATE2 CVMX_SLI_STATE2_FUNC()
static inline uint64_t CVMX_SLI_STATE2_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_STATE2 not supported on this chip\n");
return 0x0000000000000630ull;
}
#else
#define CVMX_SLI_STATE2 (0x0000000000000630ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_STATE3 CVMX_SLI_STATE3_FUNC()
static inline uint64_t CVMX_SLI_STATE3_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_STATE3 not supported on this chip\n");
return 0x0000000000000640ull;
}
#else
#define CVMX_SLI_STATE3 (0x0000000000000640ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_WINDOW_CTL CVMX_SLI_WINDOW_CTL_FUNC()
static inline uint64_t CVMX_SLI_WINDOW_CTL_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_WINDOW_CTL not supported on this chip\n");
return 0x00000000000002E0ull;
}
#else
#define CVMX_SLI_WINDOW_CTL (0x00000000000002E0ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_WIN_RD_ADDR CVMX_SLI_WIN_RD_ADDR_FUNC()
static inline uint64_t CVMX_SLI_WIN_RD_ADDR_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_WIN_RD_ADDR not supported on this chip\n");
return 0x0000000000000010ull;
}
#else
#define CVMX_SLI_WIN_RD_ADDR (0x0000000000000010ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_WIN_RD_DATA CVMX_SLI_WIN_RD_DATA_FUNC()
static inline uint64_t CVMX_SLI_WIN_RD_DATA_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_WIN_RD_DATA not supported on this chip\n");
return 0x0000000000000040ull;
}
#else
#define CVMX_SLI_WIN_RD_DATA (0x0000000000000040ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_WIN_WR_ADDR CVMX_SLI_WIN_WR_ADDR_FUNC()
static inline uint64_t CVMX_SLI_WIN_WR_ADDR_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_WIN_WR_ADDR not supported on this chip\n");
return 0x0000000000000000ull;
}
#else
#define CVMX_SLI_WIN_WR_ADDR (0x0000000000000000ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_WIN_WR_DATA CVMX_SLI_WIN_WR_DATA_FUNC()
static inline uint64_t CVMX_SLI_WIN_WR_DATA_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_WIN_WR_DATA not supported on this chip\n");
return 0x0000000000000020ull;
}
#else
#define CVMX_SLI_WIN_WR_DATA (0x0000000000000020ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SLI_WIN_WR_MASK CVMX_SLI_WIN_WR_MASK_FUNC()
static inline uint64_t CVMX_SLI_WIN_WR_MASK_FUNC(void)
{
if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
cvmx_warn("CVMX_SLI_WIN_WR_MASK not supported on this chip\n");
return 0x0000000000000030ull;
}
#else
#define CVMX_SLI_WIN_WR_MASK (0x0000000000000030ull)
#endif
/**
* cvmx_sli_bist_status
*
* SLI_BIST_STATUS = SLI's BIST Status Register
*
* Results from BIST runs of SLI's memories.
*/
union cvmx_sli_bist_status
{
uint64_t u64;
struct cvmx_sli_bist_status_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_31_63 : 33;
uint64_t n2p0_c : 1; /**< BIST Status for N2P Port0 Cmd */
uint64_t n2p0_o : 1; /**< BIST Status for N2P Port0 Data */
uint64_t n2p1_c : 1; /**< BIST Status for N2P Port1 Cmd */
uint64_t n2p1_o : 1; /**< BIST Status for N2P Port1 Data */
uint64_t cpl_p0 : 1; /**< BIST Status for CPL Port 0 */
uint64_t cpl_p1 : 1; /**< BIST Status for CPL Port 1 */
uint64_t reserved_19_24 : 6;
uint64_t p2n0_c0 : 1; /**< BIST Status for P2N Port0 C0 */
uint64_t p2n0_c1 : 1; /**< BIST Status for P2N Port0 C1 */
uint64_t p2n0_n : 1; /**< BIST Status for P2N Port0 N */
uint64_t p2n0_p0 : 1; /**< BIST Status for P2N Port0 P0 */
uint64_t p2n0_p1 : 1; /**< BIST Status for P2N Port0 P1 */
uint64_t p2n1_c0 : 1; /**< BIST Status for P2N Port1 C0 */
uint64_t p2n1_c1 : 1; /**< BIST Status for P2N Port1 C1 */
uint64_t p2n1_n : 1; /**< BIST Status for P2N Port1 N */
uint64_t p2n1_p0 : 1; /**< BIST Status for P2N Port1 P0 */
uint64_t p2n1_p1 : 1; /**< BIST Status for P2N Port1 P1 */
uint64_t reserved_6_8 : 3;
uint64_t dsi1_1 : 1; /**< BIST Status for DSI1 Memory 1 */
uint64_t dsi1_0 : 1; /**< BIST Status for DSI1 Memory 0 */
uint64_t dsi0_1 : 1; /**< BIST Status for DSI0 Memory 1 */
uint64_t dsi0_0 : 1; /**< BIST Status for DSI0 Memory 0 */
uint64_t msi : 1; /**< BIST Status for MSI Memory Map */
uint64_t ncb_cmd : 1; /**< BIST Status for NCB Outbound Commands */
#else
uint64_t ncb_cmd : 1;
uint64_t msi : 1;
uint64_t dsi0_0 : 1;
uint64_t dsi0_1 : 1;
uint64_t dsi1_0 : 1;
uint64_t dsi1_1 : 1;
uint64_t reserved_6_8 : 3;
uint64_t p2n1_p1 : 1;
uint64_t p2n1_p0 : 1;
uint64_t p2n1_n : 1;
uint64_t p2n1_c1 : 1;
uint64_t p2n1_c0 : 1;
uint64_t p2n0_p1 : 1;
uint64_t p2n0_p0 : 1;
uint64_t p2n0_n : 1;
uint64_t p2n0_c1 : 1;
uint64_t p2n0_c0 : 1;
uint64_t reserved_19_24 : 6;
uint64_t cpl_p1 : 1;
uint64_t cpl_p0 : 1;
uint64_t n2p1_o : 1;
uint64_t n2p1_c : 1;
uint64_t n2p0_o : 1;
uint64_t n2p0_c : 1;
uint64_t reserved_31_63 : 33;
#endif
} s;
struct cvmx_sli_bist_status_s cn63xx;
struct cvmx_sli_bist_status_s cn63xxp1;
};
typedef union cvmx_sli_bist_status cvmx_sli_bist_status_t;
/**
* cvmx_sli_ctl_port#
*
* SLI_CTL_PORTX = SLI's Control Port X
*
* Contains control for access for Port0
*/
union cvmx_sli_ctl_portx
{
uint64_t u64;
struct cvmx_sli_ctl_portx_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_22_63 : 42;
uint64_t intd : 1; /**< When '0' Intd wire asserted. Before mapping. */
uint64_t intc : 1; /**< When '0' Intc wire asserted. Before mapping. */
uint64_t intb : 1; /**< When '0' Intb wire asserted. Before mapping. */
uint64_t inta : 1; /**< When '0' Inta wire asserted. Before mapping. */
uint64_t dis_port : 1; /**< When set the output to the MAC is disabled. This
occurs when the MAC reset line transitions from
de-asserted to asserted. Writing a '1' to this
location will clear this condition when the MAC is
no longer in reset and the output to the MAC is at
the begining of a transfer. */
uint64_t waitl_com : 1; /**< When set '1' casues the SLI to wait for a commit
from the L2C before sending additional completions
to the L2C from a MAC.
Set this for more conservative behavior. Clear
this for more aggressive, higher-performance
behavior */
uint64_t intd_map : 2; /**< Maps INTD to INTA(00), INTB(01), INTC(10) or
INTD (11). */
uint64_t intc_map : 2; /**< Maps INTC to INTA(00), INTB(01), INTC(10) or
INTD (11). */
uint64_t intb_map : 2; /**< Maps INTB to INTA(00), INTB(01), INTC(10) or
INTD (11). */
uint64_t inta_map : 2; /**< Maps INTA to INTA(00), INTB(01), INTC(10) or
INTD (11). */
uint64_t ctlp_ro : 1; /**< Relaxed ordering enable for Completion TLPS. */
uint64_t reserved_6_6 : 1;
uint64_t ptlp_ro : 1; /**< Relaxed ordering enable for Posted TLPS. */
uint64_t reserved_1_4 : 4;
uint64_t wait_com : 1; /**< When set '1' casues the SLI to wait for a commit
from the L2C before sending additional stores to
the L2C from a MAC.
The SLI will request a commit on the last store
if more than one STORE operation is required on
the NCB.
Most applications will not notice a difference, so
should not set this bit. Setting the bit is more
conservative on ordering, lower performance */
#else
uint64_t wait_com : 1;
uint64_t reserved_1_4 : 4;
uint64_t ptlp_ro : 1;
uint64_t reserved_6_6 : 1;
uint64_t ctlp_ro : 1;
uint64_t inta_map : 2;
uint64_t intb_map : 2;
uint64_t intc_map : 2;
uint64_t intd_map : 2;
uint64_t waitl_com : 1;
uint64_t dis_port : 1;
uint64_t inta : 1;
uint64_t intb : 1;
uint64_t intc : 1;
uint64_t intd : 1;
uint64_t reserved_22_63 : 42;
#endif
} s;
struct cvmx_sli_ctl_portx_s cn63xx;
struct cvmx_sli_ctl_portx_s cn63xxp1;
};
typedef union cvmx_sli_ctl_portx cvmx_sli_ctl_portx_t;
/**
* cvmx_sli_ctl_status
*
* SLI_CTL_STATUS = SLI Control Status Register
*
* Contains control and status for SLI. Writes to this register are not ordered with writes/reads to the MAC Memory space.
* To ensure that a write has completed the user must read the register before making an access(i.e. MAC memory space)
* that requires the value of this register to be updated.
*/
union cvmx_sli_ctl_status
{
uint64_t u64;
struct cvmx_sli_ctl_status_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_20_63 : 44;
uint64_t p1_ntags : 6; /**< Number of tags available for MAC Port1.
In RC mode 1 tag is needed for each outbound TLP
that requires a CPL TLP. In Endpoint mode the
number of tags required for a TLP request is
1 per 64-bytes of CPL data + 1.
This field should only be written as part of
reset sequence, before issuing any reads, CFGs, or
IO transactions from the core(s). */
uint64_t p0_ntags : 6; /**< Number of tags available for MAC Port0.
In RC mode 1 tag is needed for each outbound TLP
that requires a CPL TLP. In Endpoint mode the
number of tags required for a TLP request is
1 per 64-bytes of CPL data + 1.
This field should only be written as part of
reset sequence, before issuing any reads, CFGs, or
IO transactions from the core(s). */
uint64_t chip_rev : 8; /**< The chip revision. */
#else
uint64_t chip_rev : 8;
uint64_t p0_ntags : 6;
uint64_t p1_ntags : 6;
uint64_t reserved_20_63 : 44;
#endif
} s;
struct cvmx_sli_ctl_status_s cn63xx;
struct cvmx_sli_ctl_status_s cn63xxp1;
};
typedef union cvmx_sli_ctl_status cvmx_sli_ctl_status_t;
/**
* cvmx_sli_data_out_cnt
*
* SLI_DATA_OUT_CNT = SLI DATA OUT COUNT
*
* The EXEC data out fifo-count and the data unload counter.
*/
union cvmx_sli_data_out_cnt
{
uint64_t u64;
struct cvmx_sli_data_out_cnt_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_44_63 : 20;
uint64_t p1_ucnt : 16; /**< MAC Port1 Fifo Unload Count. This counter is
incremented by '1' every time a word is removed
from the Data Out FIFO, whose count is shown in
P0_FCNT. */
uint64_t p1_fcnt : 6; /**< MAC Port1 Data Out Fifo Count. Number of address
data words to be sent out the MAC port presently
buffered in the FIFO. */
uint64_t p0_ucnt : 16; /**< MAC Port0 Fifo Unload Count. This counter is
incremented by '1' every time a word is removed
from the Data Out FIFO, whose count is shown in
P0_FCNT. */
uint64_t p0_fcnt : 6; /**< MAC Port0 Data Out Fifo Count. Number of address
data words to be sent out the MAC port presently
buffered in the FIFO. */
#else
uint64_t p0_fcnt : 6;
uint64_t p0_ucnt : 16;
uint64_t p1_fcnt : 6;
uint64_t p1_ucnt : 16;
uint64_t reserved_44_63 : 20;
#endif
} s;
struct cvmx_sli_data_out_cnt_s cn63xx;
struct cvmx_sli_data_out_cnt_s cn63xxp1;
};
typedef union cvmx_sli_data_out_cnt cvmx_sli_data_out_cnt_t;
/**
* cvmx_sli_dbg_data
*
* SLI_DBG_DATA = SLI Debug Data Register
*
* Value returned on the debug-data lines from the RSLs
*/
union cvmx_sli_dbg_data
{
uint64_t u64;
struct cvmx_sli_dbg_data_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_18_63 : 46;
uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the
debug select value. */
uint64_t data : 17; /**< Value on the debug data lines. */
#else
uint64_t data : 17;
uint64_t dsel_ext : 1;
uint64_t reserved_18_63 : 46;
#endif
} s;
struct cvmx_sli_dbg_data_s cn63xx;
struct cvmx_sli_dbg_data_s cn63xxp1;
};
typedef union cvmx_sli_dbg_data cvmx_sli_dbg_data_t;
/**
* cvmx_sli_dbg_select
*
* SLI_DBG_SELECT = Debug Select Register
*
* Contains the debug select value last written to the RSLs.
*/
union cvmx_sli_dbg_select
{
uint64_t u64;
struct cvmx_sli_dbg_select_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_33_63 : 31;
uint64_t adbg_sel : 1; /**< When set '1' the SLI_DBG_DATA[DATA] will only be
loaded when SLI_DBG_DATA[DATA] bit [16] is a '1'.
When the debug data comes from an Async-RSL bit
16 is used to tell that the data present is valid. */
uint64_t dbg_sel : 32; /**< When this register is written the RML will write
all "F"s to the previous RTL to disable it from
sending Debug-Data. The RML will then send a write
to the new RSL with the supplied Debug-Select
value. Because it takes time for the new Debug
Select value to take effect and the requested
Debug-Data to return, time is needed to the new
Debug-Data to arrive. The inititator of the Debug
Select should issue a read to a CSR before reading
the Debug Data (this read could also be to the
SLI_DBG_DATA but the returned value for the first
read will return NS data. */
#else
uint64_t dbg_sel : 32;
uint64_t adbg_sel : 1;
uint64_t reserved_33_63 : 31;
#endif
} s;
struct cvmx_sli_dbg_select_s cn63xx;
struct cvmx_sli_dbg_select_s cn63xxp1;
};
typedef union cvmx_sli_dbg_select cvmx_sli_dbg_select_t;
/**
* cvmx_sli_dma#_cnt
*
* SLI_DMAx_CNT = SLI DMA Count
*
* The DMA Count value.
*/
union cvmx_sli_dmax_cnt
{
uint64_t u64;
struct cvmx_sli_dmax_cnt_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_32_63 : 32;
uint64_t cnt : 32; /**< The DMA counter.
Writing this field will cause the written value
to be subtracted from DMA. HW will optionally
increment this field after it completes an
OUTBOUND or EXTERNAL-ONLY DMA instruction. These
increments may cause interrupts. Refer to
SLI_DMAx_INT_LEVEL and SLI_INT_SUM[DCNT,DTIME]. */
#else
uint64_t cnt : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_sli_dmax_cnt_s cn63xx;
struct cvmx_sli_dmax_cnt_s cn63xxp1;
};
typedef union cvmx_sli_dmax_cnt cvmx_sli_dmax_cnt_t;
/**
* cvmx_sli_dma#_int_level
*
* SLI_DMAx_INT_LEVEL = SLI DMAx Interrupt Level
*
* Thresholds for DMA count and timer interrupts.
*/
union cvmx_sli_dmax_int_level
{
uint64_t u64;
struct cvmx_sli_dmax_int_level_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t time : 32; /**< Whenever the SLI_DMAx_TIM[TIM] timer exceeds
this value, SLI_INT_SUM[DTIME<x>] is set.
The SLI_DMAx_TIM[TIM] timer increments every SLI
clock whenever SLI_DMAx_CNT[CNT]!=0, and is
cleared when SLI_INT_SUM[DTIME<x>] is written with
one. */
uint64_t cnt : 32; /**< Whenever SLI_DMAx_CNT[CNT] exceeds this value,
SLI_INT_SUM[DCNT<x>] is set. */
#else
uint64_t cnt : 32;
uint64_t time : 32;
#endif
} s;
struct cvmx_sli_dmax_int_level_s cn63xx;
struct cvmx_sli_dmax_int_level_s cn63xxp1;
};
typedef union cvmx_sli_dmax_int_level cvmx_sli_dmax_int_level_t;
/**
* cvmx_sli_dma#_tim
*
* SLI_DMAx_TIM = SLI DMA Timer
*
* The DMA Timer value.
*/
union cvmx_sli_dmax_tim
{
uint64_t u64;
struct cvmx_sli_dmax_tim_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_32_63 : 32;
uint64_t tim : 32; /**< The DMA timer value.
The timer will increment when SLI_DMAx_CNT[CNT]!=0
and will clear when SLI_DMAx_CNT[CNT]==0 */
#else
uint64_t tim : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_sli_dmax_tim_s cn63xx;
struct cvmx_sli_dmax_tim_s cn63xxp1;
};
typedef union cvmx_sli_dmax_tim cvmx_sli_dmax_tim_t;
/**
* cvmx_sli_int_enb_ciu
*
* SLI_INT_ENB_CIU = SLI's Interrupt Enable CIU Register
*
* Used to enable the various interrupting conditions of SLI
*/
union cvmx_sli_int_enb_ciu
{
uint64_t u64;
struct cvmx_sli_int_enb_ciu_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_61_63 : 3;
uint64_t ill_pad : 1; /**< Illegal packet csr address. */
uint64_t reserved_58_59 : 2;
uint64_t sprt1_err : 1; /**< Error Response received on SLI port 1. */
uint64_t sprt0_err : 1; /**< Error Response received on SLI port 0. */
uint64_t pins_err : 1; /**< Read Error during packet instruction fetch. */
uint64_t pop_err : 1; /**< Read Error during packet scatter pointer fetch. */
uint64_t pdi_err : 1; /**< Read Error during packet data fetch. */
uint64_t pgl_err : 1; /**< Read Error during gather list fetch. */
uint64_t pin_bp : 1; /**< Packet Input Count exceeded WMARK. */
uint64_t pout_err : 1; /**< Packet Out Interrupt, Error From PKO. */
uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell Count Overflow. */
uint64_t pidbof : 1; /**< Packet Instruction Doorbell Count Overflow. */
uint64_t reserved_38_47 : 10;
uint64_t dtime : 2; /**< DMA Timer Interrupts */
uint64_t dcnt : 2; /**< DMA Count Interrupts */
uint64_t dmafi : 2; /**< DMA set Forced Interrupts */
uint64_t reserved_18_31 : 14;
uint64_t mio_int1 : 1; /**< Enables SLI_INT_SUM[17] to generate an
interrupt on the RSL.
THIS SHOULD NEVER BE SET */
uint64_t mio_int0 : 1; /**< Enables SLI_INT_SUM[16] to generate an
interrupt on the RSL.
THIS SHOULD NEVER BE SET */
uint64_t m1_un_wi : 1; /**< Enables SLI_INT_SUM[15] to generate an
interrupt on the RSL. */
uint64_t m1_un_b0 : 1; /**< Enables SLI_INT_SUM[14] to generate an
interrupt on the RSL. */
uint64_t m1_up_wi : 1; /**< Enables SLI_INT_SUM[13] to generate an
interrupt on the RSL. */
uint64_t m1_up_b0 : 1; /**< Enables SLI_INT_SUM[12] to generate an
interrupt on the RSL. */
uint64_t m0_un_wi : 1; /**< Enables SLI_INT_SUM[11] to generate an
interrupt on the RSL. */
uint64_t m0_un_b0 : 1; /**< Enables SLI_INT_SUM[10] to generate an
interrupt on the RSL. */
uint64_t m0_up_wi : 1; /**< Enables SLI_INT_SUM[9] to generate an
interrupt on the RSL. */
uint64_t m0_up_b0 : 1; /**< Enables SLI_INT_SUM[8] to generate an
interrupt on the RSL. */
uint64_t reserved_6_7 : 2;
uint64_t ptime : 1; /**< Enables SLI_INT_SUM[5] to generate an
interrupt on the RSL. */
uint64_t pcnt : 1; /**< Enables SLI_INT_SUM[4] to generate an
interrupt on the RSL. */
uint64_t iob2big : 1; /**< Enables SLI_INT_SUM[3] to generate an
interrupt on the RSL. */
uint64_t bar0_to : 1; /**< Enables SLI_INT_SUM[2] to generate an
interrupt on the RSL. */
uint64_t reserved_1_1 : 1;
uint64_t rml_to : 1; /**< Enables SLI_INT_SUM[0] to generate an
interrupt on the RSL. */
#else
uint64_t rml_to : 1;
uint64_t reserved_1_1 : 1;
uint64_t bar0_to : 1;
uint64_t iob2big : 1;
uint64_t pcnt : 1;
uint64_t ptime : 1;
uint64_t reserved_6_7 : 2;
uint64_t m0_up_b0 : 1;
uint64_t m0_up_wi : 1;
uint64_t m0_un_b0 : 1;
uint64_t m0_un_wi : 1;
uint64_t m1_up_b0 : 1;
uint64_t m1_up_wi : 1;
uint64_t m1_un_b0 : 1;
uint64_t m1_un_wi : 1;
uint64_t mio_int0 : 1;
uint64_t mio_int1 : 1;
uint64_t reserved_18_31 : 14;
uint64_t dmafi : 2;
uint64_t dcnt : 2;
uint64_t dtime : 2;
uint64_t reserved_38_47 : 10;
uint64_t pidbof : 1;
uint64_t psldbof : 1;
uint64_t pout_err : 1;
uint64_t pin_bp : 1;
uint64_t pgl_err : 1;
uint64_t pdi_err : 1;
uint64_t pop_err : 1;
uint64_t pins_err : 1;
uint64_t sprt0_err : 1;
uint64_t sprt1_err : 1;
uint64_t reserved_58_59 : 2;
uint64_t ill_pad : 1;
uint64_t reserved_61_63 : 3;
#endif
} s;
struct cvmx_sli_int_enb_ciu_s cn63xx;
struct cvmx_sli_int_enb_ciu_s cn63xxp1;
};
typedef union cvmx_sli_int_enb_ciu cvmx_sli_int_enb_ciu_t;
/**
* cvmx_sli_int_enb_port#
*
* SLI_INT_ENB_PORTX = SLI's Interrupt Enable Register per mac port
*
* Used to allow the generation of interrupts (MSI/INTA) to the PORT X
*
* Notes:
* This CSR is not used when the corresponding MAC is sRIO.
*
*/
union cvmx_sli_int_enb_portx
{
uint64_t u64;
struct cvmx_sli_int_enb_portx_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_61_63 : 3;
uint64_t ill_pad : 1; /**< Illegal packet csr address. */
uint64_t reserved_58_59 : 2;
uint64_t sprt1_err : 1; /**< Error Response received on SLI port 1. */
uint64_t sprt0_err : 1; /**< Error Response received on SLI port 0. */
uint64_t pins_err : 1; /**< Read Error during packet instruction fetch. */
uint64_t pop_err : 1; /**< Read Error during packet scatter pointer fetch. */
uint64_t pdi_err : 1; /**< Read Error during packet data fetch. */
uint64_t pgl_err : 1; /**< Read Error during gather list fetch. */
uint64_t pin_bp : 1; /**< Packet Input Count exceeded WMARK. */
uint64_t pout_err : 1; /**< Packet Out Interrupt, Error From PKO. */
uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell Count Overflow. */
uint64_t pidbof : 1; /**< Packet Instruction Doorbell Count Overflow. */
uint64_t reserved_38_47 : 10;
uint64_t dtime : 2; /**< DMA Timer Interrupts */
uint64_t dcnt : 2; /**< DMA Count Interrupts */
uint64_t dmafi : 2; /**< DMA set Forced Interrupts */
uint64_t reserved_20_31 : 12;
uint64_t mac1_int : 1; /**< Enables SLI_INT_SUM[19] to generate an
interrupt to the PCIE-Port1 for MSI/inta.
The valuse of this bit has NO effect on PCIE Port0.
SLI_INT_ENB_PORT0[MAC1_INT] sould NEVER be set. */
uint64_t mac0_int : 1; /**< Enables SLI_INT_SUM[18] to generate an
interrupt to the PCIE-Port0 for MSI/inta.
The valus of this bit has NO effect on PCIE Port1.
SLI_INT_ENB_PORT1[MAC0_INT] sould NEVER be set. */
uint64_t mio_int1 : 1; /**< Enables SLI_INT_SUM[17] to generate an
interrupt to the PCIE core for MSI/inta.
SLI_INT_ENB_PORT0[MIO_INT1] should NEVER be set. */
uint64_t mio_int0 : 1; /**< Enables SLI_INT_SUM[16] to generate an
interrupt to the PCIE core for MSI/inta.
SLI_INT_ENB_PORT1[MIO_INT0] should NEVER be set. */
uint64_t m1_un_wi : 1; /**< Enables SLI_INT_SUM[15] to generate an
interrupt to the PCIE core for MSI/inta. */
uint64_t m1_un_b0 : 1; /**< Enables SLI_INT_SUM[14] to generate an
interrupt to the PCIE core for MSI/inta. */
uint64_t m1_up_wi : 1; /**< Enables SLI_INT_SUM[13] to generate an
interrupt to the PCIE core for MSI/inta. */
uint64_t m1_up_b0 : 1; /**< Enables SLI_INT_SUM[12] to generate an
interrupt to the PCIE core for MSI/inta. */
uint64_t m0_un_wi : 1; /**< Enables SLI_INT_SUM[11] to generate an
interrupt to the PCIE core for MSI/inta. */
uint64_t m0_un_b0 : 1; /**< Enables SLI_INT_SUM[10] to generate an
interrupt to the PCIE core for MSI/inta. */
uint64_t m0_up_wi : 1; /**< Enables SLI_INT_SUM[9] to generate an
interrupt to the PCIE core for MSI/inta. */
uint64_t m0_up_b0 : 1; /**< Enables SLI_INT_SUM[8] to generate an
interrupt to the PCIE core for MSI/inta. */
uint64_t reserved_6_7 : 2;
uint64_t ptime : 1; /**< Enables SLI_INT_SUM[5] to generate an
interrupt to the PCIE core for MSI/inta. */
uint64_t pcnt : 1; /**< Enables SLI_INT_SUM[4] to generate an
interrupt to the PCIE core for MSI/inta. */
uint64_t iob2big : 1; /**< Enables SLI_INT_SUM[3] to generate an
interrupt to the PCIE core for MSI/inta. */
uint64_t bar0_to : 1; /**< Enables SLI_INT_SUM[2] to generate an
interrupt to the PCIE core for MSI/inta. */
uint64_t reserved_1_1 : 1;
uint64_t rml_to : 1; /**< Enables SLI_INT_SUM[0] to generate an
interrupt to the PCIE core for MSI/inta. */
#else
uint64_t rml_to : 1;
uint64_t reserved_1_1 : 1;
uint64_t bar0_to : 1;
uint64_t iob2big : 1;
uint64_t pcnt : 1;
uint64_t ptime : 1;
uint64_t reserved_6_7 : 2;
uint64_t m0_up_b0 : 1;
uint64_t m0_up_wi : 1;
uint64_t m0_un_b0 : 1;
uint64_t m0_un_wi : 1;
uint64_t m1_up_b0 : 1;
uint64_t m1_up_wi : 1;
uint64_t m1_un_b0 : 1;
uint64_t m1_un_wi : 1;
uint64_t mio_int0 : 1;
uint64_t mio_int1 : 1;
uint64_t mac0_int : 1;
uint64_t mac1_int : 1;
uint64_t reserved_20_31 : 12;
uint64_t dmafi : 2;
uint64_t dcnt : 2;
uint64_t dtime : 2;
uint64_t reserved_38_47 : 10;
uint64_t pidbof : 1;
uint64_t psldbof : 1;
uint64_t pout_err : 1;
uint64_t pin_bp : 1;
uint64_t pgl_err : 1;
uint64_t pdi_err : 1;
uint64_t pop_err : 1;
uint64_t pins_err : 1;
uint64_t sprt0_err : 1;
uint64_t sprt1_err : 1;
uint64_t reserved_58_59 : 2;
uint64_t ill_pad : 1;
uint64_t reserved_61_63 : 3;
#endif
} s;
struct cvmx_sli_int_enb_portx_s cn63xx;
struct cvmx_sli_int_enb_portx_s cn63xxp1;
};
typedef union cvmx_sli_int_enb_portx cvmx_sli_int_enb_portx_t;
/**
* cvmx_sli_int_sum
*
* SLI_INT_SUM = SLI Interrupt Summary Register
*
* Set when an interrupt condition occurs, write '1' to clear.
*/
union cvmx_sli_int_sum
{
uint64_t u64;
struct cvmx_sli_int_sum_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_61_63 : 3;
uint64_t ill_pad : 1; /**< Set when a BAR0 address R/W falls into theaddress
range of the Packet-CSR, but for an unused
address. */
uint64_t reserved_58_59 : 2;
uint64_t sprt1_err : 1; /**< When an error response received on SLI port 1
this bit is set. */
uint64_t sprt0_err : 1; /**< When an error response received on SLI port 0
this bit is set. */
uint64_t pins_err : 1; /**< When a read error occurs on a packet instruction
this bit is set. */
uint64_t pop_err : 1; /**< When a read error occurs on a packet scatter
pointer pair this bit is set. */
uint64_t pdi_err : 1; /**< When a read error occurs on a packet data read
this bit is set. */
uint64_t pgl_err : 1; /**< When a read error occurs on a packet gather list
read this bit is set. */
uint64_t pin_bp : 1; /**< Packet input count has exceeded the WMARK.
See SLI_PKT_IN_BP */
uint64_t pout_err : 1; /**< Set when PKO sends packet data with the error bit
set. */
uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell count overflowed. Which
doorbell can be found in DPI_PINT_INFO[PSLDBOF] */
uint64_t pidbof : 1; /**< Packet Instruction Doorbell count overflowed. Which
doorbell can be found in DPI_PINT_INFO[PIDBOF] */
uint64_t reserved_38_47 : 10;
uint64_t dtime : 2; /**< Whenever SLI_DMAx_CNT[CNT] is not 0, the
SLI_DMAx_TIM[TIM] timer increments every SLI
clock.
DTIME[x] is set whenever SLI_DMAx_TIM[TIM] >
SLI_DMAx_INT_LEVEL[TIME].
DTIME[x] is normally cleared by clearing
SLI_DMAx_CNT[CNT] (which also clears
SLI_DMAx_TIM[TIM]). */
uint64_t dcnt : 2; /**< DCNT[x] is set whenever SLI_DMAx_CNT[CNT] >
SLI_DMAx_INT_LEVEL[CNT].
DCNT[x] is normally cleared by decreasing
SLI_DMAx_CNT[CNT]. */
uint64_t dmafi : 2; /**< DMA set Forced Interrupts. */
uint64_t reserved_20_31 : 12;
uint64_t mac1_int : 1; /**< Interrupt from MAC1.
See PEM1_INT_SUM (enabled by PEM1_INT_ENB_INT) */
uint64_t mac0_int : 1; /**< Interrupt from MAC0.
See PEM0_INT_SUM (enabled by PEM0_INT_ENB_INT) */
uint64_t mio_int1 : 1; /**< Interrupt from MIO for PORT 1.
See CIU_INT33_SUM0, CIU_INT_SUM1
(enabled by CIU_INT33_EN0, CIU_INT33_EN1) */
uint64_t mio_int0 : 1; /**< Interrupt from MIO for PORT 0.
See CIU_INT32_SUM0, CIU_INT_SUM1
(enabled by CIU_INT32_EN0, CIU_INT32_EN1) */
uint64_t m1_un_wi : 1; /**< Received Unsupported N-TLP for Window Register
from MAC 1. This occurs when the window registers
are disabeld and a window register access occurs. */
uint64_t m1_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0 from MAC 1.
This occurs when the BAR 0 address space is
disabeled. */
uint64_t m1_up_wi : 1; /**< Received Unsupported P-TLP for Window Register
from MAC 1. This occurs when the window registers
are disabeld and a window register access occurs. */
uint64_t m1_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0 from MAC 1.
This occurs when the BAR 0 address space is
disabeled. */
uint64_t m0_un_wi : 1; /**< Received Unsupported N-TLP for Window Register
from MAC 0. This occurs when the window registers
are disabeld and a window register access occurs. */
uint64_t m0_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0 from MAC 0.
This occurs when the BAR 0 address space is
disabeled. */
uint64_t m0_up_wi : 1; /**< Received Unsupported P-TLP for Window Register
from MAC 0. This occurs when the window registers
are disabeld and a window register access occurs. */
uint64_t m0_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0 from MAC 0.
This occurs when the BAR 0 address space is
disabeled. */
uint64_t reserved_6_7 : 2;
uint64_t ptime : 1; /**< Packet Timer has an interrupt. Which rings can
be found in SLI_PKT_TIME_INT. */
uint64_t pcnt : 1; /**< Packet Counter has an interrupt. Which rings can
be found in SLI_PKT_CNT_INT. */
uint64_t iob2big : 1; /**< A requested IOBDMA is to large. */
uint64_t bar0_to : 1; /**< BAR0 R/W to a NCB device did not receive
read-data/commit in 0xffff core clocks. */
uint64_t reserved_1_1 : 1;
uint64_t rml_to : 1; /**< A read or write transfer did not complete
within 0xffff core clocks. */
#else
uint64_t rml_to : 1;
uint64_t reserved_1_1 : 1;
uint64_t bar0_to : 1;
uint64_t iob2big : 1;
uint64_t pcnt : 1;
uint64_t ptime : 1;
uint64_t reserved_6_7 : 2;
uint64_t m0_up_b0 : 1;
uint64_t m0_up_wi : 1;
uint64_t m0_un_b0 : 1;
uint64_t m0_un_wi : 1;
uint64_t m1_up_b0 : 1;
uint64_t m1_up_wi : 1;
uint64_t m1_un_b0 : 1;
uint64_t m1_un_wi : 1;
uint64_t mio_int0 : 1;
uint64_t mio_int1 : 1;
uint64_t mac0_int : 1;
uint64_t mac1_int : 1;
uint64_t reserved_20_31 : 12;
uint64_t dmafi : 2;
uint64_t dcnt : 2;
uint64_t dtime : 2;
uint64_t reserved_38_47 : 10;
uint64_t pidbof : 1;
uint64_t psldbof : 1;
uint64_t pout_err : 1;
uint64_t pin_bp : 1;
uint64_t pgl_err : 1;
uint64_t pdi_err : 1;
uint64_t pop_err : 1;
uint64_t pins_err : 1;
uint64_t sprt0_err : 1;
uint64_t sprt1_err : 1;
uint64_t reserved_58_59 : 2;
uint64_t ill_pad : 1;
uint64_t reserved_61_63 : 3;
#endif
} s;
struct cvmx_sli_int_sum_s cn63xx;
struct cvmx_sli_int_sum_s cn63xxp1;
};
typedef union cvmx_sli_int_sum cvmx_sli_int_sum_t;
/**
* cvmx_sli_last_win_rdata0
*
* SLI_LAST_WIN_RDATA0 = SLI Last Window Read Data Port0
*
* The data from the last initiated window read.
*/
union cvmx_sli_last_win_rdata0
{
uint64_t u64;
struct cvmx_sli_last_win_rdata0_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t data : 64; /**< Last window read data. */
#else
uint64_t data : 64;
#endif
} s;
struct cvmx_sli_last_win_rdata0_s cn63xx;
struct cvmx_sli_last_win_rdata0_s cn63xxp1;
};
typedef union cvmx_sli_last_win_rdata0 cvmx_sli_last_win_rdata0_t;
/**
* cvmx_sli_last_win_rdata1
*
* SLI_LAST_WIN_RDATA1 = SLI Last Window Read Data Port1
*
* The data from the last initiated window read.
*/
union cvmx_sli_last_win_rdata1
{
uint64_t u64;
struct cvmx_sli_last_win_rdata1_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t data : 64; /**< Last window read data. */
#else
uint64_t data : 64;
#endif
} s;
struct cvmx_sli_last_win_rdata1_s cn63xx;
struct cvmx_sli_last_win_rdata1_s cn63xxp1;
};
typedef union cvmx_sli_last_win_rdata1 cvmx_sli_last_win_rdata1_t;
/**
* cvmx_sli_mac_credit_cnt
*
* SLI_MAC_CREDIT_CNT = SLI MAC Credit Count
*
* Contains the number of credits for the MAC port FIFOs used by the SLI. This value needs to be set BEFORE S2M traffic
* flow starts. A write to this register will cause the credit counts in the SLI for the MAC ports to be reset to the value
* in this register.
*/
union cvmx_sli_mac_credit_cnt
{
uint64_t u64;
struct cvmx_sli_mac_credit_cnt_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_54_63 : 10;
uint64_t p1_c_d : 1; /**< When set does not allow writing of P1_CCNT. */
uint64_t p1_n_d : 1; /**< When set does not allow writing of P1_NCNT. */
uint64_t p1_p_d : 1; /**< When set does not allow writing of P1_PCNT. */
uint64_t p0_c_d : 1; /**< When set does not allow writing of P0_CCNT. */
uint64_t p0_n_d : 1; /**< When set does not allow writing of P0_NCNT. */
uint64_t p0_p_d : 1; /**< When set does not allow writing of P0_PCNT. */
uint64_t p1_ccnt : 8; /**< Port1 C-TLP FIFO Credits.
Legal values are 0x25 to 0x80. */
uint64_t p1_ncnt : 8; /**< Port1 N-TLP FIFO Credits.
Legal values are 0x5 to 0x10. */
uint64_t p1_pcnt : 8; /**< Port1 P-TLP FIFO Credits.
Legal values are 0x25 to 0x80. */
uint64_t p0_ccnt : 8; /**< Port0 C-TLP FIFO Credits.
Legal values are 0x25 to 0x80. */
uint64_t p0_ncnt : 8; /**< Port0 N-TLP FIFO Credits.
Legal values are 0x5 to 0x10. */
uint64_t p0_pcnt : 8; /**< Port0 P-TLP FIFO Credits.
Legal values are 0x25 to 0x80. */
#else
uint64_t p0_pcnt : 8;
uint64_t p0_ncnt : 8;
uint64_t p0_ccnt : 8;
uint64_t p1_pcnt : 8;
uint64_t p1_ncnt : 8;
uint64_t p1_ccnt : 8;
uint64_t p0_p_d : 1;
uint64_t p0_n_d : 1;
uint64_t p0_c_d : 1;
uint64_t p1_p_d : 1;
uint64_t p1_n_d : 1;
uint64_t p1_c_d : 1;
uint64_t reserved_54_63 : 10;
#endif
} s;
struct cvmx_sli_mac_credit_cnt_s cn63xx;
struct cvmx_sli_mac_credit_cnt_cn63xxp1
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_48_63 : 16;
uint64_t p1_ccnt : 8; /**< Port1 C-TLP FIFO Credits.
Legal values are 0x25 to 0x80. */
uint64_t p1_ncnt : 8; /**< Port1 N-TLP FIFO Credits.
Legal values are 0x5 to 0x10. */
uint64_t p1_pcnt : 8; /**< Port1 P-TLP FIFO Credits.
Legal values are 0x25 to 0x80. */
uint64_t p0_ccnt : 8; /**< Port0 C-TLP FIFO Credits.
Legal values are 0x25 to 0x80. */
uint64_t p0_ncnt : 8; /**< Port0 N-TLP FIFO Credits.
Legal values are 0x5 to 0x10. */
uint64_t p0_pcnt : 8; /**< Port0 P-TLP FIFO Credits.
Legal values are 0x25 to 0x80. */
#else
uint64_t p0_pcnt : 8;
uint64_t p0_ncnt : 8;
uint64_t p0_ccnt : 8;
uint64_t p1_pcnt : 8;
uint64_t p1_ncnt : 8;
uint64_t p1_ccnt : 8;
uint64_t reserved_48_63 : 16;
#endif
} cn63xxp1;
};
typedef union cvmx_sli_mac_credit_cnt cvmx_sli_mac_credit_cnt_t;
/**
* cvmx_sli_mac_number
*
* 0x13DA0 - 0x13DF0 reserved for ports 2 - 7
*
* SLI_MAC_NUMBER = SLI MAC Number
*
* When read from a MAC port it returns the MAC's port number.
* register.
*/
union cvmx_sli_mac_number
{
uint64_t u64;
struct cvmx_sli_mac_number_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_8_63 : 56;
uint64_t num : 8; /**< The mac number. */
#else
uint64_t num : 8;
uint64_t reserved_8_63 : 56;
#endif
} s;
struct cvmx_sli_mac_number_s cn63xx;
};
typedef union cvmx_sli_mac_number cvmx_sli_mac_number_t;
/**
* cvmx_sli_mem_access_ctl
*
* SLI_MEM_ACCESS_CTL = SLI's Memory Access Control
*
* Contains control for access to the MAC address space.
*/
union cvmx_sli_mem_access_ctl
{
uint64_t u64;
struct cvmx_sli_mem_access_ctl_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_14_63 : 50;
uint64_t max_word : 4; /**< The maximum number of words to merge into a single
write operation from the PPs to the MAC. Legal
values are 1 to 16, where a '0' is treated as 16. */
uint64_t timer : 10; /**< When the SLI starts a PP to MAC write it waits
no longer than the value of TIMER in eclks to
merge additional writes from the PPs into 1
large write. The values for this field is 1 to
1024 where a value of '0' is treated as 1024. */
#else
uint64_t timer : 10;
uint64_t max_word : 4;
uint64_t reserved_14_63 : 50;
#endif
} s;
struct cvmx_sli_mem_access_ctl_s cn63xx;
struct cvmx_sli_mem_access_ctl_s cn63xxp1;
};
typedef union cvmx_sli_mem_access_ctl cvmx_sli_mem_access_ctl_t;
/**
* cvmx_sli_mem_access_subid#
*
* // *
* // * 8070 - 80C0 saved for ports 2 through 7
* // *
* // *
* // * 0x80d0 free
* // *
*
* SLI_MEM_ACCESS_SUBIDX = SLI Memory Access SubidX Register
*
* Contains address index and control bits for access to memory from Core PPs.
*/
union cvmx_sli_mem_access_subidx
{
uint64_t u64;
struct cvmx_sli_mem_access_subidx_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_43_63 : 21;
uint64_t zero : 1; /**< Causes all byte reads to be zero length reads.
Returns to the EXEC a zero for all read data.
This must be zero for sRIO ports. */
uint64_t port : 3; /**< Physical MAC Port that reads/writes to
this subid are sent to. Must be <= 1, as there are
only two ports present. */
uint64_t nmerge : 1; /**< When set, no merging is allowed in this window. */
uint64_t esr : 2; /**< ES<1:0> for reads to this subid.
ES<1:0> is the endian-swap attribute for these MAC
memory space reads. */
uint64_t esw : 2; /**< ES<1:0> for writes to this subid.
ES<1:0> is the endian-swap attribute for these MAC
memory space writes. */
uint64_t wtype : 2; /**< ADDRTYPE<1:0> for writes to this subid
For PCIe:
- ADDRTYPE<0> is the relaxed-order attribute
- ADDRTYPE<1> is the no-snoop attribute
For sRIO:
- ADDRTYPE<1:0> help select an SRIO*_S2M_TYPE*
entry */
uint64_t rtype : 2; /**< ADDRTYPE<1:0> for reads to this subid
For PCIe:
- ADDRTYPE<0> is the relaxed-order attribute
- ADDRTYPE<1> is the no-snoop attribute
For sRIO:
- ADDRTYPE<1:0> help select an SRIO*_S2M_TYPE*
entry */
uint64_t ba : 30; /**< Address Bits <63:34> for reads/writes that use
this subid. */
#else
uint64_t ba : 30;
uint64_t rtype : 2;
uint64_t wtype : 2;
uint64_t esw : 2;
uint64_t esr : 2;
uint64_t nmerge : 1;
uint64_t port : 3;
uint64_t zero : 1;
uint64_t reserved_43_63 : 21;
#endif
} s;
struct cvmx_sli_mem_access_subidx_s cn63xx;
struct cvmx_sli_mem_access_subidx_s cn63xxp1;
};
typedef union cvmx_sli_mem_access_subidx cvmx_sli_mem_access_subidx_t;
/**
* cvmx_sli_msi_enb0
*
* SLI_MSI_ENB0 = SLI MSI Enable0
*
* Used to enable the interrupt generation for the bits in the SLI_MSI_RCV0.
*/
union cvmx_sli_msi_enb0
{
uint64_t u64;
struct cvmx_sli_msi_enb0_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t enb : 64; /**< Enables bit [63:0] of SLI_MSI_RCV0. */
#else
uint64_t enb : 64;
#endif
} s;
struct cvmx_sli_msi_enb0_s cn63xx;
struct cvmx_sli_msi_enb0_s cn63xxp1;
};
typedef union cvmx_sli_msi_enb0 cvmx_sli_msi_enb0_t;
/**
* cvmx_sli_msi_enb1
*
* SLI_MSI_ENB1 = SLI MSI Enable1
*
* Used to enable the interrupt generation for the bits in the SLI_MSI_RCV1.
*/
union cvmx_sli_msi_enb1
{
uint64_t u64;
struct cvmx_sli_msi_enb1_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t enb : 64; /**< Enables bit [63:0] of SLI_MSI_RCV1. */
#else
uint64_t enb : 64;
#endif
} s;
struct cvmx_sli_msi_enb1_s cn63xx;
struct cvmx_sli_msi_enb1_s cn63xxp1;
};
typedef union cvmx_sli_msi_enb1 cvmx_sli_msi_enb1_t;
/**
* cvmx_sli_msi_enb2
*
* SLI_MSI_ENB2 = SLI MSI Enable2
*
* Used to enable the interrupt generation for the bits in the SLI_MSI_RCV2.
*/
union cvmx_sli_msi_enb2
{
uint64_t u64;
struct cvmx_sli_msi_enb2_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t enb : 64; /**< Enables bit [63:0] of SLI_MSI_RCV2. */
#else
uint64_t enb : 64;
#endif
} s;
struct cvmx_sli_msi_enb2_s cn63xx;
struct cvmx_sli_msi_enb2_s cn63xxp1;
};
typedef union cvmx_sli_msi_enb2 cvmx_sli_msi_enb2_t;
/**
* cvmx_sli_msi_enb3
*
* SLI_MSI_ENB3 = SLI MSI Enable3
*
* Used to enable the interrupt generation for the bits in the SLI_MSI_RCV3.
*/
union cvmx_sli_msi_enb3
{
uint64_t u64;
struct cvmx_sli_msi_enb3_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t enb : 64; /**< Enables bit [63:0] of SLI_MSI_RCV3. */
#else
uint64_t enb : 64;
#endif
} s;
struct cvmx_sli_msi_enb3_s cn63xx;
struct cvmx_sli_msi_enb3_s cn63xxp1;
};
typedef union cvmx_sli_msi_enb3 cvmx_sli_msi_enb3_t;
/**
* cvmx_sli_msi_rcv0
*
* SLI_MSI_RCV0 = SLI MSI Receive0
*
* Contains bits [63:0] of the 256 bits of MSI interrupts.
*/
union cvmx_sli_msi_rcv0
{
uint64_t u64;
struct cvmx_sli_msi_rcv0_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t intr : 64; /**< Bits 63-0 of the 256 bits of MSI interrupt. */
#else
uint64_t intr : 64;
#endif
} s;
struct cvmx_sli_msi_rcv0_s cn63xx;
struct cvmx_sli_msi_rcv0_s cn63xxp1;
};
typedef union cvmx_sli_msi_rcv0 cvmx_sli_msi_rcv0_t;
/**
* cvmx_sli_msi_rcv1
*
* SLI_MSI_RCV1 = SLI MSI Receive1
*
* Contains bits [127:64] of the 256 bits of MSI interrupts.
*/
union cvmx_sli_msi_rcv1
{
uint64_t u64;
struct cvmx_sli_msi_rcv1_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t intr : 64; /**< Bits 127-64 of the 256 bits of MSI interrupt. */
#else
uint64_t intr : 64;
#endif
} s;
struct cvmx_sli_msi_rcv1_s cn63xx;
struct cvmx_sli_msi_rcv1_s cn63xxp1;
};
typedef union cvmx_sli_msi_rcv1 cvmx_sli_msi_rcv1_t;
/**
* cvmx_sli_msi_rcv2
*
* SLI_MSI_RCV2 = SLI MSI Receive2
*
* Contains bits [191:128] of the 256 bits of MSI interrupts.
*/
union cvmx_sli_msi_rcv2
{
uint64_t u64;
struct cvmx_sli_msi_rcv2_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t intr : 64; /**< Bits 191-128 of the 256 bits of MSI interrupt. */
#else
uint64_t intr : 64;
#endif
} s;
struct cvmx_sli_msi_rcv2_s cn63xx;
struct cvmx_sli_msi_rcv2_s cn63xxp1;
};
typedef union cvmx_sli_msi_rcv2 cvmx_sli_msi_rcv2_t;
/**
* cvmx_sli_msi_rcv3
*
* SLI_MSI_RCV3 = SLI MSI Receive3
*
* Contains bits [255:192] of the 256 bits of MSI interrupts.
*/
union cvmx_sli_msi_rcv3
{
uint64_t u64;
struct cvmx_sli_msi_rcv3_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t intr : 64; /**< Bits 255-192 of the 256 bits of MSI interrupt. */
#else
uint64_t intr : 64;
#endif
} s;
struct cvmx_sli_msi_rcv3_s cn63xx;
struct cvmx_sli_msi_rcv3_s cn63xxp1;
};
typedef union cvmx_sli_msi_rcv3 cvmx_sli_msi_rcv3_t;
/**
* cvmx_sli_msi_rd_map
*
* SLI_MSI_RD_MAP = SLI MSI Read MAP
*
* Used to read the mapping function of the SLI_PCIE_MSI_RCV to SLI_MSI_RCV registers.
*/
union cvmx_sli_msi_rd_map
{
uint64_t u64;
struct cvmx_sli_msi_rd_map_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_16_63 : 48;
uint64_t rd_int : 8; /**< The value of the map at the location PREVIOUSLY
written to the MSI_INT field of this register. */
uint64_t msi_int : 8; /**< Selects the value that would be received when the
SLI_PCIE_MSI_RCV register is written. */
#else
uint64_t msi_int : 8;
uint64_t rd_int : 8;
uint64_t reserved_16_63 : 48;
#endif
} s;
struct cvmx_sli_msi_rd_map_s cn63xx;
struct cvmx_sli_msi_rd_map_s cn63xxp1;
};
typedef union cvmx_sli_msi_rd_map cvmx_sli_msi_rd_map_t;
/**
* cvmx_sli_msi_w1c_enb0
*
* SLI_MSI_W1C_ENB0 = SLI MSI Write 1 To Clear Enable0
*
* Used to clear bits in SLI_MSI_ENB0.
*/
union cvmx_sli_msi_w1c_enb0
{
uint64_t u64;
struct cvmx_sli_msi_w1c_enb0_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t clr : 64; /**< A write of '1' to a vector will clear the
cooresponding bit in SLI_MSI_ENB0.
A read to this address will return 0. */
#else
uint64_t clr : 64;
#endif
} s;
struct cvmx_sli_msi_w1c_enb0_s cn63xx;
struct cvmx_sli_msi_w1c_enb0_s cn63xxp1;
};
typedef union cvmx_sli_msi_w1c_enb0 cvmx_sli_msi_w1c_enb0_t;
/**
* cvmx_sli_msi_w1c_enb1
*
* SLI_MSI_W1C_ENB1 = SLI MSI Write 1 To Clear Enable1
*
* Used to clear bits in SLI_MSI_ENB1.
*/
union cvmx_sli_msi_w1c_enb1
{
uint64_t u64;
struct cvmx_sli_msi_w1c_enb1_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t clr : 64; /**< A write of '1' to a vector will clear the
cooresponding bit in SLI_MSI_ENB1.
A read to this address will return 0. */
#else
uint64_t clr : 64;
#endif
} s;
struct cvmx_sli_msi_w1c_enb1_s cn63xx;
struct cvmx_sli_msi_w1c_enb1_s cn63xxp1;
};
typedef union cvmx_sli_msi_w1c_enb1 cvmx_sli_msi_w1c_enb1_t;
/**
* cvmx_sli_msi_w1c_enb2
*
* SLI_MSI_W1C_ENB2 = SLI MSI Write 1 To Clear Enable2
*
* Used to clear bits in SLI_MSI_ENB2.
*/
union cvmx_sli_msi_w1c_enb2
{
uint64_t u64;
struct cvmx_sli_msi_w1c_enb2_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t clr : 64; /**< A write of '1' to a vector will clear the
cooresponding bit in SLI_MSI_ENB2.
A read to this address will return 0. */
#else
uint64_t clr : 64;
#endif
} s;
struct cvmx_sli_msi_w1c_enb2_s cn63xx;
struct cvmx_sli_msi_w1c_enb2_s cn63xxp1;
};
typedef union cvmx_sli_msi_w1c_enb2 cvmx_sli_msi_w1c_enb2_t;
/**
* cvmx_sli_msi_w1c_enb3
*
* SLI_MSI_W1C_ENB3 = SLI MSI Write 1 To Clear Enable3
*
* Used to clear bits in SLI_MSI_ENB3.
*/
union cvmx_sli_msi_w1c_enb3
{
uint64_t u64;
struct cvmx_sli_msi_w1c_enb3_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t clr : 64; /**< A write of '1' to a vector will clear the
cooresponding bit in SLI_MSI_ENB3.
A read to this address will return 0. */
#else
uint64_t clr : 64;
#endif
} s;
struct cvmx_sli_msi_w1c_enb3_s cn63xx;
struct cvmx_sli_msi_w1c_enb3_s cn63xxp1;
};
typedef union cvmx_sli_msi_w1c_enb3 cvmx_sli_msi_w1c_enb3_t;
/**
* cvmx_sli_msi_w1s_enb0
*
* SLI_MSI_W1S_ENB0 = SLI MSI Write 1 To Set Enable0
*
* Used to set bits in SLI_MSI_ENB0.
*/
union cvmx_sli_msi_w1s_enb0
{
uint64_t u64;
struct cvmx_sli_msi_w1s_enb0_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t set : 64; /**< A write of '1' to a vector will set the
cooresponding bit in SLI_MSI_ENB0.
A read to this address will return 0. */
#else
uint64_t set : 64;
#endif
} s;
struct cvmx_sli_msi_w1s_enb0_s cn63xx;
struct cvmx_sli_msi_w1s_enb0_s cn63xxp1;
};
typedef union cvmx_sli_msi_w1s_enb0 cvmx_sli_msi_w1s_enb0_t;
/**
* cvmx_sli_msi_w1s_enb1
*
* SLI_MSI_W1S_ENB0 = SLI MSI Write 1 To Set Enable1
*
* Used to set bits in SLI_MSI_ENB1.
*/
union cvmx_sli_msi_w1s_enb1
{
uint64_t u64;
struct cvmx_sli_msi_w1s_enb1_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t set : 64; /**< A write of '1' to a vector will set the
cooresponding bit in SLI_MSI_ENB1.
A read to this address will return 0. */
#else
uint64_t set : 64;
#endif
} s;
struct cvmx_sli_msi_w1s_enb1_s cn63xx;
struct cvmx_sli_msi_w1s_enb1_s cn63xxp1;
};
typedef union cvmx_sli_msi_w1s_enb1 cvmx_sli_msi_w1s_enb1_t;
/**
* cvmx_sli_msi_w1s_enb2
*
* SLI_MSI_W1S_ENB2 = SLI MSI Write 1 To Set Enable2
*
* Used to set bits in SLI_MSI_ENB2.
*/
union cvmx_sli_msi_w1s_enb2
{
uint64_t u64;
struct cvmx_sli_msi_w1s_enb2_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t set : 64; /**< A write of '1' to a vector will set the
cooresponding bit in SLI_MSI_ENB2.
A read to this address will return 0. */
#else
uint64_t set : 64;
#endif
} s;
struct cvmx_sli_msi_w1s_enb2_s cn63xx;
struct cvmx_sli_msi_w1s_enb2_s cn63xxp1;
};
typedef union cvmx_sli_msi_w1s_enb2 cvmx_sli_msi_w1s_enb2_t;
/**
* cvmx_sli_msi_w1s_enb3
*
* SLI_MSI_W1S_ENB3 = SLI MSI Write 1 To Set Enable3
*
* Used to set bits in SLI_MSI_ENB3.
*/
union cvmx_sli_msi_w1s_enb3
{
uint64_t u64;
struct cvmx_sli_msi_w1s_enb3_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t set : 64; /**< A write of '1' to a vector will set the
cooresponding bit in SLI_MSI_ENB3.
A read to this address will return 0. */
#else
uint64_t set : 64;
#endif
} s;
struct cvmx_sli_msi_w1s_enb3_s cn63xx;
struct cvmx_sli_msi_w1s_enb3_s cn63xxp1;
};
typedef union cvmx_sli_msi_w1s_enb3 cvmx_sli_msi_w1s_enb3_t;
/**
* cvmx_sli_msi_wr_map
*
* SLI_MSI_WR_MAP = SLI MSI Write MAP
*
* Used to write the mapping function of the SLI_PCIE_MSI_RCV to SLI_MSI_RCV registers.
*/
union cvmx_sli_msi_wr_map
{
uint64_t u64;
struct cvmx_sli_msi_wr_map_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_16_63 : 48;
uint64_t ciu_int : 8; /**< Selects which bit in the SLI_MSI_RCV# (0-255)
will be set when the value specified in the
MSI_INT of this register is recevied during a
write to the SLI_PCIE_MSI_RCV register. */
uint64_t msi_int : 8; /**< Selects the value that would be received when the
SLI_PCIE_MSI_RCV register is written. */
#else
uint64_t msi_int : 8;
uint64_t ciu_int : 8;
uint64_t reserved_16_63 : 48;
#endif
} s;
struct cvmx_sli_msi_wr_map_s cn63xx;
struct cvmx_sli_msi_wr_map_s cn63xxp1;
};
typedef union cvmx_sli_msi_wr_map cvmx_sli_msi_wr_map_t;
/**
* cvmx_sli_pcie_msi_rcv
*
* SLI_PCIE_MSI_RCV = SLI MAC MSI Receive
*
* Register where MSI writes are directed from the MAC.
*/
union cvmx_sli_pcie_msi_rcv
{
uint64_t u64;
struct cvmx_sli_pcie_msi_rcv_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_8_63 : 56;
uint64_t intr : 8; /**< A write to this register will result in a bit in
one of the SLI_MSI_RCV# registers being set.
Which bit is set is dependent on the previously
written using the SLI_MSI_WR_MAP register or if
not previously written the reset value of the MAP. */
#else
uint64_t intr : 8;
uint64_t reserved_8_63 : 56;
#endif
} s;
struct cvmx_sli_pcie_msi_rcv_s cn63xx;
struct cvmx_sli_pcie_msi_rcv_s cn63xxp1;
};
typedef union cvmx_sli_pcie_msi_rcv cvmx_sli_pcie_msi_rcv_t;
/**
* cvmx_sli_pcie_msi_rcv_b1
*
* SLI_PCIE_MSI_RCV_B1 = SLI MAC MSI Receive Byte 1
*
* Register where MSI writes are directed from the MAC.
*
* Notes:
* This CSR can be used by PCIe and sRIO MACs.
*
*/
union cvmx_sli_pcie_msi_rcv_b1
{
uint64_t u64;
struct cvmx_sli_pcie_msi_rcv_b1_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_16_63 : 48;
uint64_t intr : 8; /**< A write to this register will result in a bit in
one of the SLI_MSI_RCV# registers being set.
Which bit is set is dependent on the previously
written using the SLI_MSI_WR_MAP register or if
not previously written the reset value of the MAP. */
uint64_t reserved_0_7 : 8;
#else
uint64_t reserved_0_7 : 8;
uint64_t intr : 8;
uint64_t reserved_16_63 : 48;
#endif
} s;
struct cvmx_sli_pcie_msi_rcv_b1_s cn63xx;
struct cvmx_sli_pcie_msi_rcv_b1_s cn63xxp1;
};
typedef union cvmx_sli_pcie_msi_rcv_b1 cvmx_sli_pcie_msi_rcv_b1_t;
/**
* cvmx_sli_pcie_msi_rcv_b2
*
* SLI_PCIE_MSI_RCV_B2 = SLI MAC MSI Receive Byte 2
*
* Register where MSI writes are directed from the MAC.
*
* Notes:
* This CSR can be used by PCIe and sRIO MACs.
*
*/
union cvmx_sli_pcie_msi_rcv_b2
{
uint64_t u64;
struct cvmx_sli_pcie_msi_rcv_b2_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_24_63 : 40;
uint64_t intr : 8; /**< A write to this register will result in a bit in
one of the SLI_MSI_RCV# registers being set.
Which bit is set is dependent on the previously
written using the SLI_MSI_WR_MAP register or if
not previously written the reset value of the MAP. */
uint64_t reserved_0_15 : 16;
#else
uint64_t reserved_0_15 : 16;
uint64_t intr : 8;
uint64_t reserved_24_63 : 40;
#endif
} s;
struct cvmx_sli_pcie_msi_rcv_b2_s cn63xx;
struct cvmx_sli_pcie_msi_rcv_b2_s cn63xxp1;
};
typedef union cvmx_sli_pcie_msi_rcv_b2 cvmx_sli_pcie_msi_rcv_b2_t;
/**
* cvmx_sli_pcie_msi_rcv_b3
*
* SLI_PCIE_MSI_RCV_B3 = SLI MAC MSI Receive Byte 3
*
* Register where MSI writes are directed from the MAC.
*
* Notes:
* This CSR can be used by PCIe and sRIO MACs.
*
*/
union cvmx_sli_pcie_msi_rcv_b3
{
uint64_t u64;
struct cvmx_sli_pcie_msi_rcv_b3_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_32_63 : 32;
uint64_t intr : 8; /**< A write to this register will result in a bit in
one of the SLI_MSI_RCV# registers being set.
Which bit is set is dependent on the previously
written using the SLI_MSI_WR_MAP register or if
not previously written the reset value of the MAP. */
uint64_t reserved_0_23 : 24;
#else
uint64_t reserved_0_23 : 24;
uint64_t intr : 8;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_sli_pcie_msi_rcv_b3_s cn63xx;
struct cvmx_sli_pcie_msi_rcv_b3_s cn63xxp1;
};
typedef union cvmx_sli_pcie_msi_rcv_b3 cvmx_sli_pcie_msi_rcv_b3_t;
/**
* cvmx_sli_pkt#_cnts
*
* SLI_PKT[0..31]_CNTS = SLI Packet ring# Counts
*
* The counters for output rings.
*/
union cvmx_sli_pktx_cnts
{
uint64_t u64;
struct cvmx_sli_pktx_cnts_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_54_63 : 10;
uint64_t timer : 22; /**< Timer incremented every 1024 core clocks
when SLI_PKTS#_CNTS[CNT] is non zero. Field
cleared when SLI_PKTS#_CNTS[CNT] goes to 0.
Field is also cleared when SLI_PKT_TIME_INT is
cleared.
The first increment of this count can occur
between 0 to 1023 core clocks. */
uint64_t cnt : 32; /**< ring counter. This field is incremented as
packets are sent out and decremented in response to
writes to this field.
When SLI_PKT_OUT_BMODE is '0' a value of 1 is
added to the register for each packet, when '1'
and the info-pointer is NOT used the length of the
packet plus 8 is added, when '1' and info-pointer
mode IS used the packet length is added to this
field. */
#else
uint64_t cnt : 32;
uint64_t timer : 22;
uint64_t reserved_54_63 : 10;
#endif
} s;
struct cvmx_sli_pktx_cnts_s cn63xx;
struct cvmx_sli_pktx_cnts_s cn63xxp1;
};
typedef union cvmx_sli_pktx_cnts cvmx_sli_pktx_cnts_t;
/**
* cvmx_sli_pkt#_in_bp
*
* SLI_PKT[0..31]_IN_BP = SLI Packet ring# Input Backpressure
*
* The counters and thresholds for input packets to apply backpressure to processing of the packets.
*/
union cvmx_sli_pktx_in_bp
{
uint64_t u64;
struct cvmx_sli_pktx_in_bp_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t wmark : 32; /**< When CNT is greater than this threshold no more
packets will be processed for this ring.
When writing this field of the SLI_PKT#_IN_BP
register, use a 4-byte write so as to not write
any other field of this register. */
uint64_t cnt : 32; /**< ring counter. This field is incremented by one
whenever OCTEON receives, buffers, and creates a
work queue entry for a packet that arrives by the
cooresponding input ring. A write to this field
will be subtracted from the field value.
When writing this field of the SLI_PKT#_IN_BP
register, use a 4-byte write so as to not write
any other field of this register. */
#else
uint64_t cnt : 32;
uint64_t wmark : 32;
#endif
} s;
struct cvmx_sli_pktx_in_bp_s cn63xx;
struct cvmx_sli_pktx_in_bp_s cn63xxp1;
};
typedef union cvmx_sli_pktx_in_bp cvmx_sli_pktx_in_bp_t;
/**
* cvmx_sli_pkt#_instr_baddr
*
* SLI_PKT[0..31]_INSTR_BADDR = SLI Packet ring# Instruction Base Address
*
* Start of Instruction for input packets.
*/
union cvmx_sli_pktx_instr_baddr
{
uint64_t u64;
struct cvmx_sli_pktx_instr_baddr_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t addr : 61; /**< Base address for Instructions. */
uint64_t reserved_0_2 : 3;
#else
uint64_t reserved_0_2 : 3;
uint64_t addr : 61;
#endif
} s;
struct cvmx_sli_pktx_instr_baddr_s cn63xx;
struct cvmx_sli_pktx_instr_baddr_s cn63xxp1;
};
typedef union cvmx_sli_pktx_instr_baddr cvmx_sli_pktx_instr_baddr_t;
/**
* cvmx_sli_pkt#_instr_baoff_dbell
*
* SLI_PKT[0..31]_INSTR_BAOFF_DBELL = SLI Packet ring# Instruction Base Address Offset and Doorbell
*
* The doorbell and base address offset for next read.
*/
union cvmx_sli_pktx_instr_baoff_dbell
{
uint64_t u64;
struct cvmx_sli_pktx_instr_baoff_dbell_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t aoff : 32; /**< The offset from the SLI_PKT[0..31]_INSTR_BADDR
where the next instruction will be read. */
uint64_t dbell : 32; /**< Instruction doorbell count. Writes to this field
will increment the value here. Reads will return
present value. A write of 0xffffffff will set the
DBELL and AOFF fields to '0'. */
#else
uint64_t dbell : 32;
uint64_t aoff : 32;
#endif
} s;
struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx;
struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xxp1;
};
typedef union cvmx_sli_pktx_instr_baoff_dbell cvmx_sli_pktx_instr_baoff_dbell_t;
/**
* cvmx_sli_pkt#_instr_fifo_rsize
*
* SLI_PKT[0..31]_INSTR_FIFO_RSIZE = SLI Packet ring# Instruction FIFO and Ring Size.
*
* Fifo field and ring size for Instructions.
*/
union cvmx_sli_pktx_instr_fifo_rsize
{
uint64_t u64;
struct cvmx_sli_pktx_instr_fifo_rsize_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t max : 9; /**< Max Fifo Size. */
uint64_t rrp : 9; /**< Fifo read pointer. */
uint64_t wrp : 9; /**< Fifo write pointer. */
uint64_t fcnt : 5; /**< Fifo count. */
uint64_t rsize : 32; /**< Instruction ring size. */
#else
uint64_t rsize : 32;
uint64_t fcnt : 5;
uint64_t wrp : 9;
uint64_t rrp : 9;
uint64_t max : 9;
#endif
} s;
struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx;
struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xxp1;
};
typedef union cvmx_sli_pktx_instr_fifo_rsize cvmx_sli_pktx_instr_fifo_rsize_t;
/**
* cvmx_sli_pkt#_instr_header
*
* SLI_PKT[0..31]_INSTR_HEADER = SLI Packet ring# Instruction Header.
*
* VAlues used to build input packet header.
*/
union cvmx_sli_pktx_instr_header
{
uint64_t u64;
struct cvmx_sli_pktx_instr_header_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_44_63 : 20;
uint64_t pbp : 1; /**< Enable Packet-by-packet mode. */
uint64_t reserved_38_42 : 5;
uint64_t rparmode : 2; /**< Parse Mode. Used when packet is raw and PBP==0. */
uint64_t reserved_35_35 : 1;
uint64_t rskp_len : 7; /**< Skip Length. Used when packet is raw and PBP==0. */
uint64_t reserved_26_27 : 2;
uint64_t rnqos : 1; /**< RNQOS. Used when packet is raw and PBP==0. */
uint64_t rngrp : 1; /**< RNGRP. Used when packet is raw and PBP==0. */
uint64_t rntt : 1; /**< RNTT. Used when packet is raw and PBP==0. */
uint64_t rntag : 1; /**< RNTAG. Used when packet is raw and PBP==0. */
uint64_t use_ihdr : 1; /**< When set '1' the instruction header will be sent
as part of the packet data, regardless of the
value of bit [63] of the instruction header.
USE_IHDR must be set whenever PBP is set. */
uint64_t reserved_16_20 : 5;
uint64_t par_mode : 2; /**< Parse Mode. Used when USE_IHDR is set and packet
is not raw and PBP is not set. */
uint64_t reserved_13_13 : 1;
uint64_t skp_len : 7; /**< Skip Length. Used when USE_IHDR is set and packet
is not raw and PBP is not set. */
uint64_t reserved_4_5 : 2;
uint64_t nqos : 1; /**< NQOS. Used when packet is raw and PBP==0. */
uint64_t ngrp : 1; /**< NGRP. Used when packet is raw and PBP==0. */
uint64_t ntt : 1; /**< NTT. Used when packet is raw and PBP==0. */
uint64_t ntag : 1; /**< NTAG. Used when packet is raw and PBP==0. */
#else
uint64_t ntag : 1;
uint64_t ntt : 1;
uint64_t ngrp : 1;
uint64_t nqos : 1;
uint64_t reserved_4_5 : 2;
uint64_t skp_len : 7;
uint64_t reserved_13_13 : 1;
uint64_t par_mode : 2;
uint64_t reserved_16_20 : 5;
uint64_t use_ihdr : 1;
uint64_t rntag : 1;
uint64_t rntt : 1;
uint64_t rngrp : 1;
uint64_t rnqos : 1;
uint64_t reserved_26_27 : 2;
uint64_t rskp_len : 7;
uint64_t reserved_35_35 : 1;
uint64_t rparmode : 2;
uint64_t reserved_38_42 : 5;
uint64_t pbp : 1;
uint64_t reserved_44_63 : 20;
#endif
} s;
struct cvmx_sli_pktx_instr_header_s cn63xx;
struct cvmx_sli_pktx_instr_header_s cn63xxp1;
};
typedef union cvmx_sli_pktx_instr_header cvmx_sli_pktx_instr_header_t;
/**
* cvmx_sli_pkt#_out_size
*
* SLI_PKT[0..31]_OUT_SIZE = SLI Packet Out Size
*
* Contains the BSIZE and ISIZE for output packet ports.
*/
union cvmx_sli_pktx_out_size
{
uint64_t u64;
struct cvmx_sli_pktx_out_size_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_23_63 : 41;
uint64_t isize : 7; /**< INFO BYTES size (bytes) for ring X. Legal sizes
are 0 to 120. Not used in buffer-pointer-only mode. */
uint64_t bsize : 16; /**< BUFFER SIZE (bytes) for ring X. */
#else
uint64_t bsize : 16;
uint64_t isize : 7;
uint64_t reserved_23_63 : 41;
#endif
} s;
struct cvmx_sli_pktx_out_size_s cn63xx;
struct cvmx_sli_pktx_out_size_s cn63xxp1;
};
typedef union cvmx_sli_pktx_out_size cvmx_sli_pktx_out_size_t;
/**
* cvmx_sli_pkt#_slist_baddr
*
* SLI_PKT[0..31]_SLIST_BADDR = SLI Packet ring# Scatter List Base Address
*
* Start of Scatter List for output packet pointers - MUST be 16 byte alligned
*/
union cvmx_sli_pktx_slist_baddr
{
uint64_t u64;
struct cvmx_sli_pktx_slist_baddr_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t addr : 60; /**< Base address for scatter list pointers. */
uint64_t reserved_0_3 : 4;
#else
uint64_t reserved_0_3 : 4;
uint64_t addr : 60;
#endif
} s;
struct cvmx_sli_pktx_slist_baddr_s cn63xx;
struct cvmx_sli_pktx_slist_baddr_s cn63xxp1;
};
typedef union cvmx_sli_pktx_slist_baddr cvmx_sli_pktx_slist_baddr_t;
/**
* cvmx_sli_pkt#_slist_baoff_dbell
*
* SLI_PKT[0..31]_SLIST_BAOFF_DBELL = SLI Packet ring# Scatter List Base Address Offset and Doorbell
*
* The doorbell and base address offset for next read.
*/
union cvmx_sli_pktx_slist_baoff_dbell
{
uint64_t u64;
struct cvmx_sli_pktx_slist_baoff_dbell_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t aoff : 32; /**< The offset from the SLI_PKT[0..31]_SLIST_BADDR
where the next SList pointer will be read.
A write of 0xFFFFFFFF to the DBELL field will
clear DBELL and AOFF */
uint64_t dbell : 32; /**< Scatter list doorbell count. Writes to this field
will increment the value here. Reads will return
present value. The value of this field is
decremented as read operations are ISSUED for
scatter pointers.
A write of 0xFFFFFFFF will clear DBELL and AOFF */
#else
uint64_t dbell : 32;
uint64_t aoff : 32;
#endif
} s;
struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx;
struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xxp1;
};
typedef union cvmx_sli_pktx_slist_baoff_dbell cvmx_sli_pktx_slist_baoff_dbell_t;
/**
* cvmx_sli_pkt#_slist_fifo_rsize
*
* SLI_PKT[0..31]_SLIST_FIFO_RSIZE = SLI Packet ring# Scatter List FIFO and Ring Size.
*
* The number of scatter pointer pairs in the scatter list.
*/
union cvmx_sli_pktx_slist_fifo_rsize
{
uint64_t u64;
struct cvmx_sli_pktx_slist_fifo_rsize_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_32_63 : 32;
uint64_t rsize : 32; /**< The number of scatter pointer pairs contained in
the scatter list ring. */
#else
uint64_t rsize : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx;
struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xxp1;
};
typedef union cvmx_sli_pktx_slist_fifo_rsize cvmx_sli_pktx_slist_fifo_rsize_t;
/**
* cvmx_sli_pkt_cnt_int
*
* SLI_PKT_CNT_INT = SLI Packet Counter Interrupt
*
* The packets rings that are interrupting because of Packet Counters.
*/
union cvmx_sli_pkt_cnt_int
{
uint64_t u64;
struct cvmx_sli_pkt_cnt_int_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_32_63 : 32;
uint64_t port : 32; /**< Output ring packet counter interrupt bits
SLI sets PORT<i> whenever
SLI_PKTi_CNTS[CNT] > SLI_PKT_INT_LEVELS[CNT].
SLI_PKT_CNT_INT_ENB[PORT<i>] is the corresponding
enable. */
#else
uint64_t port : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_sli_pkt_cnt_int_s cn63xx;
struct cvmx_sli_pkt_cnt_int_s cn63xxp1;
};
typedef union cvmx_sli_pkt_cnt_int cvmx_sli_pkt_cnt_int_t;
/**
* cvmx_sli_pkt_cnt_int_enb
*
* SLI_PKT_CNT_INT_ENB = SLI Packet Counter Interrupt Enable
*
* Enable for the packets rings that are interrupting because of Packet Counters.
*/
union cvmx_sli_pkt_cnt_int_enb
{
uint64_t u64;
struct cvmx_sli_pkt_cnt_int_enb_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_32_63 : 32;
uint64_t port : 32; /**< Output ring packet counter interrupt enables
When both PORT<i> and corresponding
SLI_PKT_CNT_INT[PORT<i>] are set, for any i,
then SLI_INT_SUM[PCNT] is set, which can cause
an interrupt. */
#else
uint64_t port : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_sli_pkt_cnt_int_enb_s cn63xx;
struct cvmx_sli_pkt_cnt_int_enb_s cn63xxp1;
};
typedef union cvmx_sli_pkt_cnt_int_enb cvmx_sli_pkt_cnt_int_enb_t;
/**
* cvmx_sli_pkt_ctl
*
* SLI_PKT_CTL = SLI Packet Control
*
* Control for packets.
*/
union cvmx_sli_pkt_ctl
{
uint64_t u64;
struct cvmx_sli_pkt_ctl_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_5_63 : 59;
uint64_t ring_en : 1; /**< When '0' forces "relative Q position" received
from PKO to be zero, and replicates the back-
pressure indication for the first ring attached
to a PKO port across all the rings attached to a
PKO port. When '1' backpressure is on a per
port/ring. */
uint64_t pkt_bp : 4; /**< When set '1' enable the port level backpressure for
PKO ports associated with the bit. */
#else
uint64_t pkt_bp : 4;
uint64_t ring_en : 1;
uint64_t reserved_5_63 : 59;
#endif
} s;
struct cvmx_sli_pkt_ctl_s cn63xx;
struct cvmx_sli_pkt_ctl_s cn63xxp1;
};
typedef union cvmx_sli_pkt_ctl cvmx_sli_pkt_ctl_t;
/**
* cvmx_sli_pkt_data_out_es
*
* SLI_PKT_DATA_OUT_ES = SLI's Packet Data Out Endian Swap
*
* The Endian Swap for writing Data Out.
*/
union cvmx_sli_pkt_data_out_es
{
uint64_t u64;
struct cvmx_sli_pkt_data_out_es_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t es : 64; /**< ES<1:0> or MACADD<63:62> for buffer/info writes.
ES<2i+1:2i> becomes either ES<1:0> or
MACADD<63:62> for writes to buffer/info pair
MAC memory space addresses fetched from packet
output ring i. ES<1:0> if SLI_PKT_DPADDR[DPTR<i>]=1
, else MACADD<63:62>.
In the latter case, ES<1:0> comes from DPTR<63:62>.
ES<1:0> is the endian-swap attribute for these MAC
memory space writes. */
#else
uint64_t es : 64;
#endif
} s;
struct cvmx_sli_pkt_data_out_es_s cn63xx;
struct cvmx_sli_pkt_data_out_es_s cn63xxp1;
};
typedef union cvmx_sli_pkt_data_out_es cvmx_sli_pkt_data_out_es_t;
/**
* cvmx_sli_pkt_data_out_ns
*
* SLI_PKT_DATA_OUT_NS = SLI's Packet Data Out No Snoop
*
* The NS field for the TLP when writing packet data.
*/
union cvmx_sli_pkt_data_out_ns
{
uint64_t u64;
struct cvmx_sli_pkt_data_out_ns_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_32_63 : 32;
uint64_t nsr : 32; /**< ADDRTYPE<1> or MACADD<61> for buffer/info writes.
NSR<i> becomes either ADDRTYPE<1> or MACADD<61>
for writes to buffer/info pair MAC memory space
addresses fetched from packet output ring i.
ADDRTYPE<1> if SLI_PKT_DPADDR[DPTR<i>]=1, else
MACADD<61>.
In the latter case,ADDRTYPE<1> comes from DPTR<61>.
ADDRTYPE<1> is the no-snoop attribute for PCIe
, helps select an SRIO*_S2M_TYPE* entry with sRIO. */
#else
uint64_t nsr : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_sli_pkt_data_out_ns_s cn63xx;
struct cvmx_sli_pkt_data_out_ns_s cn63xxp1;
};
typedef union cvmx_sli_pkt_data_out_ns cvmx_sli_pkt_data_out_ns_t;
/**
* cvmx_sli_pkt_data_out_ror
*
* SLI_PKT_DATA_OUT_ROR = SLI's Packet Data Out Relaxed Ordering
*
* The ROR field for the TLP when writing Packet Data.
*/
union cvmx_sli_pkt_data_out_ror
{
uint64_t u64;
struct cvmx_sli_pkt_data_out_ror_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_32_63 : 32;
uint64_t ror : 32; /**< ADDRTYPE<0> or MACADD<60> for buffer/info writes.
ROR<i> becomes either ADDRTYPE<0> or MACADD<60>
for writes to buffer/info pair MAC memory space
addresses fetched from packet output ring i.
ADDRTYPE<0> if SLI_PKT_DPADDR[DPTR<i>]=1, else
MACADD<60>.
In the latter case,ADDRTYPE<0> comes from DPTR<60>.
ADDRTYPE<0> is the relaxed-order attribute for PCIe
, helps select an SRIO*_S2M_TYPE* entry with sRIO. */
#else
uint64_t ror : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_sli_pkt_data_out_ror_s cn63xx;
struct cvmx_sli_pkt_data_out_ror_s cn63xxp1;
};
typedef union cvmx_sli_pkt_data_out_ror cvmx_sli_pkt_data_out_ror_t;
/**
* cvmx_sli_pkt_dpaddr
*
* SLI_PKT_DPADDR = SLI's Packet Data Pointer Addr
*
* Used to detemine address and attributes for packet data writes.
*/
union cvmx_sli_pkt_dpaddr
{
uint64_t u64;
struct cvmx_sli_pkt_dpaddr_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_32_63 : 32;
uint64_t dptr : 32; /**< Determines whether buffer/info pointers are
DPTR format 0 or DPTR format 1.
When DPTR<i>=1, the buffer/info pointers fetched
from packet output ring i are DPTR format 0.
When DPTR<i>=0, the buffer/info pointers fetched
from packet output ring i are DPTR format 1.
(Replace SLI_PKT_INPUT_CONTROL[D_ESR,D_NSR,D_ROR]
in the HRM descriptions of DPTR format 0/1 with
SLI_PKT_DATA_OUT_ES[ES<2i+1:2i>],
SLI_PKT_DATA_OUT_NS[NSR<i>], and
SLI_PKT_DATA_OUT_ROR[ROR<i>], respectively,
though.) */
#else
uint64_t dptr : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_sli_pkt_dpaddr_s cn63xx;
struct cvmx_sli_pkt_dpaddr_s cn63xxp1;
};
typedef union cvmx_sli_pkt_dpaddr cvmx_sli_pkt_dpaddr_t;
/**
* cvmx_sli_pkt_in_bp
*
* SLI_PKT_IN_BP = SLI Packet Input Backpressure
*
* Which input rings have backpressure applied.
*/
union cvmx_sli_pkt_in_bp
{
uint64_t u64;
struct cvmx_sli_pkt_in_bp_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_32_63 : 32;
uint64_t bp : 32; /**< A packet input ring that has its count greater
than its WMARK will have backpressure applied.
Each of the 32 bits coorespond to an input ring.
When '1' that ring has backpressure applied an
will fetch no more instructions, but will process
any previously fetched instructions. */
#else
uint64_t bp : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_sli_pkt_in_bp_s cn63xx;
struct cvmx_sli_pkt_in_bp_s cn63xxp1;
};
typedef union cvmx_sli_pkt_in_bp cvmx_sli_pkt_in_bp_t;
/**
* cvmx_sli_pkt_in_done#_cnts
*
* SLI_PKT_IN_DONE[0..31]_CNTS = SLI Instruction Done ring# Counts
*
* Counters for instructions completed on Input rings.
*/
union cvmx_sli_pkt_in_donex_cnts
{
uint64_t u64;
struct cvmx_sli_pkt_in_donex_cnts_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_32_63 : 32;
uint64_t cnt : 32; /**< This field is incrmented by '1' when an instruction
is completed. This field is incremented as the
last of the data is read from the MAC. */
#else
uint64_t cnt : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_sli_pkt_in_donex_cnts_s cn63xx;
struct cvmx_sli_pkt_in_donex_cnts_s cn63xxp1;
};
typedef union cvmx_sli_pkt_in_donex_cnts cvmx_sli_pkt_in_donex_cnts_t;
/**
* cvmx_sli_pkt_in_instr_counts
*
* SLI_PKT_IN_INSTR_COUNTS = SLI Packet Input Instrutction Counts
*
* Keeps track of the number of instructions read into the FIFO and Packets sent to IPD.
*/
union cvmx_sli_pkt_in_instr_counts
{
uint64_t u64;
struct cvmx_sli_pkt_in_instr_counts_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t wr_cnt : 32; /**< Shows the number of packets sent to the IPD. */
uint64_t rd_cnt : 32; /**< Shows the value of instructions that have had reads
issued for them.
to the Packet-ring is in reset. */
#else
uint64_t rd_cnt : 32;
uint64_t wr_cnt : 32;
#endif
} s;
struct cvmx_sli_pkt_in_instr_counts_s cn63xx;
struct cvmx_sli_pkt_in_instr_counts_s cn63xxp1;
};
typedef union cvmx_sli_pkt_in_instr_counts cvmx_sli_pkt_in_instr_counts_t;
/**
* cvmx_sli_pkt_in_pcie_port
*
* SLI_PKT_IN_PCIE_PORT = SLI's Packet In To MAC Port Assignment
*
* Assigns Packet Input rings to MAC ports.
*/
union cvmx_sli_pkt_in_pcie_port
{
uint64_t u64;
struct cvmx_sli_pkt_in_pcie_port_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t pp : 64; /**< The MAC port that the Packet ring number is
assigned. Two bits are used per ring (i.e. ring 0
[1:0], ring 1 [3:2], ....). A value of '0 means
that the Packetring is assign to MAC Port 0, a '1'
MAC Port 1, '2' and '3' are reserved. */
#else
uint64_t pp : 64;
#endif
} s;
struct cvmx_sli_pkt_in_pcie_port_s cn63xx;
struct cvmx_sli_pkt_in_pcie_port_s cn63xxp1;
};
typedef union cvmx_sli_pkt_in_pcie_port cvmx_sli_pkt_in_pcie_port_t;
/**
* cvmx_sli_pkt_input_control
*
* SLI_PKT_INPUT_CONTROL = SLI's Packet Input Control
*
* Control for reads for gather list and instructions.
*/
union cvmx_sli_pkt_input_control
{
uint64_t u64;
struct cvmx_sli_pkt_input_control_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_23_63 : 41;
uint64_t pkt_rr : 1; /**< When set '1' the input packet selection will be
made with a Round Robin arbitration. When '0'
the input packet ring is fixed in priority,
where the lower ring number has higher priority. */
uint64_t pbp_dhi : 13; /**< PBP_DHI replaces address bits that are used
for parse mode and skip-length when
SLI_PKTi_INSTR_HEADER[PBP]=1.
PBP_DHI becomes either MACADD<63:55> or MACADD<59:51>
for the instruction DPTR reads in this case.
The instruction DPTR reads are called
"First Direct" or "First Indirect" in the HRM.
When PBP=1, if "First Direct" and USE_CSR=0, PBP_DHI
becomes MACADD<59:51>, else MACADD<63:55>. */
uint64_t d_nsr : 1; /**< ADDRTYPE<1> or MACADD<61> for packet input data
reads.
D_NSR becomes either ADDRTYPE<1> or MACADD<61>
for MAC memory space reads of packet input data
fetched for any packet input ring.
ADDRTYPE<1> if USE_CSR=1, else MACADD<61>.
In the latter case, ADDRTYPE<1> comes from DPTR<61>.
ADDRTYPE<1> is the no-snoop attribute for PCIe
, helps select an SRIO*_S2M_TYPE* entry with sRIO. */
uint64_t d_esr : 2; /**< ES<1:0> or MACADD<63:62> for packet input data
reads.
D_ESR becomes either ES<1:0> or MACADD<63:62>
for MAC memory space reads of packet input data
fetched for any packet input ring.
ES<1:0> if USE_CSR=1, else MACADD<63:62>.
In the latter case, ES<1:0> comes from DPTR<63:62>.
ES<1:0> is the endian-swap attribute for these MAC
memory space reads. */
uint64_t d_ror : 1; /**< ADDRTYPE<0> or MACADD<60> for packet input data
reads.
D_ROR becomes either ADDRTYPE<0> or MACADD<60>
for MAC memory space reads of packet input data
fetched for any packet input ring.
ADDRTYPE<0> if USE_CSR=1, else MACADD<60>.
In the latter case, ADDRTYPE<0> comes from DPTR<60>.
ADDRTYPE<0> is the relaxed-order attribute for PCIe
, helps select an SRIO*_S2M_TYPE* entry with sRIO. */
uint64_t use_csr : 1; /**< When set '1' the csr value will be used for
ROR, ESR, and NSR. When clear '0' the value in
DPTR will be used. In turn the bits not used for
ROR, ESR, and NSR, will be used for bits [63:60]
of the address used to fetch packet data. */
uint64_t nsr : 1; /**< ADDRTYPE<1> for packet input instruction reads and
gather list (i.e. DPI component) reads from MAC
memory space.
ADDRTYPE<1> is the no-snoop attribute for PCIe
, helps select an SRIO*_S2M_TYPE* entry with sRIO. */
uint64_t esr : 2; /**< ES<1:0> for packet input instruction reads and
gather list (i.e. DPI component) reads from MAC
memory space.
ES<1:0> is the endian-swap attribute for these MAC
memory space reads. */
uint64_t ror : 1; /**< ADDRTYPE<0> for packet input instruction reads and
gather list (i.e. DPI component) reads from MAC
memory space.
ADDRTYPE<0> is the relaxed-order attribute for PCIe
, helps select an SRIO*_S2M_TYPE* entry with sRIO. */
#else
uint64_t ror : 1;
uint64_t esr : 2;
uint64_t nsr : 1;
uint64_t use_csr : 1;
uint64_t d_ror : 1;
uint64_t d_esr : 2;
uint64_t d_nsr : 1;
uint64_t pbp_dhi : 13;
uint64_t pkt_rr : 1;
uint64_t reserved_23_63 : 41;
#endif
} s;
struct cvmx_sli_pkt_input_control_s cn63xx;
struct cvmx_sli_pkt_input_control_s cn63xxp1;
};
typedef union cvmx_sli_pkt_input_control cvmx_sli_pkt_input_control_t;
/**
* cvmx_sli_pkt_instr_enb
*
* SLI_PKT_INSTR_ENB = SLI's Packet Instruction Enable
*
* Enables the instruction fetch for a Packet-ring.
*/
union cvmx_sli_pkt_instr_enb
{
uint64_t u64;
struct cvmx_sli_pkt_instr_enb_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_32_63 : 32;
uint64_t enb : 32; /**< When ENB<i>=1, instruction input ring i is enabled. */
#else
uint64_t enb : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_sli_pkt_instr_enb_s cn63xx;
struct cvmx_sli_pkt_instr_enb_s cn63xxp1;
};
typedef union cvmx_sli_pkt_instr_enb cvmx_sli_pkt_instr_enb_t;
/**
* cvmx_sli_pkt_instr_rd_size
*
* SLI_PKT_INSTR_RD_SIZE = SLI Instruction Read Size
*
* The number of instruction allowed to be read at one time.
*/
union cvmx_sli_pkt_instr_rd_size
{
uint64_t u64;
struct cvmx_sli_pkt_instr_rd_size_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t rdsize : 64; /**< Number of instructions to be read in one MAC read
request for the 4 ports - 8 rings. Every two bits
(i.e. 1:0, 3:2, 5:4..) are assign to the port/ring
combinations.
- 15:0 PKIPort0,Ring 7..0 31:16 PKIPort1,Ring 7..0
- 47:32 PKIPort2,Ring 7..0 63:48 PKIPort3,Ring 7..0
Two bit value are:
0 - 1 Instruction
1 - 2 Instructions
2 - 3 Instructions
3 - 4 Instructions */
#else
uint64_t rdsize : 64;
#endif
} s;
struct cvmx_sli_pkt_instr_rd_size_s cn63xx;
struct cvmx_sli_pkt_instr_rd_size_s cn63xxp1;
};
typedef union cvmx_sli_pkt_instr_rd_size cvmx_sli_pkt_instr_rd_size_t;
/**
* cvmx_sli_pkt_instr_size
*
* SLI_PKT_INSTR_SIZE = SLI's Packet Instruction Size
*
* Determines if instructions are 64 or 32 byte in size for a Packet-ring.
*/
union cvmx_sli_pkt_instr_size
{
uint64_t u64;
struct cvmx_sli_pkt_instr_size_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_32_63 : 32;
uint64_t is_64b : 32; /**< When IS_64B<i>=1, instruction input ring i uses 64B
instructions, else 32B instructions. */
#else
uint64_t is_64b : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_sli_pkt_instr_size_s cn63xx;
struct cvmx_sli_pkt_instr_size_s cn63xxp1;
};
typedef union cvmx_sli_pkt_instr_size cvmx_sli_pkt_instr_size_t;
/**
* cvmx_sli_pkt_int_levels
*
* 0x90F0 reserved SLI_PKT_PCIE_PORT2
*
*
* SLI_PKT_INT_LEVELS = SLI's Packet Interrupt Levels
*
* Output packet interrupt levels.
*/
union cvmx_sli_pkt_int_levels
{
uint64_t u64;
struct cvmx_sli_pkt_int_levels_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_54_63 : 10;
uint64_t time : 22; /**< Output ring counter time interrupt threshold
SLI sets SLI_PKT_TIME_INT[PORT<i>] whenever
SLI_PKTi_CNTS[TIMER] > TIME */
uint64_t cnt : 32; /**< Output ring counter interrupt threshold
SLI sets SLI_PKT_CNT_INT[PORT<i>] whenever
SLI_PKTi_CNTS[CNT] > CNT */
#else
uint64_t cnt : 32;
uint64_t time : 22;
uint64_t reserved_54_63 : 10;
#endif
} s;
struct cvmx_sli_pkt_int_levels_s cn63xx;
struct cvmx_sli_pkt_int_levels_s cn63xxp1;
};
typedef union cvmx_sli_pkt_int_levels cvmx_sli_pkt_int_levels_t;
/**
* cvmx_sli_pkt_iptr
*
* SLI_PKT_IPTR = SLI's Packet Info Poitner
*
* Controls using the Info-Pointer to store length and data.
*/
union cvmx_sli_pkt_iptr
{
uint64_t u64;
struct cvmx_sli_pkt_iptr_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_32_63 : 32;
uint64_t iptr : 32; /**< When IPTR<i>=1, packet output ring i is in info-
pointer mode, else buffer-pointer-only mode. */
#else
uint64_t iptr : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_sli_pkt_iptr_s cn63xx;
struct cvmx_sli_pkt_iptr_s cn63xxp1;
};
typedef union cvmx_sli_pkt_iptr cvmx_sli_pkt_iptr_t;
/**
* cvmx_sli_pkt_out_bmode
*
* SLI_PKT_OUT_BMODE = SLI's Packet Out Byte Mode
*
* Control the updating of the SLI_PKT#_CNT register.
*/
union cvmx_sli_pkt_out_bmode
{
uint64_t u64;
struct cvmx_sli_pkt_out_bmode_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_32_63 : 32;
uint64_t bmode : 32; /**< Determines whether SLI_PKTi_CNTS[CNT] is a byte or
packet counter.
When BMODE<i>=1, SLI_PKTi_CNTS[CNT] is a byte
counter, else SLI_PKTi_CNTS[CNT] is a packet
counter. */
#else
uint64_t bmode : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_sli_pkt_out_bmode_s cn63xx;
struct cvmx_sli_pkt_out_bmode_s cn63xxp1;
};
typedef union cvmx_sli_pkt_out_bmode cvmx_sli_pkt_out_bmode_t;
/**
* cvmx_sli_pkt_out_enb
*
* SLI_PKT_OUT_ENB = SLI's Packet Output Enable
*
* Enables the output packet engines.
*/
union cvmx_sli_pkt_out_enb
{
uint64_t u64;
struct cvmx_sli_pkt_out_enb_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_32_63 : 32;
uint64_t enb : 32; /**< When ENB<i>=1, packet output ring i is enabled.
If an error occurs on reading pointers for an
output ring, the ring will be disabled by clearing
the bit associated with the ring to '0'. */
#else
uint64_t enb : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_sli_pkt_out_enb_s cn63xx;
struct cvmx_sli_pkt_out_enb_s cn63xxp1;
};
typedef union cvmx_sli_pkt_out_enb cvmx_sli_pkt_out_enb_t;
/**
* cvmx_sli_pkt_output_wmark
*
* SLI_PKT_OUTPUT_WMARK = SLI's Packet Output Water Mark
*
* Value that when the SLI_PKT#_SLIST_BAOFF_DBELL[DBELL] value is less then that backpressure for the rings will be applied.
*/
union cvmx_sli_pkt_output_wmark
{
uint64_t u64;
struct cvmx_sli_pkt_output_wmark_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_32_63 : 32;
uint64_t wmark : 32; /**< Value when DBELL count drops below backpressure
for the ring will be applied to the PKO. */
#else
uint64_t wmark : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_sli_pkt_output_wmark_s cn63xx;
struct cvmx_sli_pkt_output_wmark_s cn63xxp1;
};
typedef union cvmx_sli_pkt_output_wmark cvmx_sli_pkt_output_wmark_t;
/**
* cvmx_sli_pkt_pcie_port
*
* SLI_PKT_PCIE_PORT = SLI's Packet To MAC Port Assignment
*
* Assigns Packet Ports to MAC ports.
*/
union cvmx_sli_pkt_pcie_port
{
uint64_t u64;
struct cvmx_sli_pkt_pcie_port_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t pp : 64; /**< The physical MAC port that the output ring uses.
Two bits are used per ring (i.e. ring 0 [1:0],
ring 1 [3:2], ....). A value of '0 means
that the Packetring is assign to MAC Port 0, a '1'
MAC Port 1, '2' and '3' are reserved. */
#else
uint64_t pp : 64;
#endif
} s;
struct cvmx_sli_pkt_pcie_port_s cn63xx;
struct cvmx_sli_pkt_pcie_port_s cn63xxp1;
};
typedef union cvmx_sli_pkt_pcie_port cvmx_sli_pkt_pcie_port_t;
/**
* cvmx_sli_pkt_port_in_rst
*
* 91c0 reserved
* 91d0 reserved
* 91e0 reserved
*
*
* SLI_PKT_PORT_IN_RST = SLI Packet Port In Reset
*
* Vector bits related to ring-port for ones that are reset.
*/
union cvmx_sli_pkt_port_in_rst
{
uint64_t u64;
struct cvmx_sli_pkt_port_in_rst_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t in_rst : 32; /**< When asserted '1' the vector bit cooresponding
to the inbound Packet-ring is in reset. */
uint64_t out_rst : 32; /**< When asserted '1' the vector bit cooresponding
to the outbound Packet-ring is in reset. */
#else
uint64_t out_rst : 32;
uint64_t in_rst : 32;
#endif
} s;
struct cvmx_sli_pkt_port_in_rst_s cn63xx;
struct cvmx_sli_pkt_port_in_rst_s cn63xxp1;
};
typedef union cvmx_sli_pkt_port_in_rst cvmx_sli_pkt_port_in_rst_t;
/**
* cvmx_sli_pkt_slist_es
*
* SLI_PKT_SLIST_ES = SLI's Packet Scatter List Endian Swap
*
* The Endian Swap for Scatter List Read.
*/
union cvmx_sli_pkt_slist_es
{
uint64_t u64;
struct cvmx_sli_pkt_slist_es_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t es : 64; /**< ES<1:0> for the packet output ring reads that
fetch buffer/info pointer pairs.
ES<2i+1:2i> becomes ES<1:0> in DPI/SLI reads that
fetch buffer/info pairs from packet output ring i
(from address SLI_PKTi_SLIST_BADDR+ in MAC memory
space.)
ES<1:0> is the endian-swap attribute for these MAC
memory space reads. */
#else
uint64_t es : 64;
#endif
} s;
struct cvmx_sli_pkt_slist_es_s cn63xx;
struct cvmx_sli_pkt_slist_es_s cn63xxp1;
};
typedef union cvmx_sli_pkt_slist_es cvmx_sli_pkt_slist_es_t;
/**
* cvmx_sli_pkt_slist_ns
*
* SLI_PKT_SLIST_NS = SLI's Packet Scatter List No Snoop
*
* The NS field for the TLP when fetching Scatter List.
*/
union cvmx_sli_pkt_slist_ns
{
uint64_t u64;
struct cvmx_sli_pkt_slist_ns_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_32_63 : 32;
uint64_t nsr : 32; /**< ADDRTYPE<1> for the packet output ring reads that
fetch buffer/info pointer pairs.
NSR<i> becomes ADDRTYPE<1> in DPI/SLI reads that
fetch buffer/info pairs from packet output ring i
(from address SLI_PKTi_SLIST_BADDR+ in MAC memory
space.)
ADDRTYPE<1> is the relaxed-order attribute for PCIe
, helps select an SRIO*_S2M_TYPE* entry with sRIO. */
#else
uint64_t nsr : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_sli_pkt_slist_ns_s cn63xx;
struct cvmx_sli_pkt_slist_ns_s cn63xxp1;
};
typedef union cvmx_sli_pkt_slist_ns cvmx_sli_pkt_slist_ns_t;
/**
* cvmx_sli_pkt_slist_ror
*
* SLI_PKT_SLIST_ROR = SLI's Packet Scatter List Relaxed Ordering
*
* The ROR field for the TLP when fetching Scatter List.
*/
union cvmx_sli_pkt_slist_ror
{
uint64_t u64;
struct cvmx_sli_pkt_slist_ror_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_32_63 : 32;
uint64_t ror : 32; /**< ADDRTYPE<0> for the packet output ring reads that
fetch buffer/info pointer pairs.
ROR<i> becomes ADDRTYPE<0> in DPI/SLI reads that
fetch buffer/info pairs from packet output ring i
(from address SLI_PKTi_SLIST_BADDR+ in MAC memory
space.)
ADDRTYPE<0> is the relaxed-order attribute for PCIe
, helps select an SRIO*_S2M_TYPE* entry with sRIO. */
#else
uint64_t ror : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_sli_pkt_slist_ror_s cn63xx;
struct cvmx_sli_pkt_slist_ror_s cn63xxp1;
};
typedef union cvmx_sli_pkt_slist_ror cvmx_sli_pkt_slist_ror_t;
/**
* cvmx_sli_pkt_time_int
*
* SLI_PKT_TIME_INT = SLI Packet Timer Interrupt
*
* The packets rings that are interrupting because of Packet Timers.
*/
union cvmx_sli_pkt_time_int
{
uint64_t u64;
struct cvmx_sli_pkt_time_int_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_32_63 : 32;
uint64_t port : 32; /**< Output ring packet timer interrupt bits
SLI sets PORT<i> whenever
SLI_PKTi_CNTS[TIMER] > SLI_PKT_INT_LEVELS[TIME].
SLI_PKT_TIME_INT_ENB[PORT<i>] is the corresponding
enable. */
#else
uint64_t port : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_sli_pkt_time_int_s cn63xx;
struct cvmx_sli_pkt_time_int_s cn63xxp1;
};
typedef union cvmx_sli_pkt_time_int cvmx_sli_pkt_time_int_t;
/**
* cvmx_sli_pkt_time_int_enb
*
* SLI_PKT_TIME_INT_ENB = SLI Packet Timer Interrupt Enable
*
* The packets rings that are interrupting because of Packet Timers.
*/
union cvmx_sli_pkt_time_int_enb
{
uint64_t u64;
struct cvmx_sli_pkt_time_int_enb_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_32_63 : 32;
uint64_t port : 32; /**< Output ring packet timer interrupt enables
When both PORT<i> and corresponding
SLI_PKT_TIME_INT[PORT<i>] are set, for any i,
then SLI_INT_SUM[PTIME] is set, which can cause
an interrupt. */
#else
uint64_t port : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_sli_pkt_time_int_enb_s cn63xx;
struct cvmx_sli_pkt_time_int_enb_s cn63xxp1;
};
typedef union cvmx_sli_pkt_time_int_enb cvmx_sli_pkt_time_int_enb_t;
/**
* cvmx_sli_s2m_port#_ctl
*
* SLI_S2M_PORTX_CTL = SLI's S2M Port 0 Control
*
* Contains control for access from SLI to a MAC port.
* Writes to this register are not ordered with writes/reads to the MAC Memory space.
* To ensure that a write has completed the user must read the register before
* making an access(i.e. MAC memory space) that requires the value of this register to be updated.
*/
union cvmx_sli_s2m_portx_ctl
{
uint64_t u64;
struct cvmx_sli_s2m_portx_ctl_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_5_63 : 59;
uint64_t wind_d : 1; /**< When set '1' disables access to the Window
Registers from the MAC-Port. */
uint64_t bar0_d : 1; /**< When set '1' disables access from MAC to
BAR-0 address offsets: Less Than 0x330,
0x3CD0, and greater than 0x3D70. */
uint64_t mrrs : 3; /**< Max Read Request Size
0 = 128B
1 = 256B
2 = 512B
3 = 1024B
4 = 2048B
5-7 = Reserved
This field should not exceed the desired
max read request size. This field is used to
determine if an IOBDMA is too large.
For a PCIe MAC, this field should not exceed
PCIE*_CFG030[MRRS].
For a sRIO MAC, this field should indicate a size
of 256B or smaller. */
#else
uint64_t mrrs : 3;
uint64_t bar0_d : 1;
uint64_t wind_d : 1;
uint64_t reserved_5_63 : 59;
#endif
} s;
struct cvmx_sli_s2m_portx_ctl_s cn63xx;
struct cvmx_sli_s2m_portx_ctl_s cn63xxp1;
};
typedef union cvmx_sli_s2m_portx_ctl cvmx_sli_s2m_portx_ctl_t;
/**
* cvmx_sli_scratch_1
*
* SLI_SCRATCH_1 = SLI's Scratch 1
*
* A general purpose 64 bit register for SW use.
*/
union cvmx_sli_scratch_1
{
uint64_t u64;
struct cvmx_sli_scratch_1_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t data : 64; /**< The value in this register is totaly SW dependent. */
#else
uint64_t data : 64;
#endif
} s;
struct cvmx_sli_scratch_1_s cn63xx;
struct cvmx_sli_scratch_1_s cn63xxp1;
};
typedef union cvmx_sli_scratch_1 cvmx_sli_scratch_1_t;
/**
* cvmx_sli_scratch_2
*
* SLI_SCRATCH_2 = SLI's Scratch 2
*
* A general purpose 64 bit register for SW use.
*/
union cvmx_sli_scratch_2
{
uint64_t u64;
struct cvmx_sli_scratch_2_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t data : 64; /**< The value in this register is totaly SW dependent. */
#else
uint64_t data : 64;
#endif
} s;
struct cvmx_sli_scratch_2_s cn63xx;
struct cvmx_sli_scratch_2_s cn63xxp1;
};
typedef union cvmx_sli_scratch_2 cvmx_sli_scratch_2_t;
/**
* cvmx_sli_state1
*
* SLI_STATE1 = SLI State 1
*
* State machines in SLI. For debug.
*/
union cvmx_sli_state1
{
uint64_t u64;
struct cvmx_sli_state1_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t cpl1 : 12; /**< CPL1 State */
uint64_t cpl0 : 12; /**< CPL0 State */
uint64_t arb : 1; /**< ARB State */
uint64_t csr : 39; /**< CSR State */
#else
uint64_t csr : 39;
uint64_t arb : 1;
uint64_t cpl0 : 12;
uint64_t cpl1 : 12;
#endif
} s;
struct cvmx_sli_state1_s cn63xx;
struct cvmx_sli_state1_s cn63xxp1;
};
typedef union cvmx_sli_state1 cvmx_sli_state1_t;
/**
* cvmx_sli_state2
*
* SLI_STATE2 = SLI State 2
*
* State machines in SLI. For debug.
*/
union cvmx_sli_state2
{
uint64_t u64;
struct cvmx_sli_state2_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_56_63 : 8;
uint64_t nnp1 : 8; /**< NNP1 State */
uint64_t reserved_47_47 : 1;
uint64_t rac : 1; /**< RAC State */
uint64_t csm1 : 15; /**< CSM1 State */
uint64_t csm0 : 15; /**< CSM0 State */
uint64_t nnp0 : 8; /**< NNP0 State */
uint64_t nnd : 8; /**< NND State */
#else
uint64_t nnd : 8;
uint64_t nnp0 : 8;
uint64_t csm0 : 15;
uint64_t csm1 : 15;
uint64_t rac : 1;
uint64_t reserved_47_47 : 1;
uint64_t nnp1 : 8;
uint64_t reserved_56_63 : 8;
#endif
} s;
struct cvmx_sli_state2_s cn63xx;
struct cvmx_sli_state2_s cn63xxp1;
};
typedef union cvmx_sli_state2 cvmx_sli_state2_t;
/**
* cvmx_sli_state3
*
* SLI_STATE3 = SLI State 3
*
* State machines in SLI. For debug.
*/
union cvmx_sli_state3
{
uint64_t u64;
struct cvmx_sli_state3_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_56_63 : 8;
uint64_t psm1 : 15; /**< PSM1 State */
uint64_t psm0 : 15; /**< PSM0 State */
uint64_t nsm1 : 13; /**< NSM1 State */
uint64_t nsm0 : 13; /**< NSM0 State */
#else
uint64_t nsm0 : 13;
uint64_t nsm1 : 13;
uint64_t psm0 : 15;
uint64_t psm1 : 15;
uint64_t reserved_56_63 : 8;
#endif
} s;
struct cvmx_sli_state3_s cn63xx;
struct cvmx_sli_state3_s cn63xxp1;
};
typedef union cvmx_sli_state3 cvmx_sli_state3_t;
/**
* cvmx_sli_win_rd_addr
*
* SLI_WIN_RD_ADDR = SLI Window Read Address Register
*
* The address to be read when the SLI_WIN_RD_DATA register is read.
* This register should NOT be used to read SLI_* registers.
*/
union cvmx_sli_win_rd_addr
{
uint64_t u64;
struct cvmx_sli_win_rd_addr_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_51_63 : 13;
uint64_t ld_cmd : 2; /**< The load command sent wit hthe read.
0x3 == Load 8-bytes, 0x2 == Load 4-bytes,
0x1 == Load 2-bytes, 0x0 == Load 1-bytes, */
uint64_t iobit : 1; /**< A 1 or 0 can be written here but will not be used
in address generation. */
uint64_t rd_addr : 48; /**< The address to be read from.
[47:40] = NCB_ID
[39:0] = Address
When [47:43] == SLI & [42:40] == 0 bits [39:0] are:
[39:32] == x, Not Used
[31:24] == RSL_ID
[23:0] == RSL Register Offset */
#else
uint64_t rd_addr : 48;
uint64_t iobit : 1;
uint64_t ld_cmd : 2;
uint64_t reserved_51_63 : 13;
#endif
} s;
struct cvmx_sli_win_rd_addr_s cn63xx;
struct cvmx_sli_win_rd_addr_s cn63xxp1;
};
typedef union cvmx_sli_win_rd_addr cvmx_sli_win_rd_addr_t;
/**
* cvmx_sli_win_rd_data
*
* SLI_WIN_RD_DATA = SLI Window Read Data Register
*
* Reading this register causes a window read operation to take place. Address read is that contained in the SLI_WIN_RD_ADDR
* register.
*/
union cvmx_sli_win_rd_data
{
uint64_t u64;
struct cvmx_sli_win_rd_data_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t rd_data : 64; /**< The read data. */
#else
uint64_t rd_data : 64;
#endif
} s;
struct cvmx_sli_win_rd_data_s cn63xx;
struct cvmx_sli_win_rd_data_s cn63xxp1;
};
typedef union cvmx_sli_win_rd_data cvmx_sli_win_rd_data_t;
/**
* cvmx_sli_win_wr_addr
*
* Add Lock Register (Set on Read, Clear on write), SW uses to control access to BAR0 space.
*
* Total Address is 16Kb; 0x0000 - 0x3fff, 0x000 - 0x7fe(Reg, every other 8B)
*
* General 5kb; 0x0000 - 0x13ff, 0x000 - 0x27e(Reg-General)
* PktMem 10Kb; 0x1400 - 0x3bff, 0x280 - 0x77e(Reg-General-Packet)
* Rsvd 1Kb; 0x3c00 - 0x3fff, 0x780 - 0x7fe(Reg-NCB Only Mode)
*
* SLI_WIN_WR_ADDR = SLI Window Write Address Register
*
* Contains the address to be writen to when a write operation is started by writing the
* SLI_WIN_WR_DATA register (see below).
*
* This register should NOT be used to write SLI_* registers.
*/
union cvmx_sli_win_wr_addr
{
uint64_t u64;
struct cvmx_sli_win_wr_addr_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_49_63 : 15;
uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always
read as '0'. */
uint64_t wr_addr : 45; /**< The address that will be written to when the
SLI_WIN_WR_DATA register is written.
[47:40] = NCB_ID
[39:3] = Address
When [47:43] == SLI & [42:40] == 0 bits [39:0] are:
[39:32] == x, Not Used
[31:24] == RSL_ID
[23:3] == RSL Register Offset */
uint64_t reserved_0_2 : 3;
#else
uint64_t reserved_0_2 : 3;
uint64_t wr_addr : 45;
uint64_t iobit : 1;
uint64_t reserved_49_63 : 15;
#endif
} s;
struct cvmx_sli_win_wr_addr_s cn63xx;
struct cvmx_sli_win_wr_addr_s cn63xxp1;
};
typedef union cvmx_sli_win_wr_addr cvmx_sli_win_wr_addr_t;
/**
* cvmx_sli_win_wr_data
*
* SLI_WIN_WR_DATA = SLI Window Write Data Register
*
* Contains the data to write to the address located in the SLI_WIN_WR_ADDR Register.
* Writing the least-significant-byte of this register will cause a write operation to take place.
*/
union cvmx_sli_win_wr_data
{
uint64_t u64;
struct cvmx_sli_win_wr_data_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t wr_data : 64; /**< The data to be written. Whenever the LSB of this
register is written, the Window Write will take
place. */
#else
uint64_t wr_data : 64;
#endif
} s;
struct cvmx_sli_win_wr_data_s cn63xx;
struct cvmx_sli_win_wr_data_s cn63xxp1;
};
typedef union cvmx_sli_win_wr_data cvmx_sli_win_wr_data_t;
/**
* cvmx_sli_win_wr_mask
*
* SLI_WIN_WR_MASK = SLI Window Write Mask Register
*
* Contains the mask for the data in the SLI_WIN_WR_DATA Register.
*/
union cvmx_sli_win_wr_mask
{
uint64_t u64;
struct cvmx_sli_win_wr_mask_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_8_63 : 56;
uint64_t wr_mask : 8; /**< The data to be written. When a bit is '1'
the corresponding byte will be written. The values
of this field must be contiguos and for 1, 2, 4, or
8 byte operations and aligned to operation size.
A Value of 0 will produce unpredictable results */
#else
uint64_t wr_mask : 8;
uint64_t reserved_8_63 : 56;
#endif
} s;
struct cvmx_sli_win_wr_mask_s cn63xx;
struct cvmx_sli_win_wr_mask_s cn63xxp1;
};
typedef union cvmx_sli_win_wr_mask cvmx_sli_win_wr_mask_t;
/**
* cvmx_sli_window_ctl
*
* // *
* // * 81e0 - 82d0 Reserved for future subids
* // *
*
* SLI_WINDOW_CTL = SLI's Window Control
*
* Access to register space on the NCB (caused by Window Reads/Writes) will wait for a period of time specified
* by this register before timeing out. Because a Window Access can access the RML, which has a fixed timeout of 0xFFFF
* core clocks, the value of this register should be set to a minimum of 0x200000 to ensure that a timeout to an RML register
* occurs on the RML 0xFFFF timer before the timeout for a BAR0 access from the MAC.
*/
union cvmx_sli_window_ctl
{
uint64_t u64;
struct cvmx_sli_window_ctl_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_32_63 : 32;
uint64_t time : 32; /**< Time to wait in core clocks for a
BAR0 access to completeon the NCB
before timing out. A value of 0 will cause no
timeouts. A minimum value of 0x200000 should be
used when this register is not set to 0x0. */
#else
uint64_t time : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_sli_window_ctl_s cn63xx;
struct cvmx_sli_window_ctl_s cn63xxp1;
};
typedef union cvmx_sli_window_ctl cvmx_sli_window_ctl_t;
#endif
|