1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
|
/***********************license start***************
* Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
* This Software, including technical data, may be subject to U.S. export control
* laws, including the U.S. Export Administration Act and its associated
* regulations, and may be subject to export or import regulations in other
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
***********************license end**************************************/
/**
* cvmx-pcsxx-defs.h
*
* Configuration and status register (CSR) type definitions for
* Octeon pcsxx.
*
* This file is auto generated. Do not edit.
*
* <hr>$Revision$<hr>
*
*/
#ifndef __CVMX_PCSXX_DEFS_H__
#define __CVMX_PCSXX_DEFS_H__
static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id)
{
switch(cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
if ((block_id <= 1))
return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 1) * 0x8000000ull;
break;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
if ((block_id == 0))
return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 0) * 0x8000000ull;
break;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
if ((block_id <= 4))
return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 7) * 0x1000000ull;
break;
}
cvmx_warn("CVMX_PCSXX_10GBX_STATUS_REG (block_id = %lu) not supported on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 7) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id)
{
switch(cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
if ((block_id <= 1))
return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 1) * 0x8000000ull;
break;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
if ((block_id == 0))
return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 0) * 0x8000000ull;
break;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
if ((block_id <= 4))
return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 7) * 0x1000000ull;
break;
}
cvmx_warn("CVMX_PCSXX_BIST_STATUS_REG (block_id = %lu) not supported on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 7) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id)
{
switch(cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
if ((block_id <= 1))
return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 1) * 0x8000000ull;
break;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
if ((block_id == 0))
return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 0) * 0x8000000ull;
break;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
if ((block_id <= 4))
return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 7) * 0x1000000ull;
break;
}
cvmx_warn("CVMX_PCSXX_BIT_LOCK_STATUS_REG (block_id = %lu) not supported on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 7) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id)
{
switch(cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
if ((block_id <= 1))
return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + ((block_id) & 1) * 0x8000000ull;
break;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
if ((block_id == 0))
return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + ((block_id) & 0) * 0x8000000ull;
break;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
if ((block_id <= 4))
return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + ((block_id) & 7) * 0x1000000ull;
break;
}
cvmx_warn("CVMX_PCSXX_CONTROL1_REG (block_id = %lu) not supported on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + ((block_id) & 7) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id)
{
switch(cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
if ((block_id <= 1))
return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + ((block_id) & 1) * 0x8000000ull;
break;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
if ((block_id == 0))
return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + ((block_id) & 0) * 0x8000000ull;
break;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
if ((block_id <= 4))
return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + ((block_id) & 7) * 0x1000000ull;
break;
}
cvmx_warn("CVMX_PCSXX_CONTROL2_REG (block_id = %lu) not supported on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + ((block_id) & 7) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id)
{
switch(cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
if ((block_id <= 1))
return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + ((block_id) & 1) * 0x8000000ull;
break;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
if ((block_id == 0))
return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + ((block_id) & 0) * 0x8000000ull;
break;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
if ((block_id <= 4))
return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + ((block_id) & 7) * 0x1000000ull;
break;
}
cvmx_warn("CVMX_PCSXX_INT_EN_REG (block_id = %lu) not supported on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + ((block_id) & 7) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id)
{
switch(cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
if ((block_id <= 1))
return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + ((block_id) & 1) * 0x8000000ull;
break;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
if ((block_id == 0))
return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + ((block_id) & 0) * 0x8000000ull;
break;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
if ((block_id <= 4))
return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + ((block_id) & 7) * 0x1000000ull;
break;
}
cvmx_warn("CVMX_PCSXX_INT_REG (block_id = %lu) not supported on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + ((block_id) & 7) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id)
{
switch(cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
if ((block_id <= 1))
return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + ((block_id) & 1) * 0x8000000ull;
break;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
if ((block_id == 0))
return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + ((block_id) & 0) * 0x8000000ull;
break;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
if ((block_id <= 4))
return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + ((block_id) & 7) * 0x1000000ull;
break;
}
cvmx_warn("CVMX_PCSXX_LOG_ANL_REG (block_id = %lu) not supported on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + ((block_id) & 7) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id)
{
switch(cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
if ((block_id <= 1))
return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + ((block_id) & 1) * 0x8000000ull;
break;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
if ((block_id == 0))
return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + ((block_id) & 0) * 0x8000000ull;
break;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
if ((block_id <= 4))
return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + ((block_id) & 7) * 0x1000000ull;
break;
}
cvmx_warn("CVMX_PCSXX_MISC_CTL_REG (block_id = %lu) not supported on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + ((block_id) & 7) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id)
{
switch(cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
if ((block_id <= 1))
return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + ((block_id) & 1) * 0x8000000ull;
break;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
if ((block_id == 0))
return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + ((block_id) & 0) * 0x8000000ull;
break;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
if ((block_id <= 4))
return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + ((block_id) & 7) * 0x1000000ull;
break;
}
cvmx_warn("CVMX_PCSXX_RX_SYNC_STATES_REG (block_id = %lu) not supported on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + ((block_id) & 7) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id)
{
switch(cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
if ((block_id <= 1))
return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + ((block_id) & 1) * 0x8000000ull;
break;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
if ((block_id == 0))
return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + ((block_id) & 0) * 0x8000000ull;
break;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
if ((block_id <= 4))
return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + ((block_id) & 7) * 0x1000000ull;
break;
}
cvmx_warn("CVMX_PCSXX_SPD_ABIL_REG (block_id = %lu) not supported on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + ((block_id) & 7) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id)
{
switch(cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
if ((block_id <= 1))
return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + ((block_id) & 1) * 0x8000000ull;
break;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
if ((block_id == 0))
return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + ((block_id) & 0) * 0x8000000ull;
break;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
if ((block_id <= 4))
return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + ((block_id) & 7) * 0x1000000ull;
break;
}
cvmx_warn("CVMX_PCSXX_STATUS1_REG (block_id = %lu) not supported on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + ((block_id) & 7) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id)
{
switch(cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
if ((block_id <= 1))
return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + ((block_id) & 1) * 0x8000000ull;
break;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
if ((block_id == 0))
return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + ((block_id) & 0) * 0x8000000ull;
break;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
if ((block_id <= 4))
return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + ((block_id) & 7) * 0x1000000ull;
break;
}
cvmx_warn("CVMX_PCSXX_STATUS2_REG (block_id = %lu) not supported on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + ((block_id) & 7) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id)
{
switch(cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
if ((block_id <= 1))
return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + ((block_id) & 1) * 0x8000000ull;
break;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
if ((block_id == 0))
return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + ((block_id) & 0) * 0x8000000ull;
break;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
if ((block_id <= 4))
return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + ((block_id) & 7) * 0x1000000ull;
break;
}
cvmx_warn("CVMX_PCSXX_TX_RX_POLARITY_REG (block_id = %lu) not supported on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + ((block_id) & 7) * 0x1000000ull;
}
static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id)
{
switch(cvmx_get_octeon_family()) {
case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
if ((block_id <= 1))
return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + ((block_id) & 1) * 0x8000000ull;
break;
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
if ((block_id == 0))
return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + ((block_id) & 0) * 0x8000000ull;
break;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
if ((block_id <= 4))
return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + ((block_id) & 7) * 0x1000000ull;
break;
}
cvmx_warn("CVMX_PCSXX_TX_RX_STATES_REG (block_id = %lu) not supported on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + ((block_id) & 7) * 0x1000000ull;
}
/**
* cvmx_pcsx#_10gbx_status_reg
*
* PCSX_10GBX_STATUS_REG = 10gbx_status_reg
*
*/
union cvmx_pcsxx_10gbx_status_reg {
uint64_t u64;
struct cvmx_pcsxx_10gbx_status_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_13_63 : 51;
uint64_t alignd : 1; /**< 1=Lane alignment achieved, 0=Lanes not aligned */
uint64_t pattst : 1; /**< Always at 0, no pattern testing capability */
uint64_t reserved_4_10 : 7;
uint64_t l3sync : 1; /**< 1=Rcv lane 3 code grp synchronized, 0=not sync'ed */
uint64_t l2sync : 1; /**< 1=Rcv lane 2 code grp synchronized, 0=not sync'ed */
uint64_t l1sync : 1; /**< 1=Rcv lane 1 code grp synchronized, 0=not sync'ed */
uint64_t l0sync : 1; /**< 1=Rcv lane 0 code grp synchronized, 0=not sync'ed */
#else
uint64_t l0sync : 1;
uint64_t l1sync : 1;
uint64_t l2sync : 1;
uint64_t l3sync : 1;
uint64_t reserved_4_10 : 7;
uint64_t pattst : 1;
uint64_t alignd : 1;
uint64_t reserved_13_63 : 51;
#endif
} s;
struct cvmx_pcsxx_10gbx_status_reg_s cn52xx;
struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1;
struct cvmx_pcsxx_10gbx_status_reg_s cn56xx;
struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1;
struct cvmx_pcsxx_10gbx_status_reg_s cn61xx;
struct cvmx_pcsxx_10gbx_status_reg_s cn63xx;
struct cvmx_pcsxx_10gbx_status_reg_s cn63xxp1;
struct cvmx_pcsxx_10gbx_status_reg_s cn66xx;
struct cvmx_pcsxx_10gbx_status_reg_s cn68xx;
struct cvmx_pcsxx_10gbx_status_reg_s cn68xxp1;
};
typedef union cvmx_pcsxx_10gbx_status_reg cvmx_pcsxx_10gbx_status_reg_t;
/**
* cvmx_pcsx#_bist_status_reg
*
* NOTE: Logic Analyzer is enabled with LA_EN for xaui only. PKT_SZ is effective only when LA_EN=1
* For normal operation(xaui), this bit must be 0. The dropped lane is used to send rxc[3:0].
* See pcs.csr for sgmii/1000Base-X logic analyzer mode.
* For full description see document at .../rtl/pcs/readme_logic_analyzer.txt
*
*
* PCSX Bist Status Register
*/
union cvmx_pcsxx_bist_status_reg {
uint64_t u64;
struct cvmx_pcsxx_bist_status_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63 : 63;
uint64_t bist_status : 1; /**< 1=bist failure, 0=bisted memory ok or bist in progress
pcsx.tx_sm.drf8x36m1_async_bist */
#else
uint64_t bist_status : 1;
uint64_t reserved_1_63 : 63;
#endif
} s;
struct cvmx_pcsxx_bist_status_reg_s cn52xx;
struct cvmx_pcsxx_bist_status_reg_s cn52xxp1;
struct cvmx_pcsxx_bist_status_reg_s cn56xx;
struct cvmx_pcsxx_bist_status_reg_s cn56xxp1;
struct cvmx_pcsxx_bist_status_reg_s cn61xx;
struct cvmx_pcsxx_bist_status_reg_s cn63xx;
struct cvmx_pcsxx_bist_status_reg_s cn63xxp1;
struct cvmx_pcsxx_bist_status_reg_s cn66xx;
struct cvmx_pcsxx_bist_status_reg_s cn68xx;
struct cvmx_pcsxx_bist_status_reg_s cn68xxp1;
};
typedef union cvmx_pcsxx_bist_status_reg cvmx_pcsxx_bist_status_reg_t;
/**
* cvmx_pcsx#_bit_lock_status_reg
*
* LN_SWAP for XAUI is to simplify interconnection layout between devices
*
*
* PCSX Bit Lock Status Register
*/
union cvmx_pcsxx_bit_lock_status_reg {
uint64_t u64;
struct cvmx_pcsxx_bit_lock_status_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63 : 60;
uint64_t bitlck3 : 1; /**< Receive Lane 3 bit lock status */
uint64_t bitlck2 : 1; /**< Receive Lane 2 bit lock status */
uint64_t bitlck1 : 1; /**< Receive Lane 1 bit lock status */
uint64_t bitlck0 : 1; /**< Receive Lane 0 bit lock status */
#else
uint64_t bitlck0 : 1;
uint64_t bitlck1 : 1;
uint64_t bitlck2 : 1;
uint64_t bitlck3 : 1;
uint64_t reserved_4_63 : 60;
#endif
} s;
struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx;
struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1;
struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx;
struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1;
struct cvmx_pcsxx_bit_lock_status_reg_s cn61xx;
struct cvmx_pcsxx_bit_lock_status_reg_s cn63xx;
struct cvmx_pcsxx_bit_lock_status_reg_s cn63xxp1;
struct cvmx_pcsxx_bit_lock_status_reg_s cn66xx;
struct cvmx_pcsxx_bit_lock_status_reg_s cn68xx;
struct cvmx_pcsxx_bit_lock_status_reg_s cn68xxp1;
};
typedef union cvmx_pcsxx_bit_lock_status_reg cvmx_pcsxx_bit_lock_status_reg_t;
/**
* cvmx_pcsx#_control1_reg
*
* NOTE: Logic Analyzer is enabled with LA_EN for the specified PCS lane only. PKT_SZ is effective only when LA_EN=1
* For normal operation(sgmii or 1000Base-X), this bit must be 0.
* See pcsx.csr for xaui logic analyzer mode.
* For full description see document at .../rtl/pcs/readme_logic_analyzer.txt
*
*
* PCSX regs follow IEEE Std 802.3-2005, Section: 45.2.3
*
*
* PCSX_CONTROL1_REG = Control Register1
*/
union cvmx_pcsxx_control1_reg {
uint64_t u64;
struct cvmx_pcsxx_control1_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t reset : 1; /**< 1=SW PCSX Reset, the bit will return to 0 after pcs
has been reset. Takes 32 eclk cycles to reset pcs
0=Normal operation */
uint64_t loopbck1 : 1; /**< 0=normal operation, 1=internal loopback mode
xgmii tx data received from gmx tx port is returned
back into gmx, xgmii rx port. */
uint64_t spdsel1 : 1; /**< See bit 6 description */
uint64_t reserved_12_12 : 1;
uint64_t lo_pwr : 1; /**< 1=Power Down(HW reset), 0=Normal operation */
uint64_t reserved_7_10 : 4;
uint64_t spdsel0 : 1; /**< SPDSEL1 and SPDSEL0 are always at 1'b1. Write has
no effect.
[<6>, <13>]Link Speed selection
1 1 Bits 5:2 select speed */
uint64_t spd : 4; /**< Always select 10Gb/s, writes have no effect */
uint64_t reserved_0_1 : 2;
#else
uint64_t reserved_0_1 : 2;
uint64_t spd : 4;
uint64_t spdsel0 : 1;
uint64_t reserved_7_10 : 4;
uint64_t lo_pwr : 1;
uint64_t reserved_12_12 : 1;
uint64_t spdsel1 : 1;
uint64_t loopbck1 : 1;
uint64_t reset : 1;
uint64_t reserved_16_63 : 48;
#endif
} s;
struct cvmx_pcsxx_control1_reg_s cn52xx;
struct cvmx_pcsxx_control1_reg_s cn52xxp1;
struct cvmx_pcsxx_control1_reg_s cn56xx;
struct cvmx_pcsxx_control1_reg_s cn56xxp1;
struct cvmx_pcsxx_control1_reg_s cn61xx;
struct cvmx_pcsxx_control1_reg_s cn63xx;
struct cvmx_pcsxx_control1_reg_s cn63xxp1;
struct cvmx_pcsxx_control1_reg_s cn66xx;
struct cvmx_pcsxx_control1_reg_s cn68xx;
struct cvmx_pcsxx_control1_reg_s cn68xxp1;
};
typedef union cvmx_pcsxx_control1_reg cvmx_pcsxx_control1_reg_t;
/**
* cvmx_pcsx#_control2_reg
*
* PCSX_CONTROL2_REG = Control Register2
*
*/
union cvmx_pcsxx_control2_reg {
uint64_t u64;
struct cvmx_pcsxx_control2_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63 : 62;
uint64_t type : 2; /**< Always 2'b01, 10GBASE-X only supported */
#else
uint64_t type : 2;
uint64_t reserved_2_63 : 62;
#endif
} s;
struct cvmx_pcsxx_control2_reg_s cn52xx;
struct cvmx_pcsxx_control2_reg_s cn52xxp1;
struct cvmx_pcsxx_control2_reg_s cn56xx;
struct cvmx_pcsxx_control2_reg_s cn56xxp1;
struct cvmx_pcsxx_control2_reg_s cn61xx;
struct cvmx_pcsxx_control2_reg_s cn63xx;
struct cvmx_pcsxx_control2_reg_s cn63xxp1;
struct cvmx_pcsxx_control2_reg_s cn66xx;
struct cvmx_pcsxx_control2_reg_s cn68xx;
struct cvmx_pcsxx_control2_reg_s cn68xxp1;
};
typedef union cvmx_pcsxx_control2_reg cvmx_pcsxx_control2_reg_t;
/**
* cvmx_pcsx#_int_en_reg
*
* Note: DBG_SYNC is a edge triggered interrupt. When set it indicates PCS Synchronization state machine in
* Figure 48-7 state diagram in IEEE Std 802.3-2005 changes state SYNC_ACQUIRED_1 to SYNC_ACQUIRED_2
* indicating an invalid code group was received on one of the 4 receive lanes.
* This interrupt should be always disabled and used only for link problem debugging help.
*
*
* PCSX Interrupt Enable Register
*/
union cvmx_pcsxx_int_en_reg {
uint64_t u64;
struct cvmx_pcsxx_int_en_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_7_63 : 57;
uint64_t dbg_sync_en : 1; /**< Code Group sync failure debug help */
uint64_t algnlos_en : 1; /**< Enable ALGNLOS interrupt */
uint64_t synlos_en : 1; /**< Enable SYNLOS interrupt */
uint64_t bitlckls_en : 1; /**< Enable BITLCKLS interrupt */
uint64_t rxsynbad_en : 1; /**< Enable RXSYNBAD interrupt */
uint64_t rxbad_en : 1; /**< Enable RXBAD interrupt */
uint64_t txflt_en : 1; /**< Enable TXFLT interrupt */
#else
uint64_t txflt_en : 1;
uint64_t rxbad_en : 1;
uint64_t rxsynbad_en : 1;
uint64_t bitlckls_en : 1;
uint64_t synlos_en : 1;
uint64_t algnlos_en : 1;
uint64_t dbg_sync_en : 1;
uint64_t reserved_7_63 : 57;
#endif
} s;
struct cvmx_pcsxx_int_en_reg_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63 : 58;
uint64_t algnlos_en : 1; /**< Enable ALGNLOS interrupt */
uint64_t synlos_en : 1; /**< Enable SYNLOS interrupt */
uint64_t bitlckls_en : 1; /**< Enable BITLCKLS interrupt */
uint64_t rxsynbad_en : 1; /**< Enable RXSYNBAD interrupt */
uint64_t rxbad_en : 1; /**< Enable RXBAD interrupt */
uint64_t txflt_en : 1; /**< Enable TXFLT interrupt */
#else
uint64_t txflt_en : 1;
uint64_t rxbad_en : 1;
uint64_t rxsynbad_en : 1;
uint64_t bitlckls_en : 1;
uint64_t synlos_en : 1;
uint64_t algnlos_en : 1;
uint64_t reserved_6_63 : 58;
#endif
} cn52xx;
struct cvmx_pcsxx_int_en_reg_cn52xx cn52xxp1;
struct cvmx_pcsxx_int_en_reg_cn52xx cn56xx;
struct cvmx_pcsxx_int_en_reg_cn52xx cn56xxp1;
struct cvmx_pcsxx_int_en_reg_s cn61xx;
struct cvmx_pcsxx_int_en_reg_s cn63xx;
struct cvmx_pcsxx_int_en_reg_s cn63xxp1;
struct cvmx_pcsxx_int_en_reg_s cn66xx;
struct cvmx_pcsxx_int_en_reg_s cn68xx;
struct cvmx_pcsxx_int_en_reg_s cn68xxp1;
};
typedef union cvmx_pcsxx_int_en_reg cvmx_pcsxx_int_en_reg_t;
/**
* cvmx_pcsx#_int_reg
*
* PCSX Interrupt Register
*
*/
union cvmx_pcsxx_int_reg {
uint64_t u64;
struct cvmx_pcsxx_int_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_7_63 : 57;
uint64_t dbg_sync : 1; /**< Code Group sync failure debug help, see Note below */
uint64_t algnlos : 1; /**< Set when XAUI lanes lose alignment */
uint64_t synlos : 1; /**< Set when Code group sync lost on 1 or more lanes */
uint64_t bitlckls : 1; /**< Set when Bit lock lost on 1 or more xaui lanes */
uint64_t rxsynbad : 1; /**< Set when RX code grp sync st machine in bad state
in one of the 4 xaui lanes */
uint64_t rxbad : 1; /**< Set when RX state machine in bad state */
uint64_t txflt : 1; /**< None defined at this time, always 0x0 */
#else
uint64_t txflt : 1;
uint64_t rxbad : 1;
uint64_t rxsynbad : 1;
uint64_t bitlckls : 1;
uint64_t synlos : 1;
uint64_t algnlos : 1;
uint64_t dbg_sync : 1;
uint64_t reserved_7_63 : 57;
#endif
} s;
struct cvmx_pcsxx_int_reg_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63 : 58;
uint64_t algnlos : 1; /**< Set when XAUI lanes lose alignment */
uint64_t synlos : 1; /**< Set when Code group sync lost on 1 or more lanes */
uint64_t bitlckls : 1; /**< Set when Bit lock lost on 1 or more xaui lanes */
uint64_t rxsynbad : 1; /**< Set when RX code grp sync st machine in bad state
in one of the 4 xaui lanes */
uint64_t rxbad : 1; /**< Set when RX state machine in bad state */
uint64_t txflt : 1; /**< None defined at this time, always 0x0 */
#else
uint64_t txflt : 1;
uint64_t rxbad : 1;
uint64_t rxsynbad : 1;
uint64_t bitlckls : 1;
uint64_t synlos : 1;
uint64_t algnlos : 1;
uint64_t reserved_6_63 : 58;
#endif
} cn52xx;
struct cvmx_pcsxx_int_reg_cn52xx cn52xxp1;
struct cvmx_pcsxx_int_reg_cn52xx cn56xx;
struct cvmx_pcsxx_int_reg_cn52xx cn56xxp1;
struct cvmx_pcsxx_int_reg_s cn61xx;
struct cvmx_pcsxx_int_reg_s cn63xx;
struct cvmx_pcsxx_int_reg_s cn63xxp1;
struct cvmx_pcsxx_int_reg_s cn66xx;
struct cvmx_pcsxx_int_reg_s cn68xx;
struct cvmx_pcsxx_int_reg_s cn68xxp1;
};
typedef union cvmx_pcsxx_int_reg cvmx_pcsxx_int_reg_t;
/**
* cvmx_pcsx#_log_anl_reg
*
* PCSX Logic Analyzer Register
*
*/
union cvmx_pcsxx_log_anl_reg {
uint64_t u64;
struct cvmx_pcsxx_log_anl_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_7_63 : 57;
uint64_t enc_mode : 1; /**< 1=send xaui encoded data, 0=send xaui raw data to GMX
See .../rtl/pcs/readme_logic_analyzer.txt for details */
uint64_t drop_ln : 2; /**< xaui lane# to drop from logic analyzer packets
[<5>, <4>] Drop lane \#
0 0 Drop lane 0 data
0 1 Drop lane 1 data
1 0 Drop lane 2 data
1 1 Drop lane 3 data */
uint64_t lafifovfl : 1; /**< 1=logic analyser fif overflowed one or more times
during packetization.
Write 1 to clear this bit */
uint64_t la_en : 1; /**< 1= Logic Analyzer enabled, 0=Logic Analyzer disabled */
uint64_t pkt_sz : 2; /**< [<1>, <0>] Logic Analyzer Packet Size
0 0 Packet size 1k bytes
0 1 Packet size 4k bytes
1 0 Packet size 8k bytes
1 1 Packet size 16k bytes */
#else
uint64_t pkt_sz : 2;
uint64_t la_en : 1;
uint64_t lafifovfl : 1;
uint64_t drop_ln : 2;
uint64_t enc_mode : 1;
uint64_t reserved_7_63 : 57;
#endif
} s;
struct cvmx_pcsxx_log_anl_reg_s cn52xx;
struct cvmx_pcsxx_log_anl_reg_s cn52xxp1;
struct cvmx_pcsxx_log_anl_reg_s cn56xx;
struct cvmx_pcsxx_log_anl_reg_s cn56xxp1;
struct cvmx_pcsxx_log_anl_reg_s cn61xx;
struct cvmx_pcsxx_log_anl_reg_s cn63xx;
struct cvmx_pcsxx_log_anl_reg_s cn63xxp1;
struct cvmx_pcsxx_log_anl_reg_s cn66xx;
struct cvmx_pcsxx_log_anl_reg_s cn68xx;
struct cvmx_pcsxx_log_anl_reg_s cn68xxp1;
};
typedef union cvmx_pcsxx_log_anl_reg cvmx_pcsxx_log_anl_reg_t;
/**
* cvmx_pcsx#_misc_ctl_reg
*
* RX lane polarity vector [3:0] = XOR_RXPLRT<9:6> ^ [4[RXPLRT<1>]];
*
* TX lane polarity vector [3:0] = XOR_TXPLRT<5:2> ^ [4[TXPLRT<0>]];
*
* In short keep <1:0> to 2'b00, and use <5:2> and <9:6> fields to define per lane polarities
*
*
*
* PCSX Misc Control Register
*/
union cvmx_pcsxx_misc_ctl_reg {
uint64_t u64;
struct cvmx_pcsxx_misc_ctl_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63 : 60;
uint64_t tx_swap : 1; /**< 0=do not swap xaui lanes going out to qlm's
1=swap lanes 3 <-> 0 and 2 <-> 1 */
uint64_t rx_swap : 1; /**< 0=do not swap xaui lanes coming in from qlm's
1=swap lanes 3 <-> 0 and 2 <-> 1 */
uint64_t xaui : 1; /**< 1=XAUI mode selected, 0=not XAUI mode selected
This bit represents pi_qlm1/3_cfg[1:0] pin status */
uint64_t gmxeno : 1; /**< GMX port enable override, GMX en/dis status is held
during data packet reception. */
#else
uint64_t gmxeno : 1;
uint64_t xaui : 1;
uint64_t rx_swap : 1;
uint64_t tx_swap : 1;
uint64_t reserved_4_63 : 60;
#endif
} s;
struct cvmx_pcsxx_misc_ctl_reg_s cn52xx;
struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1;
struct cvmx_pcsxx_misc_ctl_reg_s cn56xx;
struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1;
struct cvmx_pcsxx_misc_ctl_reg_s cn61xx;
struct cvmx_pcsxx_misc_ctl_reg_s cn63xx;
struct cvmx_pcsxx_misc_ctl_reg_s cn63xxp1;
struct cvmx_pcsxx_misc_ctl_reg_s cn66xx;
struct cvmx_pcsxx_misc_ctl_reg_s cn68xx;
struct cvmx_pcsxx_misc_ctl_reg_s cn68xxp1;
};
typedef union cvmx_pcsxx_misc_ctl_reg cvmx_pcsxx_misc_ctl_reg_t;
/**
* cvmx_pcsx#_rx_sync_states_reg
*
* PCSX_RX_SYNC_STATES_REG = Receive Sync States Register
*
*/
union cvmx_pcsxx_rx_sync_states_reg {
uint64_t u64;
struct cvmx_pcsxx_rx_sync_states_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t sync3st : 4; /**< Receive lane 3 code grp sync state machine state */
uint64_t sync2st : 4; /**< Receive lane 2 code grp sync state machine state */
uint64_t sync1st : 4; /**< Receive lane 1 code grp sync state machine state */
uint64_t sync0st : 4; /**< Receive lane 0 code grp sync state machine state */
#else
uint64_t sync0st : 4;
uint64_t sync1st : 4;
uint64_t sync2st : 4;
uint64_t sync3st : 4;
uint64_t reserved_16_63 : 48;
#endif
} s;
struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx;
struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1;
struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx;
struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1;
struct cvmx_pcsxx_rx_sync_states_reg_s cn61xx;
struct cvmx_pcsxx_rx_sync_states_reg_s cn63xx;
struct cvmx_pcsxx_rx_sync_states_reg_s cn63xxp1;
struct cvmx_pcsxx_rx_sync_states_reg_s cn66xx;
struct cvmx_pcsxx_rx_sync_states_reg_s cn68xx;
struct cvmx_pcsxx_rx_sync_states_reg_s cn68xxp1;
};
typedef union cvmx_pcsxx_rx_sync_states_reg cvmx_pcsxx_rx_sync_states_reg_t;
/**
* cvmx_pcsx#_spd_abil_reg
*
* PCSX_SPD_ABIL_REG = Speed ability register
*
*/
union cvmx_pcsxx_spd_abil_reg {
uint64_t u64;
struct cvmx_pcsxx_spd_abil_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63 : 62;
uint64_t tenpasst : 1; /**< Always 0, no 10PASS-TS/2BASE-TL capability support */
uint64_t tengb : 1; /**< Always 1, 10Gb/s supported */
#else
uint64_t tengb : 1;
uint64_t tenpasst : 1;
uint64_t reserved_2_63 : 62;
#endif
} s;
struct cvmx_pcsxx_spd_abil_reg_s cn52xx;
struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1;
struct cvmx_pcsxx_spd_abil_reg_s cn56xx;
struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1;
struct cvmx_pcsxx_spd_abil_reg_s cn61xx;
struct cvmx_pcsxx_spd_abil_reg_s cn63xx;
struct cvmx_pcsxx_spd_abil_reg_s cn63xxp1;
struct cvmx_pcsxx_spd_abil_reg_s cn66xx;
struct cvmx_pcsxx_spd_abil_reg_s cn68xx;
struct cvmx_pcsxx_spd_abil_reg_s cn68xxp1;
};
typedef union cvmx_pcsxx_spd_abil_reg cvmx_pcsxx_spd_abil_reg_t;
/**
* cvmx_pcsx#_status1_reg
*
* PCSX_STATUS1_REG = Status Register1
*
*/
union cvmx_pcsxx_status1_reg {
uint64_t u64;
struct cvmx_pcsxx_status1_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63 : 56;
uint64_t flt : 1; /**< 1=Fault condition detected, 0=No fault condition
This bit is a logical OR of Status2 reg bits 11,10 */
uint64_t reserved_3_6 : 4;
uint64_t rcv_lnk : 1; /**< 1=Receive Link up, 0=Receive Link down
Latching Low version of r_10gbx_status_reg[12],
Link down status continues until SW read. */
uint64_t lpable : 1; /**< Always set to 1 for Low Power ablility indication */
uint64_t reserved_0_0 : 1;
#else
uint64_t reserved_0_0 : 1;
uint64_t lpable : 1;
uint64_t rcv_lnk : 1;
uint64_t reserved_3_6 : 4;
uint64_t flt : 1;
uint64_t reserved_8_63 : 56;
#endif
} s;
struct cvmx_pcsxx_status1_reg_s cn52xx;
struct cvmx_pcsxx_status1_reg_s cn52xxp1;
struct cvmx_pcsxx_status1_reg_s cn56xx;
struct cvmx_pcsxx_status1_reg_s cn56xxp1;
struct cvmx_pcsxx_status1_reg_s cn61xx;
struct cvmx_pcsxx_status1_reg_s cn63xx;
struct cvmx_pcsxx_status1_reg_s cn63xxp1;
struct cvmx_pcsxx_status1_reg_s cn66xx;
struct cvmx_pcsxx_status1_reg_s cn68xx;
struct cvmx_pcsxx_status1_reg_s cn68xxp1;
};
typedef union cvmx_pcsxx_status1_reg cvmx_pcsxx_status1_reg_t;
/**
* cvmx_pcsx#_status2_reg
*
* PCSX_STATUS2_REG = Status Register2
*
*/
union cvmx_pcsxx_status2_reg {
uint64_t u64;
struct cvmx_pcsxx_status2_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t dev : 2; /**< Always at 2'b10, means a Device present at the addr */
uint64_t reserved_12_13 : 2;
uint64_t xmtflt : 1; /**< 0=No xmit fault, 1=xmit fault. Implements latching
High function until SW read. */
uint64_t rcvflt : 1; /**< 0=No rcv fault, 1=rcv fault. Implements latching
High function until SW read */
uint64_t reserved_3_9 : 7;
uint64_t tengb_w : 1; /**< Always 0, no 10GBASE-W capability */
uint64_t tengb_x : 1; /**< Always 1, 10GBASE-X capable */
uint64_t tengb_r : 1; /**< Always 0, no 10GBASE-R capability */
#else
uint64_t tengb_r : 1;
uint64_t tengb_x : 1;
uint64_t tengb_w : 1;
uint64_t reserved_3_9 : 7;
uint64_t rcvflt : 1;
uint64_t xmtflt : 1;
uint64_t reserved_12_13 : 2;
uint64_t dev : 2;
uint64_t reserved_16_63 : 48;
#endif
} s;
struct cvmx_pcsxx_status2_reg_s cn52xx;
struct cvmx_pcsxx_status2_reg_s cn52xxp1;
struct cvmx_pcsxx_status2_reg_s cn56xx;
struct cvmx_pcsxx_status2_reg_s cn56xxp1;
struct cvmx_pcsxx_status2_reg_s cn61xx;
struct cvmx_pcsxx_status2_reg_s cn63xx;
struct cvmx_pcsxx_status2_reg_s cn63xxp1;
struct cvmx_pcsxx_status2_reg_s cn66xx;
struct cvmx_pcsxx_status2_reg_s cn68xx;
struct cvmx_pcsxx_status2_reg_s cn68xxp1;
};
typedef union cvmx_pcsxx_status2_reg cvmx_pcsxx_status2_reg_t;
/**
* cvmx_pcsx#_tx_rx_polarity_reg
*
* PCSX_POLARITY_REG = TX_RX polarity reg
*
*/
union cvmx_pcsxx_tx_rx_polarity_reg {
uint64_t u64;
struct cvmx_pcsxx_tx_rx_polarity_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63 : 54;
uint64_t xor_rxplrt : 4; /**< Per lane RX polarity control */
uint64_t xor_txplrt : 4; /**< Per lane TX polarity control */
uint64_t rxplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */
uint64_t txplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */
#else
uint64_t txplrt : 1;
uint64_t rxplrt : 1;
uint64_t xor_txplrt : 4;
uint64_t xor_rxplrt : 4;
uint64_t reserved_10_63 : 54;
#endif
} s;
struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx;
struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63 : 62;
uint64_t rxplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */
uint64_t txplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */
#else
uint64_t txplrt : 1;
uint64_t rxplrt : 1;
uint64_t reserved_2_63 : 62;
#endif
} cn52xxp1;
struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx;
struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1;
struct cvmx_pcsxx_tx_rx_polarity_reg_s cn61xx;
struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xx;
struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xxp1;
struct cvmx_pcsxx_tx_rx_polarity_reg_s cn66xx;
struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xx;
struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xxp1;
};
typedef union cvmx_pcsxx_tx_rx_polarity_reg cvmx_pcsxx_tx_rx_polarity_reg_t;
/**
* cvmx_pcsx#_tx_rx_states_reg
*
* PCSX_TX_RX_STATES_REG = Transmit Receive States Register
*
*/
union cvmx_pcsxx_tx_rx_states_reg {
uint64_t u64;
struct cvmx_pcsxx_tx_rx_states_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_14_63 : 50;
uint64_t term_err : 1; /**< 1=Check end function detected error in packet
terminate ||T|| column or the one after it */
uint64_t syn3bad : 1; /**< 1=lane 3 code grp sync state machine in bad state */
uint64_t syn2bad : 1; /**< 1=lane 2 code grp sync state machine in bad state */
uint64_t syn1bad : 1; /**< 1=lane 1 code grp sync state machine in bad state */
uint64_t syn0bad : 1; /**< 1=lane 0 code grp sync state machine in bad state */
uint64_t rxbad : 1; /**< 1=Rcv state machine in a bad state, HW malfunction */
uint64_t algn_st : 3; /**< Lane alignment state machine state state */
uint64_t rx_st : 2; /**< Receive state machine state state */
uint64_t tx_st : 3; /**< Transmit state machine state state */
#else
uint64_t tx_st : 3;
uint64_t rx_st : 2;
uint64_t algn_st : 3;
uint64_t rxbad : 1;
uint64_t syn0bad : 1;
uint64_t syn1bad : 1;
uint64_t syn2bad : 1;
uint64_t syn3bad : 1;
uint64_t term_err : 1;
uint64_t reserved_14_63 : 50;
#endif
} s;
struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx;
struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_13_63 : 51;
uint64_t syn3bad : 1; /**< 1=lane 3 code grp sync state machine in bad state */
uint64_t syn2bad : 1; /**< 1=lane 2 code grp sync state machine in bad state */
uint64_t syn1bad : 1; /**< 1=lane 1 code grp sync state machine in bad state */
uint64_t syn0bad : 1; /**< 1=lane 0 code grp sync state machine in bad state */
uint64_t rxbad : 1; /**< 1=Rcv state machine in a bad state, HW malfunction */
uint64_t algn_st : 3; /**< Lane alignment state machine state state */
uint64_t rx_st : 2; /**< Receive state machine state state */
uint64_t tx_st : 3; /**< Transmit state machine state state */
#else
uint64_t tx_st : 3;
uint64_t rx_st : 2;
uint64_t algn_st : 3;
uint64_t rxbad : 1;
uint64_t syn0bad : 1;
uint64_t syn1bad : 1;
uint64_t syn2bad : 1;
uint64_t syn3bad : 1;
uint64_t reserved_13_63 : 51;
#endif
} cn52xxp1;
struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx;
struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1;
struct cvmx_pcsxx_tx_rx_states_reg_s cn61xx;
struct cvmx_pcsxx_tx_rx_states_reg_s cn63xx;
struct cvmx_pcsxx_tx_rx_states_reg_s cn63xxp1;
struct cvmx_pcsxx_tx_rx_states_reg_s cn66xx;
struct cvmx_pcsxx_tx_rx_states_reg_s cn68xx;
struct cvmx_pcsxx_tx_rx_states_reg_s cn68xxp1;
};
typedef union cvmx_pcsxx_tx_rx_states_reg cvmx_pcsxx_tx_rx_states_reg_t;
#endif
|
