1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
|
/***********************license start***************
* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
* reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of Cavium Networks nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
* This Software, including technical data, may be subject to U.S. export control
* laws, including the U.S. Export Administration Act and its associated
* regulations, and may be subject to export or import regulations in other
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
***********************license end**************************************/
/**
* cvmx-asxx-defs.h
*
* Configuration and status register (CSR) type definitions for
* Octeon asxx.
*
* This file is auto generated. Do not edit.
*
* <hr>$Revision$<hr>
*
*/
#ifndef __CVMX_ASXX_TYPEDEFS_H__
#define __CVMX_ASXX_TYPEDEFS_H__
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_GMII_RX_CLK_SET(unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
cvmx_warn("CVMX_ASXX_GMII_RX_CLK_SET(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000180ull);
}
#else
#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_GMII_RX_DAT_SET(unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
cvmx_warn("CVMX_ASXX_GMII_RX_DAT_SET(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000188ull);
}
#else
#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_INT_EN(unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_ASXX_INT_EN(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull;
}
#else
#define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_INT_REG(unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_ASXX_INT_REG(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull;
}
#else
#define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_MII_RX_DAT_SET(unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
cvmx_warn("CVMX_ASXX_MII_RX_DAT_SET(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000190ull);
}
#else
#define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000190ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_PRT_LOOP(unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_ASXX_PRT_LOOP(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull;
}
#else
#define CVMX_ASXX_PRT_LOOP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_RLD_BYPASS(unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_ASXX_RLD_BYPASS(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull;
}
#else
#define CVMX_ASXX_RLD_BYPASS(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_RLD_BYPASS_SETTING(unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_ASXX_RLD_BYPASS_SETTING(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull;
}
#else
#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_RLD_COMP(unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_ASXX_RLD_COMP(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull;
}
#else
#define CVMX_ASXX_RLD_COMP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_RLD_DATA_DRV(unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_ASXX_RLD_DATA_DRV(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull;
}
#else
#define CVMX_ASXX_RLD_DATA_DRV(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_RLD_FCRAM_MODE(unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_ASXX_RLD_FCRAM_MODE(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull;
}
#else
#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_RLD_NCTL_STRONG(unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_ASXX_RLD_NCTL_STRONG(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull;
}
#else
#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_RLD_NCTL_WEAK(unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_ASXX_RLD_NCTL_WEAK(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull;
}
#else
#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_RLD_PCTL_STRONG(unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_ASXX_RLD_PCTL_STRONG(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull;
}
#else
#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_RLD_PCTL_WEAK(unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_ASXX_RLD_PCTL_WEAK(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull;
}
#else
#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_RLD_SETTING(unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_ASXX_RLD_SETTING(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull;
}
#else
#define CVMX_ASXX_RLD_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_RX_CLK_SETX(unsigned long offset, unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
(OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
(OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
cvmx_warn("CVMX_ASXX_RX_CLK_SETX(%lu,%lu) is invalid on this chip\n", offset, block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
}
#else
#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_RX_PRT_EN(unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_ASXX_RX_PRT_EN(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull;
}
#else
#define CVMX_ASXX_RX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_RX_WOL(unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_ASXX_RX_WOL(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull;
}
#else
#define CVMX_ASXX_RX_WOL(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_RX_WOL_MSK(unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_ASXX_RX_WOL_MSK(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull;
}
#else
#define CVMX_ASXX_RX_WOL_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_RX_WOL_POWOK(unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_ASXX_RX_WOL_POWOK(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull;
}
#else
#define CVMX_ASXX_RX_WOL_POWOK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_RX_WOL_SIG(unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_ASXX_RX_WOL_SIG(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull;
}
#else
#define CVMX_ASXX_RX_WOL_SIG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_TX_CLK_SETX(unsigned long offset, unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
(OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
(OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
cvmx_warn("CVMX_ASXX_TX_CLK_SETX(%lu,%lu) is invalid on this chip\n", offset, block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
}
#else
#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_TX_COMP_BYP(unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_ASXX_TX_COMP_BYP(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull;
}
#else
#define CVMX_ASXX_TX_COMP_BYP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_TX_HI_WATERX(unsigned long offset, unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
(OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
(OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
cvmx_warn("CVMX_ASXX_TX_HI_WATERX(%lu,%lu) is invalid on this chip\n", offset, block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
}
#else
#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_TX_PRT_EN(unsigned long block_id)
{
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_ASXX_TX_PRT_EN(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull;
}
#else
#define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull)
#endif
/**
* cvmx_asx#_gmii_rx_clk_set
*
* ASX_GMII_RX_CLK_SET = GMII Clock delay setting
*
*/
union cvmx_asxx_gmii_rx_clk_set
{
uint64_t u64;
struct cvmx_asxx_gmii_rx_clk_set_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_5_63 : 59;
uint64_t setting : 5; /**< Setting to place on the RXCLK (GMII receive clk)
delay line. The intrinsic delay can range from
50ps to 80ps per tap. */
#else
uint64_t setting : 5;
uint64_t reserved_5_63 : 59;
#endif
} s;
struct cvmx_asxx_gmii_rx_clk_set_s cn30xx;
struct cvmx_asxx_gmii_rx_clk_set_s cn31xx;
struct cvmx_asxx_gmii_rx_clk_set_s cn50xx;
};
typedef union cvmx_asxx_gmii_rx_clk_set cvmx_asxx_gmii_rx_clk_set_t;
/**
* cvmx_asx#_gmii_rx_dat_set
*
* ASX_GMII_RX_DAT_SET = GMII Clock delay setting
*
*/
union cvmx_asxx_gmii_rx_dat_set
{
uint64_t u64;
struct cvmx_asxx_gmii_rx_dat_set_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_5_63 : 59;
uint64_t setting : 5; /**< Setting to place on the RXD (GMII receive data)
delay lines. The intrinsic delay can range from
50ps to 80ps per tap. */
#else
uint64_t setting : 5;
uint64_t reserved_5_63 : 59;
#endif
} s;
struct cvmx_asxx_gmii_rx_dat_set_s cn30xx;
struct cvmx_asxx_gmii_rx_dat_set_s cn31xx;
struct cvmx_asxx_gmii_rx_dat_set_s cn50xx;
};
typedef union cvmx_asxx_gmii_rx_dat_set cvmx_asxx_gmii_rx_dat_set_t;
/**
* cvmx_asx#_int_en
*
* ASX_INT_EN = Interrupt Enable
*
*/
union cvmx_asxx_int_en
{
uint64_t u64;
struct cvmx_asxx_int_en_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_12_63 : 52;
uint64_t txpsh : 4; /**< TX FIFO overflow on RMGII port */
uint64_t txpop : 4; /**< TX FIFO underflow on RMGII port */
uint64_t ovrflw : 4; /**< RX FIFO overflow on RMGII port */
#else
uint64_t ovrflw : 4;
uint64_t txpop : 4;
uint64_t txpsh : 4;
uint64_t reserved_12_63 : 52;
#endif
} s;
struct cvmx_asxx_int_en_cn30xx
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_11_63 : 53;
uint64_t txpsh : 3; /**< TX FIFO overflow on RMGII port */
uint64_t reserved_7_7 : 1;
uint64_t txpop : 3; /**< TX FIFO underflow on RMGII port */
uint64_t reserved_3_3 : 1;
uint64_t ovrflw : 3; /**< RX FIFO overflow on RMGII port */
#else
uint64_t ovrflw : 3;
uint64_t reserved_3_3 : 1;
uint64_t txpop : 3;
uint64_t reserved_7_7 : 1;
uint64_t txpsh : 3;
uint64_t reserved_11_63 : 53;
#endif
} cn30xx;
struct cvmx_asxx_int_en_cn30xx cn31xx;
struct cvmx_asxx_int_en_s cn38xx;
struct cvmx_asxx_int_en_s cn38xxp2;
struct cvmx_asxx_int_en_cn30xx cn50xx;
struct cvmx_asxx_int_en_s cn58xx;
struct cvmx_asxx_int_en_s cn58xxp1;
};
typedef union cvmx_asxx_int_en cvmx_asxx_int_en_t;
/**
* cvmx_asx#_int_reg
*
* ASX_INT_REG = Interrupt Register
*
*/
union cvmx_asxx_int_reg
{
uint64_t u64;
struct cvmx_asxx_int_reg_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_12_63 : 52;
uint64_t txpsh : 4; /**< TX FIFO overflow on RMGII port */
uint64_t txpop : 4; /**< TX FIFO underflow on RMGII port */
uint64_t ovrflw : 4; /**< RX FIFO overflow on RMGII port */
#else
uint64_t ovrflw : 4;
uint64_t txpop : 4;
uint64_t txpsh : 4;
uint64_t reserved_12_63 : 52;
#endif
} s;
struct cvmx_asxx_int_reg_cn30xx
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_11_63 : 53;
uint64_t txpsh : 3; /**< TX FIFO overflow on RMGII port */
uint64_t reserved_7_7 : 1;
uint64_t txpop : 3; /**< TX FIFO underflow on RMGII port */
uint64_t reserved_3_3 : 1;
uint64_t ovrflw : 3; /**< RX FIFO overflow on RMGII port */
#else
uint64_t ovrflw : 3;
uint64_t reserved_3_3 : 1;
uint64_t txpop : 3;
uint64_t reserved_7_7 : 1;
uint64_t txpsh : 3;
uint64_t reserved_11_63 : 53;
#endif
} cn30xx;
struct cvmx_asxx_int_reg_cn30xx cn31xx;
struct cvmx_asxx_int_reg_s cn38xx;
struct cvmx_asxx_int_reg_s cn38xxp2;
struct cvmx_asxx_int_reg_cn30xx cn50xx;
struct cvmx_asxx_int_reg_s cn58xx;
struct cvmx_asxx_int_reg_s cn58xxp1;
};
typedef union cvmx_asxx_int_reg cvmx_asxx_int_reg_t;
/**
* cvmx_asx#_mii_rx_dat_set
*
* ASX_MII_RX_DAT_SET = GMII Clock delay setting
*
*/
union cvmx_asxx_mii_rx_dat_set
{
uint64_t u64;
struct cvmx_asxx_mii_rx_dat_set_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_5_63 : 59;
uint64_t setting : 5; /**< Setting to place on the RXD (MII receive data)
delay lines. The intrinsic delay can range from
50ps to 80ps per tap. */
#else
uint64_t setting : 5;
uint64_t reserved_5_63 : 59;
#endif
} s;
struct cvmx_asxx_mii_rx_dat_set_s cn30xx;
struct cvmx_asxx_mii_rx_dat_set_s cn50xx;
};
typedef union cvmx_asxx_mii_rx_dat_set cvmx_asxx_mii_rx_dat_set_t;
/**
* cvmx_asx#_prt_loop
*
* ASX_PRT_LOOP = Internal Loopback mode - TX FIFO output goes into RX FIFO (and maybe pins)
*
*/
union cvmx_asxx_prt_loop
{
uint64_t u64;
struct cvmx_asxx_prt_loop_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_8_63 : 56;
uint64_t ext_loop : 4; /**< External Loopback Enable
0 = No Loopback (TX FIFO is filled by RMGII)
1 = RX FIFO drives the TX FIFO
- GMX_PRT_CFG[DUPLEX] must be 1 (FullDuplex)
- GMX_PRT_CFG[SPEED] must be 1 (GigE speed)
- core clock > 250MHZ
- rxc must not deviate from the +-50ppm
- if txc>rxc, idle cycle may drop over time */
uint64_t int_loop : 4; /**< Internal Loopback Enable
0 = No Loopback (RX FIFO is filled by RMGII pins)
1 = TX FIFO drives the RX FIFO
Note, in internal loop-back mode, the RGMII link
status is not used (since there is no real PHY).
Software cannot use the inband status. */
#else
uint64_t int_loop : 4;
uint64_t ext_loop : 4;
uint64_t reserved_8_63 : 56;
#endif
} s;
struct cvmx_asxx_prt_loop_cn30xx
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_7_63 : 57;
uint64_t ext_loop : 3; /**< External Loopback Enable
0 = No Loopback (TX FIFO is filled by RMGII)
1 = RX FIFO drives the TX FIFO
- GMX_PRT_CFG[DUPLEX] must be 1 (FullDuplex)
- GMX_PRT_CFG[SPEED] must be 1 (GigE speed)
- core clock > 250MHZ
- rxc must not deviate from the +-50ppm
- if txc>rxc, idle cycle may drop over time */
uint64_t reserved_3_3 : 1;
uint64_t int_loop : 3; /**< Internal Loopback Enable
0 = No Loopback (RX FIFO is filled by RMGII pins)
1 = TX FIFO drives the RX FIFO
- GMX_PRT_CFG[DUPLEX] must be 1 (FullDuplex)
- GMX_PRT_CFG[SPEED] must be 1 (GigE speed)
- GMX_TX_CLK[CLK_CNT] must be 1
Note, in internal loop-back mode, the RGMII link
status is not used (since there is no real PHY).
Software cannot use the inband status. */
#else
uint64_t int_loop : 3;
uint64_t reserved_3_3 : 1;
uint64_t ext_loop : 3;
uint64_t reserved_7_63 : 57;
#endif
} cn30xx;
struct cvmx_asxx_prt_loop_cn30xx cn31xx;
struct cvmx_asxx_prt_loop_s cn38xx;
struct cvmx_asxx_prt_loop_s cn38xxp2;
struct cvmx_asxx_prt_loop_cn30xx cn50xx;
struct cvmx_asxx_prt_loop_s cn58xx;
struct cvmx_asxx_prt_loop_s cn58xxp1;
};
typedef union cvmx_asxx_prt_loop cvmx_asxx_prt_loop_t;
/**
* cvmx_asx#_rld_bypass
*
* ASX_RLD_BYPASS
*
*/
union cvmx_asxx_rld_bypass
{
uint64_t u64;
struct cvmx_asxx_rld_bypass_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_1_63 : 63;
uint64_t bypass : 1; /**< When set, the rld_dll setting is bypassed with
ASX_RLD_BYPASS_SETTING */
#else
uint64_t bypass : 1;
uint64_t reserved_1_63 : 63;
#endif
} s;
struct cvmx_asxx_rld_bypass_s cn38xx;
struct cvmx_asxx_rld_bypass_s cn38xxp2;
struct cvmx_asxx_rld_bypass_s cn58xx;
struct cvmx_asxx_rld_bypass_s cn58xxp1;
};
typedef union cvmx_asxx_rld_bypass cvmx_asxx_rld_bypass_t;
/**
* cvmx_asx#_rld_bypass_setting
*
* ASX_RLD_BYPASS_SETTING
*
*/
union cvmx_asxx_rld_bypass_setting
{
uint64_t u64;
struct cvmx_asxx_rld_bypass_setting_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_5_63 : 59;
uint64_t setting : 5; /**< The rld_dll setting bypass value */
#else
uint64_t setting : 5;
uint64_t reserved_5_63 : 59;
#endif
} s;
struct cvmx_asxx_rld_bypass_setting_s cn38xx;
struct cvmx_asxx_rld_bypass_setting_s cn38xxp2;
struct cvmx_asxx_rld_bypass_setting_s cn58xx;
struct cvmx_asxx_rld_bypass_setting_s cn58xxp1;
};
typedef union cvmx_asxx_rld_bypass_setting cvmx_asxx_rld_bypass_setting_t;
/**
* cvmx_asx#_rld_comp
*
* ASX_RLD_COMP
*
*/
union cvmx_asxx_rld_comp
{
uint64_t u64;
struct cvmx_asxx_rld_comp_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_9_63 : 55;
uint64_t pctl : 5; /**< PCTL Compensation Value
These bits reflect the computed compensation
values from the built-in compensation circuit. */
uint64_t nctl : 4; /**< These bits reflect the computed compensation
values from the built-in compensation circuit. */
#else
uint64_t nctl : 4;
uint64_t pctl : 5;
uint64_t reserved_9_63 : 55;
#endif
} s;
struct cvmx_asxx_rld_comp_cn38xx
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_8_63 : 56;
uint64_t pctl : 4; /**< These bits reflect the computed compensation
values from the built-in compensation circuit. */
uint64_t nctl : 4; /**< These bits reflect the computed compensation
values from the built-in compensation circuit. */
#else
uint64_t nctl : 4;
uint64_t pctl : 4;
uint64_t reserved_8_63 : 56;
#endif
} cn38xx;
struct cvmx_asxx_rld_comp_cn38xx cn38xxp2;
struct cvmx_asxx_rld_comp_s cn58xx;
struct cvmx_asxx_rld_comp_s cn58xxp1;
};
typedef union cvmx_asxx_rld_comp cvmx_asxx_rld_comp_t;
/**
* cvmx_asx#_rld_data_drv
*
* ASX_RLD_DATA_DRV
*
*/
union cvmx_asxx_rld_data_drv
{
uint64_t u64;
struct cvmx_asxx_rld_data_drv_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_8_63 : 56;
uint64_t pctl : 4; /**< These bits specify a driving strength (positive
integer) for the RLD I/Os when the built-in
compensation circuit is bypassed. */
uint64_t nctl : 4; /**< These bits specify a driving strength (positive
integer) for the RLD I/Os when the built-in
compensation circuit is bypassed. */
#else
uint64_t nctl : 4;
uint64_t pctl : 4;
uint64_t reserved_8_63 : 56;
#endif
} s;
struct cvmx_asxx_rld_data_drv_s cn38xx;
struct cvmx_asxx_rld_data_drv_s cn38xxp2;
struct cvmx_asxx_rld_data_drv_s cn58xx;
struct cvmx_asxx_rld_data_drv_s cn58xxp1;
};
typedef union cvmx_asxx_rld_data_drv cvmx_asxx_rld_data_drv_t;
/**
* cvmx_asx#_rld_fcram_mode
*
* ASX_RLD_FCRAM_MODE
*
*/
union cvmx_asxx_rld_fcram_mode
{
uint64_t u64;
struct cvmx_asxx_rld_fcram_mode_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_1_63 : 63;
uint64_t mode : 1; /**< Memory Mode
- 0: RLDRAM
- 1: FCRAM */
#else
uint64_t mode : 1;
uint64_t reserved_1_63 : 63;
#endif
} s;
struct cvmx_asxx_rld_fcram_mode_s cn38xx;
struct cvmx_asxx_rld_fcram_mode_s cn38xxp2;
};
typedef union cvmx_asxx_rld_fcram_mode cvmx_asxx_rld_fcram_mode_t;
/**
* cvmx_asx#_rld_nctl_strong
*
* ASX_RLD_NCTL_STRONG
*
*/
union cvmx_asxx_rld_nctl_strong
{
uint64_t u64;
struct cvmx_asxx_rld_nctl_strong_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_5_63 : 59;
uint64_t nctl : 5; /**< Duke's drive control */
#else
uint64_t nctl : 5;
uint64_t reserved_5_63 : 59;
#endif
} s;
struct cvmx_asxx_rld_nctl_strong_s cn38xx;
struct cvmx_asxx_rld_nctl_strong_s cn38xxp2;
struct cvmx_asxx_rld_nctl_strong_s cn58xx;
struct cvmx_asxx_rld_nctl_strong_s cn58xxp1;
};
typedef union cvmx_asxx_rld_nctl_strong cvmx_asxx_rld_nctl_strong_t;
/**
* cvmx_asx#_rld_nctl_weak
*
* ASX_RLD_NCTL_WEAK
*
*/
union cvmx_asxx_rld_nctl_weak
{
uint64_t u64;
struct cvmx_asxx_rld_nctl_weak_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_5_63 : 59;
uint64_t nctl : 5; /**< UNUSED (not needed for CN58XX) */
#else
uint64_t nctl : 5;
uint64_t reserved_5_63 : 59;
#endif
} s;
struct cvmx_asxx_rld_nctl_weak_s cn38xx;
struct cvmx_asxx_rld_nctl_weak_s cn38xxp2;
struct cvmx_asxx_rld_nctl_weak_s cn58xx;
struct cvmx_asxx_rld_nctl_weak_s cn58xxp1;
};
typedef union cvmx_asxx_rld_nctl_weak cvmx_asxx_rld_nctl_weak_t;
/**
* cvmx_asx#_rld_pctl_strong
*
* ASX_RLD_PCTL_STRONG
*
*/
union cvmx_asxx_rld_pctl_strong
{
uint64_t u64;
struct cvmx_asxx_rld_pctl_strong_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_5_63 : 59;
uint64_t pctl : 5; /**< Duke's drive control */
#else
uint64_t pctl : 5;
uint64_t reserved_5_63 : 59;
#endif
} s;
struct cvmx_asxx_rld_pctl_strong_s cn38xx;
struct cvmx_asxx_rld_pctl_strong_s cn38xxp2;
struct cvmx_asxx_rld_pctl_strong_s cn58xx;
struct cvmx_asxx_rld_pctl_strong_s cn58xxp1;
};
typedef union cvmx_asxx_rld_pctl_strong cvmx_asxx_rld_pctl_strong_t;
/**
* cvmx_asx#_rld_pctl_weak
*
* ASX_RLD_PCTL_WEAK
*
*/
union cvmx_asxx_rld_pctl_weak
{
uint64_t u64;
struct cvmx_asxx_rld_pctl_weak_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_5_63 : 59;
uint64_t pctl : 5; /**< UNUSED (not needed for CN58XX) */
#else
uint64_t pctl : 5;
uint64_t reserved_5_63 : 59;
#endif
} s;
struct cvmx_asxx_rld_pctl_weak_s cn38xx;
struct cvmx_asxx_rld_pctl_weak_s cn38xxp2;
struct cvmx_asxx_rld_pctl_weak_s cn58xx;
struct cvmx_asxx_rld_pctl_weak_s cn58xxp1;
};
typedef union cvmx_asxx_rld_pctl_weak cvmx_asxx_rld_pctl_weak_t;
/**
* cvmx_asx#_rld_setting
*
* ASX_RLD_SETTING
*
*/
union cvmx_asxx_rld_setting
{
uint64_t u64;
struct cvmx_asxx_rld_setting_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_13_63 : 51;
uint64_t dfaset : 5; /**< RLD ClkGen DLL Setting(debug) */
uint64_t dfalag : 1; /**< RLD ClkGen DLL Lag Error(debug) */
uint64_t dfalead : 1; /**< RLD ClkGen DLL Lead Error(debug) */
uint64_t dfalock : 1; /**< RLD ClkGen DLL Lock acquisition(debug) */
uint64_t setting : 5; /**< RLDCK90 DLL Setting(debug) */
#else
uint64_t setting : 5;
uint64_t dfalock : 1;
uint64_t dfalead : 1;
uint64_t dfalag : 1;
uint64_t dfaset : 5;
uint64_t reserved_13_63 : 51;
#endif
} s;
struct cvmx_asxx_rld_setting_cn38xx
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_5_63 : 59;
uint64_t setting : 5; /**< This is the read-only true rld dll_setting. */
#else
uint64_t setting : 5;
uint64_t reserved_5_63 : 59;
#endif
} cn38xx;
struct cvmx_asxx_rld_setting_cn38xx cn38xxp2;
struct cvmx_asxx_rld_setting_s cn58xx;
struct cvmx_asxx_rld_setting_s cn58xxp1;
};
typedef union cvmx_asxx_rld_setting cvmx_asxx_rld_setting_t;
/**
* cvmx_asx#_rx_clk_set#
*
* ASX_RX_CLK_SET = RGMII Clock delay setting
*
*
* Notes:
* Setting to place on the open-loop RXC (RGMII receive clk)
* delay line, which can delay the recieved clock. This
* can be used if the board and/or transmitting device
* has not otherwise delayed the clock.
*
* A value of SETTING=0 disables the delay line. The delay
* line should be disabled unless the transmitter or board
* does not delay the clock.
*
* Note that this delay line provides only a coarse control
* over the delay. Generally, it can only reliably provide
* a delay in the range 1.25-2.5ns, which may not be adequate
* for some system applications.
*
* The open loop delay line selects
* from among a series of tap positions. Each incremental
* tap position adds a delay of 50ps to 135ps per tap, depending
* on the chip, its temperature, and the voltage.
* To achieve from 1.25-2.5ns of delay on the recieved
* clock, a fixed value of SETTING=24 may work.
* For more precision, we recommend the following settings
* based on the chip voltage:
*
* VDD SETTING
* -----------------------------
* 1.0 18
* 1.05 19
* 1.1 21
* 1.15 22
* 1.2 23
* 1.25 24
* 1.3 25
*/
union cvmx_asxx_rx_clk_setx
{
uint64_t u64;
struct cvmx_asxx_rx_clk_setx_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_5_63 : 59;
uint64_t setting : 5; /**< Setting to place on the open-loop RXC delay line */
#else
uint64_t setting : 5;
uint64_t reserved_5_63 : 59;
#endif
} s;
struct cvmx_asxx_rx_clk_setx_s cn30xx;
struct cvmx_asxx_rx_clk_setx_s cn31xx;
struct cvmx_asxx_rx_clk_setx_s cn38xx;
struct cvmx_asxx_rx_clk_setx_s cn38xxp2;
struct cvmx_asxx_rx_clk_setx_s cn50xx;
struct cvmx_asxx_rx_clk_setx_s cn58xx;
struct cvmx_asxx_rx_clk_setx_s cn58xxp1;
};
typedef union cvmx_asxx_rx_clk_setx cvmx_asxx_rx_clk_setx_t;
/**
* cvmx_asx#_rx_prt_en
*
* ASX_RX_PRT_EN = RGMII Port Enable
*
*/
union cvmx_asxx_rx_prt_en
{
uint64_t u64;
struct cvmx_asxx_rx_prt_en_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_4_63 : 60;
uint64_t prt_en : 4; /**< Port enable. Must be set for Octane to receive
RMGII traffic. When this bit clear on a given
port, then the all RGMII cycles will appear as
inter-frame cycles. */
#else
uint64_t prt_en : 4;
uint64_t reserved_4_63 : 60;
#endif
} s;
struct cvmx_asxx_rx_prt_en_cn30xx
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_3_63 : 61;
uint64_t prt_en : 3; /**< Port enable. Must be set for Octane to receive
RMGII traffic. When this bit clear on a given
port, then the all RGMII cycles will appear as
inter-frame cycles. */
#else
uint64_t prt_en : 3;
uint64_t reserved_3_63 : 61;
#endif
} cn30xx;
struct cvmx_asxx_rx_prt_en_cn30xx cn31xx;
struct cvmx_asxx_rx_prt_en_s cn38xx;
struct cvmx_asxx_rx_prt_en_s cn38xxp2;
struct cvmx_asxx_rx_prt_en_cn30xx cn50xx;
struct cvmx_asxx_rx_prt_en_s cn58xx;
struct cvmx_asxx_rx_prt_en_s cn58xxp1;
};
typedef union cvmx_asxx_rx_prt_en cvmx_asxx_rx_prt_en_t;
/**
* cvmx_asx#_rx_wol
*
* ASX_RX_WOL = RGMII RX Wake on LAN status register
*
*/
union cvmx_asxx_rx_wol
{
uint64_t u64;
struct cvmx_asxx_rx_wol_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_2_63 : 62;
uint64_t status : 1; /**< Copy of PMCSR[15] - PME_status */
uint64_t enable : 1; /**< Copy of PMCSR[8] - PME_enable */
#else
uint64_t enable : 1;
uint64_t status : 1;
uint64_t reserved_2_63 : 62;
#endif
} s;
struct cvmx_asxx_rx_wol_s cn38xx;
struct cvmx_asxx_rx_wol_s cn38xxp2;
};
typedef union cvmx_asxx_rx_wol cvmx_asxx_rx_wol_t;
/**
* cvmx_asx#_rx_wol_msk
*
* ASX_RX_WOL_MSK = RGMII RX Wake on LAN byte mask
*
*/
union cvmx_asxx_rx_wol_msk
{
uint64_t u64;
struct cvmx_asxx_rx_wol_msk_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t msk : 64; /**< Bytes to include in the CRC signature */
#else
uint64_t msk : 64;
#endif
} s;
struct cvmx_asxx_rx_wol_msk_s cn38xx;
struct cvmx_asxx_rx_wol_msk_s cn38xxp2;
};
typedef union cvmx_asxx_rx_wol_msk cvmx_asxx_rx_wol_msk_t;
/**
* cvmx_asx#_rx_wol_powok
*
* ASX_RX_WOL_POWOK = RGMII RX Wake on LAN Power OK
*
*/
union cvmx_asxx_rx_wol_powok
{
uint64_t u64;
struct cvmx_asxx_rx_wol_powok_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_1_63 : 63;
uint64_t powerok : 1; /**< Power OK */
#else
uint64_t powerok : 1;
uint64_t reserved_1_63 : 63;
#endif
} s;
struct cvmx_asxx_rx_wol_powok_s cn38xx;
struct cvmx_asxx_rx_wol_powok_s cn38xxp2;
};
typedef union cvmx_asxx_rx_wol_powok cvmx_asxx_rx_wol_powok_t;
/**
* cvmx_asx#_rx_wol_sig
*
* ASX_RX_WOL_SIG = RGMII RX Wake on LAN CRC signature
*
*/
union cvmx_asxx_rx_wol_sig
{
uint64_t u64;
struct cvmx_asxx_rx_wol_sig_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_32_63 : 32;
uint64_t sig : 32; /**< CRC signature */
#else
uint64_t sig : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_asxx_rx_wol_sig_s cn38xx;
struct cvmx_asxx_rx_wol_sig_s cn38xxp2;
};
typedef union cvmx_asxx_rx_wol_sig cvmx_asxx_rx_wol_sig_t;
/**
* cvmx_asx#_tx_clk_set#
*
* ASX_TX_CLK_SET = RGMII Clock delay setting
*
*
* Notes:
* Setting to place on the open-loop TXC (RGMII transmit clk)
* delay line, which can delay the transmited clock. This
* can be used if the board and/or transmitting device
* has not otherwise delayed the clock.
*
* A value of SETTING=0 disables the delay line. The delay
* line should be disabled unless the transmitter or board
* does not delay the clock.
*
* Note that this delay line provides only a coarse control
* over the delay. Generally, it can only reliably provide
* a delay in the range 1.25-2.5ns, which may not be adequate
* for some system applications.
*
* The open loop delay line selects
* from among a series of tap positions. Each incremental
* tap position adds a delay of 50ps to 135ps per tap, depending
* on the chip, its temperature, and the voltage.
* To achieve from 1.25-2.5ns of delay on the recieved
* clock, a fixed value of SETTING=24 may work.
* For more precision, we recommend the following settings
* based on the chip voltage:
*
* VDD SETTING
* -----------------------------
* 1.0 18
* 1.05 19
* 1.1 21
* 1.15 22
* 1.2 23
* 1.25 24
* 1.3 25
*/
union cvmx_asxx_tx_clk_setx
{
uint64_t u64;
struct cvmx_asxx_tx_clk_setx_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_5_63 : 59;
uint64_t setting : 5; /**< Setting to place on the open-loop TXC delay line */
#else
uint64_t setting : 5;
uint64_t reserved_5_63 : 59;
#endif
} s;
struct cvmx_asxx_tx_clk_setx_s cn30xx;
struct cvmx_asxx_tx_clk_setx_s cn31xx;
struct cvmx_asxx_tx_clk_setx_s cn38xx;
struct cvmx_asxx_tx_clk_setx_s cn38xxp2;
struct cvmx_asxx_tx_clk_setx_s cn50xx;
struct cvmx_asxx_tx_clk_setx_s cn58xx;
struct cvmx_asxx_tx_clk_setx_s cn58xxp1;
};
typedef union cvmx_asxx_tx_clk_setx cvmx_asxx_tx_clk_setx_t;
/**
* cvmx_asx#_tx_comp_byp
*
* ASX_TX_COMP_BYP = RGMII Clock delay setting
*
*/
union cvmx_asxx_tx_comp_byp
{
uint64_t u64;
struct cvmx_asxx_tx_comp_byp_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_0_63 : 64;
#else
uint64_t reserved_0_63 : 64;
#endif
} s;
struct cvmx_asxx_tx_comp_byp_cn30xx
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_9_63 : 55;
uint64_t bypass : 1; /**< Compensation bypass */
uint64_t pctl : 4; /**< PCTL Compensation Value (see Duke) */
uint64_t nctl : 4; /**< NCTL Compensation Value (see Duke) */
#else
uint64_t nctl : 4;
uint64_t pctl : 4;
uint64_t bypass : 1;
uint64_t reserved_9_63 : 55;
#endif
} cn30xx;
struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx;
struct cvmx_asxx_tx_comp_byp_cn38xx
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_8_63 : 56;
uint64_t pctl : 4; /**< PCTL Compensation Value (see Duke) */
uint64_t nctl : 4; /**< NCTL Compensation Value (see Duke) */
#else
uint64_t nctl : 4;
uint64_t pctl : 4;
uint64_t reserved_8_63 : 56;
#endif
} cn38xx;
struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2;
struct cvmx_asxx_tx_comp_byp_cn50xx
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_17_63 : 47;
uint64_t bypass : 1; /**< Compensation bypass */
uint64_t reserved_13_15 : 3;
uint64_t pctl : 5; /**< PCTL Compensation Value (see Duke) */
uint64_t reserved_5_7 : 3;
uint64_t nctl : 5; /**< NCTL Compensation Value (see Duke) */
#else
uint64_t nctl : 5;
uint64_t reserved_5_7 : 3;
uint64_t pctl : 5;
uint64_t reserved_13_15 : 3;
uint64_t bypass : 1;
uint64_t reserved_17_63 : 47;
#endif
} cn50xx;
struct cvmx_asxx_tx_comp_byp_cn58xx
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_13_63 : 51;
uint64_t pctl : 5; /**< PCTL Compensation Value (see Duke) */
uint64_t reserved_5_7 : 3;
uint64_t nctl : 5; /**< NCTL Compensation Value (see Duke) */
#else
uint64_t nctl : 5;
uint64_t reserved_5_7 : 3;
uint64_t pctl : 5;
uint64_t reserved_13_63 : 51;
#endif
} cn58xx;
struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1;
};
typedef union cvmx_asxx_tx_comp_byp cvmx_asxx_tx_comp_byp_t;
/**
* cvmx_asx#_tx_hi_water#
*
* ASX_TX_HI_WATER = RGMII TX FIFO Hi WaterMark
*
*/
union cvmx_asxx_tx_hi_waterx
{
uint64_t u64;
struct cvmx_asxx_tx_hi_waterx_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_4_63 : 60;
uint64_t mark : 4; /**< TX FIFO HiWatermark to stall GMX
Value of 0 maps to 16
Reset value changed from 10 in pass1
Pass1 settings (assuming 125 tclk)
- 325-375: 12
- 375-437: 11
- 437-550: 10
- 550-687: 9 */
#else
uint64_t mark : 4;
uint64_t reserved_4_63 : 60;
#endif
} s;
struct cvmx_asxx_tx_hi_waterx_cn30xx
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_3_63 : 61;
uint64_t mark : 3; /**< TX FIFO HiWatermark to stall GMX
Value 0 maps to 8. */
#else
uint64_t mark : 3;
uint64_t reserved_3_63 : 61;
#endif
} cn30xx;
struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx;
struct cvmx_asxx_tx_hi_waterx_s cn38xx;
struct cvmx_asxx_tx_hi_waterx_s cn38xxp2;
struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx;
struct cvmx_asxx_tx_hi_waterx_s cn58xx;
struct cvmx_asxx_tx_hi_waterx_s cn58xxp1;
};
typedef union cvmx_asxx_tx_hi_waterx cvmx_asxx_tx_hi_waterx_t;
/**
* cvmx_asx#_tx_prt_en
*
* ASX_TX_PRT_EN = RGMII Port Enable
*
*/
union cvmx_asxx_tx_prt_en
{
uint64_t u64;
struct cvmx_asxx_tx_prt_en_s
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_4_63 : 60;
uint64_t prt_en : 4; /**< Port enable. Must be set for Octane to send
RMGII traffic. When this bit clear on a given
port, then all RGMII cycles will appear as
inter-frame cycles. */
#else
uint64_t prt_en : 4;
uint64_t reserved_4_63 : 60;
#endif
} s;
struct cvmx_asxx_tx_prt_en_cn30xx
{
#if __BYTE_ORDER == __BIG_ENDIAN
uint64_t reserved_3_63 : 61;
uint64_t prt_en : 3; /**< Port enable. Must be set for Octane to send
RMGII traffic. When this bit clear on a given
port, then all RGMII cycles will appear as
inter-frame cycles. */
#else
uint64_t prt_en : 3;
uint64_t reserved_3_63 : 61;
#endif
} cn30xx;
struct cvmx_asxx_tx_prt_en_cn30xx cn31xx;
struct cvmx_asxx_tx_prt_en_s cn38xx;
struct cvmx_asxx_tx_prt_en_s cn38xxp2;
struct cvmx_asxx_tx_prt_en_cn30xx cn50xx;
struct cvmx_asxx_tx_prt_en_s cn58xx;
struct cvmx_asxx_tx_prt_en_s cn58xxp1;
};
typedef union cvmx_asxx_tx_prt_en cvmx_asxx_tx_prt_en_t;
#endif
|