1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
|
/*-
* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
* All rights reserved.
*
* This software was developed by SRI International and the University of
* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
* ("CTSRD"), as part of the DARPA CRASH research programme.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/ {
compatible = "altr,socfpga";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&GIC>;
aliases {
soc = &SOC;
rstmgr = &rstmgr;
l3regs = &l3regs;
serial0 = &serial0;
serial1 = &serial1;
};
SOC: socfpga {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
bus-frequency = <0>;
GIC: interrupt-controller@fffed000 {
compatible = "arm,gic";
reg = < 0xfffed000 0x1000 >, /* Distributor */
< 0xfffec100 0x100 >; /* CPU Interface */
interrupt-controller;
#interrupt-cells = <1>;
};
mp_tmr@40002100 {
compatible = "arm,mpcore-timers";
clock-frequency = <200000000>;
#address-cells = <1>;
#size-cells = <0>;
reg = < 0xfffec200 0x100 >, /* Global Timer */
< 0xfffec600 0x100 >; /* Private Timer */
interrupts = < 27 29 >;
interrupt-parent = < &GIC >;
};
sysmgr: sysmgr@ffd08000 {
compatible = "altr,sys-mgr";
reg = <0xffd08000 0x1000>;
};
clkmgr: clkmgr@ffd04000 {
compatible = "altr,clk-mgr";
reg = <0xffd04000 0x1000>;
};
rstmgr: rstmgr@ffd05000 {
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
};
l3regs: l3regs@ff800000 {
compatible = "altr,l3regs";
reg = <0xff800000 0x1000>;
};
fpgamgr: fpgamgr@ff706000 {
compatible = "altr,fpga-mgr";
reg = <0xff706000 0x1000>, /* FPGAMGRREGS */
<0xffb90000 0x1000>; /* FPGAMGRDATA */
interrupts = < 207 >;
interrupt-parent = <&GIC>;
};
gpio0: gpio@ff708000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff708000 0x1000>;
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
snps,nr-gpios = <29>;
};
};
gpio1: gpio@ff709000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff709000 0x1000>;
portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
snps,nr-gpios = <29>;
};
};
gpio2: gpio@ff70a000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff70a000 0x1000>;
portc: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
snps,nr-gpios = <27>;
};
};
serial0: serial@ffc02000 {
compatible = "ns16550";
reg = <0xffc02000 0x1000>;
reg-shift = <2>;
interrupts = <194>;
interrupt-parent = <&GIC>;
current-speed = <115200>;
clock-frequency = < 100000000 >;
status = "disabled";
};
serial1: serial@ffc03000 {
compatible = "ns16550";
reg = <0xffc03000 0x1000>;
reg-shift = <2>;
interrupts = <195>;
interrupt-parent = <&GIC>;
current-speed = <115200>;
clock-frequency = < 100000000 >;
status = "disabled";
};
usb0: usb@ffb00000 {
compatible = "synopsys,designware-hs-otg2";
reg = <0xffb00000 0xffff>;
interrupts = <157>;
interrupt-parent = <&GIC>;
status = "disabled";
};
usb1: usb@ffb40000 {
compatible = "synopsys,designware-hs-otg2";
reg = <0xffb40000 0xffff>;
interrupts = <160>;
interrupt-parent = <&GIC>;
dr_mode = "host";
status = "disabled";
};
gmac0: ethernet@ff700000 {
compatible = "altr,socfpga-stmmac",
"snps,dwmac-3.70a", "snps,dwmac";
reg = <0xff700000 0x2000>;
interrupts = <147>;
interrupt-parent = <&GIC>;
phy-mode = "rgmii";
status = "disabled";
};
gmac1: ethernet@ff702000 {
compatible = "altr,socfpga-stmmac",
"snps,dwmac-3.70a", "snps,dwmac";
reg = <0xff702000 0x2000>;
interrupts = <152>;
interrupt-parent = <&GIC>;
phy-mode = "rgmii";
status = "disabled";
};
mmc: dwmmc@ff704000 {
compatible = "altr,socfpga-dw-mshc";
reg = <0xff704000 0x1000>;
interrupts = <171>;
interrupt-parent = <&GIC>;
fifo-depth = <0x400>;
status = "disabled";
};
};
};
|