path: root/sys/arm/freescale/imx/imx6_iomuxreg.h

/*-
 * Copyright (c) 2014 Boris Samorodov <bsam@FreeBSD.org>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * $FreeBSD$
 */

/*
 * Pad                            : pin ("pin" is used at electric schemes,
 *                                  while at HW SOC it's named "pad").
 * Drive strength                 : the current that can be drawn with
 *                                  appropriate voltage (varies inversely with
 *                                  the supply impedance of the output pin).
 * Drive strength enable (DSE)    : The value of the current the pin uses.
 * HiZ (HYZ)                      : high input impedance value.
 * Daisy chain (DAISY)            : the one after another interconnection of
 *                                  devices.
 * On die termination (ODT)       : the termination resistor for impedance
 *                                  matching.
 * Software input on (SION)       : the value to force the pin to be an input
 *                                  one (i.e. to force the pin state reading).
 * Hysteresis (HYS)               : Controls if the value of the input pin
 *                                  remains the same until a sufficient change
 *                                  is applied.
 * Slow rate enable (SRE)         : How slow the pin value changes (slow rate
 *                                  saves power).
 * Open drain enable (ODE)        : If the input pin drains on low input or
 *                                  goes down.
 * Pull/keep enable (PKE)         : Enables pull/keep functionality.
 * PUll/keep select (PUE)         : Selects if the pin is pullup/pulldown one
 *                                  or remains it's previous role.
 *                                  A note: I'm not sure why it's not PKS...
 * Pullup (Pic.1)/pulldown (Pic.2): the pin's resistor connected to VCC (GND)
 *                                  to prevent random value drai.
 * Pullup/pulldown select (PUS)   : Selects the value of pullup/pulldown
 *                                  resistor.
 * Open drain (Pic.3)             : the output signal is applied to the base
 *                                  of a transistor whose collector is used
 *                                  as a pin.
 *
 * VCC o                VCC o                                 Open drain
 *     |                    |                             ---->  pin
 *    +++                   o|                           /
 *    | | R                  | Switch                   /
 *    +++  pullup           o|                      .---.
 *     |                    |                      / |/  \
 * >---+------> Pin     >---+------> Pin      >---{--|    )
 *     |                    |                      \ |\  /
 *     o|                  +++                      `--v'
 *      | Switch           | | R                        \
 *     o|                  +++  pulldown                 |
 *     |                    |                            |
 *   -----                -----                        -----
 *    ---                  ---                          ---
 *     -                    -                            -
 *
 *   Pic.1                Pic.2                        Pic.3
 */

#ifndef	IMX6_IOMUXREG_H
#define	IMX6_IOMUXREG_H

/*
 * Multiplex control
 */
#define	IOMUXC_MUX_CTL		0x004c
#define	IOMUX_CONFIG_SION	(1<<4)
#define	IOMUX_CONFIG_ALT0	0
#define	IOMUX_CONFIG_ALT1	1
#define	IOMUX_CONFIG_ALT2	2
#define	IOMUX_CONFIG_ALT3	3
#define	IOMUX_CONFIG_ALT4	4
#define	IOMUX_CONFIG_ALT5	5
#define	IOMUX_CONFIG_ALT6	6
#define	IOMUX_CONFIG_ALT7	7

/*
 * Pad control
 */
#define	IOMUXC_PAD_CTL		0x0360
						/* DDR Select Field */
#define	PAD_CTL_DDR_SEL_0	(0x0<<18)
#define	PAD_CTL_DDR_SEL_1	(0x1<<18)
#define	PAD_CTL_DDR_SEL_2	(0x2<<18)
#define	PAD_CTL_DDR_SEL_3	(0x3<<18)
#define	PAD_CTL_DDR_INPUT	(0x1<<17)	/* DDR/CMOS Input Mode Field */
#define	PAD_CTL_HYS		(1<<16)		/* Hysteresis Enable Field */
						/* PullUp/Down Config Field: */
#define	PAD_CTL_PUS_100K_PD	(0x0<<14)	/*   100K Ohm Pull Down */
#define	PAD_CTL_PUS_47K_PU	(0x1<<14)	/*   47K Ohn Pull Up */
#define	PAD_CTL_PUS_100K_PU	(0x2<<14)	/*   100K Ohm Pull Up */
#define	PAD_CTL_PUS_22K_PU	(0x3<<14)	/*   22K Ohm Pull Up */
#define	PAD_CTL_PUE		(1<<13)		/* Pull/Keep Select Field */
#define	PAD_CTL_PKE		(1<<12)		/* Pull/Keep Enable Field */
#define	PAD_CTL_ODE		(1<<11)		/* Open Drain Enable Field */
						/* On Die Termination Field: */
#define	PAD_CTL_ODT_DISABLED	(0x0<<8)	/*   Disabled */
#define	PAD_CTL_ODT_1		(0x1<<8)
#define	PAD_CTL_ODT_2		(0x2<<8)
#define	PAD_CTL_ODT_3		(0x3<<8)
#define	PAD_CTL_ODT_4		(0x4<<8)
#define	PAD_CTL_ODT_5		(0x5<<8)
#define	PAD_CTL_ODT_6		(0x6<<8)
#define	PAD_CTL_ODT_7		(0x7<<8)
						/* Speed Field: */
#define	PAD_CTL_SPEED_RESERVED0	(0x0<<6)	/*   RESERVED */
#define	PAD_CTL_SPEED_50_MHZ	(0x1<<6)	/*   50 MHz */
#define	PAD_CTL_SPEED_100_MHZ	(0x2<<6)	/*   100 MHz */
#define	PAD_CTL_SPEED_200_MHZ	(0x3<<6)	/*   200 MHz */
						/* Drive Strength Field */
#define	PAD_CTL_DSE_HIZ		(0x0<<3)	/*   HI-Z */
#define	PAD_CTL_DSE_1		(0x1<<3)
#define	PAD_CTL_DSE_2		(0x2<<3)
#define	PAD_CTL_DSE_3		(0x3<<3)
#define	PAD_CTL_DSE_4		(0x4<<3)
#define	PAD_CTL_DSE_5		(0x5<<3)
#define	PAD_CTL_DSE_6		(0x6<<3)
#define	PAD_CTL_DSE_7		(0x7<<3)
#define	PAD_CTL_SRE		(0x1<<0)	/* Slew rate Field */

/*
 * Input control
 */
#define	IOMUXC_INPUT_CTL	0x07b0			/* input control */
#define	INPUT_DAISY_0		0
#define	INPUT_DAISY_1		1
#define	INPUT_DAISY_2		2
#define	INPUT_DAISY_3		3
#define	INPUT_DAISY_4		4
#define	INPUT_DAISY_5		5
#define	INPUT_DAISY_6		6
#define	INPUT_DAISY_7		7

/*
 * IOMUX index
 */
#define	IOMUX_PIN_TO_MUX_ADDRESS(pin)	  (((pin) >> 16) & 0xffff)
#define	IOMUX_PIN_TO_PAD_ADDRESS(pin)	  (((pin) >>  0) & 0xffff)
#define	IOMUX_PIN(mux_adr, pad_adr) \
	(((mux_adr) << 16) | (((pad_adr) << 0)))
#define	IOMUX_MUX_NONE	 0xffff
#define	IOMUX_PAD_NONE	 0xffff

/*
 * MUX & PAD Control
 */
#define MUX_PIN(name) \
	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_##name, \
	    IOMUXC_SW_PAD_CTL_PAD_##name)

#define MUX_PIN_MUX(name) \
	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_##name, IOMUX_PAD_NONE)

#define MUX_PIN_PAD(name) \
	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_##name)

#define MUX_PIN_GRP(name) \
	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_GRP_##name)

#define MUX_PIN_PATH(name) \
	IOMUX_PIN(IOMUXC_##name##_SELECT_INPUT, IOMUX_MUX_NONE)

/*
 * INPUT Control
 */
#define MUX_SELECT(name) (name##_SELECT_INPUT)

/*
 * Register names, offset addresses (and reset values for reference)
 * from Chapter 36 IOMUX Controller (IOMUXC), IMX6DQRM, Rev.1, 04/2013
 *
 * General Purpose Registers
 */
#define IOMUXC_GPR0					0x0000	/* 0x00000000 */
#define IOMUXC_GPR1					0x0004	/* 0x48400005 */
#define IOMUXC_GPR2					0x0008	/* 0x00000000 */
#define IOMUXC_GPR3					0x000c	/* 0x01e00000 */
#define IOMUXC_GPR4					0x0010	/* 0x00000000 */
#define IOMUXC_GPR5					0x0014	/* 0x00000000 */
#define IOMUXC_GPR6					0x0018	/* 0x22222222 */
#define IOMUXC_GPR7					0x001c	/* 0x22222222 */
#define IOMUXC_GPR8					0x0020	/* 0x00000000 */
#define IOMUXC_GPR9					0x0024	/* 0x00000000 */
#define IOMUXC_GPR10					0x0028	/* 0x00003800 */
#define IOMUXC_GPR11					0x002c	/* 0x00003800 */
#define IOMUXC_GPR12					0x0030	/* 0x0f000000 */
#define IOMUXC_GPR13					0x0034	/* 0x059124c4 */
/*
 * Pad Mux Registers
 */
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1			0x004c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2			0x0050	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0			0x0054	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC			0x0058	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0			0x005c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1			0x0060	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2			0x0064	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3			0x0068	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL		0x006c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0			0x0070	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL		0x0074	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1			0x0078	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2			0x007c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3			0x0080	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC			0x0084	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25		0x0088	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_B			0x008c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16		0x0090	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17		0x0094	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18		0x0098	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19		0x009c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20		0x00a0	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21		0x00a4	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22		0x00a8	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23		0x00ac	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_B			0x00b0	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24		0x00b4	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25		0x00b8	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26		0x00bc	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27		0x00c0	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28		0x00c4	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29		0x00c8	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30		0x00cc	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31		0x00d0	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24		0x00d4	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23		0x00d8	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22		0x00dc	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21		0x00e0	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20		0x00e4	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19		0x00e8	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18		0x00ec	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17		0x00f0	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16		0x00f4	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B			0x00f8	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_B			0x00fc	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B			0x0100	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_RW			0x0104	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B			0x0108	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_B			0x010c	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_B			0x0110	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD00			0x0114	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD01			0x0118	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD02			0x011c	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD03			0x0120	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD04			0x0124	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD05			0x0128	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD06			0x012c	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD07			0x0130	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD08			0x0134	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD09			0x0138	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD10			0x013c	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD11			0x0140	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD12			0x0144	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD13			0x0148	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD14			0x014c	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD15			0x0150	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B		0x0154	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK			0x0158	/* 0x00000000 */
#define IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK		0x015c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15			0x0160	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02			0x0164	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03			0x0168	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04			0x016c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00		0x0170	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01		0x0174	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02		0x0178	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03		0x017c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04		0x0180	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05		0x0184	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06		0x0188	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07		0x018c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08		0x0190	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09		0x0194	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10		0x0198	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11		0x019c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12		0x01a0	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13		0x01a4	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14		0x01a8	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15		0x01ac	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16		0x01b0	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17		0x01b4	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18		0x01b8	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19		0x01bc	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20		0x01c0	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21		0x01c4	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22		0x01c8	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23		0x01cc	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO			0x01d0	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK		0x01d4	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER		0x01d8	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV		0x01dc	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1		0x01e0	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0		0x01e4	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN		0x01e8	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1		0x01ec	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0		0x01f0	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_ENET_MDC			0x01f4	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0			0x01f8	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0			0x01fc	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1			0x0200	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1			0x0204	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2			0x0208	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2			0x020c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3			0x0210	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3			0x0214	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4			0x0218	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4			0x021c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_GPIO00			0x0220	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_GPIO01			0x0224	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_GPIO09			0x0228	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_GPIO03			0x022c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_GPIO06			0x0230	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_GPIO02			0x0234	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_GPIO04			0x0238	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_GPIO05			0x023c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_GPIO07			0x0240	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_GPIO08			0x0244	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_GPIO16			0x0248	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_GPIO17			0x024c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_GPIO18			0x0250	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_GPIO19			0x0254	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK		0x0258	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC		0x025c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN		0x0260	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC		0x0264	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04		0x0268	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05		0x026c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06		0x0270	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07		0x0274	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08		0x0278	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09		0x027c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10		0x0280	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11		0x0284	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12		0x0288	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13		0x028c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14		0x0290	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15		0x0294	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16		0x0298	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17		0x029c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18		0x02a0	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19		0x02a4	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7			0x02a8	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6			0x02ac	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5			0x02b0	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4			0x02b4	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD			0x02b8	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK			0x02bc	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0			0x02c0	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1			0x02c4	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2			0x02c8	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3			0x02cc	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET			0x02d0	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE			0x02d4	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE			0x02d8	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B			0x02dc	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B		0x02e0	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B		0x02e4	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B		0x02e8	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B		0x02ec	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B		0x02f0	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD			0x02f4	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK			0x02f8	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00		0x02fc	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01		0x0300	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02		0x0304	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03		0x0308	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04		0x030c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05		0x0310	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06		0x0314	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07		0x0318	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0			0x031c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1			0x0320	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2			0x0324	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3			0x0328	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4			0x032c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5			0x0330	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6			0x0334	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7			0x0338	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1			0x033c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0			0x0340	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3			0x0344	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD			0x0348	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2			0x034c	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK			0x0350	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK			0x0354	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD			0x0358	/* 0x00000005 */
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3			0x035c	/* 0x00000005 */
/*
 * Pad Control registers
 */
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1			0x0360	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2			0x0364	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0			0x0368	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC			0x036c	/* 0x00013030 */
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0			0x0370	/* 0x0001b030 */
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1			0x0374	/* 0x0001b030 */
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2			0x0378	/* 0x0001b030 */
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3			0x037c	/* 0x0001b030 */
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL		0x0380	/* 0x00013030 */
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0			0x0384	/* 0x0001b030 */
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL		0x0388	/* 0x00013030 */
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1			0x038c	/* 0x0001b030 */
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2			0x0390	/* 0x0001b030 */
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3			0x0394	/* 0x0001b030 */
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC			0x0398	/* 0x00013030 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25		0x039c	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_B			0x03a0	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16		0x03a4	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17		0x03a8	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18		0x03ac	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19		0x03b0	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20		0x03b4	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21		0x03b8	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22		0x03bc	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23		0x03c0	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_B			0x03c4	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24		0x03c8	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25		0x03cc	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26		0x03d0	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27		0x03d4	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28		0x03d8	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29		0x03dc	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30		0x03e0	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31		0x03e4	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24		0x03e8	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23		0x03ec	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22		0x03f0	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21		0x03f4	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20		0x03f8	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19		0x03fc	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18		0x0400	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17		0x0404	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16		0x0408	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_B			0x040c	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_B			0x0410	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_OE_B			0x0414	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_RW			0x0418	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_B			0x041c	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_B			0x0420	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_B			0x0424	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD00			0x0428	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD01			0x042c	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD02			0x0430	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD03			0x0434	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD04			0x0438	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD05			0x043c	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD06			0x0440	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD07			0x0444	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD08			0x0448	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD09			0x044c	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD10			0x0450	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD11			0x0454	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD12			0x0458	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD13			0x045c	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD14			0x0460	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD15			0x0464	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_B		0x0468	/* 0x0000b060 */
#define IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK			0x046c	/* 0x0000b0b1 */
#define IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK		0x0470	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15			0x0474	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02			0x0478	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03			0x047c	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04			0x0480	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00		0x0484	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01		0x0488	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02		0x048c	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03		0x0490	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04		0x0494	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05		0x0498	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06		0x049c	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07		0x04a0	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08		0x04a4	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09		0x04a8	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10		0x04ac	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11		0x04b0	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12		0x04b4	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13		0x04b8	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14		0x04bc	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15		0x04c0	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16		0x04c4	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17		0x04c8	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18		0x04cc	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19		0x04d0	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20		0x04d4	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21		0x04d8	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22		0x04dc	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23		0x04e0	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO			0x04e4	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK		0x04e8	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER		0x04ec	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV		0x04f0	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1		0x04f4	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0		0x04f8	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN		0x04fc	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1		0x0500	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0		0x0504	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_ENET_MDC			0x0508	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P		0x050c	/* 0x00002030 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5			0x0510	/* 0x00008030 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4			0x0514	/* 0x00008030 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P		0x0518	/* 0x00002030 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P		0x051c	/* 0x00002030 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3			0x0520	/* 0x00008030 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P		0x0524	/* 0x00002030 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2			0x0528	/* 0x00008030 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00		0x052c	/* 0x00008000 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01		0x0530	/* 0x00008000 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02		0x0534	/* 0x00008000 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03		0x0538	/* 0x00008000 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04		0x053c	/* 0x00008000 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05		0x0540	/* 0x00008000 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06		0x0544	/* 0x00008000 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07		0x0548	/* 0x00008000 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08		0x054c	/* 0x00008000 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09		0x0550	/* 0x00008000 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10		0x0554	/* 0x00008000 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11		0x0558	/* 0x00008000 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12		0x055c	/* 0x00008000 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13		0x0560	/* 0x00008000 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14		0x0564	/* 0x00008000 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15		0x0568	/* 0x00008000 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B		0x056c	/* 0x00008030 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B		0x0570	/* 0x00008000 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B		0x0574	/* 0x00008000 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B		0x0578	/* 0x00008030 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET		0x057c	/* 0x00083030 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0		0x0580	/* 0x00008000 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1		0x0584	/* 0x00008000 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P		0x0588	/* 0x00008030 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2		0x058c	/* 0x0000b000 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0		0x0590	/* 0x00003000 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P		0x0594	/* 0x00008030 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1		0x0598	/* 0x00003000 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0			0x059c	/* 0x00003030 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1			0x05a0	/* 0x00003030 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B		0x05a4	/* 0x00008000 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P		0x05a8	/* 0x00002030 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0			0x05ac	/* 0x00008030 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P		0x05b0	/* 0x00002030 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1			0x05b4	/* 0x00008030 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P		0x05b8	/* 0x00002030 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6			0x05bc	/* 0x00008030 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P		0x05c0	/* 0x00002030 */
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7			0x05c4	/* 0x00008030 */
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0			0x05c8	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0			0x05cc	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1			0x05d0	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1			0x05d4	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2			0x05d8	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2			0x05dc	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3			0x05e0	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3			0x05e4	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4			0x05e8	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4			0x05ec	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_GPIO00			0x05f0	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_GPIO01			0x05f4	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_GPIO09			0x05f8	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_GPIO03			0x05fc	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_GPIO06			0x0600	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_GPIO02			0x0604	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_GPIO04			0x0608	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_GPIO05			0x060c	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_GPIO07			0x0610	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_GPIO08			0x0614	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_GPIO16			0x0618	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_GPIO17			0x061c	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_GPIO18			0x0620	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_GPIO19			0x0624	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK		0x0628	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC		0x062c	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN		0x0630	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC		0x0634	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04		0x0638	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05		0x063c	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06		0x0640	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07		0x0644	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08		0x0648	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09		0x064c	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10		0x0650	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11		0x0654	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12		0x0658	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13		0x065c	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14		0x0660	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15		0x0664	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16		0x0668	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17		0x066c	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18		0x0670	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19		0x0674	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS			0x0678	/* 0x00007060 */
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD			0x067c	/* 0x0000b060 */
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB		0x0680	/* 0x00007060 */
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI			0x0684	/* 0x00007060 */
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK			0x0688	/* 0x00007060 */
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO			0x068c	/* 0x000090b1 */
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7			0x0690	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6			0x0694	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5			0x0698	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4			0x069c	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD			0x06a0	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK			0x06a4	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0			0x06a8	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1			0x06ac	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2			0x06b0	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3			0x06b4	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET			0x06b8	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE			0x06bc	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE			0x06c0	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B			0x06c4	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B		0x06c8	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B		0x06cc	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B		0x06d0	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B		0x06d4	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B		0x06d8	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD			0x06dc	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK			0x06e0	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00		0x06e4	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01		0x06e8	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02		0x06ec	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03		0x06f0	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04		0x06f4	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05		0x06f8	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06		0x06fc	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07		0x0700	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0			0x0704	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1			0x0708	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2			0x070c	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3			0x0710	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4			0x0714	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5			0x0718	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6			0x071c	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7			0x0720	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1			0x0724	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0			0x0728	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3			0x072c	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD			0x0730	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2			0x0734	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK			0x0738	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK			0x073c	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD			0x0740	/* 0x0001b0b0 */
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3			0x0744	/* 0x0001b0b0 */
/*
 * Pad Group Control Registers
 */
#define IOMUXC_SW_PAD_CTL_GRP_B7DS			0x0748	/* 0x00000030 */
#define IOMUXC_SW_PAD_CTL_GRP_ADDDS			0x074c	/* 0x00000030 */
#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL		0x0750	/* 0x00000000 */
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0			0x0754	/* 0x00000000 */
#define IOMUXC_SW_PAD_CTL_GRP_DDRPKE			0x0758	/* 0x00001000 */
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1			0x075c	/* 0x00000000 */
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2			0x0760	/* 0x00000000 */
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3			0x0764	/* 0x00000000 */
#define IOMUXC_SW_PAD_CTL_GRP_DDRPK			0x0768	/* 0x00002000 */
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4			0x076c	/* 0x00000000 */
#define IOMUXC_SW_PAD_CTL_GRP_DDRHYS			0x0770	/* 0x00000000 */
#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE			0x0774	/* 0x00000000 */
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5			0x0778	/* 0x00000000 */
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6			0x077c	/* 0x00000000 */
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7			0x0780	/* 0x00000000 */
#define IOMUXC_SW_PAD_CTL_GRP_B0DS			0x0784	/* 0x00000030 */
#define IOMUXC_SW_PAD_CTL_GRP_B1DS			0x0788	/* 0x00000030 */
#define IOMUXC_SW_PAD_CTL_GRP_CTLDS			0x078c	/* 0x00000030 */
#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII		0x0790	/* 0x00080000 */
#define IOMUXC_SW_PAD_CTL_GRP_B2DS			0x0794	/* 0x00000030 */
#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE			0x0798	/* 0x00080000 */
#define IOMUXC_SW_PAD_CTL_GRP_B3DS			0x079c	/* 0x00000030 */
#define IOMUXC_SW_PAD_CTL_GRP_B4DS			0x07a0	/* 0x00000030 */
#define IOMUXC_SW_PAD_CTL_GRP_B5DS			0x07a4	/* 0x00000030 */
#define IOMUXC_SW_PAD_CTL_GRP_B6DS			0x07a8	/* 0x00000030 */
#define IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM		0x07ac	/* 0x00000000 */
/*
 * Select Input Registers
 */
#define IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT		0x07b0	/* 0x00000000 */
#define IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT		0x07b4	/* 0x00000000 */
#define IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT		0x07b8	/* 0x00000000 */
#define IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT	0x07bc	/* 0x00000000 */
#define IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT		0x07c0	/* 0x00000000 */
#define IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT	0x07c4	/* 0x00000000 */
#define IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT		0x07c8	/* 0x00000000 */
#define IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT		0x07cc	/* 0x00000000 */
#define IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT		0x07d0	/* 0x00000000 */
#define IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT	0x07d4	/* 0x00000000 */
#define IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT		0x07d8	/* 0x00000000 */
#define IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT	0x07dc	/* 0x00000000 */
#define IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT		0x07e0	/* 0x00000000 */
#define IOMUXC_FLEXCAN1_RX_SELECT_INPUT			0x07e4	/* 0x00000000 */
#define IOMUXC_FLEXCAN2_RX_SELECT_INPUT			0x07e8	/* 0x00000000 */
#define IOMUXC_CCM_PMIC_READY_SELECT_INPUT		0x07f0	/* 0x00000000 */
#define IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT		0x07f4	/* 0x00000000 */
#define IOMUXC_ECSPI1_MISO_SELECT_INPUT			0x07f8	/* 0x00000000 */
#define IOMUXC_ECSPI1_MOSI_SELECT_INPUT			0x07fc	/* 0x00000000 */
#define IOMUXC_ECSPI1_SS0_SELECT_INPUT			0x0800	/* 0x00000000 */
#define IOMUXC_ECSPI1_SS1_SELECT_INPUT			0x0804	/* 0x00000000 */
#define IOMUXC_ECSPI1_SS2_SELECT_INPUT			0x0808	/* 0x00000000 */
#define IOMUXC_ECSPI1_SS3_SELECT_INPUT			0x080c	/* 0x00000000 */
#define IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT		0x0810	/* 0x00000000 */
#define IOMUXC_ECSPI2_MISO_SELECT_INPUT			0x0814	/* 0x00000000 */
#define IOMUXC_ECSPI2_MOSI_SELECT_INPUT			0x0818	/* 0x00000000 */
#define IOMUXC_ECSPI2_SS0_SELECT_INPUT			0x081c	/* 0x00000000 */
#define IOMUXC_ECSPI2_SS1_SELECT_INPUT			0x0820	/* 0x00000000 */
#define IOMUXC_ECSPI4_SS0_SELECT_INPUT			0x0824	/* 0x00000000 */
#define IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT		0x0828	/* 0x00000000 */
#define IOMUXC_ECSPI5_MISO_SELECT_INPUT			0x082c	/* 0x00000000 */
#define IOMUXC_ECSPI5_MOSI_SELECT_INPUT			0x0830	/* 0x00000000 */
#define IOMUXC_ECSPI5_SS0_SELECT_INPUT			0x0834	/* 0x00000000 */
#define IOMUXC_ECSPI5_SS1_SELECT_INPUT			0x0838	/* 0x00000000 */
#define IOMUXC_ENET_REF_CLK_SELECT_INPUT		0x083c	/* 0x00000000 */
#define IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT		0x0840	/* 0x00000000 */
#define IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT		0x0844	/* 0x00000000 */
#define IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT		0x0848	/* 0x00000000 */
#define IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT		0x084c	/* 0x00000000 */
#define IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT		0x0850	/* 0x00000000 */
#define IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT		0x0854	/* 0x00000000 */
#define IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT		0x0858	/* 0x00000000 */
#define IOMUXC_ESAI_RX_FS_SELECT_INPUT			0x085c	/* 0x00000000 */
#define IOMUXC_ESAI_TX_FS_SELECT_INPUT			0x0860	/* 0x00000000 */
#define IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT		0x0864	/* 0x00000000 */
#define IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT		0x0868	/* 0x00000000 */
#define IOMUXC_ESAI_RX_CLK_SELECT_INPUT			0x086c	/* 0x00000000 */
#define IOMUXC_ESAI_TX_CLK_SELECT_INPUT			0x0870	/* 0x00000000 */
#define IOMUXC_ESAI_SDO0_SELECT_INPUT			0x0874	/* 0x00000000 */
#define IOMUXC_ESAI_SDO1_SELECT_INPUT			0x0878	/* 0x00000000 */
#define IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT		0x087c	/* 0x00000000 */
#define IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT		0x0880	/* 0x00000000 */
#define IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT		0x0884	/* 0x00000000 */
#define IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT		0x0888	/* 0x00000000 */
#define IOMUXC_HDMI_ICECIN_SELECT_INPUT			0x088c	/* 0x00000000 */
#define IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT		0x0890	/* 0x00000000 */
#define IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT		0x0894	/* 0x00000000 */
#define IOMUXC_I2C1_SCL_IN_SELECT_INPUT			0x0898	/* 0x00000000 */
#define IOMUXC_I2C1_SDA_IN_SELECT_INPUT			0x089c	/* 0x00000000 */
#define IOMUXC_I2C2_SCL_IN_SELECT_INPUT			0x08a0	/* 0x00000000 */
#define IOMUXC_I2C2_SDA_IN_SELECT_INPUT			0x08a4	/* 0x00000000 */
#define IOMUXC_I2C3_SCL_IN_SELECT_INPUT			0x08a8	/* 0x00000000 */
#define IOMUXC_I2C3_SDA_IN_SELECT_INPUT			0x08ac	/* 0x00000000 */
#define IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT		0x08b0	/* 0x00000000 */
#define IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT		0x08b4	/* 0x00000000 */
#define IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT		0x08b8	/* 0x00000000 */
#define IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT		0x08bc	/* 0x00000000 */
#define IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT		0x08c0	/* 0x00000000 */
#define IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT		0x08c4	/* 0x00000000 */
#define IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT		0x08c8	/* 0x00000000 */
#define IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT		0x08cc	/* 0x00000000 */
#define IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT		0x08d0	/* 0x00000000 */
#define IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT		0x08d4	/* 0x00000000 */
#define IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT		0x08d8	/* 0x00000000 */
#define IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT		0x08dc	/* 0x00000000 */
#define IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT		0x08e0	/* 0x00000000 */
#define IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT		0x08e4	/* 0x00000000 */
#define IOMUXC_KEY_COL5_SELECT_INPUT			0x08e8	/* 0x00000000 */
#define IOMUXC_KEY_COL6_SELECT_INPUT			0x08ec	/* 0x00000000 */
#define IOMUXC_KEY_COL7_SELECT_INPUT			0x08f0	/* 0x00000000 */
#define IOMUXC_KEY_ROW5_SELECT_INPUT			0x08f4	/* 0x00000000 */
#define IOMUXC_KEY_ROW6_SELECT_INPUT			0x08f8	/* 0x00000000 */
#define IOMUXC_KEY_ROW7_SELECT_INPUT			0x08fc	/* 0x00000000 */
#define IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT		0x0900	/* 0x00000000 */
#define IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT		0x0904	/* 0x00000000 */
#define IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT		0x0908	/* 0x00000000 */
#define IOMUXC_SDMA_EVENTS14_SELECT_INPUT		0x090c	/* 0x00000000 */
#define IOMUXC_SDMA_EVENTS15_SELECT_INPUT		0x0910	/* 0x00000000 */
#define IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT		0x0914	/* 0x00000000 */
#define IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT		0x0918	/* 0x00000000 */
#define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT		0x091c	/* 0x00000000 */
#define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT		0x0920	/* 0x00000000 */
#define IOMUXC_UART2_UART_RTS_B_SELECT_INPUT		0x0924	/* 0x00000000 */
#define IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT		0x0928	/* 0x00000000 */
#define IOMUXC_UART3_UART_RTS_B_SELECT_INPUT		0x092c	/* 0x00000000 */
#define IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT		0x0930	/* 0x00000000 */
#define IOMUXC_UART4_UART_RTS_B_SELECT_INPUT		0x0934	/* 0x00000000 */
#define IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT		0x0938	/* 0x00000000 */
#define IOMUXC_UART5_UART_RTS_B_SELECT_INPUT		0x093c	/* 0x00000000 */
#define IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT		0x0940	/* 0x00000000 */
#define IOMUXC_USB_OTG_OC_SELECT_INPUT			0x0944	/* 0x00000000 */
#define IOMUXC_USB_H1_OC_SELECT_INPUT			0x0948	/* 0x00000000 */
#define IOMUXC_USDHC1_WP_ON_SELECT_INPUT		0x094c	/* 0x00000000 */

#endif /* IMX6_IOMUXREG_H */