blob: ac094f6644195008d1dce76a8510476583914410 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
|
//==-- llvm/Target/TargetSubtarget.h - Target Information --------*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes the subtarget options of a Target machine.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_TARGET_TARGETSUBTARGET_H
#define LLVM_TARGET_TARGETSUBTARGET_H
namespace llvm {
class SDep;
class SUnit;
//===----------------------------------------------------------------------===//
///
/// TargetSubtarget - Generic base class for all target subtargets. All
/// Target-specific options that control code generation and printing should
/// be exposed through a TargetSubtarget-derived class.
///
class TargetSubtarget {
TargetSubtarget(const TargetSubtarget&); // DO NOT IMPLEMENT
void operator=(const TargetSubtarget&); // DO NOT IMPLEMENT
protected: // Can only create subclasses...
TargetSubtarget();
public:
virtual ~TargetSubtarget();
/// getSpecialAddressLatency - For targets where it is beneficial to
/// backschedule instructions that compute addresses, return a value
/// indicating the number of scheduling cycles of backscheduling that
/// should be attempted.
virtual unsigned getSpecialAddressLatency() const { return 0; }
// enablePostRAScheduler - Return true to enable
// post-register-allocation scheduling.
virtual bool enablePostRAScheduler() const { return false; }
// adjustSchedDependency - Perform target specific adjustments to
// the latency of a schedule dependency.
virtual void adjustSchedDependency(SUnit *def, SUnit *use,
SDep& dep) const { }
};
} // End llvm namespace
#endif
|
