1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
|
/* Definitions of target machine GNU compiler. IA-64 version.
Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
Contributed by James E. Wilson <wilson@cygnus.com> and
David Mosberger <davidm@hpl.hp.com>.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
/* ??? Look at ABI group documents for list of preprocessor macros and
other features required for ABI compliance. */
/* ??? Functions containing a non-local goto target save many registers. Why?
See for instance execute/920428-2.c. */
/* ??? Add support for short data/bss sections. */
/* Run-time target specifications */
/* Target CPU builtins. */
#define TARGET_CPU_CPP_BUILTINS() \
do { \
builtin_assert("cpu=ia64"); \
builtin_assert("machine=ia64"); \
builtin_define("__ia64"); \
builtin_define("__ia64__"); \
builtin_define("__itanium__"); \
if (TARGET_BIG_ENDIAN) \
builtin_define("__BIG_ENDIAN__"); \
} while (0)
#ifndef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS
#endif
#define EXTRA_SPECS \
{ "asm_extra", ASM_EXTRA_SPEC }, \
SUBTARGET_EXTRA_SPECS
#define CC1_SPEC "%(cc1_cpu) "
#define ASM_EXTRA_SPEC ""
/* This declaration should be present. */
extern int target_flags;
/* This series of macros is to allow compiler command arguments to enable or
disable the use of optional features of the target machine. */
#define MASK_BIG_ENDIAN 0x00000001 /* Generate big endian code. */
#define MASK_GNU_AS 0x00000002 /* Generate code for GNU as. */
#define MASK_GNU_LD 0x00000004 /* Generate code for GNU ld. */
#define MASK_NO_PIC 0x00000008 /* Generate code without GP reg. */
#define MASK_VOL_ASM_STOP 0x00000010 /* Emit stop bits for vol ext asm. */
#define MASK_ILP32 0x00000020 /* Generate ILP32 code. */
#define MASK_B_STEP 0x00000040 /* Emit code for Itanium B step. */
#define MASK_REG_NAMES 0x00000080 /* Use in/loc/out register names. */
#define MASK_NO_SDATA 0x00000100 /* Disable sdata/scommon/sbss. */
#define MASK_CONST_GP 0x00000200 /* treat gp as program-wide constant */
#define MASK_AUTO_PIC 0x00000400 /* generate automatically PIC */
#define MASK_INLINE_FLOAT_DIV_LAT 0x00000800 /* inline div, min latency. */
#define MASK_INLINE_FLOAT_DIV_THR 0x00001000 /* inline div, max throughput. */
#define MASK_INLINE_INT_DIV_LAT 0x00000800 /* inline div, min latency. */
#define MASK_INLINE_INT_DIV_THR 0x00001000 /* inline div, max throughput. */
#define MASK_INLINE_SQRT_LAT 0x00002000 /* inline sqrt, min latency. */
#define MASK_INLINE_SQRT_THR 0x00004000 /* inline sqrt, max throughput. */
#define MASK_DWARF2_ASM 0x40000000 /* test dwarf2 line info via gas. */
#define MASK_EARLY_STOP_BITS 0x00002000 /* tune stop bits for the model. */
#define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
#define TARGET_GNU_AS (target_flags & MASK_GNU_AS)
#define TARGET_GNU_LD (target_flags & MASK_GNU_LD)
#define TARGET_NO_PIC (target_flags & MASK_NO_PIC)
#define TARGET_VOL_ASM_STOP (target_flags & MASK_VOL_ASM_STOP)
#define TARGET_ILP32 (target_flags & MASK_ILP32)
#define TARGET_B_STEP (target_flags & MASK_B_STEP)
#define TARGET_REG_NAMES (target_flags & MASK_REG_NAMES)
#define TARGET_NO_SDATA (target_flags & MASK_NO_SDATA)
#define TARGET_CONST_GP (target_flags & MASK_CONST_GP)
#define TARGET_AUTO_PIC (target_flags & MASK_AUTO_PIC)
#define TARGET_INLINE_FLOAT_DIV_LAT (target_flags & MASK_INLINE_FLOAT_DIV_LAT)
#define TARGET_INLINE_FLOAT_DIV_THR (target_flags & MASK_INLINE_FLOAT_DIV_THR)
#define TARGET_INLINE_INT_DIV_LAT (target_flags & MASK_INLINE_INT_DIV_LAT)
#define TARGET_INLINE_INT_DIV_THR (target_flags & MASK_INLINE_INT_DIV_THR)
#define TARGET_INLINE_FLOAT_DIV \
(target_flags & (MASK_INLINE_FLOAT_DIV_LAT | MASK_INLINE_FLOAT_DIV_THR))
#define TARGET_INLINE_INT_DIV \
(target_flags & (MASK_INLINE_INT_DIV_LAT | MASK_INLINE_INT_DIV_THR))
#define TARGET_INLINE_SQRT_LAT (target_flags & MASK_INLINE_SQRT_LAT)
#define TARGET_INLINE_SQRT_THR (target_flags & MASK_INLINE_SQRT_THR)
#define TARGET_INLINE_SQRT \
(target_flags & (MASK_INLINE_SQRT_LAT | MASK_INLINE_SQRT_THR))
#define TARGET_DWARF2_ASM (target_flags & MASK_DWARF2_ASM)
/* If the assembler supports thread-local storage, assume that the
system does as well. If a particular target system has an
assembler that supports TLS -- but the rest of the system does not
support TLS -- that system should explicit define TARGET_HAVE_TLS
to false in its own configuration file. */
#if !defined(TARGET_HAVE_TLS) && defined(HAVE_AS_TLS)
#define TARGET_HAVE_TLS true
#endif
extern int ia64_tls_size;
#define TARGET_TLS14 (ia64_tls_size == 14)
#define TARGET_TLS22 (ia64_tls_size == 22)
#define TARGET_TLS64 (ia64_tls_size == 64)
#define TARGET_EARLY_STOP_BITS (target_flags & MASK_EARLY_STOP_BITS)
#define TARGET_HPUX 0
#define TARGET_HPUX_LD 0
#ifndef HAVE_AS_LTOFFX_LDXMOV_RELOCS
#define HAVE_AS_LTOFFX_LDXMOV_RELOCS 0
#endif
/* This macro defines names of command options to set and clear bits in
`target_flags'. Its definition is an initializer with a subgrouping for
each command option. */
#define TARGET_SWITCHES \
{ \
{ "big-endian", MASK_BIG_ENDIAN, \
N_("Generate big endian code") }, \
{ "little-endian", -MASK_BIG_ENDIAN, \
N_("Generate little endian code") }, \
{ "gnu-as", MASK_GNU_AS, \
N_("Generate code for GNU as") }, \
{ "no-gnu-as", -MASK_GNU_AS, \
N_("Generate code for Intel as") }, \
{ "gnu-ld", MASK_GNU_LD, \
N_("Generate code for GNU ld") }, \
{ "no-gnu-ld", -MASK_GNU_LD, \
N_("Generate code for Intel ld") }, \
{ "no-pic", MASK_NO_PIC, \
N_("Generate code without GP reg") }, \
{ "volatile-asm-stop", MASK_VOL_ASM_STOP, \
N_("Emit stop bits before and after volatile extended asms") }, \
{ "no-volatile-asm-stop", -MASK_VOL_ASM_STOP, \
N_("Don't emit stop bits before and after volatile extended asms") }, \
{ "b-step", MASK_B_STEP, \
N_("Emit code for Itanium (TM) processor B step")}, \
{ "register-names", MASK_REG_NAMES, \
N_("Use in/loc/out register names")}, \
{ "no-sdata", MASK_NO_SDATA, \
N_("Disable use of sdata/scommon/sbss")}, \
{ "sdata", -MASK_NO_SDATA, \
N_("Enable use of sdata/scommon/sbss")}, \
{ "constant-gp", MASK_CONST_GP, \
N_("gp is constant (but save/restore gp on indirect calls)") }, \
{ "auto-pic", MASK_AUTO_PIC, \
N_("Generate self-relocatable code") }, \
{ "inline-float-divide-min-latency", MASK_INLINE_FLOAT_DIV_LAT, \
N_("Generate inline floating point division, optimize for latency") },\
{ "inline-float-divide-max-throughput", MASK_INLINE_FLOAT_DIV_THR, \
N_("Generate inline floating point division, optimize for throughput") },\
{ "inline-int-divide-min-latency", MASK_INLINE_INT_DIV_LAT, \
N_("Generate inline integer division, optimize for latency") }, \
{ "inline-int-divide-max-throughput", MASK_INLINE_INT_DIV_THR, \
N_("Generate inline integer division, optimize for throughput") },\
{ "inline-sqrt-min-latency", MASK_INLINE_SQRT_LAT, \
N_("Generate inline square root, optimize for latency") }, \
{ "inline-sqrt-max-throughput", MASK_INLINE_SQRT_THR, \
N_("Generate inline square root, optimize for throughput") }, \
{ "dwarf2-asm", MASK_DWARF2_ASM, \
N_("Enable Dwarf 2 line debug info via GNU as")}, \
{ "no-dwarf2-asm", -MASK_DWARF2_ASM, \
N_("Disable Dwarf 2 line debug info via GNU as")}, \
{ "early-stop-bits", MASK_EARLY_STOP_BITS, \
N_("Enable earlier placing stop bits for better scheduling")}, \
{ "no-early-stop-bits", -MASK_EARLY_STOP_BITS, \
N_("Disable earlier placing stop bits")}, \
SUBTARGET_SWITCHES \
{ "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, \
NULL } \
}
/* Default target_flags if no switches are specified */
#ifndef TARGET_DEFAULT
#define TARGET_DEFAULT MASK_DWARF2_ASM
#endif
#ifndef TARGET_CPU_DEFAULT
#define TARGET_CPU_DEFAULT 0
#endif
#ifndef SUBTARGET_SWITCHES
#define SUBTARGET_SWITCHES
#endif
/* This macro is similar to `TARGET_SWITCHES' but defines names of command
options that have values. Its definition is an initializer with a
subgrouping for each command option. */
extern const char *ia64_fixed_range_string;
extern const char *ia64_tls_size_string;
/* Which processor to schedule for. The cpu attribute defines a list
that mirrors this list, so changes to i64.md must be made at the
same time. */
enum processor_type
{
PROCESSOR_ITANIUM, /* Original Itanium. */
PROCESSOR_ITANIUM2,
PROCESSOR_max
};
extern enum processor_type ia64_tune;
extern const char *ia64_tune_string;
#define TARGET_OPTIONS \
{ \
{ "fixed-range=", &ia64_fixed_range_string, \
N_("Specify range of registers to make fixed"), 0}, \
{ "tls-size=", &ia64_tls_size_string, \
N_("Specify bit size of immediate TLS offsets"), 0}, \
{ "tune=", &ia64_tune_string, \
N_("Schedule code for given CPU"), 0}, \
}
/* Sometimes certain combinations of command options do not make sense on a
particular target machine. You can define a macro `OVERRIDE_OPTIONS' to
take account of this. This macro, if defined, is executed once just after
all the command options have been parsed. */
#define OVERRIDE_OPTIONS ia64_override_options ()
/* Some machines may desire to change what optimizations are performed for
various optimization levels. This macro, if defined, is executed once just
after the optimization level is determined and before the remainder of the
command options have been parsed. Values set in this macro are used as the
default values for the other command line options. */
/* #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) */
/* Driver configuration */
/* A C string constant that tells the GCC driver program options to pass to
`cc1'. It can also specify how to translate options you give to GCC into
options for GCC to pass to the `cc1'. */
#undef CC1_SPEC
#define CC1_SPEC "%{G*}"
/* A C string constant that tells the GCC driver program options to pass to
`cc1plus'. It can also specify how to translate options you give to GCC
into options for GCC to pass to the `cc1plus'. */
/* #define CC1PLUS_SPEC "" */
/* Storage Layout */
/* Define this macro to have the value 1 if the most significant bit in a byte
has the lowest number; otherwise define it to have the value zero. */
#define BITS_BIG_ENDIAN 0
#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
/* Define this macro to have the value 1 if, in a multiword object, the most
significant word has the lowest number. */
#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
#if defined(__BIG_ENDIAN__)
#define LIBGCC2_WORDS_BIG_ENDIAN 1
#else
#define LIBGCC2_WORDS_BIG_ENDIAN 0
#endif
#define UNITS_PER_WORD 8
#define POINTER_SIZE (TARGET_ILP32 ? 32 : 64)
/* A C expression whose value is zero if pointers that need to be extended
from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if
they are zero-extended and negative one if there is a ptr_extend operation.
You need not define this macro if the `POINTER_SIZE' is equal to the width
of `Pmode'. */
/* Need this for 32 bit pointers, see hpux.h for setting it. */
/* #define POINTERS_EXTEND_UNSIGNED */
/* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and
which has the specified mode and signedness is to be stored in a register.
This macro is only called when TYPE is a scalar type. */
#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
do \
{ \
if (GET_MODE_CLASS (MODE) == MODE_INT \
&& GET_MODE_SIZE (MODE) < 4) \
(MODE) = SImode; \
} \
while (0)
/* ??? ABI doesn't allow us to define this. */
/* #define PROMOTE_FUNCTION_ARGS */
/* ??? ABI doesn't allow us to define this. */
/* #define PROMOTE_FUNCTION_RETURN */
#define PARM_BOUNDARY 64
/* Define this macro if you wish to preserve a certain alignment for the stack
pointer. The definition is a C expression for the desired alignment
(measured in bits). */
#define STACK_BOUNDARY 128
/* Align frames on double word boundaries */
#ifndef IA64_STACK_ALIGN
#define IA64_STACK_ALIGN(LOC) (((LOC) + 15) & ~15)
#endif
#define FUNCTION_BOUNDARY 128
/* Optional x86 80-bit float, quad-precision 128-bit float, and quad-word
128 bit integers all require 128 bit alignment. */
#define BIGGEST_ALIGNMENT 128
/* If defined, a C expression to compute the alignment for a static variable.
TYPE is the data type, and ALIGN is the alignment that the object
would ordinarily have. The value of this macro is used instead of that
alignment to align the object. */
#define DATA_ALIGNMENT(TYPE, ALIGN) \
(TREE_CODE (TYPE) == ARRAY_TYPE \
&& TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
&& (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
/* If defined, a C expression to compute the alignment given to a constant that
is being placed in memory. CONSTANT is the constant and ALIGN is the
alignment that the object would ordinarily have. The value of this macro is
used instead of that alignment to align the object. */
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
(TREE_CODE (EXP) == STRING_CST \
&& (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
#define STRICT_ALIGNMENT 1
/* Define this if you wish to imitate the way many other C compilers handle
alignment of bitfields and the structures that contain them.
The behavior is that the type written for a bit-field (`int', `short', or
other integer type) imposes an alignment for the entire structure, as if the
structure really did contain an ordinary field of that type. In addition,
the bit-field is placed within the structure so that it would fit within such
a field, not crossing a boundary for it. */
#define PCC_BITFIELD_TYPE_MATTERS 1
/* An integer expression for the size in bits of the largest integer machine
mode that should actually be used. */
/* Allow pairs of registers to be used, which is the intent of the default. */
#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
/* By default, the C++ compiler will use function addresses in the
vtable entries. Setting this nonzero tells the compiler to use
function descriptors instead. The value of this macro says how
many words wide the descriptor is (normally 2). It is assumed
that the address of a function descriptor may be treated as a
pointer to a function.
For reasons known only to HP, the vtable entries (as opposed to
normal function descriptors) are 16 bytes wide in 32-bit mode as
well, even though the 3rd and 4th words are unused. */
#define TARGET_VTABLE_USES_DESCRIPTORS (TARGET_ILP32 ? 4 : 2)
/* Due to silliness in the HPUX linker, vtable entries must be
8-byte aligned even in 32-bit mode. Rather than create multiple
ABIs, force this restriction on everyone else too. */
#define TARGET_VTABLE_ENTRY_ALIGN 64
/* Due to the above, we need extra padding for the data entries below 0
to retain the alignment of the descriptors. */
#define TARGET_VTABLE_DATA_ENTRY_DISTANCE (TARGET_ILP32 ? 2 : 1)
/* Layout of Source Language Data Types */
#define INT_TYPE_SIZE 32
#define SHORT_TYPE_SIZE 16
#define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64)
#define MAX_LONG_TYPE_SIZE 64
#define LONG_LONG_TYPE_SIZE 64
#define FLOAT_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE 64
/* long double is XFmode normally, TFmode for HPUX. */
#define LONG_DOUBLE_TYPE_SIZE (TARGET_HPUX ? 128 : 96)
/* We always want the XFmode operations from libgcc2.c. */
#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
#define DEFAULT_SIGNED_CHAR 1
/* A C expression for a string describing the name of the data type to use for
size values. The typedef name `size_t' is defined using the contents of the
string. */
/* ??? Needs to be defined for P64 code. */
/* #define SIZE_TYPE */
/* A C expression for a string describing the name of the data type to use for
the result of subtracting two pointers. The typedef name `ptrdiff_t' is
defined using the contents of the string. See `SIZE_TYPE' above for more
information. */
/* ??? Needs to be defined for P64 code. */
/* #define PTRDIFF_TYPE */
/* A C expression for a string describing the name of the data type to use for
wide characters. The typedef name `wchar_t' is defined using the contents
of the string. See `SIZE_TYPE' above for more information. */
/* #define WCHAR_TYPE */
/* A C expression for the size in bits of the data type for wide characters.
This is used in `cpp', which cannot make use of `WCHAR_TYPE'. */
/* #define WCHAR_TYPE_SIZE */
/* Register Basics */
/* Number of hardware registers known to the compiler.
We have 128 general registers, 128 floating point registers,
64 predicate registers, 8 branch registers, one frame pointer,
and several "application" registers. */
#define FIRST_PSEUDO_REGISTER 334
/* Ranges for the various kinds of registers. */
#define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3)
#define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127)
#define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255)
#define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319)
#define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327)
#define GENERAL_REGNO_P(REGNO) \
(GR_REGNO_P (REGNO) || (REGNO) == FRAME_POINTER_REGNUM)
#define GR_REG(REGNO) ((REGNO) + 0)
#define FR_REG(REGNO) ((REGNO) + 128)
#define PR_REG(REGNO) ((REGNO) + 256)
#define BR_REG(REGNO) ((REGNO) + 320)
#define OUT_REG(REGNO) ((REGNO) + 120)
#define IN_REG(REGNO) ((REGNO) + 112)
#define LOC_REG(REGNO) ((REGNO) + 32)
#define AR_CCV_REGNUM 329
#define AR_UNAT_REGNUM 330
#define AR_PFS_REGNUM 331
#define AR_LC_REGNUM 332
#define AR_EC_REGNUM 333
#define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7))
#define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79))
#define OUT_REGNO_P(REGNO) ((REGNO) >= OUT_REG (0) && (REGNO) <= OUT_REG (7))
#define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM \
|| (REGNO) == AR_UNAT_REGNUM)
#define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_PFS_REGNUM \
&& (REGNO) < FIRST_PSEUDO_REGISTER)
#define AR_REGNO_P(REGNO) ((REGNO) >= AR_CCV_REGNUM \
&& (REGNO) < FIRST_PSEUDO_REGISTER)
/* ??? Don't really need two sets of macros. I like this one better because
it is less typing. */
#define R_GR(REGNO) GR_REG (REGNO)
#define R_FR(REGNO) FR_REG (REGNO)
#define R_PR(REGNO) PR_REG (REGNO)
#define R_BR(REGNO) BR_REG (REGNO)
/* An initializer that says which registers are used for fixed purposes all
throughout the compiled code and are therefore not available for general
allocation.
r0: constant 0
r1: global pointer (gp)
r12: stack pointer (sp)
r13: thread pointer (tp)
f0: constant 0.0
f1: constant 1.0
p0: constant true
fp: eliminable frame pointer */
/* The last 16 stacked regs are reserved for the 8 input and 8 output
registers. */
#define FIXED_REGISTERS \
{ /* General registers. */ \
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
/* Floating-point registers. */ \
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
/* Predicate registers. */ \
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
/* Branch registers. */ \
0, 0, 0, 0, 0, 0, 0, 0, \
/*FP CCV UNAT PFS LC EC */ \
1, 1, 1, 1, 0, 1 \
}
/* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered
(in general) by function calls as well as for fixed registers. This
macro therefore identifies the registers that are not available for
general allocation of values that must live across function calls. */
#define CALL_USED_REGISTERS \
{ /* General registers. */ \
1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
/* Floating-point registers. */ \
1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
/* Predicate registers. */ \
1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
/* Branch registers. */ \
1, 0, 0, 0, 0, 0, 1, 1, \
/*FP CCV UNAT PFS LC EC */ \
1, 1, 1, 1, 0, 1 \
}
/* Like `CALL_USED_REGISTERS' but used to overcome a historical
problem which makes CALL_USED_REGISTERS *always* include
all the FIXED_REGISTERS. Until this problem has been
resolved this macro can be used to overcome this situation.
In particular, block_propagate() requires this list
be accurate, or we can remove registers which should be live.
This macro is used in regs_invalidated_by_call. */
#define CALL_REALLY_USED_REGISTERS \
{ /* General registers. */ \
1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
/* Floating-point registers. */ \
1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
/* Predicate registers. */ \
1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
/* Branch registers. */ \
1, 0, 0, 0, 0, 0, 1, 1, \
/*FP CCV UNAT PFS LC EC */ \
0, 1, 0, 1, 0, 0 \
}
/* Define this macro if the target machine has register windows. This C
expression returns the register number as seen by the called function
corresponding to the register number OUT as seen by the calling function.
Return OUT if register number OUT is not an outbound register. */
#define INCOMING_REGNO(OUT) \
((unsigned) ((OUT) - OUT_REG (0)) < 8 ? IN_REG ((OUT) - OUT_REG (0)) : (OUT))
/* Define this macro if the target machine has register windows. This C
expression returns the register number as seen by the calling function
corresponding to the register number IN as seen by the called function.
Return IN if register number IN is not an inbound register. */
#define OUTGOING_REGNO(IN) \
((unsigned) ((IN) - IN_REG (0)) < 8 ? OUT_REG ((IN) - IN_REG (0)) : (IN))
/* Define this macro if the target machine has register windows. This
C expression returns true if the register is call-saved but is in the
register window. */
#define LOCAL_REGNO(REGNO) \
(IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO))
/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
return the mode to be used for the comparison. Must be defined if
EXTRA_CC_MODES is defined. */
#define SELECT_CC_MODE(OP,X,Y) CCmode
/* Order of allocation of registers */
/* If defined, an initializer for a vector of integers, containing the numbers
of hard registers in the order in which GCC should prefer to use them
(from most preferred to least).
If this macro is not defined, registers are used lowest numbered first (all
else being equal).
One use of this macro is on machines where the highest numbered registers
must always be saved and the save-multiple-registers instruction supports
only sequences of consecutive registers. On such machines, define
`REG_ALLOC_ORDER' to be an initializer that lists the highest numbered
allocatable register first. */
/* ??? Should the GR return value registers come before or after the rest
of the caller-save GRs? */
#define REG_ALLOC_ORDER \
{ \
/* Caller-saved general registers. */ \
R_GR (14), R_GR (15), R_GR (16), R_GR (17), \
R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23), \
R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29), \
R_GR (30), R_GR (31), \
/* Output registers. */ \
R_GR (120), R_GR (121), R_GR (122), R_GR (123), R_GR (124), R_GR (125), \
R_GR (126), R_GR (127), \
/* Caller-saved general registers, also used for return values. */ \
R_GR (8), R_GR (9), R_GR (10), R_GR (11), \
/* addl caller-saved general registers. */ \
R_GR (2), R_GR (3), \
/* Caller-saved FP registers. */ \
R_FR (6), R_FR (7), \
/* Caller-saved FP registers, used for parameters and return values. */ \
R_FR (8), R_FR (9), R_FR (10), R_FR (11), \
R_FR (12), R_FR (13), R_FR (14), R_FR (15), \
/* Rotating caller-saved FP registers. */ \
R_FR (32), R_FR (33), R_FR (34), R_FR (35), \
R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41), \
R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47), \
R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53), \
R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59), \
R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65), \
R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71), \
R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77), \
R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83), \
R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89), \
R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95), \
R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101), \
R_FR (102), R_FR (103), R_FR (104), R_FR (105), R_FR (106), R_FR (107), \
R_FR (108), R_FR (109), R_FR (110), R_FR (111), R_FR (112), R_FR (113), \
R_FR (114), R_FR (115), R_FR (116), R_FR (117), R_FR (118), R_FR (119), \
R_FR (120), R_FR (121), R_FR (122), R_FR (123), R_FR (124), R_FR (125), \
R_FR (126), R_FR (127), \
/* Caller-saved predicate registers. */ \
R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11), \
R_PR (12), R_PR (13), R_PR (14), R_PR (15), \
/* Rotating caller-saved predicate registers. */ \
R_PR (16), R_PR (17), \
R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23), \
R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29), \
R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35), \
R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41), \
R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47), \
R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53), \
R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59), \
R_PR (60), R_PR (61), R_PR (62), R_PR (63), \
/* Caller-saved branch registers. */ \
R_BR (6), R_BR (7), \
\
/* Stacked callee-saved general registers. */ \
R_GR (32), R_GR (33), R_GR (34), R_GR (35), \
R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41), \
R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47), \
R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53), \
R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59), \
R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65), \
R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71), \
R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77), \
R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83), \
R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89), \
R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95), \
R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101), \
R_GR (102), R_GR (103), R_GR (104), R_GR (105), R_GR (106), R_GR (107), \
R_GR (108), \
/* Input registers. */ \
R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (116), R_GR (117), \
R_GR (118), R_GR (119), \
/* Callee-saved general registers. */ \
R_GR (4), R_GR (5), R_GR (6), R_GR (7), \
/* Callee-saved FP registers. */ \
R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17), \
R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23), \
R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29), \
R_FR (30), R_FR (31), \
/* Callee-saved predicate registers. */ \
R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5), \
/* Callee-saved branch registers. */ \
R_BR (1), R_BR (2), R_BR (3), R_BR (4), R_BR (5), \
\
/* ??? Stacked registers reserved for fp, rp, and ar.pfs. */ \
R_GR (109), R_GR (110), R_GR (111), \
\
/* Special general registers. */ \
R_GR (0), R_GR (1), R_GR (12), R_GR (13), \
/* Special FP registers. */ \
R_FR (0), R_FR (1), \
/* Special predicate registers. */ \
R_PR (0), \
/* Special branch registers. */ \
R_BR (0), \
/* Other fixed registers. */ \
FRAME_POINTER_REGNUM, \
AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM, \
AR_EC_REGNUM \
}
/* How Values Fit in Registers */
/* A C expression for the number of consecutive hard registers, starting at
register number REGNO, required to hold a value of mode MODE. */
/* ??? We say that BImode PR values require two registers. This allows us to
easily store the normal and inverted values. We use CCImode to indicate
a single predicate register. */
#define HARD_REGNO_NREGS(REGNO, MODE) \
((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \
: PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \
: PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \
: FR_REGNO_P (REGNO) && (MODE) == XFmode ? 1 \
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* A C expression that is nonzero if it is permissible to store a value of mode
MODE in hard register number REGNO (or in several registers starting with
that one). */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
(FR_REGNO_P (REGNO) ? \
GET_MODE_CLASS (MODE) != MODE_CC && \
(MODE) != TImode && \
(MODE) != BImode && \
(MODE) != TFmode \
: PR_REGNO_P (REGNO) ? \
(MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \
: GR_REGNO_P (REGNO) ? (MODE) != CCImode && (MODE) != XFmode \
: AR_REGNO_P (REGNO) ? (MODE) == DImode \
: BR_REGNO_P (REGNO) ? (MODE) == DImode \
: 0)
/* A C expression that is nonzero if it is desirable to choose register
allocation so as to avoid move instructions between a value of mode MODE1
and a value of mode MODE2.
If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
zero. */
/* Don't tie integer and FP modes, as that causes us to get integer registers
allocated for FP instructions. XFmode only supported in FP registers so
we can't tie it with any other modes. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
(GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
&& (((MODE1) == XFmode) == ((MODE2) == XFmode)) \
&& (((MODE1) == BImode) == ((MODE2) == BImode)))
/* Specify the modes required to caller save a given hard regno.
We need to ensure floating pt regs are not saved as DImode. */
#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
((FR_REGNO_P (REGNO) && (NREGS) == 1) ? XFmode \
: choose_hard_reg_mode ((REGNO), (NREGS), false))
/* Handling Leaf Functions */
/* A C initializer for a vector, indexed by hard register number, which
contains 1 for a register that is allowable in a candidate for leaf function
treatment. */
/* ??? This might be useful. */
/* #define LEAF_REGISTERS */
/* A C expression whose value is the register number to which REGNO should be
renumbered, when a function is treated as a leaf function. */
/* ??? This might be useful. */
/* #define LEAF_REG_REMAP(REGNO) */
/* Register Classes */
/* An enumeral type that must be defined with all the register class names as
enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last
register class, followed by one more enumeral value, `LIM_REG_CLASSES',
which is not a register class but rather tells how many classes there
are. */
/* ??? When compiling without optimization, it is possible for the only use of
a pseudo to be a parameter load from the stack with a REG_EQUIV note.
Regclass handles this case specially and does not assign any costs to the
pseudo. The pseudo then ends up using the last class before ALL_REGS.
Thus we must not let either PR_REGS or BR_REGS be the last class. The
testcase for this is gcc.c-torture/execute/va-arg-7.c. */
enum reg_class
{
NO_REGS,
PR_REGS,
BR_REGS,
AR_M_REGS,
AR_I_REGS,
ADDL_REGS,
GR_REGS,
FR_REGS,
GR_AND_BR_REGS,
GR_AND_FR_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
#define GENERAL_REGS GR_REGS
/* The number of distinct register classes. */
#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
/* An initializer containing the names of the register classes as C string
constants. These names are used in writing some of the debugging dumps. */
#define REG_CLASS_NAMES \
{ "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \
"ADDL_REGS", "GR_REGS", "FR_REGS", \
"GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" }
/* An initializer containing the contents of the register classes, as integers
which are bit masks. The Nth integer specifies the contents of class N.
The way the integer MASK is interpreted is that register R is in the class
if `MASK & (1 << R)' is 1. */
#define REG_CLASS_CONTENTS \
{ \
/* NO_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x0000 }, \
/* PR_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0xFFFFFFFF, 0xFFFFFFFF, 0x0000 }, \
/* BR_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00FF }, \
/* AR_M_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x0600 }, \
/* AR_I_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x3800 }, \
/* ADDL_REGS. */ \
{ 0x0000000F, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x0000 }, \
/* GR_REGS. */ \
{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x0100 }, \
/* FR_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0x00000000, 0x00000000, 0x0000 }, \
/* GR_AND_BR_REGS. */ \
{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x01FF }, \
/* GR_AND_FR_REGS. */ \
{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0x00000000, 0x00000000, 0x0100 }, \
/* ALL_REGS. */ \
{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0xFFFFFFFF, 0xFFFFFFFF, 0x3FFF }, \
}
/* A C expression whose value is a register class containing hard register
REGNO. In general there is more than one such class; choose a class which
is "minimal", meaning that no smaller class also contains the register. */
/* The NO_REGS case is primarily for the benefit of rws_access_reg, which
may call here with private (invalid) register numbers, such as
REG_VOLATILE. */
#define REGNO_REG_CLASS(REGNO) \
(ADDL_REGNO_P (REGNO) ? ADDL_REGS \
: GENERAL_REGNO_P (REGNO) ? GR_REGS \
: FR_REGNO_P (REGNO) ? FR_REGS \
: PR_REGNO_P (REGNO) ? PR_REGS \
: BR_REGNO_P (REGNO) ? BR_REGS \
: AR_M_REGNO_P (REGNO) ? AR_M_REGS \
: AR_I_REGNO_P (REGNO) ? AR_I_REGS \
: NO_REGS)
/* A macro whose definition is the name of the class to which a valid base
register must belong. A base register is one used in an address which is
the register value plus a displacement. */
#define BASE_REG_CLASS GENERAL_REGS
/* A macro whose definition is the name of the class to which a valid index
register must belong. An index register is one used in an address where its
value is either multiplied by a scale factor or added to another register
(as well as added to a displacement). This is needed for POST_MODIFY. */
#define INDEX_REG_CLASS GENERAL_REGS
/* A C expression which defines the machine-dependent operand constraint
letters for register classes. If CHAR is such a letter, the value should be
the register class corresponding to it. Otherwise, the value should be
`NO_REGS'. The register letter `r', corresponding to class `GENERAL_REGS',
will not be passed to this macro; you do not need to handle it. */
#define REG_CLASS_FROM_LETTER(CHAR) \
((CHAR) == 'f' ? FR_REGS \
: (CHAR) == 'a' ? ADDL_REGS \
: (CHAR) == 'b' ? BR_REGS \
: (CHAR) == 'c' ? PR_REGS \
: (CHAR) == 'd' ? AR_M_REGS \
: (CHAR) == 'e' ? AR_I_REGS \
: NO_REGS)
/* A C expression which is nonzero if register number NUM is suitable for use
as a base register in operand addresses. It may be either a suitable hard
register or a pseudo register that has been allocated such a hard reg. */
#define REGNO_OK_FOR_BASE_P(REGNO) \
(GENERAL_REGNO_P (REGNO) || GENERAL_REGNO_P (reg_renumber[REGNO]))
/* A C expression which is nonzero if register number NUM is suitable for use
as an index register in operand addresses. It may be either a suitable hard
register or a pseudo register that has been allocated such a hard reg.
This is needed for POST_MODIFY. */
#define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)
/* A C expression that places additional restrictions on the register class to
use when it is necessary to copy value X into a register in class CLASS.
The value is a register class; perhaps CLASS, or perhaps another, smaller
class. */
/* Don't allow volatile mem reloads into floating point registers. This
is defined to force reload to choose the r/m case instead of the f/f case
when reloading (set (reg fX) (mem/v)).
Do not reload expressions into AR regs. */
#define PREFERRED_RELOAD_CLASS(X, CLASS) \
(CLASS == FR_REGS && GET_CODE (X) == MEM && MEM_VOLATILE_P (X) ? NO_REGS \
: CLASS == FR_REGS && GET_CODE (X) == CONST_DOUBLE ? NO_REGS \
: GET_RTX_CLASS (GET_CODE (X)) != 'o' \
&& (CLASS == AR_M_REGS || CLASS == AR_I_REGS) ? NO_REGS \
: CLASS)
/* You should define this macro to indicate to the reload phase that it may
need to allocate at least one register for a reload in addition to the
register to contain the data. Specifically, if copying X to a register
CLASS in MODE requires an intermediate register, you should define this
to return the largest register class all of whose registers can be used
as intermediate registers or scratch registers. */
#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
ia64_secondary_reload_class (CLASS, MODE, X)
/* Certain machines have the property that some registers cannot be copied to
some other registers without using memory. Define this macro on those
machines to be a C expression that is nonzero if objects of mode M in
registers of CLASS1 can only be copied to registers of class CLASS2 by
storing a register of CLASS1 into memory and loading that memory location
into a register of CLASS2. */
#if 0
/* ??? May need this, but since we've disallowed XFmode in GR_REGS,
I'm not quite sure how it could be invoked. The normal problems
with unions should be solved with the addressof fiddling done by
movxf and friends. */
#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
((MODE) == XFmode && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS) \
|| ((CLASS1) == FR_REGS && (CLASS2) == GR_REGS)))
#endif
/* A C expression for the maximum number of consecutive registers of
class CLASS needed to hold a value of mode MODE.
This is closely related to the macro `HARD_REGNO_NREGS'. */
#define CLASS_MAX_NREGS(CLASS, MODE) \
((MODE) == BImode && (CLASS) == PR_REGS ? 2 \
: ((CLASS) == FR_REGS && (MODE) == XFmode) ? 1 \
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* In FP regs, we can't change FP values to integer values and vice
versa, but we can change e.g. DImode to SImode. */
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
(GET_MODE_CLASS (FROM) != GET_MODE_CLASS (TO) \
? reg_classes_intersect_p (CLASS, FR_REGS) : 0)
/* A C expression that defines the machine-dependent operand constraint
letters (`I', `J', `K', .. 'P') that specify particular ranges of
integer values. */
/* 14 bit signed immediate for arithmetic instructions. */
#define CONST_OK_FOR_I(VALUE) \
((unsigned HOST_WIDE_INT)(VALUE) + 0x2000 < 0x4000)
/* 22 bit signed immediate for arith instructions with r0/r1/r2/r3 source. */
#define CONST_OK_FOR_J(VALUE) \
((unsigned HOST_WIDE_INT)(VALUE) + 0x200000 < 0x400000)
/* 8 bit signed immediate for logical instructions. */
#define CONST_OK_FOR_K(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x80 < 0x100)
/* 8 bit adjusted signed immediate for compare pseudo-ops. */
#define CONST_OK_FOR_L(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x7F < 0x100)
/* 6 bit unsigned immediate for shift counts. */
#define CONST_OK_FOR_M(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) < 0x40)
/* 9 bit signed immediate for load/store post-increments. */
#define CONST_OK_FOR_N(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x100 < 0x200)
/* 0 for r0. Used by Linux kernel, do not change. */
#define CONST_OK_FOR_O(VALUE) ((VALUE) == 0)
/* 0 or -1 for dep instruction. */
#define CONST_OK_FOR_P(VALUE) ((VALUE) == 0 || (VALUE) == -1)
#define CONST_OK_FOR_LETTER_P(VALUE, C) \
((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
: (C) == 'J' ? CONST_OK_FOR_J (VALUE) \
: (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
: (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
: (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
: (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
: (C) == 'O' ? CONST_OK_FOR_O (VALUE) \
: (C) == 'P' ? CONST_OK_FOR_P (VALUE) \
: 0)
/* A C expression that defines the machine-dependent operand constraint letters
(`G', `H') that specify particular ranges of `const_double' values. */
/* 0.0 and 1.0 for fr0 and fr1. */
#define CONST_DOUBLE_OK_FOR_G(VALUE) \
((VALUE) == CONST0_RTX (GET_MODE (VALUE)) \
|| (VALUE) == CONST1_RTX (GET_MODE (VALUE)))
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
((C) == 'G' ? CONST_DOUBLE_OK_FOR_G (VALUE) : 0)
/* A C expression that defines the optional machine-dependent constraint
letters (`Q', `R', `S', `T', `U') that can be used to segregate specific
types of operands, usually memory references, for the target machine. */
/* Non-volatile memory for FP_REG loads/stores. */
#define CONSTRAINT_OK_FOR_Q(VALUE) \
(memory_operand((VALUE), VOIDmode) && ! MEM_VOLATILE_P (VALUE))
/* 1..4 for shladd arguments. */
#define CONSTRAINT_OK_FOR_R(VALUE) \
(GET_CODE (VALUE) == CONST_INT && INTVAL (VALUE) >= 1 && INTVAL (VALUE) <= 4)
/* Non-post-inc memory for asms and other unsavory creatures. */
#define CONSTRAINT_OK_FOR_S(VALUE) \
(GET_CODE (VALUE) == MEM \
&& GET_RTX_CLASS (GET_CODE (XEXP ((VALUE), 0))) != 'a' \
&& (reload_in_progress || memory_operand ((VALUE), VOIDmode)))
/* Symbol ref to small-address-area: */
#define CONSTRAINT_OK_FOR_T(VALUE) \
(GET_CODE (VALUE) == SYMBOL_REF && SYMBOL_REF_SMALL_ADDR_P (VALUE))
#define EXTRA_CONSTRAINT(VALUE, C) \
((C) == 'Q' ? CONSTRAINT_OK_FOR_Q (VALUE) \
: (C) == 'R' ? CONSTRAINT_OK_FOR_R (VALUE) \
: (C) == 'S' ? CONSTRAINT_OK_FOR_S (VALUE) \
: (C) == 'T' ? CONSTRAINT_OK_FOR_T (VALUE) \
: 0)
/* Basic Stack Layout */
/* Define this macro if pushing a word onto the stack moves the stack pointer
to a smaller address. */
#define STACK_GROWS_DOWNWARD 1
/* Define this macro if the addresses of local variable slots are at negative
offsets from the frame pointer. */
/* #define FRAME_GROWS_DOWNWARD */
/* Offset from the frame pointer to the first local variable slot to
be allocated. */
#define STARTING_FRAME_OFFSET 0
/* Offset from the stack pointer register to the first location at which
outgoing arguments are placed. If not specified, the default value of zero
is used. This is the proper value for most machines. */
/* IA64 has a 16 byte scratch area that is at the bottom of the stack. */
#define STACK_POINTER_OFFSET 16
/* Offset from the argument pointer register to the first argument's address.
On some machines it may depend on the data type of the function. */
#define FIRST_PARM_OFFSET(FUNDECL) 0
/* A C expression whose value is RTL representing the value of the return
address for the frame COUNT steps up from the current frame, after the
prologue. */
/* ??? Frames other than zero would likely require interpreting the frame
unwind info, so we don't try to support them. We would also need to define
DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush). */
#define RETURN_ADDR_RTX(COUNT, FRAME) \
ia64_return_addr_rtx (COUNT, FRAME)
/* A C expression whose value is RTL representing the location of the incoming
return address at the beginning of any function, before the prologue. This
RTL is either a `REG', indicating that the return value is saved in `REG',
or a `MEM' representing a location in the stack. This enables DWARF2
unwind info for C++ EH. */
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, BR_REG (0))
/* ??? This is not defined because of three problems.
1) dwarf2out.c assumes that DWARF_FRAME_RETURN_COLUMN fits in one byte.
The default value is FIRST_PSEUDO_REGISTER which doesn't. This can be
worked around by setting PC_REGNUM to FR_REG (0) which is an otherwise
unused register number.
2) dwarf2out_frame_debug core dumps while processing prologue insns. We
need to refine which insns have RTX_FRAME_RELATED_P set and which don't.
3) It isn't possible to turn off EH frame info by defining DWARF2_UNIND_INFO
to zero, despite what the documentation implies, because it is tested in
a few places with #ifdef instead of #if. */
#undef INCOMING_RETURN_ADDR_RTX
/* A C expression whose value is an integer giving the offset, in bytes, from
the value of the stack pointer register to the top of the stack frame at the
beginning of any function, before the prologue. The top of the frame is
defined to be the value of the stack pointer in the previous frame, just
before the call instruction. */
#define INCOMING_FRAME_SP_OFFSET 0
/* Register That Address the Stack Frame. */
/* The register number of the stack pointer register, which must also be a
fixed register according to `FIXED_REGISTERS'. On most machines, the
hardware determines which register this is. */
#define STACK_POINTER_REGNUM 12
/* The register number of the frame pointer register, which is used to access
automatic variables in the stack frame. On some machines, the hardware
determines which register this is. On other machines, you can choose any
register you wish for this purpose. */
#define FRAME_POINTER_REGNUM 328
/* Base register for access to local variables of the function. */
#define HARD_FRAME_POINTER_REGNUM LOC_REG (79)
/* The register number of the arg pointer register, which is used to access the
function's argument list. */
/* r0 won't otherwise be used, so put the always eliminated argument pointer
in it. */
#define ARG_POINTER_REGNUM R_GR(0)
/* Due to the way varargs and argument spilling happens, the argument
pointer is not 16-byte aligned like the stack pointer. */
#define INIT_EXPANDERS \
do { \
if (cfun && cfun->emit->regno_pointer_align) \
REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = 64; \
} while (0)
/* Register numbers used for passing a function's static chain pointer. */
/* ??? The ABI sez the static chain should be passed as a normal parameter. */
#define STATIC_CHAIN_REGNUM 15
/* Eliminating the Frame Pointer and the Arg Pointer */
/* A C expression which is nonzero if a function must have and use a frame
pointer. This expression is evaluated in the reload pass. If its value is
nonzero the function will have a frame pointer. */
#define FRAME_POINTER_REQUIRED 0
/* Show we can debug even without a frame pointer. */
#define CAN_DEBUG_WITHOUT_FP
/* If defined, this macro specifies a table of register pairs used to eliminate
unneeded registers that point into the stack frame. */
#define ELIMINABLE_REGS \
{ \
{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
{FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
}
/* A C expression that returns nonzero if the compiler is allowed to try to
replace register number FROM with register number TO. The frame pointer
is automatically handled. */
#define CAN_ELIMINATE(FROM, TO) \
(TO == BR_REG (0) ? current_function_is_leaf : 1)
/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
specifies the initial difference between the specified pair of
registers. This macro must be defined if `ELIMINABLE_REGS' is
defined. */
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO)))
/* Passing Function Arguments on the Stack */
/* Define this macro if an argument declared in a prototype as an integral type
smaller than `int' should actually be passed as an `int'. In addition to
avoiding errors in certain cases of mismatch, it also makes for better code
on certain machines. */
/* ??? Investigate. */
/* #define PROMOTE_PROTOTYPES */
/* If defined, the maximum amount of space required for outgoing arguments will
be computed and placed into the variable
`current_function_outgoing_args_size'. */
#define ACCUMULATE_OUTGOING_ARGS 1
/* A C expression that should indicate the number of bytes of its own arguments
that a function pops on returning, or 0 if the function pops no arguments
and the caller must therefore pop them all after the function returns. */
#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
/* Function Arguments in Registers */
#define MAX_ARGUMENT_SLOTS 8
#define MAX_INT_RETURN_SLOTS 4
#define GR_ARG_FIRST IN_REG (0)
#define GR_RET_FIRST GR_REG (8)
#define GR_RET_LAST GR_REG (11)
#define FR_ARG_FIRST FR_REG (8)
#define FR_RET_FIRST FR_REG (8)
#define FR_RET_LAST FR_REG (15)
#define AR_ARG_FIRST OUT_REG (0)
/* A C expression that controls whether a function argument is passed in a
register, and which register. */
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
ia64_function_arg (&CUM, MODE, TYPE, NAMED, 0)
/* Define this macro if the target machine has "register windows", so that the
register in which a function sees an arguments is not necessarily the same
as the one in which the caller passed the argument. */
#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
ia64_function_arg (&CUM, MODE, TYPE, NAMED, 1)
/* A C expression for the number of words, at the beginning of an argument,
must be put in registers. The value must be zero for arguments that are
passed entirely in registers or that are entirely pushed on the stack. */
#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
ia64_function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
/* A C expression that indicates when an argument must be passed by reference.
If nonzero for an argument, a copy of that argument is made in memory and a
pointer to the argument is passed instead of the argument itself. The
pointer is passed in whatever way is appropriate for passing a pointer to
that type. */
#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
ia64_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
/* Nonzero if we do not know how to pass TYPE solely in registers. */
#define MUST_PASS_IN_STACK(MODE, TYPE) \
((TYPE) != 0 \
&& (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
|| TREE_ADDRESSABLE (TYPE)))
/* A C type for declaring a variable that is used as the first argument of
`FUNCTION_ARG' and other related values. For some target machines, the type
`int' suffices and can hold the number of bytes of argument so far. */
typedef struct ia64_args
{
int words; /* # words of arguments so far */
int int_regs; /* # GR registers used so far */
int fp_regs; /* # FR registers used so far */
int prototype; /* whether function prototyped */
} CUMULATIVE_ARGS;
/* A C statement (sans semicolon) for initializing the variable CUM for the
state at the beginning of the argument list. */
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
do { \
(CUM).words = 0; \
(CUM).int_regs = 0; \
(CUM).fp_regs = 0; \
(CUM).prototype = ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE)) || (LIBNAME); \
} while (0)
/* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the
arguments for the function being compiled. If this macro is undefined,
`INIT_CUMULATIVE_ARGS' is used instead. */
/* We set prototype to true so that we never try to return a PARALLEL from
function_arg. */
#define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
do { \
(CUM).words = 0; \
(CUM).int_regs = 0; \
(CUM).fp_regs = 0; \
(CUM).prototype = 1; \
} while (0)
/* A C statement (sans semicolon) to update the summarizer variable CUM to
advance past an argument in the argument list. The values MODE, TYPE and
NAMED describe that argument. Once this is done, the variable CUM is
suitable for analyzing the *following* argument with `FUNCTION_ARG'. */
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
ia64_function_arg_advance (&CUM, MODE, TYPE, NAMED)
/* If defined, a C expression that gives the alignment boundary, in bits, of an
argument with the specified mode and type. */
/* Arguments with alignment larger than 8 bytes start at the next even
boundary. See ia64_function_arg. */
#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
(((TYPE) ? (TYPE_ALIGN (TYPE) > 8 * BITS_PER_UNIT) \
: (((((MODE) == BLKmode \
? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \
+ UNITS_PER_WORD - 1) / UNITS_PER_WORD) > 1)) \
? 128 : PARM_BOUNDARY)
/* A C expression that is nonzero if REGNO is the number of a hard register in
which function arguments are sometimes passed. This does *not* include
implicit arguments such as the static chain and the structure-value address.
On many machines, no registers can be used for this purpose since all
function arguments are pushed on the stack. */
#define FUNCTION_ARG_REGNO_P(REGNO) \
(((REGNO) >= AR_ARG_FIRST && (REGNO) < (AR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \
|| ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS)))
/* Implement `va_arg'. */
#define EXPAND_BUILTIN_VA_ARG(valist, type) \
ia64_va_arg (valist, type)
/* How Scalar Function Values are Returned */
/* A C expression to create an RTX representing the place where a function
returns a value of data type VALTYPE. */
#define FUNCTION_VALUE(VALTYPE, FUNC) \
ia64_function_value (VALTYPE, FUNC)
/* A C expression to create an RTX representing the place where a library
function returns a value of mode MODE. */
#define LIBCALL_VALUE(MODE) \
gen_rtx_REG (MODE, \
(((GET_MODE_CLASS (MODE) == MODE_FLOAT \
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) && \
(MODE) != TFmode) \
? FR_RET_FIRST : GR_RET_FIRST))
/* A C expression that is nonzero if REGNO is the number of a hard register in
which the values of called function may come back. */
#define FUNCTION_VALUE_REGNO_P(REGNO) \
(((REGNO) >= GR_RET_FIRST && (REGNO) <= GR_RET_LAST) \
|| ((REGNO) >= FR_RET_FIRST && (REGNO) <= FR_RET_LAST))
/* How Large Values are Returned */
/* A nonzero value says to return the function value in memory, just as large
structures are always returned. */
#define RETURN_IN_MEMORY(TYPE) \
ia64_return_in_memory (TYPE)
/* If you define this macro to be 0, then the conventions used for structure
and union return values are decided by the `RETURN_IN_MEMORY' macro. */
#define DEFAULT_PCC_STRUCT_RETURN 0
/* Caller-Saves Register Allocation */
/* A C expression to determine whether it is worthwhile to consider placing a
pseudo-register in a call-clobbered hard register and saving and restoring
it around each function call. The expression should be 1 when this is worth
doing, and 0 otherwise.
If you don't define this macro, a default is used which is good on most
machines: `4 * CALLS < REFS'. */
/* ??? Investigate. */
/* #define CALLER_SAVE_PROFITABLE(REFS, CALLS) */
/* Function Entry and Exit */
/* Define this macro as a C expression that is nonzero if the return
instruction or the function epilogue ignores the value of the stack pointer;
in other words, if it is safe to delete an instruction to adjust the stack
pointer before a return from the function. */
#define EXIT_IGNORE_STACK 1
/* Define this macro as a C expression that is nonzero for registers
used by the epilogue or the `return' pattern. */
#define EPILOGUE_USES(REGNO) ia64_epilogue_uses (REGNO)
/* Nonzero for registers used by the exception handling mechanism. */
#define EH_USES(REGNO) ia64_eh_uses (REGNO)
/* Output part N of a function descriptor for DECL. For ia64, both
words are emitted with a single relocation, so ignore N > 0. */
#define ASM_OUTPUT_FDESC(FILE, DECL, PART) \
do { \
if ((PART) == 0) \
{ \
if (TARGET_ILP32) \
fputs ("\tdata8.ua @iplt(", FILE); \
else \
fputs ("\tdata16.ua @iplt(", FILE); \
assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0)); \
fputs (")\n", FILE); \
if (TARGET_ILP32) \
fputs ("\tdata8.ua 0\n", FILE); \
} \
} while (0)
/* Generating Code for Profiling. */
/* A C statement or compound statement to output to FILE some assembler code to
call the profiling subroutine `mcount'. */
#undef FUNCTION_PROFILER
#define FUNCTION_PROFILER(FILE, LABELNO) \
do { \
char buf[20]; \
ASM_GENERATE_INTERNAL_LABEL (buf, "LP", LABELNO); \
fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", FILE); \
if (TARGET_AUTO_PIC) \
fputs ("\tmovl out3 = @gprel(", FILE); \
else \
fputs ("\taddl out3 = @ltoff(", FILE); \
assemble_name (FILE, buf); \
if (TARGET_AUTO_PIC) \
fputs (");;\n", FILE); \
else \
fputs ("), r1;;\n", FILE); \
fputs ("\tmov out1 = r1\n", FILE); \
fputs ("\tmov out2 = b0\n", FILE); \
fputs ("\tbr.call.sptk.many b0 = _mcount;;\n", FILE); \
} while (0)
/* Implementing the Varargs Macros. */
/* Define this macro to store the anonymous register arguments into the stack
so that all the arguments appear to have been passed consecutively on the
stack. */
#define SETUP_INCOMING_VARARGS(ARGS_SO_FAR, MODE, TYPE, PRETEND_ARGS_SIZE, SECOND_TIME) \
ia64_setup_incoming_varargs (ARGS_SO_FAR, MODE, TYPE, & PRETEND_ARGS_SIZE, SECOND_TIME)
/* Define this macro if the location where a function argument is passed
depends on whether or not it is a named argument. */
#define STRICT_ARGUMENT_NAMING 1
/* Trampolines for Nested Functions. */
/* We need 32 bytes, so we can save the sp, ar.rnat, ar.bsp, and ar.pfs of
the function containing a non-local goto target. */
#define STACK_SAVEAREA_MODE(LEVEL) \
((LEVEL) == SAVE_NONLOCAL ? OImode : Pmode)
/* Output assembler code for a block containing the constant parts of
a trampoline, leaving space for the variable parts.
The trampoline should set the static chain pointer to value placed
into the trampoline and should branch to the specified routine.
To make the normal indirect-subroutine calling convention work,
the trampoline must look like a function descriptor; the first
word being the target address and the second being the target's
global pointer.
We abuse the concept of a global pointer by arranging for it
to point to the data we need to load. The complete trampoline
has the following form:
+-------------------+ \
TRAMP: | __ia64_trampoline | |
+-------------------+ > fake function descriptor
| TRAMP+16 | |
+-------------------+ /
| target descriptor |
+-------------------+
| static link |
+-------------------+
*/
/* A C expression for the size in bytes of the trampoline, as an integer. */
#define TRAMPOLINE_SIZE 32
/* Alignment required for trampolines, in bits. */
#define TRAMPOLINE_ALIGNMENT 64
/* A C statement to initialize the variable parts of a trampoline. */
#define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, STATIC_CHAIN) \
ia64_initialize_trampoline((ADDR), (FNADDR), (STATIC_CHAIN))
/* Implicit Calls to Library Routines */
/* Define this macro if GCC should generate calls to the System V (and ANSI
C) library functions `memcpy' and `memset' rather than the BSD functions
`bcopy' and `bzero'. */
#define TARGET_MEM_FUNCTIONS
/* Addressing Modes */
/* Define this macro if the machine supports post-increment addressing. */
#define HAVE_POST_INCREMENT 1
#define HAVE_POST_DECREMENT 1
#define HAVE_POST_MODIFY_DISP 1
#define HAVE_POST_MODIFY_REG 1
/* A C expression that is 1 if the RTX X is a constant which is a valid
address. */
#define CONSTANT_ADDRESS_P(X) 0
/* The max number of registers that can appear in a valid memory address. */
#define MAX_REGS_PER_ADDRESS 2
/* A C compound statement with a conditional `goto LABEL;' executed if X (an
RTX) is a legitimate memory address on the target machine for a memory
operand of mode MODE. */
#define LEGITIMATE_ADDRESS_REG(X) \
((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
|| (GET_CODE (X) == SUBREG && GET_CODE (XEXP (X, 0)) == REG \
&& REG_OK_FOR_BASE_P (XEXP (X, 0))))
#define LEGITIMATE_ADDRESS_DISP(R, X) \
(GET_CODE (X) == PLUS \
&& rtx_equal_p (R, XEXP (X, 0)) \
&& (LEGITIMATE_ADDRESS_REG (XEXP (X, 1)) \
|| (GET_CODE (XEXP (X, 1)) == CONST_INT \
&& INTVAL (XEXP (X, 1)) >= -256 \
&& INTVAL (XEXP (X, 1)) < 256)))
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
do { \
if (LEGITIMATE_ADDRESS_REG (X)) \
goto LABEL; \
else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
&& LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \
&& XEXP (X, 0) != arg_pointer_rtx) \
goto LABEL; \
else if (GET_CODE (X) == POST_MODIFY \
&& LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \
&& XEXP (X, 0) != arg_pointer_rtx \
&& LEGITIMATE_ADDRESS_DISP (XEXP (X, 0), XEXP (X, 1))) \
goto LABEL; \
} while (0)
/* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
use as a base register. */
#ifdef REG_OK_STRICT
#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
#else
#define REG_OK_FOR_BASE_P(X) \
(GENERAL_REGNO_P (REGNO (X)) || (REGNO (X) >= FIRST_PSEUDO_REGISTER))
#endif
/* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
use as an index register. This is needed for POST_MODIFY. */
#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
/* A C compound statement that attempts to replace X with a valid memory
address for an operand of mode MODE.
This must be present, but there is nothing useful to be done here. */
#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)
/* A C statement or compound statement with a conditional `goto LABEL;'
executed if memory address X (an RTX) can have different meanings depending
on the machine mode of the memory reference it is used for or if the address
is valid for some modes but not others. */
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
if (GET_CODE (ADDR) == POST_DEC || GET_CODE (ADDR) == POST_INC) \
goto LABEL;
/* A C expression that is nonzero if X is a legitimate constant for an
immediate operand on the target machine. */
#define LEGITIMATE_CONSTANT_P(X) \
(GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \
|| GET_MODE (X) == DImode || CONST_DOUBLE_OK_FOR_G (X)) \
/* Condition Code Status */
/* One some machines not all possible comparisons are defined, but you can
convert an invalid comparison into a valid one. */
/* ??? Investigate. See the alpha definition. */
/* #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) */
/* Describing Relative Costs of Operations */
/* A C expression for the cost of moving data from a register in class FROM to
one in class TO, using MODE. */
#define REGISTER_MOVE_COST ia64_register_move_cost
/* A C expression for the cost of moving data of mode M between a
register and memory. */
#define MEMORY_MOVE_COST(MODE,CLASS,IN) \
((CLASS) == GENERAL_REGS || (CLASS) == FR_REGS \
|| (CLASS) == GR_AND_FR_REGS ? 4 : 10)
/* A C expression for the cost of a branch instruction. A value of 1 is the
default; other values are interpreted relative to that. Used by the
if-conversion code as max instruction count. */
/* ??? This requires investigation. The primary effect might be how
many additional insn groups we run into, vs how good the dynamic
branch predictor is. */
#define BRANCH_COST 6
/* Define this macro as a C expression which is nonzero if accessing less than
a word of memory (i.e. a `char' or a `short') is no faster than accessing a
word of memory. */
#define SLOW_BYTE_ACCESS 1
/* Define this macro if it is as good or better to call a constant function
address than to call an address kept in a register.
Indirect function calls are more expensive that direct function calls, so
don't cse function addresses. */
#define NO_FUNCTION_CSE
/* Dividing the output into sections. */
/* A C expression whose value is a string containing the assembler operation
that should precede instructions and read-only data. */
#define TEXT_SECTION_ASM_OP "\t.text"
/* A C expression whose value is a string containing the assembler operation to
identify the following data as writable initialized data. */
#define DATA_SECTION_ASM_OP "\t.data"
/* If defined, a C expression whose value is a string containing the assembler
operation to identify the following data as uninitialized global data. */
#define BSS_SECTION_ASM_OP "\t.bss"
#define IA64_DEFAULT_GVALUE 8
/* Position Independent Code. */
/* The register number of the register used to address a table of static data
addresses in memory. */
/* ??? Should modify ia64.md to use pic_offset_table_rtx instead of
gen_rtx_REG (DImode, 1). */
/* ??? Should we set flag_pic? Probably need to define
LEGITIMIZE_PIC_OPERAND_P to make that work. */
#define PIC_OFFSET_TABLE_REGNUM GR_REG (1)
/* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is
clobbered by calls. */
#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
/* The Overall Framework of an Assembler File. */
/* A C string constant describing how to begin a comment in the target
assembler language. The compiler assumes that the comment will end at the
end of the line. */
#define ASM_COMMENT_START "//"
/* A C string constant for text to be output before each `asm' statement or
group of consecutive ones. */
#define ASM_APP_ON (TARGET_GNU_AS ? "#APP\n" : "//APP\n")
/* A C string constant for text to be output after each `asm' statement or
group of consecutive ones. */
#define ASM_APP_OFF (TARGET_GNU_AS ? "#NO_APP\n" : "//NO_APP\n")
/* Output of Uninitialized Variables. */
/* This is all handled by svr4.h. */
/* Output and Generation of Labels. */
/* A C statement (sans semicolon) to output to the stdio stream STREAM the
assembler definition of a label named NAME. */
/* See the ASM_OUTPUT_LABELREF definition in sysv4.h for an explanation of
why ia64_asm_output_label exists. */
extern int ia64_asm_output_label;
#define ASM_OUTPUT_LABEL(STREAM, NAME) \
do { \
ia64_asm_output_label = 1; \
assemble_name (STREAM, NAME); \
fputs (":\n", STREAM); \
ia64_asm_output_label = 0; \
} while (0)
/* Globalizing directive for a label. */
#define GLOBAL_ASM_OP "\t.global "
/* A C statement (sans semicolon) to output to the stdio stream STREAM any text
necessary for declaring the name of an external symbol named NAME which is
referenced in this compilation but not defined. */
#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
ia64_asm_output_external (FILE, DECL, NAME)
/* A C statement to store into the string STRING a label whose name is made
from the string PREFIX and the number NUM. */
#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
do { \
sprintf (LABEL, "*.%s%d", PREFIX, NUM); \
} while (0)
/* ??? Not sure if using a ? in the name for Intel as is safe. */
#define ASM_PN_FORMAT (TARGET_GNU_AS ? "%s.%lu" : "%s?%lu")
/* A C statement to output to the stdio stream STREAM assembler code which
defines (equates) the symbol NAME to have the value VALUE. */
#define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
do { \
assemble_name (STREAM, NAME); \
fputs (" = ", STREAM); \
assemble_name (STREAM, VALUE); \
fputc ('\n', STREAM); \
} while (0)
/* Macros Controlling Initialization Routines. */
/* This is handled by svr4.h and sysv4.h. */
/* Output of Assembler Instructions. */
/* A C initializer containing the assembler's names for the machine registers,
each one as a C string constant. */
#define REGISTER_NAMES \
{ \
/* General registers. */ \
"ap", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \
"r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \
"r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \
"r30", "r31", \
/* Local registers. */ \
"loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", \
"loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", \
"loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", \
"loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", \
"loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", \
"loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", \
"loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", \
"loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", \
"loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", \
"loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79", \
/* Input registers. */ \
"in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7", \
/* Output registers. */ \
"out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7", \
/* Floating-point registers. */ \
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \
"f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \
"f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \
"f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", \
"f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", \
"f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", \
"f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69", \
"f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", \
"f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89", \
"f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99", \
"f100","f101","f102","f103","f104","f105","f106","f107","f108","f109",\
"f110","f111","f112","f113","f114","f115","f116","f117","f118","f119",\
"f120","f121","f122","f123","f124","f125","f126","f127", \
/* Predicate registers. */ \
"p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", \
"p10", "p11", "p12", "p13", "p14", "p15", "p16", "p17", "p18", "p19", \
"p20", "p21", "p22", "p23", "p24", "p25", "p26", "p27", "p28", "p29", \
"p30", "p31", "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", \
"p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", "p48", "p49", \
"p50", "p51", "p52", "p53", "p54", "p55", "p56", "p57", "p58", "p59", \
"p60", "p61", "p62", "p63", \
/* Branch registers. */ \
"b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", \
/* Frame pointer. Application registers. */ \
"sfp", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \
}
/* If defined, a C initializer for an array of structures containing a name and
a register number. This macro defines additional names for hard registers,
thus allowing the `asm' option in declarations to refer to registers using
alternate names. */
#define ADDITIONAL_REGISTER_NAMES \
{ \
{ "gp", R_GR (1) }, \
{ "sp", R_GR (12) }, \
{ "in0", IN_REG (0) }, \
{ "in1", IN_REG (1) }, \
{ "in2", IN_REG (2) }, \
{ "in3", IN_REG (3) }, \
{ "in4", IN_REG (4) }, \
{ "in5", IN_REG (5) }, \
{ "in6", IN_REG (6) }, \
{ "in7", IN_REG (7) }, \
{ "out0", OUT_REG (0) }, \
{ "out1", OUT_REG (1) }, \
{ "out2", OUT_REG (2) }, \
{ "out3", OUT_REG (3) }, \
{ "out4", OUT_REG (4) }, \
{ "out5", OUT_REG (5) }, \
{ "out6", OUT_REG (6) }, \
{ "out7", OUT_REG (7) }, \
{ "loc0", LOC_REG (0) }, \
{ "loc1", LOC_REG (1) }, \
{ "loc2", LOC_REG (2) }, \
{ "loc3", LOC_REG (3) }, \
{ "loc4", LOC_REG (4) }, \
{ "loc5", LOC_REG (5) }, \
{ "loc6", LOC_REG (6) }, \
{ "loc7", LOC_REG (7) }, \
{ "loc8", LOC_REG (8) }, \
{ "loc9", LOC_REG (9) }, \
{ "loc10", LOC_REG (10) }, \
{ "loc11", LOC_REG (11) }, \
{ "loc12", LOC_REG (12) }, \
{ "loc13", LOC_REG (13) }, \
{ "loc14", LOC_REG (14) }, \
{ "loc15", LOC_REG (15) }, \
{ "loc16", LOC_REG (16) }, \
{ "loc17", LOC_REG (17) }, \
{ "loc18", LOC_REG (18) }, \
{ "loc19", LOC_REG (19) }, \
{ "loc20", LOC_REG (20) }, \
{ "loc21", LOC_REG (21) }, \
{ "loc22", LOC_REG (22) }, \
{ "loc23", LOC_REG (23) }, \
{ "loc24", LOC_REG (24) }, \
{ "loc25", LOC_REG (25) }, \
{ "loc26", LOC_REG (26) }, \
{ "loc27", LOC_REG (27) }, \
{ "loc28", LOC_REG (28) }, \
{ "loc29", LOC_REG (29) }, \
{ "loc30", LOC_REG (30) }, \
{ "loc31", LOC_REG (31) }, \
{ "loc32", LOC_REG (32) }, \
{ "loc33", LOC_REG (33) }, \
{ "loc34", LOC_REG (34) }, \
{ "loc35", LOC_REG (35) }, \
{ "loc36", LOC_REG (36) }, \
{ "loc37", LOC_REG (37) }, \
{ "loc38", LOC_REG (38) }, \
{ "loc39", LOC_REG (39) }, \
{ "loc40", LOC_REG (40) }, \
{ "loc41", LOC_REG (41) }, \
{ "loc42", LOC_REG (42) }, \
{ "loc43", LOC_REG (43) }, \
{ "loc44", LOC_REG (44) }, \
{ "loc45", LOC_REG (45) }, \
{ "loc46", LOC_REG (46) }, \
{ "loc47", LOC_REG (47) }, \
{ "loc48", LOC_REG (48) }, \
{ "loc49", LOC_REG (49) }, \
{ "loc50", LOC_REG (50) }, \
{ "loc51", LOC_REG (51) }, \
{ "loc52", LOC_REG (52) }, \
{ "loc53", LOC_REG (53) }, \
{ "loc54", LOC_REG (54) }, \
{ "loc55", LOC_REG (55) }, \
{ "loc56", LOC_REG (56) }, \
{ "loc57", LOC_REG (57) }, \
{ "loc58", LOC_REG (58) }, \
{ "loc59", LOC_REG (59) }, \
{ "loc60", LOC_REG (60) }, \
{ "loc61", LOC_REG (61) }, \
{ "loc62", LOC_REG (62) }, \
{ "loc63", LOC_REG (63) }, \
{ "loc64", LOC_REG (64) }, \
{ "loc65", LOC_REG (65) }, \
{ "loc66", LOC_REG (66) }, \
{ "loc67", LOC_REG (67) }, \
{ "loc68", LOC_REG (68) }, \
{ "loc69", LOC_REG (69) }, \
{ "loc70", LOC_REG (70) }, \
{ "loc71", LOC_REG (71) }, \
{ "loc72", LOC_REG (72) }, \
{ "loc73", LOC_REG (73) }, \
{ "loc74", LOC_REG (74) }, \
{ "loc75", LOC_REG (75) }, \
{ "loc76", LOC_REG (76) }, \
{ "loc77", LOC_REG (77) }, \
{ "loc78", LOC_REG (78) }, \
{ "loc79", LOC_REG (79) }, \
}
/* Emit a dtp-relative reference to a TLS variable. */
#ifdef HAVE_AS_TLS
#define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
ia64_output_dwarf_dtprel (FILE, SIZE, X)
#endif
/* A C compound statement to output to stdio stream STREAM the assembler syntax
for an instruction operand X. X is an RTL expression. */
#define PRINT_OPERAND(STREAM, X, CODE) \
ia64_print_operand (STREAM, X, CODE)
/* A C expression which evaluates to true if CODE is a valid punctuation
character for use in the `PRINT_OPERAND' macro. */
/* ??? Keep this around for now, as we might need it later. */
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
((CODE) == '+' || (CODE) == ',')
/* A C compound statement to output to stdio stream STREAM the assembler syntax
for an instruction operand that is a memory reference whose address is X. X
is an RTL expression. */
#define PRINT_OPERAND_ADDRESS(STREAM, X) \
ia64_print_operand_address (STREAM, X)
/* If defined, C string expressions to be used for the `%R', `%L', `%U', and
`%I' options of `asm_fprintf' (see `final.c'). */
#define REGISTER_PREFIX ""
#define LOCAL_LABEL_PREFIX "."
#define USER_LABEL_PREFIX ""
#define IMMEDIATE_PREFIX ""
/* Output of dispatch tables. */
/* This macro should be provided on machines where the addresses in a dispatch
table are relative to the table's own address. */
/* ??? Depends on the pointer size. */
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
do { \
if (TARGET_ILP32) \
fprintf (STREAM, "\tdata4 @pcrel(.L%d)\n", VALUE); \
else \
fprintf (STREAM, "\tdata8 @pcrel(.L%d)\n", VALUE); \
} while (0)
/* This is how to output an element of a case-vector that is absolute.
(Ia64 does not use such vectors, but we must define this macro anyway.) */
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) abort ()
/* Jump tables only need 8 byte alignment. */
#define ADDR_VEC_ALIGN(ADDR_VEC) 3
/* Assembler Commands for Exception Regions. */
/* Select a format to encode pointers in exception handling data. CODE
is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
true if the symbol may be affected by dynamic relocations. */
#define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
(((CODE) == 1 ? DW_EH_PE_textrel : DW_EH_PE_datarel) \
| ((GLOBAL) ? DW_EH_PE_indirect : 0) \
| (TARGET_ILP32 ? DW_EH_PE_udata4 : DW_EH_PE_udata8))
/* Handle special EH pointer encodings. Absolute, pc-relative, and
indirect are handled automatically. */
#define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
do { \
const char *reltag = NULL; \
if (((ENCODING) & 0xF0) == DW_EH_PE_textrel) \
reltag = "@segrel("; \
else if (((ENCODING) & 0xF0) == DW_EH_PE_datarel) \
reltag = "@gprel("; \
if (reltag) \
{ \
fputs (integer_asm_op (SIZE, FALSE), FILE); \
fputs (reltag, FILE); \
assemble_name (FILE, XSTR (ADDR, 0)); \
fputc (')', FILE); \
goto DONE; \
} \
} while (0)
/* Assembler Commands for Alignment. */
/* ??? Investigate. */
/* The alignment (log base 2) to put in front of LABEL, which follows
a BARRIER. */
/* #define LABEL_ALIGN_AFTER_BARRIER(LABEL) */
/* The desired alignment for the location counter at the beginning
of a loop. */
/* #define LOOP_ALIGN(LABEL) */
/* Define this macro if `ASM_OUTPUT_SKIP' should not be used in the text
section because it fails put zeros in the bytes that are skipped. */
#define ASM_NO_SKIP_IN_TEXT 1
/* A C statement to output to the stdio stream STREAM an assembler command to
advance the location counter to a multiple of 2 to the POWER bytes. */
#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
fprintf (STREAM, "\t.align %d\n", 1<<(POWER))
/* Macros Affecting all Debug Formats. */
/* This is handled in svr4.h and sysv4.h. */
/* Specific Options for DBX Output. */
/* This is handled by dbxelf.h which is included by svr4.h. */
/* Open ended Hooks for DBX Output. */
/* Likewise. */
/* File names in DBX format. */
/* Likewise. */
/* Macros for SDB and Dwarf Output. */
/* Define this macro if GCC should produce dwarf version 2 format debugging
output in response to the `-g' option. */
#define DWARF2_DEBUGGING_INFO 1
#define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM)
/* Use tags for debug info labels, so that they don't break instruction
bundles. This also avoids getting spurious DV warnings from the
assembler. This is similar to (*targetm.asm_out.internal_label), except that we
add brackets around the label. */
#define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
fprintf (FILE, TARGET_GNU_AS ? "[.%s%d:]\n" : ".%s%d:\n", PREFIX, NUM)
/* Use section-relative relocations for debugging offsets. Unlike other
targets that fake this by putting the section VMA at 0, IA-64 has
proper relocations for them. */
#define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL) \
do { \
fputs (integer_asm_op (SIZE, FALSE), FILE); \
fputs ("@secrel(", FILE); \
assemble_name (FILE, LABEL); \
fputc (')', FILE); \
} while (0)
/* Emit a PC-relative relocation. */
#define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
do { \
fputs (integer_asm_op (SIZE, FALSE), FILE); \
fputs ("@pcrel(", FILE); \
assemble_name (FILE, LABEL); \
fputc (')', FILE); \
} while (0)
/* Register Renaming Parameters. */
/* A C expression that is nonzero if hard register number REGNO2 can be
considered for use as a rename register for REGNO1 */
#define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
ia64_hard_regno_rename_ok((REGNO1), (REGNO2))
/* Miscellaneous Parameters. */
/* Flag to mark data that is in the small address area (addressable
via "addl", that is, within a 2MByte offset of 0. */
#define SYMBOL_FLAG_SMALL_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
#define SYMBOL_REF_SMALL_ADDR_P(X) \
((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SMALL_ADDR) != 0)
/* Define this if you have defined special-purpose predicates in the file
`MACHINE.c'. For each predicate, list all rtl codes that can be in
expressions matched by the predicate. */
#define PREDICATE_CODES \
{ "call_operand", {SUBREG, REG, SYMBOL_REF}}, \
{ "got_symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
{ "sdata_symbolic_operand", {SYMBOL_REF, CONST}}, \
{ "small_addr_symbolic_operand", {SYMBOL_REF}}, \
{ "symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
{ "function_operand", {SYMBOL_REF}}, \
{ "setjmp_operand", {SYMBOL_REF}}, \
{ "destination_operand", {SUBREG, REG, MEM}}, \
{ "not_postinc_memory_operand", {MEM}}, \
{ "move_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
CONSTANT_P_RTX, SYMBOL_REF, CONST, LABEL_REF}}, \
{ "gr_register_operand", {SUBREG, REG}}, \
{ "fr_register_operand", {SUBREG, REG}}, \
{ "grfr_register_operand", {SUBREG, REG}}, \
{ "gr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
{ "fr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
{ "grfr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
{ "gr_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
{ "gr_reg_or_5bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
{ "gr_reg_or_6bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
{ "gr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
{ "grfr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
{ "gr_reg_or_8bit_adjusted_operand", {SUBREG, REG, CONST_INT, \
CONSTANT_P_RTX}}, \
{ "gr_reg_or_8bit_and_adjusted_operand", {SUBREG, REG, CONST_INT, \
CONSTANT_P_RTX}}, \
{ "gr_reg_or_14bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
{ "gr_reg_or_22bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
{ "shift_count_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
{ "shift_32bit_count_operand", {SUBREG, REG, CONST_INT, \
CONSTANT_P_RTX}}, \
{ "shladd_operand", {CONST_INT}}, \
{ "fetchadd_operand", {CONST_INT}}, \
{ "fr_reg_or_fp01_operand", {SUBREG, REG, CONST_DOUBLE}}, \
{ "normal_comparison_operator", {EQ, NE, GT, LE, GTU, LEU}}, \
{ "adjusted_comparison_operator", {LT, GE, LTU, GEU}}, \
{ "signed_inequality_operator", {GE, GT, LE, LT}}, \
{ "predicate_operator", {NE, EQ}}, \
{ "condop_operator", {PLUS, MINUS, IOR, XOR, AND}}, \
{ "ar_lc_reg_operand", {REG}}, \
{ "ar_ccv_reg_operand", {REG}}, \
{ "ar_pfs_reg_operand", {REG}}, \
{ "general_xfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
{ "destination_xfmode_operand", {SUBREG, REG, MEM}}, \
{ "xfreg_or_fp01_operand", {REG, CONST_DOUBLE}}, \
{ "basereg_operand", {SUBREG, REG}},
/* An alias for a machine mode name. This is the machine mode that elements of
a jump-table should have. */
#define CASE_VECTOR_MODE ptr_mode
/* Define as C expression which evaluates to nonzero if the tablejump
instruction expects the table to contain offsets from the address of the
table. */
#define CASE_VECTOR_PC_RELATIVE 1
/* Define this macro if operations between registers with integral mode smaller
than a word are always performed on the entire register. */
#define WORD_REGISTER_OPERATIONS
/* Define this macro to be a C expression indicating when insns that read
memory in MODE, an integral mode narrower than a word, set the bits outside
of MODE to be either the sign-extension or the zero-extension of the data
read. */
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
/* The maximum number of bytes that a single instruction can move quickly from
memory to memory. */
#define MOVE_MAX 8
/* A C expression which is nonzero if on this machine it is safe to "convert"
an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller
than INPREC) by merely operating on it as if it had only OUTPREC bits. */
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
/* A C expression describing the value returned by a comparison operator with
an integral mode and stored by a store-flag instruction (`sCOND') when the
condition is true. */
/* ??? Investigate using STORE_FLAG_VALUE of -1 instead of 1. */
/* An alias for the machine mode for pointers. */
/* ??? This would change if we had ILP32 support. */
#define Pmode DImode
/* An alias for the machine mode used for memory references to functions being
called, in `call' RTL expressions. */
#define FUNCTION_MODE Pmode
/* Define this macro to handle System V style pragmas: #pragma pack and
#pragma weak. Note, #pragma weak will only be supported if SUPPORT_WEAK is
defined. */
/* If this architecture supports prefetch, define this to be the number of
prefetch commands that can be executed in parallel.
??? This number is bogus and needs to be replaced before the value is
actually used in optimizations. */
#define SIMULTANEOUS_PREFETCHES 6
/* If this architecture supports prefetch, define this to be the size of
the cache line that is prefetched. */
#define PREFETCH_BLOCK 32
#define HANDLE_SYSV_PRAGMA 1
/* A C expression for the maximum number of instructions to execute via
conditional execution instructions instead of a branch. A value of
BRANCH_COST+1 is the default if the machine does not use
cc0, and 1 if it does use cc0. */
/* ??? Investigate. */
#define MAX_CONDITIONAL_EXECUTE 12
extern int ia64_final_schedule;
#define IA64_UNWIND_INFO 1
#define IA64_UNWIND_EMIT(f,i) process_for_unwind_directive (f,i)
#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM)
/* This function contains machine specific function data. */
struct machine_function GTY(())
{
/* The new stack pointer when unwinding from EH. */
rtx ia64_eh_epilogue_sp;
/* The new bsp value when unwinding from EH. */
rtx ia64_eh_epilogue_bsp;
/* The GP value save register. */
rtx ia64_gp_save;
/* The number of varargs registers to save. */
int n_varargs;
};
enum ia64_builtins
{
IA64_BUILTIN_SYNCHRONIZE,
IA64_BUILTIN_FETCH_AND_ADD_SI,
IA64_BUILTIN_FETCH_AND_SUB_SI,
IA64_BUILTIN_FETCH_AND_OR_SI,
IA64_BUILTIN_FETCH_AND_AND_SI,
IA64_BUILTIN_FETCH_AND_XOR_SI,
IA64_BUILTIN_FETCH_AND_NAND_SI,
IA64_BUILTIN_ADD_AND_FETCH_SI,
IA64_BUILTIN_SUB_AND_FETCH_SI,
IA64_BUILTIN_OR_AND_FETCH_SI,
IA64_BUILTIN_AND_AND_FETCH_SI,
IA64_BUILTIN_XOR_AND_FETCH_SI,
IA64_BUILTIN_NAND_AND_FETCH_SI,
IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI,
IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI,
IA64_BUILTIN_SYNCHRONIZE_SI,
IA64_BUILTIN_LOCK_TEST_AND_SET_SI,
IA64_BUILTIN_LOCK_RELEASE_SI,
IA64_BUILTIN_FETCH_AND_ADD_DI,
IA64_BUILTIN_FETCH_AND_SUB_DI,
IA64_BUILTIN_FETCH_AND_OR_DI,
IA64_BUILTIN_FETCH_AND_AND_DI,
IA64_BUILTIN_FETCH_AND_XOR_DI,
IA64_BUILTIN_FETCH_AND_NAND_DI,
IA64_BUILTIN_ADD_AND_FETCH_DI,
IA64_BUILTIN_SUB_AND_FETCH_DI,
IA64_BUILTIN_OR_AND_FETCH_DI,
IA64_BUILTIN_AND_AND_FETCH_DI,
IA64_BUILTIN_XOR_AND_FETCH_DI,
IA64_BUILTIN_NAND_AND_FETCH_DI,
IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI,
IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI,
IA64_BUILTIN_SYNCHRONIZE_DI,
IA64_BUILTIN_LOCK_TEST_AND_SET_DI,
IA64_BUILTIN_LOCK_RELEASE_DI,
IA64_BUILTIN_BSP,
IA64_BUILTIN_FLUSHRS
};
/* Codes for expand_compare_and_swap and expand_swap_and_compare. */
enum fetchop_code {
IA64_ADD_OP, IA64_SUB_OP, IA64_OR_OP, IA64_AND_OP, IA64_XOR_OP, IA64_NAND_OP
};
#define DONT_USE_BUILTIN_SETJMP
/* Output any profiling code before the prologue. */
#undef PROFILE_BEFORE_PROLOGUE
#define PROFILE_BEFORE_PROLOGUE 1
/* Switch on code for querying unit reservations. */
#define CPU_UNITS_QUERY 1
/* End of ia64.h */
|