1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
|
.\" $FreeBSD$
.\"
.\"
.\" Automatically generated by Pod::Man v1.3, Pod::Parser v1.13
.\"
.\" Standard preamble:
.\" ========================================================================
.de Sh \" Subsection heading
.br
.if t .Sp
.ne 5
.PP
\fB\\$1\fR
.PP
..
.de Sp \" Vertical space (when we can't use .PP)
.if t .sp .5v
.if n .sp
..
.de Vb \" Begin verbatim text
.ft CW
.nf
.ne \\$1
..
.de Ve \" End verbatim text
.ft R
.fi
..
.\" Set up some character translations and predefined strings. \*(-- will
.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left
.\" double quote, and \*(R" will give a right double quote. | will give a
.\" real vertical bar. \*(C+ will give a nicer C++. Capital omega is used to
.\" do unbreakable dashes and therefore won't be available. \*(C` and \*(C'
.\" expand to `' in nroff, nothing in troff, for use with C<>.
.tr \(*W-|\(bv\*(Tr
.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p'
.ie n \{\
. ds -- \(*W-
. ds PI pi
. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch
. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch
. ds L" ""
. ds R" ""
. ds C` ""
. ds C' ""
'br\}
.el\{\
. ds -- \|\(em\|
. ds PI \(*p
. ds L" ``
. ds R" ''
'br\}
.\"
.\" If the F register is turned on, we'll generate index entries on stderr for
.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index
.\" entries marked with X<> in POD. Of course, you'll have to process the
.\" output yourself in some meaningful fashion.
.if \nF \{\
. de IX
. tm Index:\\$1\t\\n%\t"\\$2"
..
. nr % 0
. rr F
.\}
.\"
.\" For nroff, turn off justification. Always turn off hyphenation; it makes
.\" way too many mistakes in technical documents.
.hy 0
.\"
.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2).
.\" Fear. Run. Save yourself. No user-serviceable parts.
. \" fudge factors for nroff and troff
.if n \{\
. ds #H 0
. ds #V .8m
. ds #F .3m
. ds #[ \f1
. ds #] \fP
.\}
.if t \{\
. ds #H ((1u-(\\\\n(.fu%2u))*.13m)
. ds #V .6m
. ds #F 0
. ds #[ \&
. ds #] \&
.\}
. \" simple accents for nroff and troff
.if n \{\
. ds ' \&
. ds ` \&
. ds ^ \&
. ds , \&
. ds ~ ~
. ds /
.\}
.if t \{\
. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u"
. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u'
. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u'
. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u'
. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u'
. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u'
.\}
. \" troff and (daisy-wheel) nroff accents
.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V'
.ds 8 \h'\*(#H'\(*b\h'-\*(#H'
.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#]
.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H'
.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u'
.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#]
.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#]
.ds ae a\h'-(\w'a'u*4/10)'e
.ds Ae A\h'-(\w'A'u*4/10)'E
. \" corrections for vroff
.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u'
.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u'
. \" for low resolution devices (crt and lpr)
.if \n(.H>23 .if \n(.V>19 \
\{\
. ds : e
. ds 8 ss
. ds o a
. ds d- d\h'-1'\(ga
. ds D- D\h'-1'\(hy
. ds th \o'bp'
. ds Th \o'LP'
. ds ae ae
. ds Ae AE
.\}
.rm #[ #] #H #V #F C
.\" ========================================================================
.\"
.IX Title "AS 1"
.TH AS 1 "2002-05-14" "binutils-2.12.1" "GNU Development Tools"
.UC
.SH "NAME"
\&\s-1AS\s0 \- the portable \s-1GNU\s0 assembler.
.SH "SYNOPSIS"
.IX Header "SYNOPSIS"
as [\fB\-a\fR[\fBcdhlns\fR][=\fIfile\fR]] [\fB\-D\fR] [\fB\-\-defsym\fR \fIsym\fR=\fIval\fR]
[\fB\-f\fR] [\fB\-\-gstabs\fR] [\fB\-\-gdwarf2\fR] [\fB\-\-help\fR] [\fB\-I\fR \fIdir\fR]
[\fB\-J\fR] [\fB\-K\fR] [\fB\-L\fR]
[\fB\-\-listing\-lhs\-width\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-lhs\-width2\fR=\fI\s-1NUM\s0\fR]
[\fB\-\-listing\-rhs\-width\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-cont\-lines\fR=\fI\s-1NUM\s0\fR]
[\fB\-\-keep\-locals\fR] [\fB\-o\fR \fIobjfile\fR] [\fB\-R\fR] [\fB\-\-statistics\fR] [\fB\-v\fR]
[\fB\-version\fR] [\fB\-\-version\fR] [\fB\-W\fR] [\fB\-\-warn\fR] [\fB\-\-fatal\-warnings\fR]
[\fB\-w\fR] [\fB\-x\fR] [\fB\-Z\fR] [\fB\-\-target\-help\fR] [\fItarget-options\fR]
[\fB\-\-\fR|\fIfiles\fR ...]
.PP
\&\fITarget Alpha options:\fR
[\fB\-m\fR\fIcpu\fR]
[\fB\-mdebug\fR | \fB\-no\-mdebug\fR]
[\fB\-relax\fR] [\fB\-g\fR] [\fB\-G\fR\fIsize\fR]
[\fB\-F\fR] [\fB\-32addr\fR]
.PP
\&\fITarget \s-1ARC\s0 options:\fR
[\fB\-marc[5|6|7|8]\fR]
[\fB\-EB\fR|\fB\-EL\fR]
.PP
\&\fITarget \s-1ARM\s0 options:\fR
[\fB\-mcpu\fR=\fIprocessor\fR[+\fIextension\fR...]]
[\fB\-march\fR=\fIarchitecture\fR[+\fIextension\fR...]]
[\fB\-mfpu\fR=\fIfloating-point-fromat\fR]
[\fB\-mthumb\fR]
[\fB\-EB\fR|\fB\-EL\fR]
[\fB\-mapcs\-32\fR|\fB\-mapcs\-26\fR|\fB\-mapcs\-float\fR|
\fB\-mapcs\-reentrant\fR]
[\fB\-mthumb\-interwork\fR] [\fB\-moabi\fR] [\fB\-k\fR]
.PP
\&\fITarget \s-1CRIS\s0 options:\fR
[\fB\-\-underscore\fR | \fB\-\-no\-underscore\fR]
[\fB\-\-pic\fR] [\fB\-N\fR]
[\fB\-\-emulation=criself\fR | \fB\-\-emulation=crisaout\fR]
.PP
\&\fITarget D10V options:\fR
[\fB\-O\fR]
.PP
\&\fITarget D30V options:\fR
[\fB\-O\fR|\fB\-n\fR|\fB\-N\fR]
.PP
\&\fITarget i386 options:\fR
[\fB\-\-32\fR|\fB\-\-64\fR]
.PP
\&\fITarget i960 options:\fR
[\fB\-ACA\fR|\fB\-ACA_A\fR|\fB\-ACB\fR|\fB\-ACC\fR|\fB\-AKA\fR|\fB\-AKB\fR|
\fB\-AKC\fR|\fB\-AMC\fR]
[\fB\-b\fR] [\fB\-no\-relax\fR]
.PP
\&\fITarget M32R options:\fR
[\fB\-\-m32rx\fR|\fB\-\-[no\-]warn\-explicit\-parallel\-conflicts\fR|
\fB\-\-W[n]p\fR]
.PP
\&\fITarget M680X0 options:\fR
[\fB\-l\fR] [\fB\-m68000\fR|\fB\-m68010\fR|\fB\-m68020\fR|...]
.PP
\&\fITarget M68HC11 options:\fR
[\fB\-m68hc11\fR|\fB\-m68hc12\fR]
[\fB\-\-force\-long\-branchs\fR] [\fB\-\-short\-branchs\fR]
[\fB\-\-strict\-direct\-mode\fR] [\fB\-\-print\-insn\-syntax\fR]
[\fB\-\-print\-opcodes\fR] [\fB\-\-generate\-example\fR]
.PP
\&\fITarget \s-1MCORE\s0 options:\fR
[\fB\-jsri2bsr\fR] [\fB\-sifilter\fR] [\fB\-relax\fR]
[\fB\-mcpu=[210|340]\fR]
.PP
\&\fITarget \s-1MIPS\s0 options:\fR
[\fB\-nocpp\fR] [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-G\fR \fInum\fR] [\fB\-mcpu\fR=\fI\s-1CPU\s0\fR ]
[\fB\-mips1\fR] [\fB\-mips2\fR] [\fB\-mips3\fR] [\fB\-mips4\fR] [\fB\-mips5\fR]
[\fB\-mips32\fR] [\fB\-mips64\fR]
[\fB\-m4650\fR] [\fB\-no\-m4650\fR]
[\fB\-\-trap\fR] [\fB\-\-break\fR] [\fB\-n\fR]
[\fB\-\-emulation\fR=\fIname\fR ]
.PP
\&\fITarget \s-1MMIX\s0 options:\fR
[\fB\-\-fixed\-special\-register\-names\fR] [\fB\-\-globalize\-symbols\fR]
[\fB\-\-gnu\-syntax\fR] [\fB\-\-relax\fR] [\fB\-\-no\-predefined\-symbols\fR]
[\fB\-\-no\-expand\fR] [\fB\-\-no\-merge\-gregs\fR] [\fB\-x\fR]
[\fB\-\-linker\-allocated\-gregs\fR]
.PP
\&\fITarget \s-1PDP11\s0 options:\fR
[\fB\-mpic\fR|\fB\-mno\-pic\fR] [\fB\-mall\fR] [\fB\-mno\-extensions\fR]
[\fB\-m\fR\fIextension\fR|\fB\-mno\-\fR\fIextension\fR]
[\fB\-m\fR\fIcpu\fR] [\fB\-m\fR\fImachine\fR]
.PP
\&\fITarget picoJava options:\fR
[\fB\-mb\fR|\fB\-me\fR]
.PP
\&\fITarget PowerPC options:\fR
[\fB\-mpwrx\fR|\fB\-mpwr2\fR|\fB\-mpwr\fR|\fB\-m601\fR|\fB\-mppc\fR|\fB\-mppc32\fR|\fB\-m603\fR|\fB\-m604\fR|
\fB\-m403\fR|\fB\-m405\fR|\fB\-mppc64\fR|\fB\-m620\fR|\fB\-mppc64bridge\fR|\fB\-mbooke\fR|
\fB\-mbooke32\fR|\fB\-mbooke64\fR]
[\fB\-mcom\fR|\fB\-many\fR|\fB\-maltivec\fR] [\fB\-memb\fR]
[\fB\-mregnames\fR|\fB\-mno\-regnames\fR]
[\fB\-mrelocatable\fR|\fB\-mrelocatable\-lib\fR]
[\fB\-mlittle\fR|\fB\-mlittle\-endian\fR|\fB\-mbig\fR|\fB\-mbig\-endian\fR]
[\fB\-msolaris\fR|\fB\-mno\-solaris\fR]
.PP
\&\fITarget \s-1SPARC\s0 options:\fR
[\fB\-Av6\fR|\fB\-Av7\fR|\fB\-Av8\fR|\fB\-Asparclet\fR|\fB\-Asparclite\fR
\fB\-Av8plus\fR|\fB\-Av8plusa\fR|\fB\-Av9\fR|\fB\-Av9a\fR]
[\fB\-xarch=v8plus\fR|\fB\-xarch=v8plusa\fR] [\fB\-bump\fR]
[\fB\-32\fR|\fB\-64\fR]
.SH "DESCRIPTION"
.IX Header "DESCRIPTION"
\&\s-1GNU\s0 \fBas\fR is really a family of assemblers.
If you use (or have used) the \s-1GNU\s0 assembler on one architecture, you
should find a fairly similar environment when you use it on another
architecture. Each version has much in common with the others,
including object file formats, most assembler directives (often called
\&\fIpseudo-ops\fR) and assembler syntax.
.PP
\&\fBas\fR is primarily intended to assemble the output of the
\&\s-1GNU\s0 C compiler for use by the linker
\&. Nevertheless, we've tried to make \fBas\fR
assemble correctly everything that other assemblers for the same
machine would assemble.
Any exceptions are documented explicitly.
This doesn't mean \fBas\fR always uses the same syntax as another
assembler for the same architecture; for example, we know of several
incompatible versions of 680x0 assembly language syntax.
.PP
Each time you run \fBas\fR it assembles exactly one source
program. The source program is made up of one or more files.
(The standard input is also a file.)
.PP
You give \fBas\fR a command line that has zero or more input file
names. The input files are read (from left file name to right). A
command line argument (in any position) that has no special meaning
is taken to be an input file name.
.PP
If you give \fBas\fR no file names it attempts to read one input file
from the \fBas\fR standard input, which is normally your terminal. You
may have to type \fBctl-D\fR to tell \fBas\fR there is no more program
to assemble.
.PP
Use \fB\-\-\fR if you need to explicitly name the standard input file
in your command line.
.PP
If the source is empty, \fBas\fR produces a small, empty object
file.
.PP
\&\fBas\fR may write warnings and error messages to the standard error
file (usually your terminal). This should not happen when a compiler
runs \fBas\fR automatically. Warnings report an assumption made so
that \fBas\fR could keep assembling a flawed program; errors report a
grave problem that stops the assembly.
.PP
If you are invoking \fBas\fR via the \s-1GNU\s0 C compiler (version 2),
you can use the \fB\-Wa\fR option to pass arguments through to the assembler.
The assembler arguments must be separated from each other (and the \fB\-Wa\fR)
by commas. For example:
.PP
.Vb 1
\& gcc -c -g -O -Wa,-alh,-L file.c
.Ve
This passes two options to the assembler: \fB\-alh\fR (emit a listing to
standard output with with high-level and assembly source) and \fB\-L\fR (retain
local symbols in the symbol table).
.PP
Usually you do not need to use this \fB\-Wa\fR mechanism, since many compiler
command-line options are automatically passed to the assembler by the compiler.
(You can call the \s-1GNU\s0 compiler driver with the \fB\-v\fR option to see
precisely what options it passes to each compilation pass, including the
assembler.)
.SH "OPTIONS"
.IX Header "OPTIONS"
.IP "\fB\-a[cdhlmns]\fR" 4
.IX Item "-a[cdhlmns]"
Turn on listings, in any of a variety of ways:
.RS 4
.IP "\fB\-ac\fR" 4
.IX Item "-ac"
omit false conditionals
.IP "\fB\-ad\fR" 4
.IX Item "-ad"
omit debugging directives
.IP "\fB\-ah\fR" 4
.IX Item "-ah"
include high-level source
.IP "\fB\-al\fR" 4
.IX Item "-al"
include assembly
.IP "\fB\-am\fR" 4
.IX Item "-am"
include macro expansions
.IP "\fB\-an\fR" 4
.IX Item "-an"
omit forms processing
.IP "\fB\-as\fR" 4
.IX Item "-as"
include symbols
.IP "\fB=file\fR" 4
.IX Item "=file"
set the name of the listing file
.RE
.RS 4
.Sp
You may combine these options; for example, use \fB\-aln\fR for assembly
listing without forms processing. The \fB=file\fR option, if used, must be
the last one. By itself, \fB\-a\fR defaults to \fB\-ahls\fR.
.RE
.IP "\fB\-D\fR" 4
.IX Item "-D"
Ignored. This option is accepted for script compatibility with calls to
other assemblers.
.IP "\fB\-\-defsym\fR \fIsym\fR\fB=\fR\fIvalue\fR" 4
.IX Item "--defsym sym=value"
Define the symbol \fIsym\fR to be \fIvalue\fR before assembling the input file.
\&\fIvalue\fR must be an integer constant. As in C, a leading \fB0x\fR
indicates a hexadecimal value, and a leading \fB0\fR indicates an octal value.
.IP "\fB\-f\fR" 4
.IX Item "-f"
``fast''\-\-\-skip whitespace and comment preprocessing (assume source is
compiler output).
.IP "\fB\-\-gstabs\fR" 4
.IX Item "--gstabs"
Generate stabs debugging information for each assembler line. This
may help debugging assembler code, if the debugger can handle it.
.IP "\fB\-\-gdwarf2\fR" 4
.IX Item "--gdwarf2"
Generate \s-1DWARF2\s0 debugging information for each assembler line. This
may help debugging assembler code, if the debugger can handle it. Note \- this
option is only supported by some targets, not all of them.
.IP "\fB\-\-help\fR" 4
.IX Item "--help"
Print a summary of the command line options and exit.
.IP "\fB\-\-target\-help\fR" 4
.IX Item "--target-help"
Print a summary of all target specific options and exit.
.IP "\fB\-I\fR \fIdir\fR" 4
.IX Item "-I dir"
Add directory \fIdir\fR to the search list for \f(CW\*(C`.include\*(C'\fR directives.
.IP "\fB\-J\fR" 4
.IX Item "-J"
Don't warn about signed overflow.
.IP "\fB\-K\fR" 4
.IX Item "-K"
This option is accepted but has no effect on the \s-1TARGET\s0 family.
.IP "\fB\-L\fR" 4
.IX Item "-L"
.PD 0
.IP "\fB\-\-keep\-locals\fR" 4
.IX Item "--keep-locals"
.PD
Keep (in the symbol table) local symbols. On traditional a.out systems
these start with \fBL\fR, but different systems have different local
label prefixes.
.IP "\fB\-\-listing\-lhs\-width=\fR\fInumber\fR" 4
.IX Item "--listing-lhs-width=number"
Set the maximum width, in words, of the output data column for an assembler
listing to \fInumber\fR.
.IP "\fB\-\-listing\-lhs\-width2=\fR\fInumber\fR" 4
.IX Item "--listing-lhs-width2=number"
Set the maximum width, in words, of the output data column for continuation
lines in an assembler listing to \fInumber\fR.
.IP "\fB\-\-listing\-rhs\-width=\fR\fInumber\fR" 4
.IX Item "--listing-rhs-width=number"
Set the maximum width of an input source line, as displayed in a listing, to
\&\fInumber\fR bytes.
.IP "\fB\-\-listing\-cont\-lines=\fR\fInumber\fR" 4
.IX Item "--listing-cont-lines=number"
Set the maximum number of lines printed in a listing for a single line of input
to \fInumber\fR + 1.
.IP "\fB\-o\fR \fIobjfile\fR" 4
.IX Item "-o objfile"
Name the object-file output from \fBas\fR \fIobjfile\fR.
.IP "\fB\-R\fR" 4
.IX Item "-R"
Fold the data section into the text section.
.IP "\fB\-\-statistics\fR" 4
.IX Item "--statistics"
Print the maximum space (in bytes) and total time (in seconds) used by
assembly.
.IP "\fB\-\-strip\-local\-absolute\fR" 4
.IX Item "--strip-local-absolute"
Remove local absolute symbols from the outgoing symbol table.
.IP "\fB\-v\fR" 4
.IX Item "-v"
.PD 0
.IP "\fB\-version\fR" 4
.IX Item "-version"
.PD
Print the \fBas\fR version.
.IP "\fB\-\-version\fR" 4
.IX Item "--version"
Print the \fBas\fR version and exit.
.IP "\fB\-W\fR" 4
.IX Item "-W"
.PD 0
.IP "\fB\-\-no\-warn\fR" 4
.IX Item "--no-warn"
.PD
Suppress warning messages.
.IP "\fB\-\-fatal\-warnings\fR" 4
.IX Item "--fatal-warnings"
Treat warnings as errors.
.IP "\fB\-\-warn\fR" 4
.IX Item "--warn"
Don't suppress warning messages or treat them as errors.
.IP "\fB\-w\fR" 4
.IX Item "-w"
Ignored.
.IP "\fB\-x\fR" 4
.IX Item "-x"
Ignored.
.IP "\fB\-Z\fR" 4
.IX Item "-Z"
Generate an object file even after errors.
.IP "\fB\-\- |\fR \fIfiles\fR \fB...\fR" 4
.IX Item "-- | files ..."
Standard input, or source files to assemble.
.PP
The following options are available when as is configured for
an \s-1ARC\s0 processor.
.IP "\fB\-marc[5|6|7|8]\fR" 4
.IX Item "-marc[5|6|7|8]"
This option selects the core processor variant.
.IP "\fB\-EB | \-EL\fR" 4
.IX Item "-EB | -EL"
Select either big-endian (\-EB) or little-endian (\-EL) output.
.PP
The following options are available when as is configured for the \s-1ARM\s0
processor family.
.IP "\fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
.IX Item "-mcpu=processor[+extension...]"
Specify which \s-1ARM\s0 processor variant is the target.
.IP "\fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
.IX Item "-march=architecture[+extension...]"
Specify which \s-1ARM\s0 architecture variant is used by the target.
.IP "\fB\-mfpu=\fR\fIfloating-point-format\fR" 4
.IX Item "-mfpu=floating-point-format"
Select which Floating Point architecture is the target.
.IP "\fB\-mthumb\fR" 4
.IX Item "-mthumb"
Enable Thumb only instruction decoding.
.IP "\fB\-mapcs\-32 | \-mapcs\-26 | \-mapcs\-float | \-mapcs\-reentrant | \-moabi\fR" 4
.IX Item "-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant | -moabi"
Select which procedure calling convention is in use.
.IP "\fB\-EB | \-EL\fR" 4
.IX Item "-EB | -EL"
Select either big-endian (\-EB) or little-endian (\-EL) output.
.IP "\fB\-mthumb\-interwork\fR" 4
.IX Item "-mthumb-interwork"
Specify that the code has been generated with interworking between Thumb and
\&\s-1ARM\s0 code in mind.
.IP "\fB\-k\fR" 4
.IX Item "-k"
Specify that \s-1PIC\s0 code has been generated.
.PP
See the info pages for documentation of the CRIS-specific options.
.PP
The following options are available when as is configured for
a D10V processor.
.IP "\fB\-O\fR" 4
.IX Item "-O"
Optimize output by parallelizing instructions.
.PP
The following options are available when as is configured for a D30V
processor.
.IP "\fB\-O\fR" 4
.IX Item "-O"
Optimize output by parallelizing instructions.
.IP "\fB\-n\fR" 4
.IX Item "-n"
Warn when nops are generated.
.IP "\fB\-N\fR" 4
.IX Item "-N"
Warn when a nop after a 32\-bit multiply instruction is generated.
.PP
The following options are available when as is configured for the
Intel 80960 processor.
.IP "\fB\-ACA | \-ACA_A | \-ACB | \-ACC | \-AKA | \-AKB | \-AKC | \-AMC\fR" 4
.IX Item "-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC"
Specify which variant of the 960 architecture is the target.
.IP "\fB\-b\fR" 4
.IX Item "-b"
Add code to collect statistics about branches taken.
.IP "\fB\-no\-relax\fR" 4
.IX Item "-no-relax"
Do not alter compare-and-branch instructions for long displacements;
error if necessary.
.PP
The following options are available when as is configured for the
Mitsubishi M32R series.
.IP "\fB\-\-m32rx\fR" 4
.IX Item "--m32rx"
Specify which processor in the M32R family is the target. The default
is normally the M32R, but this option changes it to the M32RX.
.IP "\fB\-\-warn\-explicit\-parallel\-conflicts or \-\-Wp\fR" 4
.IX Item "--warn-explicit-parallel-conflicts or --Wp"
Produce warning messages when questionable parallel constructs are
encountered.
.IP "\fB\-\-no\-warn\-explicit\-parallel\-conflicts or \-\-Wnp\fR" 4
.IX Item "--no-warn-explicit-parallel-conflicts or --Wnp"
Do not produce warning messages when questionable parallel constructs are
encountered.
.PP
The following options are available when as is configured for the
Motorola 68000 series.
.IP "\fB\-l\fR" 4
.IX Item "-l"
Shorten references to undefined symbols, to one word instead of two.
.IP "\fB\-m68000 | \-m68008 | \-m68010 | \-m68020 | \-m68030\fR" 4
.IX Item "-m68000 | -m68008 | -m68010 | -m68020 | -m68030"
.PD 0
.IP "\fB| \-m68040 | \-m68060 | \-m68302 | \-m68331 | \-m68332\fR" 4
.IX Item "| -m68040 | -m68060 | -m68302 | -m68331 | -m68332"
.IP "\fB| \-m68333 | \-m68340 | \-mcpu32 | \-m5200\fR" 4
.IX Item "| -m68333 | -m68340 | -mcpu32 | -m5200"
.PD
Specify what processor in the 68000 family is the target. The default
is normally the 68020, but this can be changed at configuration time.
.IP "\fB\-m68881 | \-m68882 | \-mno\-68881 | \-mno\-68882\fR" 4
.IX Item "-m68881 | -m68882 | -mno-68881 | -mno-68882"
The target machine does (or does not) have a floating-point coprocessor.
The default is to assume a coprocessor for 68020, 68030, and cpu32. Although
the basic 68000 is not compatible with the 68881, a combination of the
two can be specified, since it's possible to do emulation of the
coprocessor instructions with the main processor.
.IP "\fB\-m68851 | \-mno\-68851\fR" 4
.IX Item "-m68851 | -mno-68851"
The target machine does (or does not) have a memory-management
unit coprocessor. The default is to assume an \s-1MMU\s0 for 68020 and up.
.PP
For details about the \s-1PDP\-11\s0 machine dependent features options,
see \f(CW@ref\fR{PDP\-11\-Options}.
.IP "\fB\-mpic | \-mno\-pic\fR" 4
.IX Item "-mpic | -mno-pic"
Generate position-independent (or position\-dependent) code. The
default is \fB\-mpic\fR.
.IP "\fB\-mall\fR" 4
.IX Item "-mall"
.PD 0
.IP "\fB\-mall\-extensions\fR" 4
.IX Item "-mall-extensions"
.PD
Enable all instruction set extensions. This is the default.
.IP "\fB\-mno\-extensions\fR" 4
.IX Item "-mno-extensions"
Disable all instruction set extensions.
.IP "\fB\-m\fR\fIextension\fR \fB| \-mno\-\fR\fIextension\fR" 4
.IX Item "-mextension | -mno-extension"
Enable (or disable) a particular instruction set extension.
.IP "\fB\-m\fR\fIcpu\fR" 4
.IX Item "-mcpu"
Enable the instruction set extensions supported by a particular \s-1CPU\s0, and
disable all other extensions.
.IP "\fB\-m\fR\fImachine\fR" 4
.IX Item "-mmachine"
Enable the instruction set extensions supported by a particular machine
model, and disable all other extensions.
.PP
The following options are available when as is configured for
a picoJava processor.
.IP "\fB\-mb\fR" 4
.IX Item "-mb"
Generate ``big endian'' format output.
.IP "\fB\-ml\fR" 4
.IX Item "-ml"
Generate ``little endian'' format output.
.PP
The following options are available when as is configured for the
Motorola 68HC11 or 68HC12 series.
.IP "\fB\-m68hc11 | \-m68hc12\fR" 4
.IX Item "-m68hc11 | -m68hc12"
Specify what processor is the target. The default is
defined by the configuration option when building the assembler.
.IP "\fB\-\-force\-long\-branchs\fR" 4
.IX Item "--force-long-branchs"
Relative branches are turned into absolute ones. This concerns
conditional branches, unconditional branches and branches to a
sub routine.
.IP "\fB\-S | \-\-short\-branchs\fR" 4
.IX Item "-S | --short-branchs"
Do not turn relative branchs into absolute ones
when the offset is out of range.
.IP "\fB\-\-strict\-direct\-mode\fR" 4
.IX Item "--strict-direct-mode"
Do not turn the direct addressing mode into extended addressing mode
when the instruction does not support direct addressing mode.
.IP "\fB\-\-print\-insn\-syntax\fR" 4
.IX Item "--print-insn-syntax"
Print the syntax of instruction in case of error.
.IP "\fB\-\-print\-opcodes\fR" 4
.IX Item "--print-opcodes"
print the list of instructions with syntax and then exit.
.IP "\fB\-\-generate\-example\fR" 4
.IX Item "--generate-example"
print an example of instruction for each possible instruction and then exit.
This option is only useful for testing \fBas\fR.
.PP
The following options are available when \fBas\fR is configured
for the \s-1SPARC\s0 architecture:
.IP "\fB\-Av6 | \-Av7 | \-Av8 | \-Asparclet | \-Asparclite\fR" 4
.IX Item "-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite"
.PD 0
.IP "\fB\-Av8plus | \-Av8plusa | \-Av9 | \-Av9a\fR" 4
.IX Item "-Av8plus | -Av8plusa | -Av9 | -Av9a"
.PD
Explicitly select a variant of the \s-1SPARC\s0 architecture.
.Sp
\&\fB\-Av8plus\fR and \fB\-Av8plusa\fR select a 32 bit environment.
\&\fB\-Av9\fR and \fB\-Av9a\fR select a 64 bit environment.
.Sp
\&\fB\-Av8plusa\fR and \fB\-Av9a\fR enable the \s-1SPARC\s0 V9 instruction set with
UltraSPARC extensions.
.IP "\fB\-xarch=v8plus | \-xarch=v8plusa\fR" 4
.IX Item "-xarch=v8plus | -xarch=v8plusa"
For compatibility with the Solaris v9 assembler. These options are
equivalent to \-Av8plus and \-Av8plusa, respectively.
.IP "\fB\-bump\fR" 4
.IX Item "-bump"
Warn when the assembler switches to another architecture.
.PP
The following options are available when as is configured for
a \s-1MIPS\s0 processor.
.IP "\fB\-G\fR \fInum\fR" 4
.IX Item "-G num"
This option sets the largest size of an object that can be referenced
implicitly with the \f(CW\*(C`gp\*(C'\fR register. It is only accepted for targets that
use \s-1ECOFF\s0 format, such as a DECstation running Ultrix. The default value is 8.
.IP "\fB\-EB\fR" 4
.IX Item "-EB"
Generate ``big endian'' format output.
.IP "\fB\-EL\fR" 4
.IX Item "-EL"
Generate ``little endian'' format output.
.IP "\fB\-mips1\fR" 4
.IX Item "-mips1"
.PD 0
.IP "\fB\-mips2\fR" 4
.IX Item "-mips2"
.IP "\fB\-mips3\fR" 4
.IX Item "-mips3"
.IP "\fB\-mips4\fR" 4
.IX Item "-mips4"
.IP "\fB\-mips32\fR" 4
.IX Item "-mips32"
.IP "\fB\-mips64\fR" 4
.IX Item "-mips64"
.PD
Generate code for a particular \s-1MIPS\s0 Instruction Set Architecture level.
\&\fB\-mips1\fR corresponds to the R2000 and R3000 processors,
\&\fB\-mips2\fR to the R6000 processor, and \fB\-mips3\fR to the R4000
processor.
\&\fB\-mips5\fR, \fB\-mips32\fR, and \fB\-mips64\fR correspond
to generic \s-1MIPS\s0 V, \s-1MIPS32\s0, and \s-1MIPS64\s0 \s-1ISA\s0
processors, respectively.
.IP "\fB\-m4650\fR" 4
.IX Item "-m4650"
.PD 0
.IP "\fB\-no\-m4650\fR" 4
.IX Item "-no-m4650"
.PD
Generate code for the \s-1MIPS\s0 R4650 chip. This tells the assembler to accept
the \fBmad\fR and \fBmadu\fR instruction, and to not schedule \fBnop\fR
instructions around accesses to the \fB\s-1HI\s0\fR and \fB\s-1LO\s0\fR registers.
\&\fB\-no\-m4650\fR turns off this option.
.IP "\fB\-mcpu=\fR\fI\s-1CPU\s0\fR" 4
.IX Item "-mcpu=CPU"
Generate code for a particular \s-1MIPS\s0 cpu. It is exactly equivalent to
\&\fB\-m\fR\fIcpu\fR, except that there are more value of \fIcpu\fR
understood.
.IP "\fB\-\-emulation=\fR\fIname\fR" 4
.IX Item "--emulation=name"
This option causes \fBas\fR to emulate \fBas\fR configured
for some other target, in all respects, including output format (choosing
between \s-1ELF\s0 and \s-1ECOFF\s0 only), handling of pseudo-opcodes which may generate
debugging information or store symbol table information, and default
endianness. The available configuration names are: \fBmipsecoff\fR,
\&\fBmipself\fR, \fBmipslecoff\fR, \fBmipsbecoff\fR, \fBmipslelf\fR,
\&\fBmipsbelf\fR. The first two do not alter the default endianness from that
of the primary target for which the assembler was configured; the others change
the default to little\- or big-endian as indicated by the \fBb\fR or \fBl\fR
in the name. Using \fB\-EB\fR or \fB\-EL\fR will override the endianness
selection in any case.
.Sp
This option is currently supported only when the primary target
\&\fBas\fR is configured for is a \s-1MIPS\s0 \s-1ELF\s0 or \s-1ECOFF\s0 target.
Furthermore, the primary target or others specified with
\&\fB\-\-enable\-targets=...\fR at configuration time must include support for
the other format, if both are to be available. For example, the Irix 5
configuration includes support for both.
.Sp
Eventually, this option will support more configurations, with more
fine-grained control over the assembler's behavior, and will be supported for
more processors.
.IP "\fB\-nocpp\fR" 4
.IX Item "-nocpp"
\&\fBas\fR ignores this option. It is accepted for compatibility with
the native tools.
.IP "\fB\-\-trap\fR" 4
.IX Item "--trap"
.PD 0
.IP "\fB\-\-no\-trap\fR" 4
.IX Item "--no-trap"
.IP "\fB\-\-break\fR" 4
.IX Item "--break"
.IP "\fB\-\-no\-break\fR" 4
.IX Item "--no-break"
.PD
Control how to deal with multiplication overflow and division by zero.
\&\fB\-\-trap\fR or \fB\-\-no\-break\fR (which are synonyms) take a trap exception
(and only work for Instruction Set Architecture level 2 and higher);
\&\fB\-\-break\fR or \fB\-\-no\-trap\fR (also synonyms, and the default) take a
break exception.
.IP "\fB\-n\fR" 4
.IX Item "-n"
When this option is used, \fBas\fR will issue a warning every
time it generates a nop instruction from a macro.
.PP
The following options are available when as is configured for
an MCore processor.
.IP "\fB\-jsri2bsr\fR" 4
.IX Item "-jsri2bsr"
.PD 0
.IP "\fB\-nojsri2bsr\fR" 4
.IX Item "-nojsri2bsr"
.PD
Enable or disable the \s-1JSRI\s0 to \s-1BSR\s0 transformation. By default this is enabled.
The command line option \fB\-nojsri2bsr\fR can be used to disable it.
.IP "\fB\-sifilter\fR" 4
.IX Item "-sifilter"
.PD 0
.IP "\fB\-nosifilter\fR" 4
.IX Item "-nosifilter"
.PD
Enable or disable the silicon filter behaviour. By default this is disabled.
The default can be overridden by the \fB\-sifilter\fR command line option.
.IP "\fB\-relax\fR" 4
.IX Item "-relax"
Alter jump instructions for long displacements.
.IP "\fB\-mcpu=[210|340]\fR" 4
.IX Item "-mcpu=[210|340]"
Select the cpu type on the target hardware. This controls which instructions
can be assembled.
.IP "\fB\-EB\fR" 4
.IX Item "-EB"
Assemble for a big endian target.
.IP "\fB\-EL\fR" 4
.IX Item "-EL"
Assemble for a little endian target.
.PP
See the info pages for documentation of the MMIX-specific options.
.SH "SEE ALSO"
.IX Header "SEE ALSO"
\&\fIgcc\fR\|(1), \fIld\fR\|(1), and the Info entries for \fIbinutils\fR and \fIld\fR.
.SH "COPYRIGHT"
.IX Header "COPYRIGHT"
Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002 Free Software Foundation, Inc.
.PP
Permission is granted to copy, distribute and/or modify this document
under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.1
or any later version published by the Free Software Foundation;
with no Invariant Sections, with no Front-Cover Texts, and with no
Back-Cover Texts. A copy of the license is included in the
section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R".
|