From 1fc08f5e9ef733ef1ce6f363fecedc2260e78974 Mon Sep 17 00:00:00 2001
From: dim <dim@FreeBSD.org>
Date: Sat, 14 Apr 2012 13:54:10 +0000
Subject: Vendor import of llvm trunk r154661:
 http://llvm.org/svn/llvm-project/llvm/trunk@r154661

---
 utils/TableGen/TableGen.cpp | 173 ++++++++++++++++++++++----------------------
 1 file changed, 85 insertions(+), 88 deletions(-)

(limited to 'utils/TableGen/TableGen.cpp')

diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp
index eacfdf6..8c41358 100644
--- a/utils/TableGen/TableGen.cpp
+++ b/utils/TableGen/TableGen.cpp
@@ -16,6 +16,7 @@
 #include "CallingConvEmitter.h"
 #include "CodeEmitterGen.h"
 #include "DAGISelEmitter.h"
+#include "DFAPacketizerEmitter.h"
 #include "DisassemblerEmitter.h"
 #include "EDEmitter.h"
 #include "FastISelEmitter.h"
@@ -23,7 +24,6 @@
 #include "IntrinsicEmitter.h"
 #include "PseudoLoweringEmitter.h"
 #include "RegisterInfoEmitter.h"
-#include "ARMDecoderEmitter.h"
 #include "SubtargetEmitter.h"
 #include "SetTheory.h"
 
@@ -44,11 +44,11 @@ enum ActionType {
   GenInstrInfo,
   GenAsmWriter,
   GenAsmMatcher,
-  GenARMDecoder,
   GenDisassembler,
   GenPseudoLowering,
   GenCallingConv,
   GenDAGISel,
+  GenDFAPacketizer,
   GenFastISel,
   GenSubtarget,
   GenIntrinsic,
@@ -73,8 +73,6 @@ namespace {
                                "Generate calling convention descriptions"),
                     clEnumValN(GenAsmWriter, "gen-asm-writer",
                                "Generate assembly writer"),
-                    clEnumValN(GenARMDecoder, "gen-arm-decoder",
-                               "Generate decoders for ARM/Thumb"),
                     clEnumValN(GenDisassembler, "gen-disassembler",
                                "Generate disassembler"),
                     clEnumValN(GenPseudoLowering, "gen-pseudo-lowering",
@@ -83,6 +81,8 @@ namespace {
                                "Generate assembly instruction matcher"),
                     clEnumValN(GenDAGISel, "gen-dag-isel",
                                "Generate a DAG instruction selector"),
+                    clEnumValN(GenDFAPacketizer, "gen-dfa-packetizer",
+                               "Generate DFA Packetizer for VLIW targets"),
                     clEnumValN(GenFastISel, "gen-fast-isel",
                                "Generate a \"fast\" instruction selector"),
                     clEnumValN(GenSubtarget, "gen-subtarget",
@@ -101,92 +101,89 @@ namespace {
 
   cl::opt<std::string>
   Class("class", cl::desc("Print Enum list for this class"),
-        cl::value_desc("class name"));
-}
-
-class LLVMTableGenAction : public TableGenAction {
-public:
-  bool operator()(raw_ostream &OS, RecordKeeper &Records) {
-    switch (Action) {
-    case PrintRecords:
-      OS << Records;           // No argument, dump all contents
-      break;
-    case GenEmitter:
-      CodeEmitterGen(Records).run(OS);
-      break;
-    case GenRegisterInfo:
-      RegisterInfoEmitter(Records).run(OS);
-      break;
-    case GenInstrInfo:
-      InstrInfoEmitter(Records).run(OS);
-      break;
-    case GenCallingConv:
-      CallingConvEmitter(Records).run(OS);
-      break;
-    case GenAsmWriter:
-      AsmWriterEmitter(Records).run(OS);
-      break;
-    case GenARMDecoder:
-      ARMDecoderEmitter(Records).run(OS);
-      break;
-    case GenAsmMatcher:
-      AsmMatcherEmitter(Records).run(OS);
-      break;
-    case GenDisassembler:
-      DisassemblerEmitter(Records).run(OS);
-      break;
-    case GenPseudoLowering:
-      PseudoLoweringEmitter(Records).run(OS);
-      break;
-    case GenDAGISel:
-      DAGISelEmitter(Records).run(OS);
-      break;
-    case GenFastISel:
-      FastISelEmitter(Records).run(OS);
-      break;
-    case GenSubtarget:
-      SubtargetEmitter(Records).run(OS);
-      break;
-    case GenIntrinsic:
-      IntrinsicEmitter(Records).run(OS);
-      break;
-    case GenTgtIntrinsic:
-      IntrinsicEmitter(Records, true).run(OS);
-      break;
-    case GenEDInfo:
-      EDEmitter(Records).run(OS);
-      break;
-    case PrintEnums:
-    {
-      std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class);
-      for (unsigned i = 0, e = Recs.size(); i != e; ++i)
-        OS << Recs[i]->getName() << ", ";
-      OS << "\n";
-      break;
-    }
-    case PrintSets:
-    {
-      SetTheory Sets;
-      Sets.addFieldExpander("Set", "Elements");
-      std::vector<Record*> Recs = Records.getAllDerivedDefinitions("Set");
-      for (unsigned i = 0, e = Recs.size(); i != e; ++i) {
-        OS << Recs[i]->getName() << " = [";
-        const std::vector<Record*> *Elts = Sets.expand(Recs[i]);
-        assert(Elts && "Couldn't expand Set instance");
-        for (unsigned ei = 0, ee = Elts->size(); ei != ee; ++ei)
-          OS << ' ' << (*Elts)[ei]->getName();
-        OS << " ]\n";
+          cl::value_desc("class name"));
+  
+  class LLVMTableGenAction : public TableGenAction {
+  public:
+    bool operator()(raw_ostream &OS, RecordKeeper &Records) {
+      switch (Action) {
+      case PrintRecords:
+        OS << Records;           // No argument, dump all contents
+        break;
+      case GenEmitter:
+        CodeEmitterGen(Records).run(OS);
+        break;
+      case GenRegisterInfo:
+        RegisterInfoEmitter(Records).run(OS);
+        break;
+      case GenInstrInfo:
+        InstrInfoEmitter(Records).run(OS);
+        break;
+      case GenCallingConv:
+        CallingConvEmitter(Records).run(OS);
+        break;
+      case GenAsmWriter:
+        AsmWriterEmitter(Records).run(OS);
+        break;
+      case GenAsmMatcher:
+        AsmMatcherEmitter(Records).run(OS);
+        break;
+      case GenDisassembler:
+        DisassemblerEmitter(Records).run(OS);
+        break;
+      case GenPseudoLowering:
+        PseudoLoweringEmitter(Records).run(OS);
+        break;
+      case GenDAGISel:
+        DAGISelEmitter(Records).run(OS);
+        break;
+      case GenDFAPacketizer:
+        DFAGen(Records).run(OS);
+        break;
+      case GenFastISel:
+        FastISelEmitter(Records).run(OS);
+        break;
+      case GenSubtarget:
+        SubtargetEmitter(Records).run(OS);
+        break;
+      case GenIntrinsic:
+        IntrinsicEmitter(Records).run(OS);
+        break;
+      case GenTgtIntrinsic:
+        IntrinsicEmitter(Records, true).run(OS);
+        break;
+      case GenEDInfo:
+        EDEmitter(Records).run(OS);
+        break;
+      case PrintEnums:
+      {
+        std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class);
+        for (unsigned i = 0, e = Recs.size(); i != e; ++i)
+          OS << Recs[i]->getName() << ", ";
+        OS << "\n";
+        break;
       }
-      break;
-    }
-    default:
-      assert(1 && "Invalid Action");
-      return true;
+      case PrintSets:
+      {
+        SetTheory Sets;
+        Sets.addFieldExpander("Set", "Elements");
+        std::vector<Record*> Recs = Records.getAllDerivedDefinitions("Set");
+        for (unsigned i = 0, e = Recs.size(); i != e; ++i) {
+          OS << Recs[i]->getName() << " = [";
+          const std::vector<Record*> *Elts = Sets.expand(Recs[i]);
+          assert(Elts && "Couldn't expand Set instance");
+          for (unsigned ei = 0, ee = Elts->size(); ei != ee; ++ei)
+            OS << ' ' << (*Elts)[ei]->getName();
+          OS << " ]\n";
+        }
+        break;
+      }
+      }
+  
+      return false;
     }
-
-    return false;
-  }
-};
+  };
+}
 
 int main(int argc, char **argv) {
   sys::PrintStackTraceOnErrorSignal();
-- 
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