From a548ed3c677679c4a004db81bfb95f560e5d2d26 Mon Sep 17 00:00:00 2001 From: jhb Date: Tue, 24 Dec 2013 16:14:19 +0000 Subject: Support soft power-off via the ACPI S5 state for bhyve guests. - Implement the PM1_EVT and PM1_CTL registers required by ACPI. The PM1_EVT register is mostly a dummy as bhyve doesn't support any of the hardware-initiated events. The only bit of PM1_CNT that is implemented are the sleep request bits (SPL_EN and SLP_TYP) which request a graceful power off for S5. In particular, for S5, bhyve exits with a non-zero value which terminates the loop in vmrun.sh. - Emulate the Reset Control register at I/O port 0xcf9 and advertise it as the reset register via ACPI. - Advertise an _S5 package. - Extend the in/out interface to allow an in/out handler to request that the hypervisor trigger a reset or power-off. - While here, note that all vCPUs in a guest support C1 ("hlt"). Reviewed by: neel (earlier version) --- usr.sbin/bhyve/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'usr.sbin/bhyve/Makefile') diff --git a/usr.sbin/bhyve/Makefile b/usr.sbin/bhyve/Makefile index 7f2973c..c16a759 100644 --- a/usr.sbin/bhyve/Makefile +++ b/usr.sbin/bhyve/Makefile @@ -10,7 +10,7 @@ MAN= bhyve.8 SRCS= acpi.c atpic.c bhyverun.c block_if.c consport.c dbgport.c elcr.c SRCS+= inout.c legacy_irq.c mem.c mevent.c mptbl.c pci_ahci.c SRCS+= pci_emul.c pci_hostbridge.c pci_lpc.c pci_passthru.c pci_virtio_block.c -SRCS+= pci_virtio_net.c pci_uart.c pit_8254.c pmtmr.c post.c rtc.c +SRCS+= pci_virtio_net.c pci_uart.c pit_8254.c pm.c pmtmr.c post.c rtc.c SRCS+= uart_emul.c virtio.c xmsr.c spinup_ap.c .PATH: ${.CURDIR}/../../sys/amd64/vmm -- cgit v1.1