From cbb70ce070d220642b038ea101d9c0f9fbf860d6 Mon Sep 17 00:00:00 2001 From: dim Date: Sun, 20 Feb 2011 12:57:14 +0000 Subject: Vendor import of llvm trunk r126079: http://llvm.org/svn/llvm-project/llvm/trunk@126079 --- test/Analysis/BasicAA/2003-02-26-AccessSizeTest.ll | 2 +- test/Analysis/BasicAA/2003-04-22-GEPProblem.ll | 2 +- test/Analysis/BasicAA/2003-05-21-GEP-Problem.ll | 2 +- test/Analysis/BasicAA/2003-09-19-LocalArgument.ll | 2 +- test/Analysis/BasicAA/2003-11-04-SimpleCases.ll | 2 +- test/Analysis/BasicAA/2003-12-11-ConstExprGEP.ll | 2 +- test/Analysis/BasicAA/2004-07-28-MustAliasbug.ll | 2 +- test/Analysis/BasicAA/2004-12-08-BasicAACrash.ll | 2 +- test/Analysis/BasicAA/2004-12-08-BasicAACrash2.ll | 2 +- .../BasicAA/2006-03-03-BadArraySubscript.ll | 2 +- .../BasicAA/2006-11-03-BasicAAVectorCrash.ll | 2 +- test/Analysis/BasicAA/2007-11-05-SizeCrash.ll | 2 +- .../BasicAA/2007-12-08-OutOfBoundsCrash.ll | 2 +- test/Analysis/BasicAA/2008-06-02-GEPTailCrash.ll | 2 +- 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mode 100644 test/Transforms/TailCallElim/dup_tail.ll (limited to 'test') diff --git a/test/Analysis/BasicAA/2003-02-26-AccessSizeTest.ll b/test/Analysis/BasicAA/2003-02-26-AccessSizeTest.ll index 6b50a16..1c2d910 100644 --- a/test/Analysis/BasicAA/2003-02-26-AccessSizeTest.ll +++ b/test/Analysis/BasicAA/2003-02-26-AccessSizeTest.ll @@ -2,7 +2,7 @@ ; is performed. It is not legal to delete the second load instruction because ; the value computed by the first load instruction is changed by the store. -; RUN: opt < %s -gvn -instcombine -S | grep DONOTREMOVE +; RUN: opt < %s -basicaa -gvn -instcombine -S | grep DONOTREMOVE define i32 @test() { %A = alloca i32 diff --git a/test/Analysis/BasicAA/2003-04-22-GEPProblem.ll b/test/Analysis/BasicAA/2003-04-22-GEPProblem.ll index f7e8295..5d20077 100644 --- a/test/Analysis/BasicAA/2003-04-22-GEPProblem.ll +++ b/test/Analysis/BasicAA/2003-04-22-GEPProblem.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -gvn -instcombine -S | grep sub +; RUN: opt < %s -basicaa -gvn -instcombine -S | grep sub ; BasicAA was incorrectly concluding that P1 and P2 didn't conflict! diff --git a/test/Analysis/BasicAA/2003-05-21-GEP-Problem.ll b/test/Analysis/BasicAA/2003-05-21-GEP-Problem.ll index d439dfc..8ca3469 100644 --- a/test/Analysis/BasicAA/2003-05-21-GEP-Problem.ll +++ b/test/Analysis/BasicAA/2003-05-21-GEP-Problem.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -licm -disable-output +; RUN: opt < %s -basicaa -licm -disable-output %struct..apr_array_header_t = type { i32*, i32, i32, i32, i8* } %struct..apr_table_t = type { %struct..apr_array_header_t, i32, [32 x i32], [32 x i32] } diff --git a/test/Analysis/BasicAA/2003-09-19-LocalArgument.ll b/test/Analysis/BasicAA/2003-09-19-LocalArgument.ll index 637d8f0..56e3339 100644 --- a/test/Analysis/BasicAA/2003-09-19-LocalArgument.ll +++ b/test/Analysis/BasicAA/2003-09-19-LocalArgument.ll @@ -1,6 +1,6 @@ ; In this test, a local alloca cannot alias an incoming argument. -; RUN: opt < %s -gvn -instcombine -S | not grep sub +; RUN: opt < %s -basicaa -gvn -instcombine -S | not grep sub define i32 @test(i32* %P) { %X = alloca i32 diff --git a/test/Analysis/BasicAA/2003-11-04-SimpleCases.ll b/test/Analysis/BasicAA/2003-11-04-SimpleCases.ll index 911f78c..010a4588 100644 --- a/test/Analysis/BasicAA/2003-11-04-SimpleCases.ll +++ b/test/Analysis/BasicAA/2003-11-04-SimpleCases.ll @@ -1,7 +1,7 @@ ; This testcase consists of alias relations which should be completely ; resolvable by basicaa. -; RUN: opt < %s -aa-eval -print-may-aliases -disable-output \ +; RUN: opt < %s -basicaa -aa-eval -print-may-aliases -disable-output \ ; RUN: |& not grep May: %T = type { i32, [10 x i8] } diff --git a/test/Analysis/BasicAA/2003-12-11-ConstExprGEP.ll b/test/Analysis/BasicAA/2003-12-11-ConstExprGEP.ll index 8166b97..ce01db6 100644 --- a/test/Analysis/BasicAA/2003-12-11-ConstExprGEP.ll +++ b/test/Analysis/BasicAA/2003-12-11-ConstExprGEP.ll @@ -1,7 +1,7 @@ ; This testcase consists of alias relations which should be completely ; resolvable by basicaa, but require analysis of getelementptr constant exprs. -; RUN: opt < %s -aa-eval -print-may-aliases -disable-output \ +; RUN: opt < %s -basicaa -aa-eval -print-may-aliases -disable-output \ ; RUN: |& not grep May: %T = type { i32, [10 x i8] } diff --git a/test/Analysis/BasicAA/2004-07-28-MustAliasbug.ll b/test/Analysis/BasicAA/2004-07-28-MustAliasbug.ll index e1cfd03..56e4ed0 100644 --- a/test/Analysis/BasicAA/2004-07-28-MustAliasbug.ll +++ b/test/Analysis/BasicAA/2004-07-28-MustAliasbug.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -dse -S | grep {store i32 0} +; RUN: opt < %s -basicaa -dse -S | grep {store i32 0} define void @test({i32,i32 }* %P) { %Q = getelementptr {i32,i32}* %P, i32 1 diff --git a/test/Analysis/BasicAA/2004-12-08-BasicAACrash.ll b/test/Analysis/BasicAA/2004-12-08-BasicAACrash.ll index 81248db..50fb222 100644 --- a/test/Analysis/BasicAA/2004-12-08-BasicAACrash.ll +++ b/test/Analysis/BasicAA/2004-12-08-BasicAACrash.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -licm +; RUN: opt < %s -basicaa -licm %"java/lang/Object" = type { %struct.llvm_java_object_base } %"java/lang/StringBuffer" = type { "java/lang/Object", i32, { "java/lang/Object", i32, [0 x i8] }*, i1 } diff --git a/test/Analysis/BasicAA/2004-12-08-BasicAACrash2.ll b/test/Analysis/BasicAA/2004-12-08-BasicAACrash2.ll index 0e03db3..cc84314 100644 --- a/test/Analysis/BasicAA/2004-12-08-BasicAACrash2.ll +++ b/test/Analysis/BasicAA/2004-12-08-BasicAACrash2.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -dse +; RUN: opt < %s -basicaa -dse %"java/lang/Object" = type { %struct.llvm_java_object_base } %"java/lang/StringBuffer" = type { "java/lang/Object", i32, { "java/lang/Object", i32, [0 x i8] }*, i1 } diff --git a/test/Analysis/BasicAA/2006-03-03-BadArraySubscript.ll b/test/Analysis/BasicAA/2006-03-03-BadArraySubscript.ll index 49327ac..8320594 100644 --- a/test/Analysis/BasicAA/2006-03-03-BadArraySubscript.ll +++ b/test/Analysis/BasicAA/2006-03-03-BadArraySubscript.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -aa-eval -disable-output |& grep {2 no alias respon} +; RUN: opt < %s -basicaa -aa-eval -disable-output |& grep {2 no alias respon} ; TEST that A[1][0] may alias A[0][i]. target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" diff --git a/test/Analysis/BasicAA/2006-11-03-BasicAAVectorCrash.ll b/test/Analysis/BasicAA/2006-11-03-BasicAAVectorCrash.ll index 85f53a6..0db5815 100644 --- a/test/Analysis/BasicAA/2006-11-03-BasicAAVectorCrash.ll +++ b/test/Analysis/BasicAA/2006-11-03-BasicAAVectorCrash.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -licm -disable-output +; RUN: opt < %s -basicaa -licm -disable-output target datalayout = "E-p:32:32" target triple = "powerpc-apple-darwin8.7.0" diff --git a/test/Analysis/BasicAA/2007-11-05-SizeCrash.ll b/test/Analysis/BasicAA/2007-11-05-SizeCrash.ll index f699ba2..563d332 100644 --- a/test/Analysis/BasicAA/2007-11-05-SizeCrash.ll +++ b/test/Analysis/BasicAA/2007-11-05-SizeCrash.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -gvn -disable-output +; RUN: opt < %s -basicaa -gvn -disable-output ; PR1774 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" diff --git a/test/Analysis/BasicAA/2007-12-08-OutOfBoundsCrash.ll b/test/Analysis/BasicAA/2007-12-08-OutOfBoundsCrash.ll index 8028afb..52d0af1 100644 --- a/test/Analysis/BasicAA/2007-12-08-OutOfBoundsCrash.ll +++ b/test/Analysis/BasicAA/2007-12-08-OutOfBoundsCrash.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -gvn -disable-output +; RUN: opt < %s -basicaa -gvn -disable-output ; PR1782 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" diff --git a/test/Analysis/BasicAA/2008-06-02-GEPTailCrash.ll b/test/Analysis/BasicAA/2008-06-02-GEPTailCrash.ll index ba29f3a..1709144 100644 --- a/test/Analysis/BasicAA/2008-06-02-GEPTailCrash.ll +++ b/test/Analysis/BasicAA/2008-06-02-GEPTailCrash.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -gvn -disable-output +; RUN: opt < %s -basicaa -gvn -disable-output ; PR2395 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" diff --git a/test/Analysis/BasicAA/2008-11-23-NoaliasRet.ll b/test/Analysis/BasicAA/2008-11-23-NoaliasRet.ll index 06018cc..c9e553d 100644 --- a/test/Analysis/BasicAA/2008-11-23-NoaliasRet.ll +++ b/test/Analysis/BasicAA/2008-11-23-NoaliasRet.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -aa-eval |& grep {1 no alias response} +; RUN: opt < %s -basicaa -aa-eval |& grep {1 no alias response} declare noalias i32* @_Znwj(i32 %x) nounwind diff --git a/test/Analysis/BasicAA/2009-10-13-AtomicModRef.ll b/test/Analysis/BasicAA/2009-10-13-AtomicModRef.ll index 6475471..5078dd5 100644 --- a/test/Analysis/BasicAA/2009-10-13-AtomicModRef.ll +++ b/test/Analysis/BasicAA/2009-10-13-AtomicModRef.ll @@ -1,4 +1,4 @@ -; RUN: opt -gvn -instcombine -S < %s | FileCheck %s +; RUN: opt -basicaa -gvn -instcombine -S < %s | FileCheck %s target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" declare i8 @llvm.atomic.load.add.i8.p0i8(i8*, i8) diff --git a/test/Analysis/BasicAA/2009-10-13-GEP-BaseNoAlias.ll b/test/Analysis/BasicAA/2009-10-13-GEP-BaseNoAlias.ll index 771636f..17db2fd 100644 --- a/test/Analysis/BasicAA/2009-10-13-GEP-BaseNoAlias.ll +++ b/test/Analysis/BasicAA/2009-10-13-GEP-BaseNoAlias.ll @@ -1,11 +1,11 @@ -; RUN: opt < %s -aa-eval -print-all-alias-modref-info -disable-output |& grep {NoAlias:.*%P,.*@Z} +; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info -disable-output |& grep {NoAlias:.*%P,.*@Z} ; If GEP base doesn't alias Z, then GEP doesn't alias Z. ; rdar://7282591 @Y = common global i32 0 @Z = common global i32 0 -define void @foo(i32 %cond) nounwind ssp { +define void @foo(i32 %cond) nounwind { entry: %a = alloca i32 %tmp = icmp ne i32 %cond, 0 diff --git a/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll b/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll new file mode 100644 index 0000000..2b0cd78 --- /dev/null +++ b/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll @@ -0,0 +1,15 @@ +; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info -disable-output |& grep {1 may alias} +; PR7959 + +target datalayout = "e-p:32:32:32" + +define i32 @test(i32* %tab, i32 %indvar) nounwind { + %tmp31 = mul i32 %indvar, -2 + %tmp32 = add i32 %tmp31, 30 + %t.5 = getelementptr i32* %tab, i32 %tmp32 + %loada = load i32* %tab + store i32 0, i32* %t.5 + %loadb = load i32* %tab + %rval = add i32 %loada, %loadb + ret i32 %rval +} diff --git a/test/Analysis/BasicAA/args-rets-allocas-loads.ll b/test/Analysis/BasicAA/args-rets-allocas-loads.ll index 7555a4c..c3c4afc 100644 --- a/test/Analysis/BasicAA/args-rets-allocas-loads.ll +++ b/test/Analysis/BasicAA/args-rets-allocas-loads.ll @@ -1,4 +1,4 @@ -; RUN: opt -aa-eval -print-all-alias-modref-info -disable-output < %s |& FileCheck %s +; RUN: opt -basicaa -aa-eval -print-all-alias-modref-info -disable-output < %s |& FileCheck %s declare void @callee(double* %callee_arg) declare void @nocap_callee(double* nocapture %nocap_callee_arg) diff --git a/test/Analysis/BasicAA/byval.ll b/test/Analysis/BasicAA/byval.ll index cdcafdf..2aba753 100644 --- a/test/Analysis/BasicAA/byval.ll +++ b/test/Analysis/BasicAA/byval.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -gvn -S | grep {ret i32 1} +; RUN: opt < %s -basicaa -gvn -S | grep {ret i32 1} target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i686-apple-darwin8" %struct.x = type { i32, i32, i32, i32 } diff --git a/test/Analysis/BasicAA/constant-over-index.ll b/test/Analysis/BasicAA/constant-over-index.ll index 0e0c45c..8a8ac4f 100644 --- a/test/Analysis/BasicAA/constant-over-index.ll +++ b/test/Analysis/BasicAA/constant-over-index.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -aa-eval -print-all-alias-modref-info |& FileCheck %s +; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info |& FileCheck %s ; PR4267 ; CHECK: MayAlias: double* %p.0.i.0, double* %p3 diff --git a/test/Analysis/BasicAA/empty.ll b/test/Analysis/BasicAA/empty.ll index 689efec..7b06780 100644 --- a/test/Analysis/BasicAA/empty.ll +++ b/test/Analysis/BasicAA/empty.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -aa-eval -print-all-alias-modref-info -disable-output \ +; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info -disable-output \ ; RUN: |& grep {NoAlias: \{\}\\* \[%\]p, \{\}\\* \[%\]q} target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" diff --git a/test/Analysis/BasicAA/full-store-partial-alias.ll b/test/Analysis/BasicAA/full-store-partial-alias.ll new file mode 100644 index 0000000..4fa6375 --- /dev/null +++ b/test/Analysis/BasicAA/full-store-partial-alias.ll @@ -0,0 +1,33 @@ +; RUN: opt -S -tbaa -basicaa -gvn < %s | grep {ret i32 %} +; RUN: opt -S -tbaa -gvn < %s | grep {ret i32 0} +; rdar://8875631, rdar://8875069 + +; BasicAA should notice that the store stores to the entire %u object, +; so the %tmp5 load is PartialAlias with the store and suppress TBAA. +; Without BasicAA, TBAA should say that %tmp5 is NoAlias with the store. + +target datalayout = "e-p:64:64:64" + +%union.anon = type { double } + +@u = global %union.anon { double -2.500000e-01 }, align 8 +@endianness_test = global i64 1, align 8 + +define i32 @signbit(double %x) nounwind { +entry: + %u = alloca %union.anon, align 8 + %tmp9 = getelementptr inbounds %union.anon* %u, i64 0, i32 0 + store double %x, double* %tmp9, align 8, !tbaa !0 + %tmp2 = load i32* bitcast (i64* @endianness_test to i32*), align 8, !tbaa !3 + %idxprom = sext i32 %tmp2 to i64 + %tmp4 = bitcast %union.anon* %u to [2 x i32]* + %arrayidx = getelementptr inbounds [2 x i32]* %tmp4, i64 0, i64 %idxprom + %tmp5 = load i32* %arrayidx, align 4, !tbaa !3 + %tmp5.lobit = lshr i32 %tmp5, 31 + ret i32 %tmp5.lobit +} + +!0 = metadata !{metadata !"double", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA", null} +!3 = metadata !{metadata !"int", metadata !1} diff --git a/test/Analysis/BasicAA/gep-alias.ll b/test/Analysis/BasicAA/gep-alias.ll index eba9599..69f7faf 100644 --- a/test/Analysis/BasicAA/gep-alias.ll +++ b/test/Analysis/BasicAA/gep-alias.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -gvn -instcombine -S |& FileCheck %s +; RUN: opt < %s -basicaa -gvn -instcombine -S |& FileCheck %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" diff --git a/test/Analysis/BasicAA/getmodrefinfo-cs-cs.ll b/test/Analysis/BasicAA/getmodrefinfo-cs-cs.ll index 12b088b..062ea59 100644 --- a/test/Analysis/BasicAA/getmodrefinfo-cs-cs.ll +++ b/test/Analysis/BasicAA/getmodrefinfo-cs-cs.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -aa-eval -print-all-alias-modref-info -disable-output |& FileCheck %s +; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info -disable-output |& FileCheck %s ; CHECK: Just Ref: call void @ro() <-> call void @f0() diff --git a/test/Analysis/BasicAA/global-size.ll b/test/Analysis/BasicAA/global-size.ll index b9cbbcc..a7e5aab 100644 --- a/test/Analysis/BasicAA/global-size.ll +++ b/test/Analysis/BasicAA/global-size.ll @@ -1,16 +1,40 @@ ; A store or load cannot alias a global if the accessed amount is larger then ; the global. -; RUN: opt < %s -basicaa -gvn -instcombine -S | not grep load +; RUN: opt < %s -basicaa -gvn -S | FileCheck %s target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" -@B = global i16 8 ; [#uses=2] +@B = global i16 8 -define i16 @test(i32* %P) { - %X = load i16* @B ; [#uses=1] +; CHECK: @test1 +define i16 @test1(i32* %P) { + %X = load i16* @B store i32 7, i32* %P - %Y = load i16* @B ; [#uses=1] - %Z = sub i16 %Y, %X ; [#uses=1] + %Y = load i16* @B + %Z = sub i16 %Y, %X ret i16 %Z +; CHECK: ret i16 0 +} + +; Cannot know anything about the size of this global. +; rdar://8813415 +@window = external global [0 x i8] + +; CHECK: @test2 +define i8 @test2(i32 %tmp79, i32 %w.2, i32 %indvar89) nounwind { + %tmp92 = add i32 %tmp79, %indvar89 + %arrayidx412 = getelementptr [0 x i8]* @window, i32 0, i32 %tmp92 + %tmp93 = add i32 %w.2, %indvar89 + %arrayidx416 = getelementptr [0 x i8]* @window, i32 0, i32 %tmp93 + + %A = load i8* %arrayidx412, align 1 + store i8 4, i8* %arrayidx416, align 1 + + %B = load i8* %arrayidx412, align 1 + %C = sub i8 %A, %B + ret i8 %C + +; CHECK: %B = load i8 +; CHECK: ret i8 %C } diff --git a/test/Analysis/BasicAA/modref.ll b/test/Analysis/BasicAA/modref.ll index b9a3c5e..ec0c8a7 100644 --- a/test/Analysis/BasicAA/modref.ll +++ b/test/Analysis/BasicAA/modref.ll @@ -85,11 +85,11 @@ define void @test3a(i8* %P, i8 %X) { %Y = add i8 %X, 1 ;; Dead, because the only use (the store) is dead. %P2 = getelementptr i8* %P, i32 2 - store i8 %Y, i8* %P2 ;; FIXME: Killed by llvm.lifetime.end, should be zapped. -; CHECK: store i8 %Y, i8* %P2 + store i8 %Y, i8* %P2 +; CHECK-NEXT: call void @llvm.lifetime.end call void @llvm.lifetime.end(i64 10, i8* %P) ret void -; CHECK: ret void +; CHECK-NEXT: ret void } @G1 = external global i32 @@ -105,7 +105,7 @@ define i32 @test4(i8* %P) { ; CHECK: load i32* @G ; CHECK: memset.p0i8.i32 ; CHECK-NOT: load -; CHECK: sub i32 %tmp, %tmp +; CHECK: ret i32 0 } ; Verify that basicaa is handling variable length memcpy, knowing it doesn't @@ -120,7 +120,7 @@ define i32 @test5(i8* %P, i32 %Len) { ; CHECK: load i32* @G ; CHECK: memcpy.p0i8.p0i8.i32 ; CHECK-NOT: load -; CHECK: sub i32 %tmp, %tmp +; CHECK: ret i32 0 } define i8 @test6(i8* %p, i8* noalias %a) { diff --git a/test/Analysis/BasicAA/phi-aa.ll b/test/Analysis/BasicAA/phi-aa.ll index 0288960..50fd5cd 100644 --- a/test/Analysis/BasicAA/phi-aa.ll +++ b/test/Analysis/BasicAA/phi-aa.ll @@ -5,7 +5,7 @@ @Y = common global i32 0 @Z = common global i32 0 -define void @foo(i32 %cond) nounwind ssp { +define void @foo(i32 %cond) nounwind { entry: %"alloca point" = bitcast i32 0 to i32 %tmp = icmp ne i32 %cond, 0 diff --git a/test/Analysis/BasicAA/phi-and-select.ll b/test/Analysis/BasicAA/phi-and-select.ll index c69e824..9bc47ae 100644 --- a/test/Analysis/BasicAA/phi-and-select.ll +++ b/test/Analysis/BasicAA/phi-and-select.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -aa-eval -print-all-alias-modref-info -disable-output \ +; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info -disable-output \ ; RUN: |& grep {NoAlias: double\\* \[%\]a, double\\* \[%\]b\$} | count 4 ; BasicAA should detect NoAliases in PHIs and Selects. diff --git a/test/Analysis/BasicAA/unreachable-block.ll b/test/Analysis/BasicAA/unreachable-block.ll index 3382188..1ca1e66 100644 --- a/test/Analysis/BasicAA/unreachable-block.ll +++ b/test/Analysis/BasicAA/unreachable-block.ll @@ -1,4 +1,4 @@ -; RUN: opt -aa-eval -disable-output < %s >& /dev/null +; RUN: opt -basicaa -aa-eval -disable-output < %s >& /dev/null ; BasicAA shouldn't infinitely recurse on the use-def cycles in ; unreachable code. diff --git a/test/Analysis/GlobalsModRef/aliastest.ll b/test/Analysis/GlobalsModRef/aliastest.ll index 3e5d119..75af4dc 100644 --- a/test/Analysis/GlobalsModRef/aliastest.ll +++ b/test/Analysis/GlobalsModRef/aliastest.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -globalsmodref-aa -gvn -S | not grep load +; RUN: opt < %s -basicaa -globalsmodref-aa -gvn -S | not grep load @X = internal global i32 4 ; [#uses=1] define i32 @test(i32* %P) { diff --git a/test/Analysis/GlobalsModRef/chaining-analysis.ll b/test/Analysis/GlobalsModRef/chaining-analysis.ll index b1d4593..431b2a6 100644 --- a/test/Analysis/GlobalsModRef/chaining-analysis.ll +++ b/test/Analysis/GlobalsModRef/chaining-analysis.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -globalsmodref-aa -gvn -S | not grep load +; RUN: opt < %s -basicaa -globalsmodref-aa -gvn -S | not grep load ; This test requires the use of previous analyses to determine that ; doesnotmodX does not modify X (because 'sin' doesn't). diff --git a/test/Analysis/GlobalsModRef/indirect-global.ll b/test/Analysis/GlobalsModRef/indirect-global.ll index 4074909..1eab0bc 100644 --- a/test/Analysis/GlobalsModRef/indirect-global.ll +++ b/test/Analysis/GlobalsModRef/indirect-global.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -globalsmodref-aa -gvn -instcombine -S | \ +; RUN: opt < %s -basicaa -globalsmodref-aa -gvn -instcombine -S | \ ; RUN: grep {ret i32 0} @G = internal global i32* null ; [#uses=3] diff --git a/test/Analysis/GlobalsModRef/modreftest.ll b/test/Analysis/GlobalsModRef/modreftest.ll index 257c0ee..3a02a94a 100644 --- a/test/Analysis/GlobalsModRef/modreftest.ll +++ b/test/Analysis/GlobalsModRef/modreftest.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -globalsmodref-aa -gvn -S | not grep load +; RUN: opt < %s -basicaa -globalsmodref-aa -gvn -S | not grep load @X = internal global i32 4 ; [#uses=2] define i32 @test(i32* %P) { diff --git a/test/Analysis/LoopDependenceAnalysis/alias.ll b/test/Analysis/LoopDependenceAnalysis/alias.ll index 97be3fd..78d0bf4 100644 --- a/test/Analysis/LoopDependenceAnalysis/alias.ll +++ b/test/Analysis/LoopDependenceAnalysis/alias.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -analyze -lda | FileCheck %s +; RUN: opt < %s -analyze -basicaa -lda | FileCheck %s ;; x[5] = x[6] // with x being a pointer passed as argument diff --git a/test/Analysis/LoopDependenceAnalysis/siv-strong.ll b/test/Analysis/LoopDependenceAnalysis/siv-strong.ll index 36ac153..401e466 100644 --- a/test/Analysis/LoopDependenceAnalysis/siv-strong.ll +++ b/test/Analysis/LoopDependenceAnalysis/siv-strong.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -analyze -lda | FileCheck %s +; RUN: opt < %s -analyze -basicaa -lda | FileCheck %s @x = common global [256 x i32] zeroinitializer, align 4 @y = common global [256 x i32] zeroinitializer, align 4 diff --git a/test/Analysis/LoopDependenceAnalysis/siv-weak-crossing.ll b/test/Analysis/LoopDependenceAnalysis/siv-weak-crossing.ll index a7f9bda..9d0128c 100644 --- a/test/Analysis/LoopDependenceAnalysis/siv-weak-crossing.ll +++ b/test/Analysis/LoopDependenceAnalysis/siv-weak-crossing.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -analyze -lda | FileCheck %s +; RUN: opt < %s -analyze -basicaa -lda | FileCheck %s @x = common global [256 x i32] zeroinitializer, align 4 @y = common global [256 x i32] zeroinitializer, align 4 diff --git a/test/Analysis/LoopDependenceAnalysis/siv-weak-zero.ll b/test/Analysis/LoopDependenceAnalysis/siv-weak-zero.ll index e75aefd..1c5ae4c 100644 --- a/test/Analysis/LoopDependenceAnalysis/siv-weak-zero.ll +++ b/test/Analysis/LoopDependenceAnalysis/siv-weak-zero.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -analyze -lda | FileCheck %s +; RUN: opt < %s -analyze -basicaa -lda | FileCheck %s @x = common global [256 x i32] zeroinitializer, align 4 @y = common global [256 x i32] zeroinitializer, align 4 diff --git a/test/Analysis/LoopDependenceAnalysis/ziv.ll b/test/Analysis/LoopDependenceAnalysis/ziv.ll index ba45948..645ae7f 100644 --- a/test/Analysis/LoopDependenceAnalysis/ziv.ll +++ b/test/Analysis/LoopDependenceAnalysis/ziv.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -analyze -lda | FileCheck %s +; RUN: opt < %s -analyze -basicaa -lda | FileCheck %s @x = common global [256 x i32] zeroinitializer, align 4 diff --git a/test/Analysis/PointerTracking/dg.exp b/test/Analysis/PointerTracking/dg.exp deleted file mode 100644 index f200589..0000000 --- a/test/Analysis/PointerTracking/dg.exp +++ /dev/null @@ -1,3 +0,0 @@ -load_lib llvm.exp - -RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]] diff --git a/test/Analysis/PointerTracking/sizes.ll b/test/Analysis/PointerTracking/sizes.ll deleted file mode 100644 index c8ca648..0000000 --- a/test/Analysis/PointerTracking/sizes.ll +++ /dev/null @@ -1,86 +0,0 @@ -; RUN: opt < %s -pointertracking -analyze | FileCheck %s -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" -target triple = "x86_64-unknown-linux-gnu" -@.str = internal constant [5 x i8] c"1234\00" ; <[5 x i8]*> [#uses=1] -@test1p = global i8* getelementptr ([5 x i8]* @.str, i32 0, i32 0), align 8 ; [#uses=1] -@test1a = global [5 x i8] c"1234\00", align 1 ; <[5 x i8]*> [#uses=1] -@test2a = global [5 x i32] [i32 1, i32 2, i32 3, i32 4, i32 5], align 4 ; <[5 x i32]*> [#uses=2] -@test2p = global i32* getelementptr ([5 x i32]* @test2a, i32 0, i32 0), align 8 ; [#uses=1] -@test0p = common global i32* null, align 8 ; [#uses=1] -@test0i = common global i32 0, align 4 ; [#uses=1] - -define i32 @foo0() nounwind { -entry: - %tmp = load i32** @test0p ; [#uses=1] - %conv = bitcast i32* %tmp to i8* ; [#uses=1] - %call = tail call i32 @bar(i8* %conv) nounwind ; [#uses=1] - %tmp1 = load i8** @test1p ; [#uses=1] - %call2 = tail call i32 @bar(i8* %tmp1) nounwind ; [#uses=1] - %call3 = tail call i32 @bar(i8* getelementptr ([5 x i8]* @test1a, i32 0, i32 0)) nounwind ; [#uses=1] - %call5 = tail call i32 @bar(i8* bitcast ([5 x i32]* @test2a to i8*)) nounwind ; [#uses=1] - %tmp7 = load i32** @test2p ; [#uses=1] - %conv8 = bitcast i32* %tmp7 to i8* ; [#uses=1] - %call9 = tail call i32 @bar(i8* %conv8) nounwind ; [#uses=1] - %call11 = tail call i32 @bar(i8* bitcast (i32* @test0i to i8*)) nounwind ; [#uses=1] - %add = add i32 %call2, %call ; [#uses=1] - %add4 = add i32 %add, %call3 ; [#uses=1] - %add6 = add i32 %add4, %call5 ; [#uses=1] - %add10 = add i32 %add6, %call9 ; [#uses=1] - %add12 = add i32 %add10, %call11 ; [#uses=1] - ret i32 %add12 -} - -declare i32 @bar(i8*) - -define i32 @foo1(i32 %n) nounwind { -entry: -; CHECK: 'foo1': - %test4a = alloca [10 x i8], align 1 ; <[10 x i8]*> [#uses=1] -; CHECK: %test4a = -; CHECK: ==> 1 elements, 10 bytes allocated - %test6a = alloca [10 x i32], align 4 ; <[10 x i32]*> [#uses=1] -; CHECK: %test6a = -; CHECK: ==> 1 elements, 40 bytes allocated - %vla = alloca i8, i32 %n, align 1 ; [#uses=1] -; CHECK: %vla = -; CHECK: ==> %n elements, %n bytes allocated - %0 = shl i32 %n, 2 ; [#uses=1] - %vla7 = alloca i8, i32 %0, align 1 ; [#uses=1] -; CHECK: %vla7 = -; CHECK: ==> (4 * %n) elements, (4 * %n) bytes allocated - %call = call i32 @bar(i8* %vla) nounwind ; [#uses=1] - %arraydecay = getelementptr [10 x i8]* %test4a, i64 0, i64 0 ; [#uses=1] - %call10 = call i32 @bar(i8* %arraydecay) nounwind ; [#uses=1] - %call11 = call i32 @bar(i8* %vla7) nounwind ; [#uses=1] - %ptrconv14 = bitcast [10 x i32]* %test6a to i8* ; [#uses=1] - %call15 = call i32 @bar(i8* %ptrconv14) nounwind ; [#uses=1] - %add = add i32 %call10, %call ; [#uses=1] - %add12 = add i32 %add, %call11 ; [#uses=1] - %add16 = add i32 %add12, %call15 ; [#uses=1] - ret i32 %add16 -} - -define i32 @foo2(i64 %n) nounwind { -entry: - %call = tail call i8* @malloc(i64 %n) ; [#uses=1] -; CHECK: %call = -; CHECK: ==> %n elements, %n bytes allocated - %call2 = tail call i8* @calloc(i64 2, i64 4) nounwind ; [#uses=1] -; CHECK: %call2 = -; CHECK: ==> 8 elements, 8 bytes allocated - %call4 = tail call i8* @realloc(i8* null, i64 16) nounwind ; [#uses=1] -; CHECK: %call4 = -; CHECK: ==> 16 elements, 16 bytes allocated - %call6 = tail call i32 @bar(i8* %call) nounwind ; [#uses=1] - %call8 = tail call i32 @bar(i8* %call2) nounwind ; [#uses=1] - %call10 = tail call i32 @bar(i8* %call4) nounwind ; [#uses=1] - %add = add i32 %call8, %call6 ; [#uses=1] - %add11 = add i32 %add, %call10 ; [#uses=1] - ret i32 %add11 -} - -declare noalias i8* @malloc(i64) nounwind - -declare noalias i8* @calloc(i64, i64) nounwind - -declare noalias i8* @realloc(i8* nocapture, i64) nounwind diff --git a/test/Analysis/Profiling/profiling-tool-chain.ll b/test/Analysis/Profiling/profiling-tool-chain.ll index 5ac31b5..9135a85 100644 --- a/test/Analysis/Profiling/profiling-tool-chain.ll +++ b/test/Analysis/Profiling/profiling-tool-chain.ll @@ -9,8 +9,8 @@ ; Test the creation, reading and displaying of profile ; RUX: rm -f llvmprof.out -; RUX: lli -load %llvmlibsdir/profile_rt%shlibext %t2 -; RUX: lli -load %llvmlibsdir/profile_rt%shlibext %t2 1 2 +; RUX: lli -load %llvmshlibdir/profile_rt%shlibext %t2 +; RUX: lli -load %llvmshlibdir/profile_rt%shlibext %t2 1 2 ; RUX: llvm-prof -print-all-code %t1 | FileCheck --check-prefix=PROF %s ; Test the loaded profile also with verifier. diff --git a/test/Analysis/ScalarEvolution/2010-09-03-RequiredTransitive.ll b/test/Analysis/ScalarEvolution/2010-09-03-RequiredTransitive.ll new file mode 100644 index 0000000..aba0ce7 --- /dev/null +++ b/test/Analysis/ScalarEvolution/2010-09-03-RequiredTransitive.ll @@ -0,0 +1,24 @@ +; RUN: opt -indvars -scalar-evolution -analyze %s +; This test checks if the SCEV analysis is printed out at all. +; It failed once as the RequiredTransitive option was not implemented +; correctly. + +define i32 @main() nounwind { +entry: + br label %for.cond + +for.cond: ; preds = %for.inc, %entry + %indvar1 = phi i64 [ %indvar.next2, %for.inc ], [ 0, %entry ] ; [#uses=3] + %exitcond = icmp ne i64 %indvar1, 1024 ; [#uses=1] + br i1 %exitcond, label %for.body, label %for.end + +for.body: ; preds = %for.cond + br label %for.inc + +for.inc: ; preds = %for.body + %indvar.next2 = add i64 %indvar1, 1 ; [#uses=1] + br label %for.cond + +for.end: ; preds = %for.cond + ret i32 0 +} diff --git a/test/Analysis/ScalarEvolution/fold.ll b/test/Analysis/ScalarEvolution/fold.ll new file mode 100644 index 0000000..4e2adf1 --- /dev/null +++ b/test/Analysis/ScalarEvolution/fold.ll @@ -0,0 +1,62 @@ +; RUN: opt -analyze -scalar-evolution %s -S | FileCheck %s + +define i16 @test1(i8 %x) { + %A = zext i8 %x to i12 + %B = sext i12 %A to i16 +; CHECK: zext i8 %x to i16 + ret i16 %B +} + +define i8 @test2(i8 %x) { + %A = zext i8 %x to i16 + %B = add i16 %A, 1025 + %C = trunc i16 %B to i8 +; CHECK: (1 + %x) + ret i8 %C +} + +define i8 @test3(i8 %x) { + %A = zext i8 %x to i16 + %B = mul i16 %A, 1027 + %C = trunc i16 %B to i8 +; CHECK: (3 * %x) + ret i8 %C +} + +define void @test4(i32 %x, i32 %y) { +entry: + %Y = and i32 %y, 3 + br label %loop +loop: + %A = phi i32 [0, %entry], [%I, %loop] + %rand1 = icmp sgt i32 %A, %Y + %Z1 = select i1 %rand1, i32 %A, i32 %Y + %rand2 = icmp ugt i32 %A, %Z1 + %Z2 = select i1 %rand2, i32 %A, i32 %Z1 +; CHECK: %Z2 = +; CHECK-NEXT: --> ([[EXPR:.*]]){{ +}}Exits: 20 + %B = trunc i32 %Z2 to i16 + %C = sext i16 %B to i30 +; CHECK: %C = +; CHECK-NEXT: (trunc i32 ([[EXPR]]) to i30) + %D = sext i16 %B to i32 +; CHECK: %D = +; CHECK-NEXT: ([[EXPR]]) + %E = sext i16 %B to i34 +; CHECK: %E = +; CHECK-NEXT: (zext i32 ([[EXPR]]) to i34) + %F = zext i16 %B to i30 +; CHECK: %F = +; CHECK-NEXT: (trunc i32 ([[EXPR]]) to i30 + %G = zext i16 %B to i32 +; CHECK: %G = +; CHECK-NEXT: ([[EXPR]]) + %H = zext i16 %B to i34 +; CHECK: %H = +; CHECK-NEXT: (zext i32 ([[EXPR]]) to i34) + %I = add i32 %A, 1 + %0 = icmp ne i32 %A, 20 + br i1 %0, label %loop, label %exit +exit: + ret void +} diff --git a/test/Analysis/ScalarEvolution/nsw.ll b/test/Analysis/ScalarEvolution/nsw.ll index 456f3f0..9d8e2b6 100644 --- a/test/Analysis/ScalarEvolution/nsw.ll +++ b/test/Analysis/ScalarEvolution/nsw.ll @@ -1,10 +1,11 @@ -; RUN: opt < %s -analyze -scalar-evolution | grep { --> {.*,+,.*}<%bb>} | count 8 +; RUN: opt < %s -analyze -scalar-evolution | FileCheck %s ; The addrecs in this loop are analyzable only by using nsw information. target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64" -define void @foo(double* %p) nounwind { +; CHECK: Classifying expressions for: @test1 +define void @test1(double* %p) nounwind { entry: %tmp = load double* %p, align 8 ; [#uses=1] %tmp1 = fcmp ogt double %tmp, 2.000000e+00 ; [#uses=1] @@ -15,19 +16,29 @@ bb.nph: ; preds = %entry bb: ; preds = %bb1, %bb.nph %i.01 = phi i32 [ %tmp8, %bb1 ], [ 0, %bb.nph ] ; [#uses=3] +; CHECK: %i.01 +; CHECK-NEXT: --> {0,+,1}<%bb> %tmp2 = sext i32 %i.01 to i64 ; [#uses=1] %tmp3 = getelementptr double* %p, i64 %tmp2 ; [#uses=1] %tmp4 = load double* %tmp3, align 8 ; [#uses=1] %tmp5 = fmul double %tmp4, 9.200000e+00 ; [#uses=1] %tmp6 = sext i32 %i.01 to i64 ; [#uses=1] %tmp7 = getelementptr double* %p, i64 %tmp6 ; [#uses=1] +; CHECK: %tmp7 +; CHECK-NEXT: --> {%p,+,8}<%bb> store double %tmp5, double* %tmp7, align 8 %tmp8 = add nsw i32 %i.01, 1 ; [#uses=2] +; CHECK: %tmp8 +; CHECK-NEXT: --> {1,+,1}<%bb> br label %bb1 bb1: ; preds = %bb %phitmp = sext i32 %tmp8 to i64 ; [#uses=1] +; CHECK: %phitmp +; CHECK-NEXT: --> {1,+,1}<%bb> %tmp9 = getelementptr double* %p, i64 %phitmp ; [#uses=1] +; CHECK: %tmp9 +; CHECK-NEXT: --> {(8 + %p),+,8}<%bb> %tmp10 = load double* %tmp9, align 8 ; [#uses=1] %tmp11 = fcmp ogt double %tmp10, 2.000000e+00 ; [#uses=1] br i1 %tmp11, label %bb, label %bb1.return_crit_edge @@ -38,3 +49,58 @@ bb1.return_crit_edge: ; preds = %bb1 return: ; preds = %bb1.return_crit_edge, %entry ret void } + +; CHECK: Classifying expressions for: @test2 +define void @test2(i32* %begin, i32* %end) ssp { +entry: + %cmp1.i.i = icmp eq i32* %begin, %end + br i1 %cmp1.i.i, label %_ZSt4fillIPiiEvT_S1_RKT0_.exit, label %for.body.lr.ph.i.i + +for.body.lr.ph.i.i: ; preds = %entry + br label %for.body.i.i + +for.body.i.i: ; preds = %for.body.i.i, %for.body.lr.ph.i.i + %__first.addr.02.i.i = phi i32* [ %begin, %for.body.lr.ph.i.i ], [ %ptrincdec.i.i, %for.body.i.i ] +; CHECK: %__first.addr.02.i.i +; CHECK-NEXT: --> {%begin,+,4}<%for.body.i.i> + store i32 0, i32* %__first.addr.02.i.i, align 4 + %ptrincdec.i.i = getelementptr inbounds i32* %__first.addr.02.i.i, i64 1 +; CHECK: %ptrincdec.i.i +; CHECK-NEXT: --> {(4 + %begin),+,4}<%for.body.i.i> + %cmp.i.i = icmp eq i32* %ptrincdec.i.i, %end + br i1 %cmp.i.i, label %for.cond.for.end_crit_edge.i.i, label %for.body.i.i + +for.cond.for.end_crit_edge.i.i: ; preds = %for.body.i.i + br label %_ZSt4fillIPiiEvT_S1_RKT0_.exit + +_ZSt4fillIPiiEvT_S1_RKT0_.exit: ; preds = %entry, %for.cond.for.end_crit_edge.i.i + ret void +} + +; Various checks for inbounds geps. +define void @test3(i32* %begin, i32* %end) nounwind ssp { +entry: + %cmp7.i.i = icmp eq i32* %begin, %end + br i1 %cmp7.i.i, label %_ZSt4fillIPiiEvT_S1_RKT0_.exit, label %for.body.i.i + +for.body.i.i: ; preds = %entry, %for.body.i.i + %indvar.i.i = phi i64 [ %tmp, %for.body.i.i ], [ 0, %entry ] +; CHECK: %indvar.i.i +; CHECK: {0,+,1}<%for.body.i.i> + %tmp = add nsw i64 %indvar.i.i, 1 +; CHECK: %tmp = +; CHECK: {1,+,1}<%for.body.i.i> + %ptrincdec.i.i = getelementptr inbounds i32* %begin, i64 %tmp +; CHECK: %ptrincdec.i.i = +; CHECK: {(4 + %begin),+,4}<%for.body.i.i> + %__first.addr.08.i.i = getelementptr inbounds i32* %begin, i64 %indvar.i.i +; CHECK: %__first.addr.08.i.i +; CHECK: {%begin,+,4}<%for.body.i.i> + store i32 0, i32* %__first.addr.08.i.i, align 4 + %cmp.i.i = icmp eq i32* %ptrincdec.i.i, %end + br i1 %cmp.i.i, label %_ZSt4fillIPiiEvT_S1_RKT0_.exit, label %for.body.i.i +; CHECK: Loop %for.body.i.i: Unpredictable backedge-taken count. +; CHECK: Loop %for.body.i.i: Unpredictable max backedge-taken count. +_ZSt4fillIPiiEvT_S1_RKT0_.exit: ; preds = %for.body.i.i, %entry + ret void +} \ No newline at end of file diff --git a/test/Analysis/ScalarEvolution/scev-aa.ll b/test/Analysis/ScalarEvolution/scev-aa.ll index 866664a..dd5a66c 100644 --- a/test/Analysis/ScalarEvolution/scev-aa.ll +++ b/test/Analysis/ScalarEvolution/scev-aa.ll @@ -190,9 +190,8 @@ define void @bar() { ret void } -; TODO: This is theoretically provable to be NoAlias. ; CHECK: Function: nonnegative: 2 pointers, 0 call sites -; CHECK: MayAlias: i64* %arrayidx, i64* %p +; CHECK: NoAlias: i64* %arrayidx, i64* %p define void @nonnegative(i64* %p) nounwind { entry: @@ -211,6 +210,6 @@ for.end: ; preds = %for.body, %entry ret void } -; CHECK: 13 no alias responses -; CHECK: 27 may alias responses +; CHECK: 14 no alias responses +; CHECK: 26 may alias responses ; CHECK: 18 must alias responses diff --git a/test/Analysis/TypeBasedAliasAnalysis/aliastest.ll b/test/Analysis/TypeBasedAliasAnalysis/aliastest.ll new file mode 100644 index 0000000..d59e392 --- /dev/null +++ b/test/Analysis/TypeBasedAliasAnalysis/aliastest.ll @@ -0,0 +1,62 @@ +; RUN: opt < %s -tbaa -basicaa -gvn -S | FileCheck %s + +; Test that basic alias queries work. + +; CHECK: @test0_yes +; CHECK: add i8 %x, %x +define i8 @test0_yes(i8* %a, i8* %b) nounwind { + %x = load i8* %a, !tbaa !1 + store i8 0, i8* %b, !tbaa !2 + %y = load i8* %a, !tbaa !1 + %z = add i8 %x, %y + ret i8 %z +} + +; CHECK: @test0_no +; CHECK: add i8 %x, %y +define i8 @test0_no(i8* %a, i8* %b) nounwind { + %x = load i8* %a, !tbaa !3 + store i8 0, i8* %b, !tbaa !4 + %y = load i8* %a, !tbaa !3 + %z = add i8 %x, %y + ret i8 %z +} + +; Test that basic invariant-memory queries work. + +; CHECK: @test1_yes +; CHECK: add i8 %x, %x +define i8 @test1_yes(i8* %a, i8* %b) nounwind { + %x = load i8* %a, !tbaa !5 + store i8 0, i8* %b + %y = load i8* %a, !tbaa !5 + %z = add i8 %x, %y + ret i8 %z +} + +; CHECK: @test1_no +; CHECK: add i8 %x, %y +define i8 @test1_no(i8* %a, i8* %b) nounwind { + %x = load i8* %a, !tbaa !6 + store i8 0, i8* %b + %y = load i8* %a, !tbaa !6 + %z = add i8 %x, %y + ret i8 %z +} + +; Root note. +!0 = metadata !{ } +; Some type. +!1 = metadata !{ metadata !"foo", metadata !0 } +; Some other non-aliasing type. +!2 = metadata !{ metadata !"bar", metadata !0 } + +; Some type. +!3 = metadata !{ metadata !"foo", metadata !0 } +; Some type in a different type system. +!4 = metadata !{ metadata !"bar", metadata !"different" } + +; Invariant memory. +!5 = metadata !{ metadata !"qux", metadata !0, i1 1 } +; Not invariant memory. +!6 = metadata !{ metadata !"qux", metadata !0, i1 0 } diff --git a/test/Analysis/TypeBasedAliasAnalysis/argument-promotion.ll b/test/Analysis/TypeBasedAliasAnalysis/argument-promotion.ll new file mode 100644 index 0000000..3b5211e --- /dev/null +++ b/test/Analysis/TypeBasedAliasAnalysis/argument-promotion.ll @@ -0,0 +1,31 @@ +; RUN: opt < %s -tbaa -basicaa -argpromotion -mem2reg -S | not grep alloca + +target datalayout = "E-p:64:64:64" + +define internal i32 @test(i32* %X, i32* %Y, i32* %Q) { + store i32 77, i32* %Q, !tbaa !2 + %A = load i32* %X, !tbaa !1 + %B = load i32* %Y, !tbaa !1 + %C = add i32 %A, %B + ret i32 %C +} + +define internal i32 @caller(i32* %B, i32* %Q) { + %A = alloca i32 + store i32 78, i32* %Q, !tbaa !2 + store i32 1, i32* %A, !tbaa !1 + %C = call i32 @test(i32* %A, i32* %B, i32* %Q) + ret i32 %C +} + +define i32 @callercaller(i32* %Q) { + %B = alloca i32 + store i32 2, i32* %B, !tbaa !1 + store i32 79, i32* %Q, !tbaa !2 + %X = call i32 @caller(i32* %B, i32* %Q) + ret i32 %X +} + +!0 = metadata !{metadata !"test"} +!1 = metadata !{metadata !"green", metadata !0} +!2 = metadata !{metadata !"blue", metadata !0} diff --git a/test/Analysis/TypeBasedAliasAnalysis/dg.exp b/test/Analysis/TypeBasedAliasAnalysis/dg.exp new file mode 100644 index 0000000..f200589 --- /dev/null +++ b/test/Analysis/TypeBasedAliasAnalysis/dg.exp @@ -0,0 +1,3 @@ +load_lib llvm.exp + +RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]] diff --git a/test/Analysis/TypeBasedAliasAnalysis/dse.ll b/test/Analysis/TypeBasedAliasAnalysis/dse.ll new file mode 100644 index 0000000..6b44eb6 --- /dev/null +++ b/test/Analysis/TypeBasedAliasAnalysis/dse.ll @@ -0,0 +1,66 @@ +; RUN: opt < %s -tbaa -basicaa -dse -S | FileCheck %s + +; DSE should make use of TBAA. + +; CHECK: @test0_yes +; CHECK-NEXT: load i8* %b +; CHECK-NEXT: store i8 1, i8* %a +; CHECK-NEXT: ret i8 %y +define i8 @test0_yes(i8* %a, i8* %b) nounwind { + store i8 0, i8* %a, !tbaa !1 + %y = load i8* %b, !tbaa !2 + store i8 1, i8* %a, !tbaa !1 + ret i8 %y +} + +; CHECK: @test0_no +; CHECK-NEXT: store i8 0, i8* %a +; CHECK-NEXT: load i8* %b +; CHECK-NEXT: store i8 1, i8* %a +; CHECK-NEXT: ret i8 %y +define i8 @test0_no(i8* %a, i8* %b) nounwind { + store i8 0, i8* %a, !tbaa !3 + %y = load i8* %b, !tbaa !4 + store i8 1, i8* %a, !tbaa !3 + ret i8 %y +} + +; CHECK: @test1_yes +; CHECK-NEXT: load i8* %b +; CHECK-NEXT: store i8 1, i8* %a +; CHECK-NEXT: ret i8 %y +define i8 @test1_yes(i8* %a, i8* %b) nounwind { + store i8 0, i8* %a + %y = load i8* %b, !tbaa !5 + store i8 1, i8* %a + ret i8 %y +} + +; CHECK: @test1_no +; CHECK-NEXT: store i8 0, i8* %a +; CHECK-NEXT: load i8* %b +; CHECK-NEXT: store i8 1, i8* %a +; CHECK-NEXT: ret i8 %y +define i8 @test1_no(i8* %a, i8* %b) nounwind { + store i8 0, i8* %a + %y = load i8* %b, !tbaa !6 + store i8 1, i8* %a + ret i8 %y +} + +; Root note. +!0 = metadata !{ } +; Some type. +!1 = metadata !{ metadata !"foo", metadata !0 } +; Some other non-aliasing type. +!2 = metadata !{ metadata !"bar", metadata !0 } + +; Some type. +!3 = metadata !{ metadata !"foo", metadata !0 } +; Some type in a different type system. +!4 = metadata !{ metadata !"bar", metadata !"different" } + +; Invariant memory. +!5 = metadata !{ metadata !"qux", metadata !0, i1 1 } +; Not invariant memory. +!6 = metadata !{ metadata !"qux", metadata !0, i1 0 } diff --git a/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll b/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll new file mode 100644 index 0000000..8fb5fff --- /dev/null +++ b/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll @@ -0,0 +1,81 @@ +; RUN: opt < %s -tbaa -basicaa -functionattrs -S | FileCheck %s + +; FunctionAttrs should make use of TBAA. + +; Add the readnone attribute, since the only access is a store which TBAA +; says is to constant memory. +; +; It's unusual to see a store to constant memory, but it isn't necessarily +; invalid, as it's possible that this only happens after optimization on a +; code path which isn't ever executed. + +; CHECK: define void @test0_yes(i32* nocapture %p) nounwind readnone { +define void @test0_yes(i32* %p) nounwind { + store i32 0, i32* %p, !tbaa !1 + ret void +} + +; CHECK: define void @test0_no(i32* nocapture %p) nounwind { +define void @test0_no(i32* %p) nounwind { + store i32 0, i32* %p, !tbaa !2 + ret void +} + +; Add the readonly attribute, since there's just a call to a function which +; TBAA says doesn't modify any memory. + +; CHECK: define void @test1_yes(i32* %p) nounwind readonly { +define void @test1_yes(i32* %p) nounwind { + call void @callee(i32* %p), !tbaa !1 + ret void +} + +; CHECK: define void @test1_no(i32* %p) nounwind { +define void @test1_no(i32* %p) nounwind { + call void @callee(i32* %p), !tbaa !2 + ret void +} + +; Add the readonly attribute, as above, but this time BasicAA will say +; that the function accesses memory through its arguments, which TBAA +; still says that the function doesn't write to memory. +; +; This is unusual, since the function is memcpy, but as above, this +; isn't necessarily invalid. + +; CHECK: define void @test2_yes(i8* nocapture %p, i8* nocapture %q, i64 %n) nounwind readnone { +define void @test2_yes(i8* %p, i8* %q, i64 %n) nounwind { + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %p, i8* %q, i64 %n, i32 1, i1 false), !tbaa !1 + ret void +} + +; CHECK: define void @test2_no(i8* nocapture %p, i8* nocapture %q, i64 %n) nounwind { +define void @test2_no(i8* %p, i8* %q, i64 %n) nounwind { + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %p, i8* %q, i64 %n, i32 1, i1 false), !tbaa !2 + ret void +} + +; Similar to the others, va_arg only accesses memory through its operand. + +; CHECK: define i32 @test3_yes(i8* nocapture %p) nounwind readnone { +define i32 @test3_yes(i8* %p) nounwind { + %t = va_arg i8* %p, i32, !tbaa !1 + ret i32 %t +} + +; CHECK: define i32 @test3_no(i8* nocapture %p) nounwind { +define i32 @test3_no(i8* %p) nounwind { + %t = va_arg i8* %p, i32, !tbaa !2 + ret i32 %t +} + +declare void @callee(i32* %p) nounwind +declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i32, i1) nounwind + +; Root note. +!0 = metadata !{ } + +; Invariant memory. +!1 = metadata !{ metadata !"foo", metadata !0, i1 1 } +; Not invariant memory. +!2 = metadata !{ metadata !"foo", metadata !0, i1 0 } diff --git a/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll b/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll new file mode 100644 index 0000000..eceaa2c --- /dev/null +++ b/test/Analysis/TypeBasedAliasAnalysis/gvn-nonlocal-type-mismatch.ll @@ -0,0 +1,91 @@ +; RUN: opt -tbaa -basicaa -gvn -S < %s | FileCheck %s + +target datalayout = "e-p:64:64:64" + +; GVN should ignore the store to p1 to see that the load from p is +; fully redundant. + +; CHECK: @yes +; CHECK: if.then: +; CHECK-NEXT: store i32 0, i32* %q +; CHECK-NEXT: ret void + +define void @yes(i1 %c, i32* %p, i32* %p1, i32* %q) nounwind { +entry: + store i32 0, i32* %p, !tbaa !1 + store i32 1, i32* %p1, !tbaa !2 + br i1 %c, label %if.else, label %if.then + +if.then: + %t = load i32* %p, !tbaa !1 + store i32 %t, i32* %q + ret void + +if.else: + ret void +} + +; GVN should ignore the store to p1 to see that the first load from p is +; fully redundant. However, the second load uses a different type. Theoretically +; the other type could be unified with the first type, however for now, GVN +; should just be conservative. + +; CHECK: @watch_out_for_type_change +; CHECK: if.then: +; CHECK: %t = load i32* %p +; CHECK: store i32 %t, i32* %q +; CHECK: ret void +; CHECK: if.else: +; CHECK: %u = load i32* %p +; CHECK: store i32 %u, i32* %q + +define void @watch_out_for_type_change(i1 %c, i32* %p, i32* %p1, i32* %q) nounwind { +entry: + store i32 0, i32* %p, !tbaa !1 + store i32 1, i32* %p1, !tbaa !2 + br i1 %c, label %if.else, label %if.then + +if.then: + %t = load i32* %p, !tbaa !4 + store i32 %t, i32* %q + ret void + +if.else: + %u = load i32* %p, !tbaa !3 + store i32 %u, i32* %q + ret void +} + +; As before, but the types are swapped. This time GVN does managed to +; eliminate one of the loads before noticing the type mismatch. + +; CHECK: @watch_out_for_another_type_change +; CHECK: if.then: +; CHECK: %t = load i32* %p +; CHECK: store i32 %t, i32* %q +; CHECK: ret void +; CHECK: if.else: +; CHECK: store i32 0, i32* %q + +define void @watch_out_for_another_type_change(i1 %c, i32* %p, i32* %p1, i32* %q) nounwind { +entry: + store i32 0, i32* %p, !tbaa !1 + store i32 1, i32* %p1, !tbaa !2 + br i1 %c, label %if.else, label %if.then + +if.then: + %t = load i32* %p, !tbaa !3 + store i32 %t, i32* %q + ret void + +if.else: + %u = load i32* %p, !tbaa !4 + store i32 %u, i32* %q + ret void +} + +!0 = metadata !{} +!1 = metadata !{metadata !"red", metadata !0} +!2 = metadata !{metadata !"blu", metadata !0} +!3 = metadata !{metadata !"outer space"} +!4 = metadata !{metadata !"brick red", metadata !1} diff --git a/test/Analysis/TypeBasedAliasAnalysis/licm.ll b/test/Analysis/TypeBasedAliasAnalysis/licm.ll new file mode 100644 index 0000000..12a9c1d --- /dev/null +++ b/test/Analysis/TypeBasedAliasAnalysis/licm.ll @@ -0,0 +1,61 @@ +; RUN: opt -tbaa -licm -S < %s | FileCheck %s + +; LICM should be able to hoist the address load out of the loop +; by using TBAA information. + +; CHECK: @foo +; CHECK: entry: +; CHECK-NEXT: %tmp3 = load double** @P, !tbaa !0 +; CHECK-NEXT: br label %for.body + +@P = common global double* null + +define void @foo(i64 %n) nounwind { +entry: + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.07 = phi i64 [ %inc, %for.body ], [ 0, %entry ] + %tmp3 = load double** @P, !tbaa !1 + %scevgep = getelementptr double* %tmp3, i64 %i.07 + %tmp4 = load double* %scevgep, !tbaa !2 + %mul = fmul double %tmp4, 2.300000e+00 + store double %mul, double* %scevgep, !tbaa !2 + %inc = add i64 %i.07, 1 + %exitcond = icmp eq i64 %inc, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body, %entry + ret void +} + +!0 = metadata !{metadata !"root", null} +!1 = metadata !{metadata !"pointer", metadata !0} +!2 = metadata !{metadata !"double", metadata !0} + +; LICM shouldn't hoist anything here. + +; CHECK: @bar +; CHECK: loop: +; CHECK: load +; CHECK: store +; CHECK: load +; CHECK: store +; CHECK: br label %loop + +define void @bar(i8** %p) nounwind { +entry: + %q = bitcast i8** %p to i8* + br label %loop + +loop: + %tmp51 = load i8** %p, !tbaa !4 + store i8* %tmp51, i8** %p + %tmp40 = load i8* %q, !tbaa !5 + store i8 %tmp40, i8* %q + br label %loop +} + +!3 = metadata !{metadata !"pointer", metadata !4} +!4 = metadata !{metadata !"char", metadata !5} +!5 = metadata !{metadata !"root", null} diff --git a/test/Analysis/TypeBasedAliasAnalysis/memcpyopt.ll b/test/Analysis/TypeBasedAliasAnalysis/memcpyopt.ll new file mode 100644 index 0000000..c2407df --- /dev/null +++ b/test/Analysis/TypeBasedAliasAnalysis/memcpyopt.ll @@ -0,0 +1,23 @@ +; RUN: opt -S -tbaa -basicaa -memcpyopt -instcombine < %s | FileCheck %s + +target datalayout = "e-p:64:64:64" + +; The second memcpy is redundant and can be deleted. There's an intervening store, but +; it has a TBAA tag which declares that it is unrelated. + +; CHECK: @foo +; CHECK-NEXT: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %p, i8* %q, i64 16, i32 1, i1 false), !tbaa !0 +; CHECK-NEXT: store i8 2, i8* %s, align 1, !tbaa !2 +; CHECK-NEXT: ret void +define void @foo(i8* nocapture %p, i8* nocapture %q, i8* nocapture %s) nounwind { + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %p, i8* %q, i64 16, i32 1, i1 false), !tbaa !2 + store i8 2, i8* %s, align 1, !tbaa !1 + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %q, i8* %p, i64 16, i32 1, i1 false), !tbaa !2 + ret void +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind + +!0 = metadata !{metadata !"tbaa root", null} +!1 = metadata !{metadata !"A", metadata !0} +!2 = metadata !{metadata !"B", metadata !0} diff --git a/test/Analysis/TypeBasedAliasAnalysis/precedence.ll b/test/Analysis/TypeBasedAliasAnalysis/precedence.ll new file mode 100644 index 0000000..47cb5f2 --- /dev/null +++ b/test/Analysis/TypeBasedAliasAnalysis/precedence.ll @@ -0,0 +1,46 @@ +; RUN: opt -basicaa -tbaa -gvn -instcombine -S < %s | FileCheck %s --check-prefix=TBAA +; RUN: opt -tbaa -basicaa -gvn -instcombine -S < %s | FileCheck %s --check-prefix=BASICAA + +; According to the TBAA metadata the load and store don't alias. However, +; according to the actual code, they do. The order of the alias analysis +; passes should determine which of these takes precedence. + +target datalayout = "e-p:64:64:64" + +; Test for simple MustAlias aliasing. + +; TBAA: @trouble +; TBAA: ret i32 0 +; BASICAA: @trouble +; BASICAA: ret i32 1075000115 +define i32 @trouble(i32* %x) nounwind { +entry: + store i32 0, i32* %x, !tbaa !0 + %0 = bitcast i32* %x to float* + store float 0x4002666660000000, float* %0, !tbaa !3 + %tmp3 = load i32* %x, !tbaa !0 + ret i32 %tmp3 +} + +; Test for PartialAlias aliasing. GVN doesn't yet eliminate the load +; in the BasicAA case. + +; TBAA: @offset +; TBAA: ret i64 0 +; BASICAA: @offset +; BASICAA: ret i64 %tmp3 +define i64 @offset(i64* %x) nounwind { +entry: + store i64 0, i64* %x, !tbaa !4 + %0 = bitcast i64* %x to i8* + %1 = getelementptr i8* %0, i64 1 + store i8 1, i8* %1, !tbaa !5 + %tmp3 = load i64* %x, !tbaa !4 + ret i64 %tmp3 +} + +!0 = metadata !{metadata !"int", metadata !1} +!1 = metadata !{metadata !"simple"} +!3 = metadata !{metadata !"float", metadata !1} +!4 = metadata !{metadata !"long", metadata !1} +!5 = metadata !{metadata !"small", metadata !1} diff --git a/test/Analysis/TypeBasedAliasAnalysis/sink.ll b/test/Analysis/TypeBasedAliasAnalysis/sink.ll new file mode 100644 index 0000000..fd32d6a --- /dev/null +++ b/test/Analysis/TypeBasedAliasAnalysis/sink.ll @@ -0,0 +1,20 @@ +; RUN: opt -tbaa -sink -S < %s | FileCheck %s + +; CHECK: a: +; CHECK: %f = load float* %p, !tbaa !2 +; CHECK: store float %f, float* %q + +define void @foo(float* %p, i1 %c, float* %q, float* %r) { + %f = load float* %p, !tbaa !0 + store float 0.0, float* %r, !tbaa !1 + br i1 %c, label %a, label %b +a: + store float %f, float* %q + br label %b +b: + ret void +} + +!0 = metadata !{metadata !"A", metadata !2} +!1 = metadata !{metadata !"B", metadata !2} +!2 = metadata !{metadata !"test"} diff --git a/test/Archive/GNU.toc b/test/Archive/GNU.toc deleted file mode 100644 index d993413..0000000 --- a/test/Archive/GNU.toc +++ /dev/null @@ -1,4 +0,0 @@ -evenlen -oddlen -very_long_bytecode_file_name.bc -IsNAN.o diff --git a/test/Archive/MacOSX.toc b/test/Archive/MacOSX.toc deleted file mode 100644 index f971df7..0000000 --- a/test/Archive/MacOSX.toc +++ /dev/null @@ -1,5 +0,0 @@ -__.SYMDEF SORTED -evenlen -oddlen -very_long_bytecode_file_name.bc -IsNAN.o diff --git a/test/Archive/SVR4.toc b/test/Archive/SVR4.toc deleted file mode 100644 index d993413..0000000 --- a/test/Archive/SVR4.toc +++ /dev/null @@ -1,4 +0,0 @@ -evenlen -oddlen -very_long_bytecode_file_name.bc -IsNAN.o diff --git a/test/Archive/extract.ll b/test/Archive/extract.ll index 3649714..714c5f1 100644 --- a/test/Archive/extract.ll +++ b/test/Archive/extract.ll @@ -4,13 +4,13 @@ ; from various style archives. ; RUN: llvm-ar x %p/GNU.a very_long_bytecode_file_name.bc -; RUN: diff %p/very_long_bytecode_file_name.bc very_long_bytecode_file_name.bc >/dev/null 2>/dev/null +; RUN: cmp -s %p/very_long_bytecode_file_name.bc very_long_bytecode_file_name.bc ; RUN: llvm-ar x %p/MacOSX.a very_long_bytecode_file_name.bc -; RUN: diff %p/very_long_bytecode_file_name.bc very_long_bytecode_file_name.bc > /dev/null 2>/dev/null +; RUN: cmp -s %p/very_long_bytecode_file_name.bc very_long_bytecode_file_name.bc ; RUN: llvm-ar x %p/SVR4.a very_long_bytecode_file_name.bc -; RUN: diff %p/very_long_bytecode_file_name.bc very_long_bytecode_file_name.bc >/dev/null 2>/dev/null +; RUN: cmp -s %p/very_long_bytecode_file_name.bc very_long_bytecode_file_name.bc ; RUN: llvm-ar x %p/xpg4.a very_long_bytecode_file_name.bc -; RUN: diff %p/very_long_bytecode_file_name.bc very_long_bytecode_file_name.bc >/dev/null 2>/dev/null +; RUN: cmp -s %p/very_long_bytecode_file_name.bc very_long_bytecode_file_name.bc diff --git a/test/Archive/toc_GNU.ll b/test/Archive/toc_GNU.ll index 136f603..9ed7d8e 100644 --- a/test/Archive/toc_GNU.ll +++ b/test/Archive/toc_GNU.ll @@ -1,5 +1,8 @@ ;This isn't really an assembly file, its just here to run the test. ;This test just makes sure that llvm-ar can generate a table of contents for ;GNU style archives -;RUN: llvm-ar t %p/GNU.a > %t1 -;RUN: diff %t1 %p/GNU.toc +;RUN: llvm-ar t %p/GNU.a | FileCheck %s +;CHECK: evenlen +;CHECK-NEXT: oddlen +;CHECK-NEXT: very_long_bytecode_file_name.bc +;CHECK-NEXT: IsNAN.o diff --git a/test/Archive/toc_MacOSX.ll b/test/Archive/toc_MacOSX.ll index fb03223..6dbc9d2 100644 --- a/test/Archive/toc_MacOSX.ll +++ b/test/Archive/toc_MacOSX.ll @@ -1,5 +1,9 @@ ;This isn't really an assembly file, its just here to run the test. ;This test just makes sure that llvm-ar can generate a table of contents for ;MacOSX style archives -;RUN: llvm-ar t %p/MacOSX.a > %t1 -;RUN: diff %t1 %p/MacOSX.toc +;RUN: llvm-ar t %p/MacOSX.a | FileCheck %s +;CHECK: __.SYMDEF SORTED +;CHECK-NEXT: evenlen +;CHECK-NEXT: oddlen +;CHECK-NEXT: very_long_bytecode_file_name.bc +;CHECK-NEXT: IsNAN.o diff --git a/test/Archive/toc_SVR4.ll b/test/Archive/toc_SVR4.ll index 930a26f..d447b92 100644 --- a/test/Archive/toc_SVR4.ll +++ b/test/Archive/toc_SVR4.ll @@ -1,5 +1,8 @@ ;This isn't really an assembly file, its just here to run the test. ;This test just makes sure that llvm-ar can generate a table of contents for ;SVR4 style archives -;RUN: llvm-ar t %p/SVR4.a > %t1 -;RUN: diff %t1 %p/SVR4.toc +;RUN: llvm-ar t %p/SVR4.a | FileCheck %s +;CHECK: evenlen +;CHECK-NEXT: oddlen +;CHECK-NEXT: very_long_bytecode_file_name.bc +;CHECK-NEXT: IsNAN.o diff --git a/test/Archive/toc_xpg4.ll b/test/Archive/toc_xpg4.ll index 441af03..fd875ee 100644 --- a/test/Archive/toc_xpg4.ll +++ b/test/Archive/toc_xpg4.ll @@ -1,5 +1,8 @@ ;This isn't really an assembly file, its just here to run the test. ;This test just makes sure that llvm-ar can generate a table of contents for ;xpg4 style archives -;RUN: llvm-ar t %p/xpg4.a > %t1 -;RUN: diff %t1 %p/xpg4.toc +;RUN: llvm-ar t %p/xpg4.a | FileCheck %s +CHECK: evenlen +CHECK-NEXT: oddlen +CHECK-NEXT: very_long_bytecode_file_name.bc +CHECK-NEXT: IsNAN.o diff --git a/test/Archive/xpg4.toc b/test/Archive/xpg4.toc deleted file mode 100644 index d993413..0000000 --- a/test/Archive/xpg4.toc +++ /dev/null @@ -1,4 +0,0 @@ -evenlen -oddlen -very_long_bytecode_file_name.bc -IsNAN.o diff --git a/test/Assembler/2003-05-21-MalformedShiftCrash.ll b/test/Assembler/2003-05-21-MalformedShiftCrash.ll index c661f7c..a845d89 100644 --- a/test/Assembler/2003-05-21-MalformedShiftCrash.ll +++ b/test/Assembler/2003-05-21-MalformedShiftCrash.ll @@ -1,4 +1,4 @@ ; Found by inspection of the code -; RUN: not llvm-as < %s > /dev/null |& grep {constexpr requires integer or integer vector operands} +; RUN: not llvm-as < %s > /dev/null |& grep {constexpr requires integer operands} global i32 ashr (float 1.0, float 2.0) diff --git a/test/Assembler/AutoUpgradeIntrinsics.ll b/test/Assembler/AutoUpgradeIntrinsics.ll index af4ec92..6752bd8 100644 --- a/test/Assembler/AutoUpgradeIntrinsics.ll +++ b/test/Assembler/AutoUpgradeIntrinsics.ll @@ -7,7 +7,7 @@ ; RUN: llvm-as < %s | llvm-dis | \ ; RUN: not grep {llvm\\.bswap\\.i\[0-9\]*\\.i\[0-9\]*} ; RUN: llvm-as < %s | llvm-dis | \ -; RUN: grep {llvm\\.x86\\.mmx\\.ps} | grep {\\\<2 x i32\\\>} | count 6 +; RUN: grep {llvm\\.x86\\.mmx\\.ps} | grep {x86_mmx} | count 16 declare i32 @llvm.ctpop.i28(i28 %val) declare i32 @llvm.cttz.i29(i29 %val) diff --git a/test/Assembler/AutoUpgradeMMXIntrinsics.ll b/test/Assembler/AutoUpgradeMMXIntrinsics.ll new file mode 100644 index 0000000..54120ff --- /dev/null +++ b/test/Assembler/AutoUpgradeMMXIntrinsics.ll @@ -0,0 +1,223 @@ +; Tests to make sure MMX intrinsics are automatically upgraded. +; RUN: llvm-as < %s | llvm-dis -o %t +; RUN: grep {llvm\\.x86\\.mmx} %t | not grep {\\\<1 x i64\\\>} +; RUN: grep {llvm\\.x86\\.mmx} %t | not grep {\\\<2 x i32\\\>} +; RUN: grep {llvm\\.x86\\.mmx} %t | not grep {\\\<4 x i16\\\>} +; RUN: grep {llvm\\.x86\\.mmx} %t | not grep {\\\<8 x i8\\\>} +; RUN: grep {llvm\\.x86\\.sse\\.pshuf\\.w} %t | not grep i32 + +; Addition +declare <8 x i8> @llvm.x86.mmx.padd.b(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.x86.mmx.padd.w(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.x86.mmx.padd.d(<2 x i32>, <2 x i32>) nounwind readnone +declare <1 x i64> @llvm.x86.mmx.padd.q(<1 x i64>, <1 x i64>) nounwind readnone +declare <8 x i8> @llvm.x86.mmx.padds.b(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.x86.mmx.padds.w(<4 x i16>, <4 x i16>) nounwind readnone +declare <8 x i8> @llvm.x86.mmx.paddus.b(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.x86.mmx.paddus.w(<4 x i16>, <4 x i16>) nounwind readnone +define void @add(<8 x i8> %A, <8 x i8> %B, <4 x i16> %C, <4 x i16> %D, + <2 x i32> %E, <2 x i32> %F, <1 x i64> %G, <1 x i64> %H) { + %r1 = call <8 x i8> @llvm.x86.mmx.padd.b(<8 x i8> %A, <8 x i8> %B) + %r2 = call <4 x i16> @llvm.x86.mmx.padd.w(<4 x i16> %C, <4 x i16> %D) + %r3 = call <2 x i32> @llvm.x86.mmx.padd.d(<2 x i32> %E, <2 x i32> %F) + %r4 = call <1 x i64> @llvm.x86.mmx.padd.q(<1 x i64> %G, <1 x i64> %H) + %r5 = call <8 x i8> @llvm.x86.mmx.padds.b(<8 x i8> %A, <8 x i8> %B) + %r6 = call <4 x i16> @llvm.x86.mmx.padds.w(<4 x i16> %C, <4 x i16> %D) + %r7 = call <8 x i8> @llvm.x86.mmx.paddus.b(<8 x i8> %A, <8 x i8> %B) + %r8 = call <4 x i16> @llvm.x86.mmx.paddus.w(<4 x i16> %C, <4 x i16> %D) + ret void +} + +; Subtraction +declare <8 x i8> @llvm.x86.mmx.psub.b(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.x86.mmx.psub.w(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.x86.mmx.psub.d(<2 x i32>, <2 x i32>) nounwind readnone +declare <1 x i64> @llvm.x86.mmx.psub.q(<1 x i64>, <1 x i64>) nounwind readnone +declare <8 x i8> @llvm.x86.mmx.psubs.b(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.x86.mmx.psubs.w(<4 x i16>, <4 x i16>) nounwind readnone +declare <8 x i8> @llvm.x86.mmx.psubus.b(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.x86.mmx.psubus.w(<4 x i16>, <4 x i16>) nounwind readnone +define void @sub(<8 x i8> %A, <8 x i8> %B, <4 x i16> %C, <4 x i16> %D, + <2 x i32> %E, <2 x i32> %F, <1 x i64> %G, <1 x i64> %H) { + %r1 = call <8 x i8> @llvm.x86.mmx.psub.b(<8 x i8> %A, <8 x i8> %B) + %r2 = call <4 x i16> @llvm.x86.mmx.psub.w(<4 x i16> %C, <4 x i16> %D) + %r3 = call <2 x i32> @llvm.x86.mmx.psub.d(<2 x i32> %E, <2 x i32> %F) + %r4 = call <1 x i64> @llvm.x86.mmx.psub.q(<1 x i64> %G, <1 x i64> %H) + %r5 = call <8 x i8> @llvm.x86.mmx.psubs.b(<8 x i8> %A, <8 x i8> %B) + %r6 = call <4 x i16> @llvm.x86.mmx.psubs.w(<4 x i16> %C, <4 x i16> %D) + %r7 = call <8 x i8> @llvm.x86.mmx.psubus.b(<8 x i8> %A, <8 x i8> %B) + %r8 = call <4 x i16> @llvm.x86.mmx.psubus.w(<4 x i16> %C, <4 x i16> %D) + ret void +} + +; Multiplication +declare <4 x i16> @llvm.x86.mmx.pmulh.w(<4 x i16>, <4 x i16>) nounwind readnone +declare <4 x i16> @llvm.x86.mmx.pmull.w(<4 x i16>, <4 x i16>) nounwind readnone +declare <4 x i16> @llvm.x86.mmx.pmulhu.w(<4 x i16>, <4 x i16>) nounwind readnone +declare <4 x i16> @llvm.x86.mmx.pmulu.dq(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.x86.mmx.pmadd.wd(<4 x i16>, <4 x i16>) nounwind readnone +define void @mul(<4 x i16> %A, <4 x i16> %B) { + %r1 = call <4 x i16> @llvm.x86.mmx.pmulh.w(<4 x i16> %A, <4 x i16> %B) + %r2 = call <4 x i16> @llvm.x86.mmx.pmull.w(<4 x i16> %A, <4 x i16> %B) + %r3 = call <4 x i16> @llvm.x86.mmx.pmulhu.w(<4 x i16> %A, <4 x i16> %B) + %r4 = call <4 x i16> @llvm.x86.mmx.pmulu.dq(<4 x i16> %A, <4 x i16> %B) + %r5 = call <2 x i32> @llvm.x86.mmx.pmadd.wd(<4 x i16> %A, <4 x i16> %B) + ret void +} + +; Bitwise operations +declare <1 x i64> @llvm.x86.mmx.pand(<1 x i64>, <1 x i64>) nounwind readnone +declare <1 x i64> @llvm.x86.mmx.pandn(<1 x i64>, <1 x i64>) nounwind readnone +declare <1 x i64> @llvm.x86.mmx.por(<1 x i64>, <1 x i64>) nounwind readnone +declare <1 x i64> @llvm.x86.mmx.pxor(<1 x i64>, <1 x i64>) nounwind readnone +define void @bit(<1 x i64> %A, <1 x i64> %B) { + %r1 = call <1 x i64> @llvm.x86.mmx.pand(<1 x i64> %A, <1 x i64> %B) + %r2 = call <1 x i64> @llvm.x86.mmx.pandn(<1 x i64> %A, <1 x i64> %B) + %r3 = call <1 x i64> @llvm.x86.mmx.por(<1 x i64> %A, <1 x i64> %B) + %r4 = call <1 x i64> @llvm.x86.mmx.pxor(<1 x i64> %A, <1 x i64> %B) + ret void +} + +; Averages +declare <8 x i8> @llvm.x86.mmx.pavg.b(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.x86.mmx.pavg.w(<4 x i16>, <4 x i16>) nounwind readnone +define void @avg(<8 x i8> %A, <8 x i8> %B, <4 x i16> %C, <4 x i16> %D) { + %r1 = call <8 x i8> @llvm.x86.mmx.pavg.b(<8 x i8> %A, <8 x i8> %B) + %r2 = call <4 x i16> @llvm.x86.mmx.pavg.w(<4 x i16> %C, <4 x i16> %D) + ret void +} + +; Maximum +declare <8 x i8> @llvm.x86.mmx.pmaxu.b(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.x86.mmx.pmaxs.w(<4 x i16>, <4 x i16>) nounwind readnone +define void @max(<8 x i8> %A, <8 x i8> %B, <4 x i16> %C, <4 x i16> %D) { + %r1 = call <8 x i8> @llvm.x86.mmx.pmaxu.b(<8 x i8> %A, <8 x i8> %B) + %r2 = call <4 x i16> @llvm.x86.mmx.pmaxs.w(<4 x i16> %C, <4 x i16> %D) + ret void +} + +; Minimum +declare <8 x i8> @llvm.x86.mmx.pminu.b(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.x86.mmx.pmins.w(<4 x i16>, <4 x i16>) nounwind readnone +define void @min(<8 x i8> %A, <8 x i8> %B, <4 x i16> %C, <4 x i16> %D) { + %r1 = call <8 x i8> @llvm.x86.mmx.pminu.b(<8 x i8> %A, <8 x i8> %B) + %r2 = call <4 x i16> @llvm.x86.mmx.pmins.w(<4 x i16> %C, <4 x i16> %D) + ret void +} + +; Packed sum of absolute differences +declare <4 x i16> @llvm.x86.mmx.psad.bw(<8 x i8>, <8 x i8>) nounwind readnone +define void @psad(<8 x i8> %A, <8 x i8> %B) { + %r1 = call <4 x i16> @llvm.x86.mmx.psad.bw(<8 x i8> %A, <8 x i8> %B) + ret void +} + +; Shift left +declare <4 x i16> @llvm.x86.mmx.psll.w(<4 x i16>, <1 x i64>) nounwind readnone +declare <2 x i32> @llvm.x86.mmx.psll.d(<2 x i32>, <1 x i64>) nounwind readnone +declare <1 x i64> @llvm.x86.mmx.psll.q(<1 x i64>, <1 x i64>) nounwind readnone +declare <4 x i16> @llvm.x86.mmx.pslli.w(<4 x i16>, i32) nounwind readnone +declare <2 x i32> @llvm.x86.mmx.pslli.d(<2 x i32>, i32) nounwind readnone +declare <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64>, i32) nounwind readnone +define void @shl(<4 x i16> %A, <2 x i32> %B, <1 x i64> %C, i32 %D) { + %r1 = call <4 x i16> @llvm.x86.mmx.psll.w(<4 x i16> %A, <1 x i64> %C) + %r2 = call <2 x i32> @llvm.x86.mmx.psll.d(<2 x i32> %B, <1 x i64> %C) + %r3 = call <1 x i64> @llvm.x86.mmx.psll.q(<1 x i64> %C, <1 x i64> %C) + %r4 = call <4 x i16> @llvm.x86.mmx.pslli.w(<4 x i16> %A, i32 %D) + %r5 = call <2 x i32> @llvm.x86.mmx.pslli.d(<2 x i32> %B, i32 %D) + %r6 = call <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64> %C, i32 %D) + ret void +} + +; Shift right logical +declare <4 x i16> @llvm.x86.mmx.psrl.w(<4 x i16>, <1 x i64>) nounwind readnone +declare <2 x i32> @llvm.x86.mmx.psrl.d(<2 x i32>, <1 x i64>) nounwind readnone +declare <1 x i64> @llvm.x86.mmx.psrl.q(<1 x i64>, <1 x i64>) nounwind readnone +declare <4 x i16> @llvm.x86.mmx.psrli.w(<4 x i16>, i32) nounwind readnone +declare <2 x i32> @llvm.x86.mmx.psrli.d(<2 x i32>, i32) nounwind readnone +declare <1 x i64> @llvm.x86.mmx.psrli.q(<1 x i64>, i32) nounwind readnone +define void @shr(<4 x i16> %A, <2 x i32> %B, <1 x i64> %C, i32 %D) { + %r1 = call <4 x i16> @llvm.x86.mmx.psrl.w(<4 x i16> %A, <1 x i64> %C) + %r2 = call <2 x i32> @llvm.x86.mmx.psrl.d(<2 x i32> %B, <1 x i64> %C) + %r3 = call <1 x i64> @llvm.x86.mmx.psrl.q(<1 x i64> %C, <1 x i64> %C) + %r4 = call <4 x i16> @llvm.x86.mmx.psrli.w(<4 x i16> %A, i32 %D) + %r5 = call <2 x i32> @llvm.x86.mmx.psrli.d(<2 x i32> %B, i32 %D) + %r6 = call <1 x i64> @llvm.x86.mmx.psrli.q(<1 x i64> %C, i32 %D) + ret void +} + +; Shift right arithmetic +declare <4 x i16> @llvm.x86.mmx.psra.w(<4 x i16>, <1 x i64>) nounwind readnone +declare <2 x i32> @llvm.x86.mmx.psra.d(<2 x i32>, <1 x i64>) nounwind readnone +declare <4 x i16> @llvm.x86.mmx.psrai.w(<4 x i16>, i32) nounwind readnone +declare <2 x i32> @llvm.x86.mmx.psrai.d(<2 x i32>, i32) nounwind readnone +define void @sra(<4 x i16> %A, <2 x i32> %B, <1 x i64> %C, i32 %D) { + %r1 = call <4 x i16> @llvm.x86.mmx.psra.w(<4 x i16> %A, <1 x i64> %C) + %r2 = call <2 x i32> @llvm.x86.mmx.psra.d(<2 x i32> %B, <1 x i64> %C) + %r3 = call <4 x i16> @llvm.x86.mmx.psrai.w(<4 x i16> %A, i32 %D) + %r4 = call <2 x i32> @llvm.x86.mmx.psrai.d(<2 x i32> %B, i32 %D) + ret void +} + +; Pack/Unpack ops +declare <8 x i8> @llvm.x86.mmx.packsswb(<4 x i16>, <4 x i16>) nounwind readnone +declare <4 x i16> @llvm.x86.mmx.packssdw(<2 x i32>, <2 x i32>) nounwind readnone +declare <8 x i8> @llvm.x86.mmx.packuswb(<4 x i16>, <4 x i16>) nounwind readnone +declare <8 x i8> @llvm.x86.mmx.punpckhbw(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.x86.mmx.punpckhwd(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.x86.mmx.punpckhdq(<2 x i32>, <2 x i32>) nounwind readnone +declare <8 x i8> @llvm.x86.mmx.punpcklbw(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.x86.mmx.punpcklwd(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.x86.mmx.punpckldq(<2 x i32>, <2 x i32>) nounwind readnone +define void @pack_unpack(<8 x i8> %A, <8 x i8> %B, <4 x i16> %C, <4 x i16> %D, + <2 x i32> %E, <2 x i32> %F) { + %r1 = call <8 x i8> @llvm.x86.mmx.packsswb(<4 x i16> %C, <4 x i16> %D) + %r2 = call <4 x i16> @llvm.x86.mmx.packssdw(<2 x i32> %E, <2 x i32> %F) + %r3 = call <8 x i8> @llvm.x86.mmx.packuswb(<4 x i16> %C, <4 x i16> %D) + %r4 = call <8 x i8> @llvm.x86.mmx.punpckhbw(<8 x i8> %A, <8 x i8> %B) + %r5 = call <4 x i16> @llvm.x86.mmx.punpckhwd(<4 x i16> %C, <4 x i16> %D) + %r6 = call <2 x i32> @llvm.x86.mmx.punpckhdq(<2 x i32> %E, <2 x i32> %F) + %r7 = call <8 x i8> @llvm.x86.mmx.punpcklbw(<8 x i8> %A, <8 x i8> %B) + %r8 = call <4 x i16> @llvm.x86.mmx.punpcklwd(<4 x i16> %C, <4 x i16> %D) + %r9 = call <2 x i32> @llvm.x86.mmx.punpckldq(<2 x i32> %E, <2 x i32> %F) + ret void +} + +; Integer comparison ops +declare <8 x i8> @llvm.x86.mmx.pcmpeq.b(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.x86.mmx.pcmpeq.w(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.x86.mmx.pcmpeq.d(<2 x i32>, <2 x i32>) nounwind readnone +declare <8 x i8> @llvm.x86.mmx.pcmpgt.b(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.x86.mmx.pcmpgt.w(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.x86.mmx.pcmpgt.d(<2 x i32>, <2 x i32>) nounwind readnone +define void @cmp(<8 x i8> %A, <8 x i8> %B, <4 x i16> %C, <4 x i16> %D, + <2 x i32> %E, <2 x i32> %F) { + %r1 = call <8 x i8> @llvm.x86.mmx.pcmpeq.b(<8 x i8> %A, <8 x i8> %B) + %r2 = call <4 x i16> @llvm.x86.mmx.pcmpeq.w(<4 x i16> %C, <4 x i16> %D) + %r3 = call <2 x i32> @llvm.x86.mmx.pcmpeq.d(<2 x i32> %E, <2 x i32> %F) + %r4 = call <8 x i8> @llvm.x86.mmx.pcmpgt.b(<8 x i8> %A, <8 x i8> %B) + %r5 = call <4 x i16> @llvm.x86.mmx.pcmpgt.w(<4 x i16> %C, <4 x i16> %D) + %r6 = call <2 x i32> @llvm.x86.mmx.pcmpgt.d(<2 x i32> %E, <2 x i32> %F) + ret void +} + +; Miscellaneous +declare void @llvm.x86.mmx.maskmovq(<8 x i8>, <8 x i8>, i32*) nounwind readnone +declare i32 @llvm.x86.mmx.pmovmskb(<8 x i8>) nounwind readnone +declare void @llvm.x86.mmx.movnt.dq(i32*, <1 x i64>) nounwind readnone +declare <1 x i64> @llvm.x86.mmx.palignr.b(<1 x i64>, <1 x i64>, i8) nounwind readnone +declare i32 @llvm.x86.mmx.pextr.w(<1 x i64>, i32) nounwind readnone +declare <1 x i64> @llvm.x86.mmx.pinsr.w(<1 x i64>, i32, i32) nounwind readnone +declare <4 x i16> @llvm.x86.ssse3.pshuf.w(<4 x i16>, i32) nounwind readnone +define void @misc(<8 x i8> %A, <8 x i8> %B, <4 x i16> %C, <4 x i16> %D, + <2 x i32> %E, <2 x i32> %F, <1 x i64> %G, <1 x i64> %H, + i32* %I, i8 %J, i16 %K, i32 %L) { + call void @llvm.x86.mmx.maskmovq(<8 x i8> %A, <8 x i8> %B, i32* %I) + %r1 = call i32 @llvm.x86.mmx.pmovmskb(<8 x i8> %A) + call void @llvm.x86.mmx.movnt.dq(i32* %I, <1 x i64> %G) + %r2 = call <1 x i64> @llvm.x86.mmx.palignr.b(<1 x i64> %G, <1 x i64> %H, i8 %J) + %r3 = call i32 @llvm.x86.mmx.pextr.w(<1 x i64> %G, i32 37) + %r4 = call <1 x i64> @llvm.x86.mmx.pinsr.w(<1 x i64> %G, i32 37, i32 927) + %r5 = call <4 x i16> @llvm.x86.ssse3.pshuf.w(<4 x i16> %C, i32 37) + ret void +} diff --git a/test/Assembler/extractvalue-invalid-idx.ll b/test/Assembler/extractvalue-invalid-idx.ll new file mode 100644 index 0000000..f9644ea --- /dev/null +++ b/test/Assembler/extractvalue-invalid-idx.ll @@ -0,0 +1,8 @@ +; RUN: not llvm-as < %s |& grep {invalid indices for extractvalue} +; PR4170 + +define void @test() { +entry: + extractvalue [0 x i32] undef, 0 + ret void +} diff --git a/test/Assembler/flags.ll b/test/Assembler/flags.ll index 3241909..310b807 100644 --- a/test/Assembler/flags.ll +++ b/test/Assembler/flags.ll @@ -92,6 +92,12 @@ define i64 @mul_both_reversed(i64 %x, i64 %y) { ret i64 %z } +define i64 @shl_both(i64 %x, i64 %y) { +; CHECK: %z = shl nuw nsw i64 %x, %y + %z = shl nuw nsw i64 %x, %y + ret i64 %z +} + define i64 @sdiv_exact(i64 %x, i64 %y) { ; CHECK: %z = sdiv exact i64 %x, %y %z = sdiv exact i64 %x, %y @@ -104,6 +110,42 @@ define i64 @sdiv_plain(i64 %x, i64 %y) { ret i64 %z } +define i64 @udiv_exact(i64 %x, i64 %y) { +; CHECK: %z = udiv exact i64 %x, %y + %z = udiv exact i64 %x, %y + ret i64 %z +} + +define i64 @udiv_plain(i64 %x, i64 %y) { +; CHECK: %z = udiv i64 %x, %y + %z = udiv i64 %x, %y + ret i64 %z +} + +define i64 @ashr_plain(i64 %x, i64 %y) { +; CHECK: %z = ashr i64 %x, %y + %z = ashr i64 %x, %y + ret i64 %z +} + +define i64 @ashr_exact(i64 %x, i64 %y) { +; CHECK: %z = ashr exact i64 %x, %y + %z = ashr exact i64 %x, %y + ret i64 %z +} + +define i64 @lshr_plain(i64 %x, i64 %y) { +; CHECK: %z = lshr i64 %x, %y + %z = lshr i64 %x, %y + ret i64 %z +} + +define i64 @lshr_exact(i64 %x, i64 %y) { +; CHECK: %z = lshr exact i64 %x, %y + %z = lshr exact i64 %x, %y + ret i64 %z +} + define i64* @gep_nw(i64* %p, i64 %x) { ; CHECK: %z = getelementptr inbounds i64* %p, i64 %x %z = getelementptr inbounds i64* %p, i64 %x @@ -136,6 +178,21 @@ define i64 @sdiv_exact_ce() { ret i64 sdiv exact (i64 ptrtoint (i64* @addr to i64), i64 91) } +define i64 @udiv_exact_ce() { +; CHECK: ret i64 udiv exact (i64 ptrtoint (i64* @addr to i64), i64 91) + ret i64 udiv exact (i64 ptrtoint (i64* @addr to i64), i64 91) +} + +define i64 @ashr_exact_ce() { +; CHECK: ret i64 ashr exact (i64 ptrtoint (i64* @addr to i64), i64 9) + ret i64 ashr exact (i64 ptrtoint (i64* @addr to i64), i64 9) +} + +define i64 @lshr_exact_ce() { +; CHECK: ret i64 lshr exact (i64 ptrtoint (i64* @addr to i64), i64 9) + ret i64 lshr exact (i64 ptrtoint (i64* @addr to i64), i64 9) +} + define i64* @gep_nw_ce() { ; CHECK: ret i64* getelementptr inbounds (i64* @addr, i64 171) ret i64* getelementptr inbounds (i64* @addr, i64 171) @@ -196,6 +253,12 @@ define i64 @mul_signed_ce() { ret i64 mul nsw (i64 ptrtoint (i64* @addr to i64), i64 91) } +define i64 @shl_signed_ce() { +; CHECK: ret i64 shl nsw (i64 ptrtoint (i64* @addr to i64), i64 17) + ret i64 shl nsw (i64 ptrtoint (i64* @addr to i64), i64 17) +} + + define i64 @add_unsigned_ce() { ; CHECK: ret i64 add nuw (i64 ptrtoint (i64* @addr to i64), i64 91) ret i64 add nuw (i64 ptrtoint (i64* @addr to i64), i64 91) @@ -210,3 +273,4 @@ define i64 @mul_unsigned_ce() { ; CHECK: ret i64 mul nuw (i64 ptrtoint (i64* @addr to i64), i64 91) ret i64 mul nuw (i64 ptrtoint (i64* @addr to i64), i64 91) } + diff --git a/test/Assembler/insertvalue-invalid-idx.ll b/test/Assembler/insertvalue-invalid-idx.ll new file mode 100644 index 0000000..86e7258 --- /dev/null +++ b/test/Assembler/insertvalue-invalid-idx.ll @@ -0,0 +1,7 @@ +; RUN: not llvm-as < %s |& grep {invalid indices for insertvalue} + +define void @test() { +entry: + insertvalue [0 x i32] undef, i32 0, 0 + ret void +} diff --git a/test/Assembler/unnamed-addr.ll b/test/Assembler/unnamed-addr.ll new file mode 100644 index 0000000..3c94ca2 --- /dev/null +++ b/test/Assembler/unnamed-addr.ll @@ -0,0 +1,18 @@ +; RUN: llvm-as < %s | llvm-dis | FileCheck %s + +%struct.foobar = type { i32 } + +@bar.d = internal unnamed_addr constant %struct.foobar zeroinitializer, align 4 +@foo.d = internal constant %struct.foobar zeroinitializer, align 4 + +define i32 @main() unnamed_addr nounwind ssp { +entry: + %call2 = tail call i32 @zed(%struct.foobar* @foo.d, %struct.foobar* @bar.d) nounwind + ret i32 0 +} + +declare i32 @zed(%struct.foobar*, %struct.foobar*) + +; CHECK: @bar.d = internal unnamed_addr constant %struct.foobar zeroinitializer, align 4 +; CHECK: @foo.d = internal constant %struct.foobar zeroinitializer, align 4 +; CHECK: define i32 @main() unnamed_addr nounwind ssp { diff --git a/test/Assembler/x86mmx.ll b/test/Assembler/x86mmx.ll new file mode 100644 index 0000000..732d3be --- /dev/null +++ b/test/Assembler/x86mmx.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; Basic smoke test for x86_mmx type. + +; CHECK: define x86_mmx @sh16 +define x86_mmx @sh16(x86_mmx %A) { +; CHECK: ret x86_mmx %A + ret x86_mmx %A +} diff --git a/test/Bindings/Ocaml/analysis.ml b/test/Bindings/Ocaml/analysis.ml index bf21782..7df8e21 100644 --- a/test/Bindings/Ocaml/analysis.ml +++ b/test/Bindings/Ocaml/analysis.ml @@ -1,5 +1,6 @@ (* RUN: %ocamlopt -warn-error A llvm.cmxa llvm_analysis.cmxa %s -o %t * RUN: %t + * XFAIL: vg_leak *) open Llvm diff --git a/test/Bindings/Ocaml/bitreader.ml b/test/Bindings/Ocaml/bitreader.ml index 30b07d2..a3bd91a 100644 --- a/test/Bindings/Ocaml/bitreader.ml +++ b/test/Bindings/Ocaml/bitreader.ml @@ -1,6 +1,7 @@ (* RUN: %ocamlopt -warn-error A llvm.cmxa llvm_bitreader.cmxa llvm_bitwriter.cmxa %s -o %t * RUN: %t %t.bc * RUN: llvm-dis < %t.bc | grep caml_int_ty + * XFAIL: vg_leak *) (* Note that this takes a moment to link, so it's best to keep the number of diff --git a/test/Bindings/Ocaml/bitwriter.ml b/test/Bindings/Ocaml/bitwriter.ml index 8eb923e..3f55fb9 100644 --- a/test/Bindings/Ocaml/bitwriter.ml +++ b/test/Bindings/Ocaml/bitwriter.ml @@ -1,6 +1,7 @@ (* RUN: %ocamlopt -warn-error A unix.cmxa llvm.cmxa llvm_bitwriter.cmxa %s -o %t * RUN: %t %t.bc * RUN: llvm-dis < %t.bc | grep caml_int_ty + * XFAIL: vg_leak *) (* Note that this takes a moment to link, so it's best to keep the number of diff --git a/test/Bindings/Ocaml/executionengine.ml b/test/Bindings/Ocaml/executionengine.ml index 63040e4..f7a49bb 100644 --- a/test/Bindings/Ocaml/executionengine.ml +++ b/test/Bindings/Ocaml/executionengine.ml @@ -1,5 +1,6 @@ (* RUN: %ocamlopt -warn-error A llvm.cmxa llvm_target.cmxa llvm_executionengine.cmxa %s -o %t * RUN: %t + * XFAIL: vg_leak *) open Llvm diff --git a/test/Bindings/Ocaml/ext_exc.ml b/test/Bindings/Ocaml/ext_exc.ml new file mode 100644 index 0000000..b4d2e6d --- /dev/null +++ b/test/Bindings/Ocaml/ext_exc.ml @@ -0,0 +1,17 @@ +(* RUN: %ocamlopt -warn-error A llvm.cmxa llvm_bitreader.cmxa llvm_executionengine.cmxa %s -o %t + * RUN: %t ();; +let _ = + try + ignore (Llvm.MemoryBuffer.of_file "/path/to/nonexistent/file") + with + Llvm.IoError _ -> ();; diff --git a/test/Bindings/Ocaml/scalar_opts.ml b/test/Bindings/Ocaml/scalar_opts.ml index 8a6af01..1ea9785 100644 --- a/test/Bindings/Ocaml/scalar_opts.ml +++ b/test/Bindings/Ocaml/scalar_opts.ml @@ -1,5 +1,6 @@ (* RUN: %ocamlopt -warn-error A llvm.cmxa llvm_scalar_opts.cmxa llvm_target.cmxa %s -o %t * RUN: %t %t.bc + * XFAIL: vg_leak *) (* Note: It takes several seconds for ocamlopt to link an executable with @@ -42,7 +43,7 @@ let test_transforms () = ignore (PassManager.create_function m ++ TargetData.add td ++ add_constant_propagation - ++ add_sccp + ++ add_sccp ++ add_dead_store_elimination ++ add_aggressive_dce ++ add_scalar_repl_aggregation @@ -52,7 +53,6 @@ let test_transforms () = ++ add_loop_unswitch ++ add_loop_unroll ++ add_loop_rotation - ++ add_loop_index_split ++ add_memory_to_register_promotion ++ add_memory_to_register_demotion ++ add_reassociation diff --git a/test/Bindings/Ocaml/target.ml b/test/Bindings/Ocaml/target.ml index bfaf37c..5e3ab4b 100644 --- a/test/Bindings/Ocaml/target.ml +++ b/test/Bindings/Ocaml/target.ml @@ -1,5 +1,6 @@ (* RUN: %ocamlopt -warn-error A llvm.cmxa llvm_target.cmxa %s -o %t * RUN: %t %t.bc + * XFAIL: vg_leak *) (* Note: It takes several seconds for ocamlopt to link an executable with diff --git a/test/Bindings/Ocaml/vmcore.ml b/test/Bindings/Ocaml/vmcore.ml index e55ab96..ceb650e 100644 --- a/test/Bindings/Ocaml/vmcore.ml +++ b/test/Bindings/Ocaml/vmcore.ml @@ -1,6 +1,7 @@ (* RUN: %ocamlopt -warn-error A llvm.cmxa llvm_analysis.cmxa llvm_bitwriter.cmxa %s -o %t * RUN: %t %t.bc * RUN: llvm-dis < %t.bc > %t.ll + * XFAIL: vg_leak *) (* Note: It takes several seconds for ocamlopt to link an executable with diff --git a/test/Bitcode/null-type.ll b/test/Bitcode/null-type.ll new file mode 100644 index 0000000..5d3dfab --- /dev/null +++ b/test/Bitcode/null-type.ll @@ -0,0 +1,2 @@ +; RUN: not llvm-dis < %s.bc > /dev/null |& grep "Invalid MODULE_CODE_FUNCTION record" +; PR8494 diff --git a/test/Bitcode/null-type.ll.bc b/test/Bitcode/null-type.ll.bc new file mode 100644 index 0000000..f0a97d9 Binary files /dev/null and b/test/Bitcode/null-type.ll.bc differ diff --git a/test/Bitcode/ssse3_palignr.ll.bc b/test/Bitcode/ssse3_palignr.ll.bc index 642f4de..3fc9cdf 100644 Binary files a/test/Bitcode/ssse3_palignr.ll.bc and b/test/Bitcode/ssse3_palignr.ll.bc differ diff --git a/test/BugPoint/crash-narrowfunctiontest.ll b/test/BugPoint/crash-narrowfunctiontest.ll index 18a31eb..d080d9d 100644 --- a/test/BugPoint/crash-narrowfunctiontest.ll +++ b/test/BugPoint/crash-narrowfunctiontest.ll @@ -1,8 +1,7 @@ ; Test that bugpoint can narrow down the testcase to the important function -; FIXME: This likely fails on windows ; -; RUN: bugpoint -load %llvmlibsdir/BugpointPasses%shlibext %s -output-prefix %t -bugpoint-crashcalls -silence-passes > /dev/null -; XFAIL: mingw +; RUN: bugpoint -load %llvmshlibdir/BugpointPasses%shlibext %s -output-prefix %t -bugpoint-crashcalls -silence-passes > /dev/null +; REQUIRES: loadable_module define i32 @foo() { ret i32 1 } diff --git a/test/BugPoint/metadata.ll b/test/BugPoint/metadata.ll index f2541ee..0eda566 100644 --- a/test/BugPoint/metadata.ll +++ b/test/BugPoint/metadata.ll @@ -1,6 +1,6 @@ -; RUN: bugpoint -load %llvmlibsdir/BugpointPasses%shlibext %s -output-prefix %t -bugpoint-crashcalls -silence-passes > /dev/null +; RUN: bugpoint -load %llvmshlibdir/BugpointPasses%shlibext %s -output-prefix %t -bugpoint-crashcalls -silence-passes > /dev/null ; RUN: llvm-dis %t-reduced-simplified.bc -o - | FileCheck %s -; XFAIL: mingw +; REQUIRES: loadable_module ; Bugpoint should keep the call's metadata attached to the call. diff --git a/test/BugPoint/remove_arguments_test.ll b/test/BugPoint/remove_arguments_test.ll index 791ec69..29a03b8 100644 --- a/test/BugPoint/remove_arguments_test.ll +++ b/test/BugPoint/remove_arguments_test.ll @@ -1,7 +1,6 @@ -; FIXME: This likely fails on windows -; RUN: bugpoint -load %llvmlibsdir/BugpointPasses%shlibext %s -output-prefix %t -bugpoint-crashcalls -silence-passes +; RUN: bugpoint -load %llvmshlibdir/BugpointPasses%shlibext %s -output-prefix %t -bugpoint-crashcalls -silence-passes ; RUN: llvm-dis %t-reduced-simplified.bc -o - | FileCheck %s -; XFAIL: mingw +; REQUIRES: loadable_module ; Test to make sure that arguments are removed from the function if they are ; unnecessary. And clean up any types that that frees up too. diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt index ad9a243..302e141 100644 --- a/test/CMakeLists.txt +++ b/test/CMakeLists.txt @@ -7,6 +7,8 @@ set(TARGETS_TO_BUILD ${TARGETS_BUILT}) set(LLVM_LIBS_DIR "${LLVM_BINARY_DIR}/lib/${CMAKE_CFG_INTDIR}") set(SHLIBEXT "${LTDL_SHLIB_EXT}") +set(SHLIBDIR "${LLVM_BINARY_DIR}/lib/${CMAKE_CFG_INTDIR}") + if(BUILD_SHARED_LIBS) set(LLVM_SHARED_LIBS_ENABLED "1") else() @@ -18,12 +20,15 @@ if(${CMAKE_SYSTEM_NAME} MATCHES "Darwin") else() # Default for all other unix like systems. # CMake hardcodes the library locaction using rpath. # Therefore LD_LIBRARY_PATH is not required to run binaries in the - # build dir. We pass it anyways. + # build dir. We pass it anyways. set(SHLIBPATH_VAR "LD_LIBRARY_PATH") endif() include(FindPythonInterp) if(PYTHONINTERP_FOUND) + set(LIT_ARGS "${LLVM_LIT_ARGS}") + separate_arguments(LIT_ARGS) + get_directory_property(DEFINITIONS COMPILE_DEFINITIONS) foreach(DEF ${DEFINITIONS}) set(DEFS "${DEFS} -D${DEF}") @@ -47,30 +52,44 @@ if(PYTHONINTERP_FOUND) MAKE_DIRECTORY(${CMAKE_CURRENT_BINARY_DIR}/Unit) + # Configuration-time: See Unit/lit.site.cfg.in + set(LLVM_BUILD_MODE "%(build_mode)s") + + set(LLVM_SOURCE_DIR ${LLVM_MAIN_SRC_DIR}) + set(LLVM_BINARY_DIR ${LLVM_BINARY_DIR}) + set(LLVM_TOOLS_DIR "${LLVM_TOOLS_BINARY_DIR}/%(build_config)s") + set(LLVMGCCDIR "") + set(PYTHON_EXECUTABLE ${PYTHON_EXECUTABLE}) + set(ENABLE_SHARED ${LLVM_SHARED_LIBS_ENABLED}) + set(SHLIBPATH_VAR ${SHLIBPATH_VAR}) + + configure_file( + ${CMAKE_CURRENT_SOURCE_DIR}/lit.site.cfg.in + ${CMAKE_CURRENT_BINARY_DIR}/lit.site.cfg + @ONLY) + configure_file( + ${CMAKE_CURRENT_SOURCE_DIR}/Unit/lit.site.cfg.in + ${CMAKE_CURRENT_BINARY_DIR}/Unit/lit.site.cfg + @ONLY) + add_custom_target(check - COMMAND sed -e "s#\@LLVM_SOURCE_DIR\@#${LLVM_MAIN_SRC_DIR}#" - -e "s#\@LLVM_BINARY_DIR\@#${LLVM_BINARY_DIR}#" - -e "s#\@LLVM_TOOLS_DIR\@#${LLVM_TOOLS_BINARY_DIR}/${CMAKE_CFG_INTDIR}#" - -e "s#\@LLVMGCCDIR\@##" - -e "s#\@PYTHON_EXECUTABLE\@#${PYTHON_EXECUTABLE}#" - ${CMAKE_CURRENT_SOURCE_DIR}/lit.site.cfg.in > - ${CMAKE_CURRENT_BINARY_DIR}/lit.site.cfg - COMMAND sed -e "s#\@LLVM_SOURCE_DIR\@#${LLVM_MAIN_SRC_DIR}#" - -e "s#\@LLVM_BINARY_DIR\@#${LLVM_BINARY_DIR}#" - -e "s#\@LLVM_TOOLS_DIR\@#${LLVM_TOOLS_BINARY_DIR}/${CMAKE_CFG_INTDIR}#" - -e "s#\@LLVMGCCDIR\@##" - -e "s#\@LLVM_BUILD_MODE\@#${CMAKE_CFG_INTDIR}#" - -e "s#\@ENABLE_SHARED\@#${LLVM_SHARED_LIBS_ENABLED}#" - -e "s#\@SHLIBPATH_VAR\@#${SHLIBPATH_VAR}#" - ${CMAKE_CURRENT_SOURCE_DIR}/Unit/lit.site.cfg.in > - ${CMAKE_CURRENT_BINARY_DIR}/Unit/lit.site.cfg COMMAND ${PYTHON_EXECUTABLE} ${LLVM_SOURCE_DIR}/utils/lit/lit.py --param llvm_site_config=${CMAKE_CURRENT_BINARY_DIR}/lit.site.cfg --param llvm_unit_site_config=${CMAKE_CURRENT_BINARY_DIR}/Unit/lit.site.cfg - -sv + --param build_config=${CMAKE_CFG_INTDIR} + --param build_mode=${RUNTIME_BUILD_MODE} + ${LIT_ARGS} ${CMAKE_CURRENT_BINARY_DIR} - DEPENDS COMMENT "Running LLVM regression tests") + add_custom_target(check.deps) + add_dependencies(check check.deps) + add_dependencies(check.deps + UnitTests + BugpointPasses LLVMHello + llc lli llvm-ar llvm-as llvm-dis llvm-extract + llvm-ld llvm-link llvm-mc llvm-nm macho-dump opt + FileCheck count not) + endif() diff --git a/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll b/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll index ee63656..3694aaa 100644 --- a/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll +++ b/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | FileCheck %s +; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2 | FileCheck %s @quant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1] @dequant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1] @@ -8,8 +8,9 @@ define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) { entry: ; Make sure to use base-updating stores for saving callee-saved registers. +; CHECK: push ; CHECK-NOT: sub sp -; CHECK: vstmdb sp! +; CHECK: push %predicted_block = alloca [4 x [4 x i32]], align 4 ; <[4 x [4 x i32]]*> [#uses=1] br label %cond_next489 diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll deleted file mode 100644 index 5cfc68d..0000000 --- a/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll +++ /dev/null @@ -1,26 +0,0 @@ -; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler - -; ModuleID = '' -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" -target triple = "armv7-apple-darwin9" - -@.str = external constant [36 x i8], align 1 ; <[36 x i8]*> [#uses=0] -@.str1 = external constant [31 x i8], align 1 ; <[31 x i8]*> [#uses=1] -@.str2 = external constant [4 x i8], align 1 ; <[4 x i8]*> [#uses=1] - -declare i32 @getUnknown(i32, ...) nounwind - -declare void @llvm.va_start(i8*) nounwind - -declare void @llvm.va_end(i8*) nounwind - -declare i32 @printf(i8* nocapture, ...) nounwind - -define i32 @main() nounwind { -entry: - %0 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 1, i32 1, i32 1, i32 1, i32 1, i32 1) nounwind ; [#uses=0] - %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 -128, i32 116, i32 116, i32 -3852, i32 -31232, i32 -1708916736) nounwind ; [#uses=0] - %2 = tail call i32 (i32, ...)* @getUnknown(i32 undef, i32 116, i32 116, i32 -3852, i32 -31232, i32 30556, i32 -1708916736) nounwind ; [#uses=1] - %3 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @.str2, i32 0, i32 0), i32 %2) nounwind ; [#uses=0] - ret i32 0 -} diff --git a/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll b/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll deleted file mode 100644 index 06a152d..0000000 --- a/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll +++ /dev/null @@ -1,106 +0,0 @@ -; RUN: llc -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 < %s | FileCheck %s - -target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32" -target triple = "thumbv7-apple-darwin9" - -@history = internal global [2 x [56 x i32]] [[56 x i32] [i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 0, i32 1, i32 2, i32 4, i32 2, i32 1, i32 0, i32 -1, i32 1, i32 3, i32 5, i32 7, i32 5, i32 3, i32 1, i32 -1, i32 2, i32 5, i32 8, i32 10, i32 8, i32 5, i32 2, i32 -1, i32 2, i32 5, i32 8, i32 10, i32 8, i32 5, i32 2, i32 -1, i32 1, i32 3, i32 5, i32 7, i32 5, i32 3, i32 1, i32 -1, i32 0, i32 1, i32 2, i32 4, i32 2, i32 1, i32 0], [56 x i32] [i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 0, i32 1, i32 2, i32 4, i32 2, i32 1, i32 0, i32 -1, i32 1, i32 3, i32 5, i32 7, i32 5, i32 3, i32 1, i32 -1, i32 2, i32 5, i32 8, i32 10, i32 8, i32 5, i32 2, i32 -1, i32 2, i32 5, i32 8, i32 10, i32 8, i32 5, i32 2, i32 -1, i32 1, i32 3, i32 5, i32 7, i32 5, i32 3, i32 1, i32 -1, i32 0, i32 1, i32 2, i32 4, i32 2, i32 1, i32 0]] ; <[2 x [56 x i32]]*> [#uses=3] -@nodes = internal global i64 0 ; [#uses=4] -@.str = private constant [9 x i8] c"##-<=>+#\00", align 1 ; <[9 x i8]*> [#uses=2] -@.str1 = private constant [6 x i8] c"%c%d\0A\00", align 1 ; <[6 x i8]*> [#uses=1] -@.str2 = private constant [16 x i8] c"Fhourstones 2.0\00", align 1 ; <[16 x i8]*> [#uses=1] -@.str3 = private constant [54 x i8] c"Using %d transposition table entries with %d probes.\0A\00", align 1 ; <[54 x i8]*> [#uses=1] -@.str4 = private constant [31 x i8] c"Solving %d-ply position after \00", align 1 ; <[31 x i8]*> [#uses=1] -@.str5 = private constant [7 x i8] c" . . .\00", align 1 ; <[7 x i8]*> [#uses=1] -@.str6 = private constant [28 x i8] c"score = %d (%c) work = %d\0A\00", align 1 ; <[28 x i8]*> [#uses=1] -@.str7 = private constant [36 x i8] c"%lu pos / %lu msec = %.1f Kpos/sec\0A\00", align 1 ; <[36 x i8]*> [#uses=1] -@plycnt = internal global i32 0 ; [#uses=21] -@dias = internal global [19 x i32] zeroinitializer ; <[19 x i32]*> [#uses=43] -@columns = internal global [128 x i32] zeroinitializer ; <[128 x i32]*> [#uses=18] -@height = internal global [128 x i32] zeroinitializer ; <[128 x i32]*> [#uses=21] -@rows = internal global [8 x i32] zeroinitializer ; <[8 x i32]*> [#uses=20] -@colthr = internal global [128 x i32] zeroinitializer ; <[128 x i32]*> [#uses=5] -@moves = internal global [44 x i32] zeroinitializer ; <[44 x i32]*> [#uses=9] -@.str8 = private constant [3 x i8] c"%d\00", align 1 ; <[3 x i8]*> [#uses=1] -@he = internal global i8* null ; [#uses=9] -@hits = internal global i64 0 ; [#uses=8] -@posed = internal global i64 0 ; [#uses=7] -@ht = internal global i32* null ; [#uses=5] -@.str16 = private constant [19 x i8] c"store rate = %.3f\0A\00", align 1 ; <[19 x i8]*> [#uses=1] -@.str117 = private constant [45 x i8] c"- %5.3f < %5.3f = %5.3f > %5.3f + %5.3f\0A\00", align 1 ; <[45 x i8]*> [#uses=1] -@.str218 = private constant [6 x i8] c"%7d%c\00", align 1 ; <[6 x i8]*> [#uses=1] -@.str319 = private constant [30 x i8] c"Failed to allocate %u bytes.\0A\00", align 1 ; <[30 x i8]*> [#uses=1] - -declare i32 @puts(i8* nocapture) nounwind - -declare i32 @getchar() nounwind - -define internal i32 @transpose() nounwind readonly { -; CHECK: push -entry: - %0 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 1), align 4 ; [#uses=1] - %1 = shl i32 %0, 7 ; [#uses=1] - %2 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 2), align 4 ; [#uses=1] - %3 = or i32 %1, %2 ; [#uses=1] - %4 = shl i32 %3, 7 ; [#uses=1] - %5 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 3), align 4 ; [#uses=1] - %6 = or i32 %4, %5 ; [#uses=3] - %7 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 7), align 4 ; [#uses=1] - %8 = shl i32 %7, 7 ; [#uses=1] - %9 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 6), align 4 ; [#uses=1] - %10 = or i32 %8, %9 ; [#uses=1] - %11 = shl i32 %10, 7 ; [#uses=1] - %12 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 5), align 4 ; [#uses=1] - %13 = or i32 %11, %12 ; [#uses=3] - %14 = icmp ugt i32 %6, %13 ; [#uses=2] - %.pn2.in.i = select i1 %14, i32 %6, i32 %13 ; [#uses=1] - %.pn1.in.i = select i1 %14, i32 %13, i32 %6 ; [#uses=1] - %.pn2.i = shl i32 %.pn2.in.i, 7 ; [#uses=1] - %.pn3.i = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 4) ; [#uses=1] - %.pn.in.in.i = or i32 %.pn2.i, %.pn3.i ; [#uses=1] - %.pn.in.i = zext i32 %.pn.in.in.i to i64 ; [#uses=1] - %.pn.i = shl i64 %.pn.in.i, 21 ; [#uses=1] - %.pn1.i = zext i32 %.pn1.in.i to i64 ; [#uses=1] - %iftmp.22.0.i = or i64 %.pn.i, %.pn1.i ; [#uses=2] - %15 = lshr i64 %iftmp.22.0.i, 17 ; [#uses=1] - %16 = trunc i64 %15 to i32 ; [#uses=2] - %17 = urem i64 %iftmp.22.0.i, 1050011 ; [#uses=1] - %18 = trunc i64 %17 to i32 ; [#uses=1] - %19 = urem i32 %16, 179 ; [#uses=1] - %20 = or i32 %19, 131072 ; [#uses=1] - %21 = load i32** @ht, align 4 ; [#uses=1] - br label %bb5 - -bb: ; preds = %bb5 - %22 = getelementptr inbounds i32* %21, i32 %x.0 ; [#uses=1] - %23 = load i32* %22, align 4 ; [#uses=1] - %24 = icmp eq i32 %23, %16 ; [#uses=1] - br i1 %24, label %bb1, label %bb2 - -bb1: ; preds = %bb - %25 = load i8** @he, align 4 ; [#uses=1] - %26 = getelementptr inbounds i8* %25, i32 %x.0 ; [#uses=1] - %27 = load i8* %26, align 1 ; [#uses=1] - %28 = sext i8 %27 to i32 ; [#uses=1] - ret i32 %28 - -bb2: ; preds = %bb - %29 = add nsw i32 %20, %x.0 ; [#uses=3] - %30 = add i32 %29, -1050011 ; [#uses=1] - %31 = icmp sgt i32 %29, 1050010 ; [#uses=1] - %. = select i1 %31, i32 %30, i32 %29 ; [#uses=1] - %32 = add i32 %33, 1 ; [#uses=1] - br label %bb5 - -bb5: ; preds = %bb2, %entry - %33 = phi i32 [ 0, %entry ], [ %32, %bb2 ] ; [#uses=2] - %x.0 = phi i32 [ %18, %entry ], [ %., %bb2 ] ; [#uses=3] - %34 = icmp sgt i32 %33, 7 ; [#uses=1] - br i1 %34, label %bb7, label %bb - -bb7: ; preds = %bb5 - ret i32 -128 -} - -declare noalias i8* @calloc(i32, i32) nounwind - -declare void @llvm.memset.i64(i8* nocapture, i8, i64, i32) nounwind diff --git a/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll b/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll index 4aa879d..0fe3b39 100644 --- a/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll +++ b/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll @@ -5,7 +5,7 @@ define void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y.0) nounwind { ; CHECK: foo: -; CHECK: bl __adddf3 +; CHECK: bl __aeabi_dadd ; CHECK-NOT: strd ; CHECK: mov %x76 = fmul double %y.0, 0.000000e+00 ; [#uses=1] diff --git a/test/CodeGen/ARM/2009-11-02-NegativeLane.ll b/test/CodeGen/ARM/2009-11-02-NegativeLane.ll index 89c9037..ca5ae8b 100644 --- a/test/CodeGen/ARM/2009-11-02-NegativeLane.ll +++ b/test/CodeGen/ARM/2009-11-02-NegativeLane.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=cortex-a8 < %s | grep vdup.16 +; RUN: llc -mcpu=cortex-a8 < %s | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" target triple = "armv7-eabi" @@ -7,6 +7,7 @@ entry: br i1 undef, label %return, label %bb bb: ; preds = %bb, %entry +; CHECK: vld1.16 {d16[], d17[]} %0 = load i16* undef, align 2 %1 = insertelement <8 x i16> undef, i16 %0, i32 2 %2 = insertelement <8 x i16> %1, i16 undef, i32 3 diff --git a/test/CodeGen/ARM/2010-03-18-ldm-rtrn.ll b/test/CodeGen/ARM/2010-03-18-ldm-rtrn.ll index 31525ef..d9e1a14 100644 --- a/test/CodeGen/ARM/2010-03-18-ldm-rtrn.ll +++ b/test/CodeGen/ARM/2010-03-18-ldm-rtrn.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=armv4-unknown-eabi | FileCheck %s +; RUN: llc < %s -mtriple=armv4-unknown-eabi | FileCheck %s -check-prefix=V4 ; RUN: llc < %s -mtriple=armv5-unknown-eabi | FileCheck %s ; RUN: llc < %s -mtriple=armv6-unknown-eabi | FileCheck %s @@ -7,6 +7,8 @@ entry: %0 = tail call i32 @foo(i32 %a) nounwind ; [#uses=1] %1 = add nsw i32 %0, 3 ; [#uses=1] ; CHECK: ldmia sp!, {r11, pc} +; V4: pop +; V4-NEXT: mov pc, lr ret i32 %1 } diff --git a/test/CodeGen/ARM/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/ARM/2010-04-07-DbgValueOtherTargets.ll index 8a24cfa..6422689 100644 --- a/test/CodeGen/ARM/2010-04-07-DbgValueOtherTargets.ll +++ b/test/CodeGen/ARM/2010-04-07-DbgValueOtherTargets.ll @@ -1,33 +1,28 @@ ; RUN: llc -O0 -march=arm -asm-verbose < %s | FileCheck %s ; Check that DEBUG_VALUE comments come through on a variety of targets. -%tart.reflect.ComplexType = type { double, double } - -@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } - -define i32 @"main(tart.core.String[])->int32"(i32 %args) { +define i32 @main() nounwind ssp { entry: ; CHECK: DEBUG_VALUE - tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) - tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] - ret i32 3 + call void @llvm.dbg.value(metadata !6, i64 0, metadata !7), !dbg !9 + ret i32 0, !dbg !10 } +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone -declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone -!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] -!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] -!3 = metadata !{metadata !4, metadata !6, metadata !7} -!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] -!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] -!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] -!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] -!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] -!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] -!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] -!12 = metadata !{metadata !13} -!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} +!llvm.dbg.sp = !{!0} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !"clang version 2.9 (trunk 120996)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 589860, metadata !2, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 0} +!7 = metadata !{i32 590080, metadata !8, metadata !"i", metadata !1, i32 3, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!8 = metadata !{i32 589835, metadata !0, i32 2, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!9 = metadata !{i32 3, i32 11, metadata !8, null} +!10 = metadata !{i32 4, i32 2, metadata !8, null} + diff --git a/test/CodeGen/ARM/2010-05-17-DAGCombineAssert.ll b/test/CodeGen/ARM/2010-05-17-DAGCombineAssert.ll deleted file mode 100644 index 2a4bbd1..0000000 --- a/test/CodeGen/ARM/2010-05-17-DAGCombineAssert.ll +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 -; PR7158 - -define arm_aapcs_vfpcc i32 @main() nounwind { -bb.nph55.bb.nph55.split_crit_edge: - br label %bb3 - -bb3: ; preds = %bb3, %bb.nph55.bb.nph55.split_crit_edge - br i1 undef, label %bb.i19, label %bb3 - -bb.i19: ; preds = %bb.i19, %bb3 - %0 = insertelement <4 x float> undef, float undef, i32 3 ; <<4 x float>> [#uses=3] - %1 = fmul <4 x float> %0, %0 ; <<4 x float>> [#uses=1] - %2 = bitcast <4 x float> %1 to <2 x double> ; <<2 x double>> [#uses=0] - %3 = fmul <4 x float> %0, undef ; <<4 x float>> [#uses=0] - br label %bb.i19 -} diff --git a/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll b/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll deleted file mode 100644 index ad2810b..0000000 --- a/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll +++ /dev/null @@ -1,10 +0,0 @@ -; RUN: llc < %s -march=arm -mattr=+neon - -define void @main() nounwind { -entry: - store <2 x i64> undef, <2 x i64>* undef, align 16 - %0 = load <16 x i8>* undef, align 16 ; <<16 x i8>> [#uses=1] - %1 = or <16 x i8> zeroinitializer, %0 ; <<16 x i8>> [#uses=1] - store <16 x i8> %1, <16 x i8>* undef, align 16 - ret void -} diff --git a/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll b/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll index ffc47eb..b9d5600 100644 --- a/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll +++ b/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll @@ -10,9 +10,9 @@ target triple = "thumbv7-apple-darwin10" ; %reg1028 gets allocated %Q0, and if %reg1030 is reloaded for the partial ; redef, it cannot also get %Q0. -; CHECK: vld1.64 {d0, d1}, [r{{.}}] -; CHECK-NOT: vld1.64 {d0, d1} -; CHECK: vmov.f64 d3, d0 +; CHECK: vld1.64 {d16, d17}, [r{{.}}] +; CHECK-NOT: vld1.64 {d16, d17} +; CHECK: vmov.f64 d19, d16 define i32 @test(i8* %arg) nounwind { entry: diff --git a/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll b/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll new file mode 100644 index 0000000..d282091 --- /dev/null +++ b/test/CodeGen/ARM/2010-09-21-OptCmpBug.ll @@ -0,0 +1,84 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 + +declare noalias i8* @malloc(i32) nounwind + +define internal void @gl_DrawPixels(i32 %width, i32 %height, i32 %format, i32 %type, i8* %pixels) nounwind { +entry: + br i1 undef, label %bb3.i, label %bb3 + +bb3.i: ; preds = %entry + unreachable + +gl_error.exit: ; preds = %bb22 + ret void + +bb3: ; preds = %entry + br i1 false, label %bb5, label %bb4 + +bb4: ; preds = %bb3 + br label %bb5 + +bb5: ; preds = %bb4, %bb3 + br i1 undef, label %bb19, label %bb22 + +bb19: ; preds = %bb5 + switch i32 %type, label %bb3.i6.i [ + i32 5120, label %bb1.i13 + i32 5121, label %bb1.i13 + i32 6656, label %bb9.i.i6 + ] + +bb9.i.i6: ; preds = %bb19 + br label %bb1.i13 + +bb3.i6.i: ; preds = %bb19 + unreachable + +bb1.i13: ; preds = %bb9.i.i6, %bb19, %bb19 + br i1 undef, label %bb3.i17, label %bb2.i16 + +bb2.i16: ; preds = %bb1.i13 + unreachable + +bb3.i17: ; preds = %bb1.i13 + br i1 undef, label %bb4.i18, label %bb23.i + +bb4.i18: ; preds = %bb3.i17 + %0 = mul nsw i32 %height, %width + %1 = and i32 %0, 7 + %not..i = icmp ne i32 %1, 0 + %2 = zext i1 %not..i to i32 + %storemerge2.i = add i32 0, %2 + %3 = call noalias i8* @malloc(i32 %storemerge2.i) nounwind + br i1 undef, label %bb3.i9, label %bb9.i + +bb9.i: ; preds = %bb4.i18 + br i1 undef, label %bb13.i19, label %bb.i24.i + +bb13.i19: ; preds = %bb9.i + br i1 undef, label %bb14.i20, label %bb15.i + +bb14.i20: ; preds = %bb13.i19 + unreachable + +bb15.i: ; preds = %bb13.i19 + unreachable + +bb.i24.i: ; preds = %bb.i24.i, %bb9.i + %storemerge1.i21.i = phi i32 [ %4, %bb.i24.i ], [ 0, %bb9.i ] + %4 = add i32 %storemerge1.i21.i, 1 + %exitcond47.i = icmp eq i32 %4, %storemerge2.i + br i1 %exitcond47.i, label %bb22, label %bb.i24.i + +bb23.i: ; preds = %bb3.i17 + unreachable + +bb3.i9: ; preds = %bb4.i18 + unreachable + +bb22: ; preds = %bb.i24.i, %bb5 + br i1 undef, label %gl_error.exit, label %bb23 + +bb23: ; preds = %bb22 + ret void +} diff --git a/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll b/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll new file mode 100644 index 0000000..bda14bc --- /dev/null +++ b/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s +; This tests that MC/asm header conversion is smooth +; +; CHECK: .syntax unified +; CHECK: .eabi_attribute 20, 1 +; CHECK: .eabi_attribute 21, 1 +; CHECK: .eabi_attribute 23, 3 +; CHECK: .eabi_attribute 24, 1 +; CHECK: .eabi_attribute 25, 1 + +define i32 @f(i64 %z) { + ret i32 0 +} diff --git a/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll b/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll new file mode 100644 index 0000000..ee443fe --- /dev/null +++ b/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll @@ -0,0 +1,37 @@ +; RUN: llc %s -mtriple=arm-linux-gnueabi -filetype=obj -o - | \ +; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=BASIC %s +; RUN: llc %s -mtriple=armv7-linux-gnueabi -march=arm -mcpu=cortex-a8 \ +; RUN: -mattr=-neon -mattr=+vfp2 \ +; RUN: -arm-reserve-r9 -filetype=obj -o - | \ +; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=CORTEXA8 %s + + +; This tests that the extpected ARM attributes are emitted. +; +; BASIC: .ARM.attributes +; BASIC-NEXT: 0x70000003 +; BASIC-NEXT: 0x00000000 +; BASIC-NEXT: 0x00000000 +; BASIC-NEXT: 0x0000003c +; BASIC-NEXT: 0x00000020 +; BASIC-NEXT: 0x00000000 +; BASIC-NEXT: 0x00000000 +; BASIC-NEXT: 0x00000001 +; BASIC-NEXT: 0x00000000 +; BASIC-NEXT: '411f0000 00616561 62690001 15000000 06020801 09011401 15011703 18011901' + +; CORTEXA8: .ARM.attributes +; CORTEXA8-NEXT: 0x70000003 +; CORTEXA8-NEXT: 0x00000000 +; CORTEXA8-NEXT: 0x00000000 +; CORTEXA8-NEXT: 0x0000003c +; CORTEXA8-NEXT: 0x0000002f +; CORTEXA8-NEXT: 0x00000000 +; CORTEXA8-NEXT: 0x00000000 +; CORTEXA8-NEXT: 0x00000001 +; CORTEXA8-NEXT: 0x00000000 +; CORTEXA8-NEXT: '412e0000 00616561 62690001 24000000 05434f52 5445582d 41380006 0a074108 0109020a 02140115 01170318 011901' + +define i32 @f(i64 %z) { + ret i32 0 +} diff --git a/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll b/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll new file mode 100644 index 0000000..163c9b0 --- /dev/null +++ b/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll @@ -0,0 +1,31 @@ +; RUN: llc < %s -mtriple=armv6-apple-darwin -mcpu=arm1136jf-s | FileCheck %s +; Radar 8589805: Counting the number of microcoded operations, such as for an +; LDM instruction, was causing an assertion failure because the microop count +; was being treated as an instruction count. + +; CHECK: push +; CHECK: ldmia +; CHECK: ldmia +; CHECK: ldmia + +define i32 @test(i32 %x) { +entry: + %0 = tail call signext i16 undef(i32* undef) + switch i32 undef, label %bb3 [ + i32 0, label %bb4 + i32 1, label %bb1 + i32 2, label %bb2 + ] + +bb1: + ret i32 1 + +bb2: + ret i32 2 + +bb3: + ret i32 1 + +bb4: + ret i32 3 +} diff --git a/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll b/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll new file mode 100644 index 0000000..0422094 --- /dev/null +++ b/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll @@ -0,0 +1,85 @@ +; RUN: llc < %s -verify-machineinstrs -spiller=standard +; RUN: llc < %s -verify-machineinstrs -spiller=inline +; PR8612 +; +; This test has an inline asm with early-clobber arguments. +; It is big enough that one of the early clobber registers is spilled. +; +; All the spillers would get the live ranges wrong when spilling an early +; clobber, allowing the undef register to be allocated to the same register as +; the early clobber. +; +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32" +target triple = "armv7-eabi" + +%0 = type { i32, i32 } + +define void @foo(i32* %in) nounwind { +entry: + br label %bb.i + +bb.i: ; preds = %bb.i, %entry + br i1 undef, label %bb10.preheader.i, label %bb.i + +bb10.preheader.i: ; preds = %bb.i + br label %bb10.i + +bb10.i: ; preds = %bb10.i, %bb10.preheader.i + br i1 undef, label %bb27.i, label %bb10.i + +bb27.i: ; preds = %bb10.i + br label %bb28.i + +bb28.i: ; preds = %bb28.i, %bb27.i + br i1 undef, label %presymmetry.exit, label %bb28.i + +presymmetry.exit: ; preds = %bb28.i + %tmp175387 = or i32 undef, 12 + %scevgep101.i = getelementptr i32* %in, i32 undef + %tmp189401 = or i32 undef, 7 + %scevgep97.i = getelementptr i32* %in, i32 undef + %tmp198410 = or i32 undef, 1 + %scevgep.i48 = getelementptr i32* %in, i32 undef + %0 = load i32* %scevgep.i48, align 4 + %1 = add nsw i32 %0, 0 + store i32 %1, i32* undef, align 4 + %asmtmp.i.i33.i.i.i = tail call %0 asm "smull\09$0, $1, $2, $3", "=&r,=&r,%r,r,~{cc}"(i32 undef, i32 1518500250) nounwind + %asmresult1.i.i34.i.i.i = extractvalue %0 %asmtmp.i.i33.i.i.i, 1 + %2 = shl i32 %asmresult1.i.i34.i.i.i, 1 + %3 = load i32* null, align 4 + %4 = load i32* undef, align 4 + %5 = sub nsw i32 %3, %4 + %6 = load i32* undef, align 4 + %7 = load i32* null, align 4 + %8 = sub nsw i32 %6, %7 + %9 = load i32* %scevgep97.i, align 4 + %10 = load i32* undef, align 4 + %11 = sub nsw i32 %9, %10 + %12 = load i32* null, align 4 + %13 = load i32* %scevgep101.i, align 4 + %14 = sub nsw i32 %12, %13 + %15 = load i32* %scevgep.i48, align 4 + %16 = load i32* null, align 4 + %17 = add nsw i32 %16, %15 + %18 = sub nsw i32 %15, %16 + %19 = load i32* undef, align 4 + %20 = add nsw i32 %19, %2 + %21 = sub nsw i32 %19, %2 + %22 = add nsw i32 %14, %5 + %23 = sub nsw i32 %5, %14 + %24 = add nsw i32 %11, %8 + %25 = sub nsw i32 %8, %11 + %26 = add nsw i32 %21, %23 + store i32 %26, i32* %scevgep.i48, align 4 + %27 = sub nsw i32 %25, %18 + store i32 %27, i32* null, align 4 + %28 = sub nsw i32 %23, %21 + store i32 %28, i32* undef, align 4 + %29 = add nsw i32 %18, %25 + store i32 %29, i32* undef, align 4 + %30 = add nsw i32 %17, %22 + store i32 %30, i32* %scevgep101.i, align 4 + %31 = add nsw i32 %20, %24 + store i32 %31, i32* null, align 4 + unreachable +} diff --git a/test/CodeGen/ARM/2010-11-29-PrologueBug.ll b/test/CodeGen/ARM/2010-11-29-PrologueBug.ll new file mode 100644 index 0000000..8d7541f --- /dev/null +++ b/test/CodeGen/ARM/2010-11-29-PrologueBug.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB2 +; rdar://8690640 + +define i32* @t(i32* %x) nounwind { +entry: +; ARM: t: +; ARM: push +; ARM: mov r7, sp +; ARM: bl _foo +; ARM: bl _foo +; ARM: bl _foo +; ARM: ldmia sp!, {r7, pc} + +; THUMB2: t: +; THUMB2: push +; THUMB2: mov r7, sp +; THUMB2: blx _foo +; THUMB2: blx _foo +; THUMB2: blx _foo +; THUMB2: pop + %0 = tail call i32* @foo(i32* %x) nounwind + %1 = tail call i32* @foo(i32* %0) nounwind + %2 = tail call i32* @foo(i32* %1) nounwind + ret i32* %2 +} + +declare i32* @foo(i32*) diff --git a/test/CodeGen/ARM/2010-11-30-reloc-movt.ll b/test/CodeGen/ARM/2010-11-30-reloc-movt.ll new file mode 100644 index 0000000..930cd8d --- /dev/null +++ b/test/CodeGen/ARM/2010-11-30-reloc-movt.ll @@ -0,0 +1,42 @@ +; RUN: llc %s -mtriple=armv7-linux-gnueabi -filetype=obj -o - | \ +; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s + +target triple = "armv7-none-linux-gnueabi" + +@a = external global i8 + +define arm_aapcs_vfpcc i32 @barf() nounwind { +entry: + %0 = tail call arm_aapcs_vfpcc i32 @foo(i8* @a) nounwind + ret i32 %0 +; OBJ: '.text' +; OBJ-NEXT: 'sh_type' +; OBJ-NEXT: 'sh_flags' +; OBJ-NEXT: 'sh_addr' +; OBJ-NEXT: 'sh_offset' +; OBJ-NEXT: 'sh_size' +; OBJ-NEXT: 'sh_link' +; OBJ-NEXT: 'sh_info' +; OBJ-NEXT: 'sh_addralign' +; OBJ-NEXT: 'sh_entsize' +; OBJ-NEXT: '_section_data', '00482de9 000000e3 000040e3 feffffeb 0088bde8' + +; OBJ: Relocation 0x00000000 +; OBJ-NEXT: 'r_offset', 0x00000004 +; OBJ-NEXT: 'r_sym', 0x00000007 +; OBJ-NEXT: 'r_type', 0x0000002b + +; OBJ: Relocation 0x00000001 +; OBJ-NEXT: 'r_offset', 0x00000008 +; OBJ-NEXT: 'r_sym' +; OBJ-NEXT: 'r_type', 0x0000002c + +; OBJ: # Relocation 0x00000002 +; OBJ-NEXT: 'r_offset', 0x0000000c +; OBJ-NEXT: 'r_sym', 0x00000008 +; OBJ-NEXT: 'r_type', 0x0000001c + +} + +declare arm_aapcs_vfpcc i32 @foo(i8*) + diff --git a/test/CodeGen/ARM/2010-12-07-PEIBug.ll b/test/CodeGen/ARM/2010-12-07-PEIBug.ll new file mode 100644 index 0000000..c65952b --- /dev/null +++ b/test/CodeGen/ARM/2010-12-07-PEIBug.ll @@ -0,0 +1,40 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-a8 | FileCheck %s +; rdar://8728956 + +define hidden void @foo() nounwind ssp { +entry: +; CHECK: foo: +; CHECK: push {r7, lr} +; CHECK-NEXT: mov r7, sp +; CHECK-NEXT: vpush {d8} +; CHECK-NEXT: vpush {d10, d11} + %tmp40 = load <4 x i8>* undef + %tmp41 = extractelement <4 x i8> %tmp40, i32 2 + %conv42 = zext i8 %tmp41 to i32 + %conv43 = sitofp i32 %conv42 to float + %div44 = fdiv float %conv43, 2.560000e+02 + %vecinit45 = insertelement <4 x float> undef, float %div44, i32 2 + %vecinit46 = insertelement <4 x float> %vecinit45, float 1.000000e+00, i32 3 + store <4 x float> %vecinit46, <4 x float>* undef + br i1 undef, label %if.then105, label %if.else109 + +if.then105: ; preds = %entry + br label %if.end114 + +if.else109: ; preds = %entry + br label %if.end114 + +if.end114: ; preds = %if.else109, %if.then105 + %call185 = call float @bar() + %vecinit186 = insertelement <4 x float> undef, float %call185, i32 1 + %call189 = call float @bar() + %vecinit190 = insertelement <4 x float> %vecinit186, float %call189, i32 2 + %vecinit191 = insertelement <4 x float> %vecinit190, float 1.000000e+00, i32 3 + store <4 x float> %vecinit191, <4 x float>* undef +; CHECK: vpop {d10, d11} +; CHECK-NEXT: vpop {d8} +; CHECK-NEXT: pop {r7, pc} + ret void +} + +declare hidden float @bar() nounwind readnone ssp diff --git a/test/CodeGen/ARM/2010-12-08-tpsoft.ll b/test/CodeGen/ARM/2010-12-08-tpsoft.ll new file mode 100644 index 0000000..b8ed819 --- /dev/null +++ b/test/CodeGen/ARM/2010-12-08-tpsoft.ll @@ -0,0 +1,52 @@ +; RUN: llc %s -mtriple=armv7-linux-gnueabi -o - | \ +; RUN: FileCheck -check-prefix=ELFASM %s +; RUN: llc %s -mtriple=armv7-linux-gnueabi -filetype=obj -o - | \ +; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=ELFOBJ %s + +;; Make sure that bl __aeabi_read_tp is materiazlied and fixed up correctly +;; in the obj case. + +@i = external thread_local global i32 +@a = external global i8 +@b = external global [10 x i8] + +define arm_aapcs_vfpcc i32 @main() nounwind { +entry: + %0 = load i32* @i, align 4 + switch i32 %0, label %bb2 [ + i32 12, label %bb + i32 13, label %bb1 + ] + +bb: ; preds = %entry + %1 = tail call arm_aapcs_vfpcc i32 @foo(i8* @a) nounwind + ret i32 %1 +; ELFASM: bl __aeabi_read_tp + + +; ELFOBJ: '.text' +; ELFOBJ-NEXT: 'sh_type' +; ELFOBJ-NEXT: 'sh_flags' +; ELFOBJ-NEXT: 'sh_addr' +; ELFOBJ-NEXT: 'sh_offset' +; ELFOBJ-NEXT: 'sh_size' +; ELFOBJ-NEXT: 'sh_link' +; ELFOBJ-NEXT: 'sh_info' +; ELFOBJ-NEXT: 'sh_addralign' +; ELFOBJ-NEXT: 'sh_entsize' +;;; BL __aeabi_read_tp is ---+ +;;; V +; ELFOBJ-NEXT: 00482de9 3c009fe5 00109fe7 feffffeb + + +bb1: ; preds = %entry + %2 = tail call arm_aapcs_vfpcc i32 @bar(i32* bitcast ([10 x i8]* @b to i32*)) nounwind + ret i32 %2 + +bb2: ; preds = %entry + ret i32 -1 +} + +declare arm_aapcs_vfpcc i32 @foo(i8*) + +declare arm_aapcs_vfpcc i32 @bar(i32*) diff --git a/test/CodeGen/ARM/2010-12-13-reloc-pic.ll b/test/CodeGen/ARM/2010-12-13-reloc-pic.ll new file mode 100644 index 0000000..d5aefbe --- /dev/null +++ b/test/CodeGen/ARM/2010-12-13-reloc-pic.ll @@ -0,0 +1,100 @@ +; RUN: llc %s -mtriple=armv7-linux-gnueabi -relocation-model=pic -filetype=obj -o - | \ +; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=PIC01 %s + +;; FIXME: Reduce this test further, or even better, +;; redo as .s -> .o test once ARM AsmParser is working better + +; ModuleID = 'large2.pnacl.bc' +target triple = "armv7-none-linux-gnueabi" + +%struct._Bigint = type { %struct._Bigint*, i32, i32, i32, i32, [1 x i32] } +%struct.__FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, %struct._reent*, i8*, i32 (%struct._reent*, i8*, i8*, i32)*, i32 (%struct._reent*, i8*, i8*, i32)*, i32 (%struct._reent*, i8*, i32, i32)*, i32 (%struct._reent*, i8*)*, %struct.__sbuf, i8*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i32, %struct._flock_t, %struct._mbstate_t, i32 } +%struct.__sbuf = type { i8*, i32 } +%struct.__tm = type { i32, i32, i32, i32, i32, i32, i32, i32, i32 } +%struct._atexit = type { %struct._atexit*, i32, [32 x void ()*], %struct._on_exit_args* } +%struct._flock_t = type { i32, i32, i32, i32, i32 } +%struct._glue = type { %struct._glue*, i32, %struct.__FILE* } +%struct._mbstate_t = type { i32, %union.anon } +%struct._misc_reent = type { i8*, %struct._mbstate_t, %struct._mbstate_t, %struct._mbstate_t, [8 x i8], i32, %struct._mbstate_t, %struct._mbstate_t, %struct._mbstate_t, %struct._mbstate_t, %struct._mbstate_t } +%struct._mprec = type { %struct._Bigint*, i32, %struct._Bigint*, %struct._Bigint** } +%struct._on_exit_args = type { [32 x i8*], [32 x i8*], i32, i32 } +%struct._rand48 = type { [3 x i16], [3 x i16], i16, i64 } +%struct._reent = type { %struct.__FILE*, %struct.__FILE*, %struct.__FILE*, i32, i32, i8*, i32, i32, i8*, %struct._mprec*, void (%struct._reent*)*, i32, i32, i8*, %struct._rand48*, %struct.__tm*, i8*, void (i32)**, %struct._atexit*, %struct._atexit, %struct._glue, %struct.__FILE*, %struct._misc_reent*, i8* } +%union.anon = type { i32 } + +@buf = constant [2 x i8] c"x\00", align 4 +@_impure_ptr = external thread_local global %struct._reent* +@.str = private constant [22 x i8] c"This should fault...\0A\00", align 4 +@.str1 = private constant [40 x i8] c"We're still running. This is not good.\0A\00", align 4 + +define i32 @main() nounwind { +entry: + %0 = load %struct._reent** @_impure_ptr, align 4 + %1 = getelementptr inbounds %struct._reent* %0, i32 0, i32 1 + %2 = load %struct.__FILE** %1, align 4 + %3 = bitcast %struct.__FILE* %2 to i8* + %4 = tail call i32 @fwrite(i8* getelementptr inbounds ([22 x i8]* @.str, i32 0, i32 0), i32 1, i32 21, i8* %3) nounwind + %5 = load %struct._reent** @_impure_ptr, align 4 + %6 = getelementptr inbounds %struct._reent* %5, i32 0, i32 1 + %7 = load %struct.__FILE** %6, align 4 + %8 = tail call i32 @fflush(%struct.__FILE* %7) nounwind + store i8 121, i8* getelementptr inbounds ([2 x i8]* @buf, i32 0, i32 0), align 4 + %9 = load %struct._reent** @_impure_ptr, align 4 + %10 = getelementptr inbounds %struct._reent* %9, i32 0, i32 1 + %11 = load %struct.__FILE** %10, align 4 + %12 = bitcast %struct.__FILE* %11 to i8* + %13 = tail call i32 @fwrite(i8* getelementptr inbounds ([40 x i8]* @.str1, i32 0, i32 0), i32 1, i32 39, i8* %12) nounwind + ret i32 1 +} + + +; PIC01: Relocation 0x00000000 +; PIC01-NEXT: 'r_offset', 0x0000001c +; PIC01-NEXT: 'r_sym' +; PIC01-NEXT: 'r_type', 0x0000001b + + +; PIC01: Relocation 0x00000001 +; PIC01-NEXT: 'r_offset', 0x00000038 +; PIC01-NEXT: 'r_sym' +; PIC01-NEXT: 'r_type', 0x0000001b + +; PIC01: Relocation 0x00000002 +; PIC01-NEXT: 'r_offset', 0x00000044 +; PIC01-NEXT: 'r_sym' +; PIC01-NEXT: 'r_type', 0x0000001b + +; PIC01: Relocation 0x00000003 +; PIC01-NEXT: 'r_offset', 0x00000070 +; PIC01-NEXT: 'r_sym' +; PIC01-NEXT: 'r_type', 0x0000001b + +; PIC01: Relocation 0x00000004 +; PIC01-NEXT: 'r_offset', 0x0000007c +; PIC01-NEXT: 'r_sym' +; PIC01-NEXT: 'r_type', 0x00000019 + + +; PIC01: Relocation 0x00000005 +; PIC01-NEXT: 'r_offset', 0x00000080 +; PIC01-NEXT: 'r_sym' +; PIC01-NEXT: 'r_type', 0x00000018 + +; PIC01: Relocation 0x00000006 +; PIC01-NEXT: 'r_offset', 0x00000084 +; PIC01-NEXT: 'r_sym' +; PIC01-NEXT: 'r_type', 0x00000068 + +; PIC01: Relocation 0x00000007 +; PIC01-NEXT: 'r_offset', 0x00000088 +; PIC01-NEXT: 'r_sym' +; PIC01-NEXT: 'r_type', 0x0000001a + +; PIC01: Relocation 0x00000008 +; PIC01-NEXT: 'r_offset', 0x0000008c +; PIC01-NEXT: 'r_sym' +; PIC01-NEXT: 'r_type', 0x00000018 + +declare i32 @fwrite(i8* nocapture, i32, i32, i8* nocapture) nounwind + +declare i32 @fflush(%struct.__FILE* nocapture) nounwind diff --git a/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll b/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll new file mode 100644 index 0000000..eaa34e7 --- /dev/null +++ b/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll @@ -0,0 +1,35 @@ +; RUN: llc %s -mtriple=armv7-linux-gnueabi -filetype=obj -o - | \ +; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s +; RUN: llc %s -mtriple=armv7-linux-gnueabi -o - | \ +; RUN: FileCheck -check-prefix=ASM %s + + +@dummy = internal global i32 666 +@array00 = internal global [20 x i32] zeroinitializer +@sum = internal global i32 55 +@STRIDE = internal global i32 8 + +; ASM: .type array00,%object @ @array00 +; ASM-NEXT: .lcomm array00,80 @ @array00 +; ASM-NEXT: .type _MergedGlobals,%object @ @_MergedGlobals + + + +; OBJ: Section 0x00000003 +; OBJ-NEXT: '.bss' + +; OBJ: 'array00' +; OBJ-NEXT: 'st_value', 0x00000000 +; OBJ-NEXT: 'st_size', 0x00000050 +; OBJ-NEXT: 'st_bind', 0x00000000 +; OBJ-NEXT: 'st_type', 0x00000001 +; OBJ-NEXT: 'st_other', 0x00000000 +; OBJ-NEXT: 'st_shndx', 0x00000003 + +define i32 @main(i32 %argc) nounwind { + %1 = load i32* @sum, align 4 + %2 = getelementptr [20 x i32]* @array00, i32 0, i32 %argc + %3 = load i32* %2, align 4 + %4 = add i32 %1, %3 + ret i32 %4; +} diff --git a/test/CodeGen/ARM/2010-12-17-LocalStackSlotCrash.ll b/test/CodeGen/ARM/2010-12-17-LocalStackSlotCrash.ll new file mode 100644 index 0000000..a2f50b5 --- /dev/null +++ b/test/CodeGen/ARM/2010-12-17-LocalStackSlotCrash.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -mtriple=armv6-apple-darwin10 +; +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:64-n32" +target triple = "armv6-apple-darwin10" + +define void @func() nounwind optsize { +entry: + %buf = alloca [8096 x i8], align 1 + br label %bb + +bb: + %p.2 = getelementptr [8096 x i8]* %buf, i32 0, i32 0 + store i8 undef, i8* %p.2, align 1 + ret void +} diff --git a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll new file mode 100644 index 0000000..99baad2 --- /dev/null +++ b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll @@ -0,0 +1,127 @@ +; RUN: llc < %s | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10" + +@x1 = internal global i8 1 +@x2 = internal global i8 1 +@x3 = internal global i8 1 +@x4 = internal global i8 1 +@x5 = global i8 1 + +; Check debug info output for merged global. +; DW_AT_location +; DW_OP_addr +; DW_OP_plus +; .long __MergedGlobals +; DW_OP_constu +; offset + +;CHECK: .byte 7 @ Abbrev [7] 0x1a5:0x13 DW_TAG_variable +;CHECK-NEXT: .ascii "x2" @ DW_AT_name +;CHECK-NEXT: .byte 0 +;CHECK-NEXT: .long 93 @ DW_AT_type +;CHECK-NEXT: .byte 1 @ DW_AT_decl_file +;CHECK-NEXT: .byte 6 @ DW_AT_decl_line +;CHECK-NEXT: .byte 8 @ DW_AT_location +;CHECK-NEXT: .byte 3 +;CHECK-NEXT: .long __MergedGlobals +;CHECK-NEXT: .byte 16 +;CHECK-NEXT: .byte 1 +;CHECK-NEXT: .byte 34 + +define zeroext i8 @get1(i8 zeroext %a) nounwind optsize { +entry: + tail call void @llvm.dbg.value(metadata !{i8 %a}, i64 0, metadata !10), !dbg !30 + %0 = load i8* @x1, align 4, !dbg !30 + tail call void @llvm.dbg.value(metadata !{i8 %0}, i64 0, metadata !11), !dbg !30 + store i8 %a, i8* @x1, align 4, !dbg !30 + ret i8 %0, !dbg !31 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +define zeroext i8 @get2(i8 zeroext %a) nounwind optsize { +entry: + tail call void @llvm.dbg.value(metadata !{i8 %a}, i64 0, metadata !18), !dbg !32 + %0 = load i8* @x2, align 4, !dbg !32 + tail call void @llvm.dbg.value(metadata !{i8 %0}, i64 0, metadata !19), !dbg !32 + store i8 %a, i8* @x2, align 4, !dbg !32 + ret i8 %0, !dbg !33 +} + +define zeroext i8 @get3(i8 zeroext %a) nounwind optsize { +entry: + tail call void @llvm.dbg.value(metadata !{i8 %a}, i64 0, metadata !21), !dbg !34 + %0 = load i8* @x3, align 4, !dbg !34 + tail call void @llvm.dbg.value(metadata !{i8 %0}, i64 0, metadata !22), !dbg !34 + store i8 %a, i8* @x3, align 4, !dbg !34 + ret i8 %0, !dbg !35 +} + +define zeroext i8 @get4(i8 zeroext %a) nounwind optsize { +entry: + tail call void @llvm.dbg.value(metadata !{i8 %a}, i64 0, metadata !24), !dbg !36 + %0 = load i8* @x4, align 4, !dbg !36 + tail call void @llvm.dbg.value(metadata !{i8 %0}, i64 0, metadata !25), !dbg !36 + store i8 %a, i8* @x4, align 4, !dbg !36 + ret i8 %0, !dbg !37 +} + +define zeroext i8 @get5(i8 zeroext %a) nounwind optsize { +entry: + tail call void @llvm.dbg.value(metadata !{i8 %a}, i64 0, metadata !27), !dbg !38 + %0 = load i8* @x5, align 4, !dbg !38 + tail call void @llvm.dbg.value(metadata !{i8 %0}, i64 0, metadata !28), !dbg !38 + store i8 %a, i8* @x5, align 4, !dbg !38 + ret i8 %0, !dbg !39 +} + +!llvm.dbg.sp = !{!0, !6, !7, !8, !9} +!llvm.dbg.lv.get1 = !{!10, !11} +!llvm.dbg.gv = !{!13, !14, !15, !16, !17} +!llvm.dbg.lv.get2 = !{!18, !19} +!llvm.dbg.lv.get3 = !{!21, !22} +!llvm.dbg.lv.get4 = !{!24, !25} +!llvm.dbg.lv.get5 = !{!27, !28} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"get1", metadata !"get1", metadata !"get1", metadata !1, i32 4, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get1} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"foo.c", metadata !"/tmp/", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 1, metadata !"foo.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 2369.8)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5, metadata !5} +!5 = metadata !{i32 589860, metadata !1, metadata !"_Bool", metadata !1, i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 589870, i32 0, metadata !1, metadata !"get2", metadata !"get2", metadata !"get2", metadata !1, i32 7, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get2} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 589870, i32 0, metadata !1, metadata !"get3", metadata !"get3", metadata !"get3", metadata !1, i32 10, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get3} ; [ DW_TAG_subprogram ] +!8 = metadata !{i32 589870, i32 0, metadata !1, metadata !"get4", metadata !"get4", metadata !"get4", metadata !1, i32 13, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get4} ; [ DW_TAG_subprogram ] +!9 = metadata !{i32 589870, i32 0, metadata !1, metadata !"get5", metadata !"get5", metadata !"get5", metadata !1, i32 16, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get5} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 590081, metadata !0, metadata !"a", metadata !1, i32 4, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] +!11 = metadata !{i32 590080, metadata !12, metadata !"b", metadata !1, i32 4, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!12 = metadata !{i32 589835, metadata !0, i32 4, i32 0, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!13 = metadata !{i32 589876, i32 0, metadata !1, metadata !"x1", metadata !"x1", metadata !"", metadata !1, i32 3, metadata !5, i1 true, i1 true, i8* @x1} ; [ DW_TAG_variable ] +!14 = metadata !{i32 589876, i32 0, metadata !1, metadata !"x2", metadata !"x2", metadata !"", metadata !1, i32 6, metadata !5, i1 true, i1 true, i8* @x2} ; [ DW_TAG_variable ] +!15 = metadata !{i32 589876, i32 0, metadata !1, metadata !"x3", metadata !"x3", metadata !"", metadata !1, i32 9, metadata !5, i1 true, i1 true, i8* @x3} ; [ DW_TAG_variable ] +!16 = metadata !{i32 589876, i32 0, metadata !1, metadata !"x4", metadata !"x4", metadata !"", metadata !1, i32 12, metadata !5, i1 true, i1 true, i8* @x4} ; [ DW_TAG_variable ] +!17 = metadata !{i32 589876, i32 0, metadata !1, metadata !"x5", metadata !"x5", metadata !"", metadata !1, i32 15, metadata !5, i1 false, i1 true, i8* @x5} ; [ DW_TAG_variable ] +!18 = metadata !{i32 590081, metadata !6, metadata !"a", metadata !1, i32 7, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] +!19 = metadata !{i32 590080, metadata !20, metadata !"b", metadata !1, i32 7, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!20 = metadata !{i32 589835, metadata !6, i32 7, i32 0, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] +!21 = metadata !{i32 590081, metadata !7, metadata !"a", metadata !1, i32 10, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] +!22 = metadata !{i32 590080, metadata !23, metadata !"b", metadata !1, i32 10, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!23 = metadata !{i32 589835, metadata !7, i32 10, i32 0, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] +!24 = metadata !{i32 590081, metadata !8, metadata !"a", metadata !1, i32 13, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] +!25 = metadata !{i32 590080, metadata !26, metadata !"b", metadata !1, i32 13, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!26 = metadata !{i32 589835, metadata !8, i32 13, i32 0, metadata !1, i32 3} ; [ DW_TAG_lexical_block ] +!27 = metadata !{i32 590081, metadata !9, metadata !"a", metadata !1, i32 16, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] +!28 = metadata !{i32 590080, metadata !29, metadata !"b", metadata !1, i32 16, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!29 = metadata !{i32 589835, metadata !9, i32 16, i32 0, metadata !1, i32 4} ; [ DW_TAG_lexical_block ] +!30 = metadata !{i32 4, i32 0, metadata !0, null} +!31 = metadata !{i32 4, i32 0, metadata !12, null} +!32 = metadata !{i32 7, i32 0, metadata !6, null} +!33 = metadata !{i32 7, i32 0, metadata !20, null} +!34 = metadata !{i32 10, i32 0, metadata !7, null} +!35 = metadata !{i32 10, i32 0, metadata !23, null} +!36 = metadata !{i32 13, i32 0, metadata !8, null} +!37 = metadata !{i32 13, i32 0, metadata !26, null} +!38 = metadata !{i32 16, i32 0, metadata !9, null} +!39 = metadata !{i32 16, i32 0, metadata !29, null} diff --git a/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll b/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll new file mode 100644 index 0000000..85a1137 --- /dev/null +++ b/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll @@ -0,0 +1,128 @@ +; RUN: llc < %s -asm-verbose=false -O3 -mtriple=armv6-apple-darwin -relocation-model=pic -mcpu=arm1136jf-s | FileCheck %s +; rdar://8959122 illegal register operands for UMULL instruction +; in cfrac nightly test. +; Armv6 generates a umull that must write to two distinct destination regs. + +; ModuleID = 'bugpoint-reduced-simplified.bc' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:64-n32" +target triple = "armv6-apple-darwin10" + +define void @ptoa() nounwind { +entry: + br i1 false, label %bb3, label %bb + +bb: ; preds = %entry + br label %bb3 + +bb3: ; preds = %bb, %entry + %0 = call noalias i8* @malloc() nounwind + br i1 undef, label %bb46, label %bb8 + +bb8: ; preds = %bb3 + %1 = getelementptr inbounds i8* %0, i32 0 + store i8 0, i8* %1, align 1 + %2 = call i32 @ptou() nounwind + ; CHECK: umull [[REGISTER:lr|r[0-9]+]], + ; CHECK-NOT: [[REGISTER]], + ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} + ; CHECK: umull [[REGISTER:lr|r[0-9]+]], + ; CHECK-NOT: [[REGISTER]], + ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} + %3 = udiv i32 %2, 10 + %4 = urem i32 %3, 10 + %5 = icmp ult i32 %4, 10 + %6 = trunc i32 %4 to i8 + %7 = or i8 %6, 48 + %8 = add i8 %6, 87 + %iftmp.5.0.1 = select i1 %5, i8 %7, i8 %8 + store i8 %iftmp.5.0.1, i8* undef, align 1 + ; CHECK: umull [[REGISTER:lr|r[0-9]+]], + ; CHECK-NOT: [[REGISTER]], + ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} + ; CHECK: umull [[REGISTER:lr|r[0-9]+]], + ; CHECK-NOT: [[REGISTER]], + ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} + %9 = udiv i32 %2, 100 + %10 = urem i32 %9, 10 + %11 = icmp ult i32 %10, 10 + %12 = trunc i32 %10 to i8 + %13 = or i8 %12, 48 + %14 = add i8 %12, 87 + %iftmp.5.0.2 = select i1 %11, i8 %13, i8 %14 + store i8 %iftmp.5.0.2, i8* undef, align 1 + ; CHECK: umull [[REGISTER:lr|r[0-9]+]], + ; CHECK-NOT: [[REGISTER]], + ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} + ; CHECK: umull [[REGISTER:lr|r[0-9]+]], + ; CHECK-NOT: [[REGISTER]], + ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} + %15 = udiv i32 %2, 10000 + %16 = urem i32 %15, 10 + %17 = icmp ult i32 %16, 10 + %18 = trunc i32 %16 to i8 + %19 = or i8 %18, 48 + %20 = add i8 %18, 87 + %iftmp.5.0.4 = select i1 %17, i8 %19, i8 %20 + store i8 %iftmp.5.0.4, i8* null, align 1 + ; CHECK: umull [[REGISTER:lr|r[0-9]+]], + ; CHECK-NOT: [[REGISTER]], + ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} + ; CHECK: umull [[REGISTER:lr|r[0-9]+]], + ; CHECK-NOT: [[REGISTER]], + ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} + %21 = udiv i32 %2, 100000 + %22 = urem i32 %21, 10 + %23 = icmp ult i32 %22, 10 + %iftmp.5.0.5 = select i1 %23, i8 0, i8 undef + store i8 %iftmp.5.0.5, i8* undef, align 1 + ; CHECK: umull [[REGISTER:lr|r[0-9]+]], + ; CHECK-NOT: [[REGISTER]], + ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} + ; CHECK: umull [[REGISTER:lr|r[0-9]+]], + ; CHECK-NOT: [[REGISTER]], + ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} + %24 = udiv i32 %2, 1000000 + %25 = urem i32 %24, 10 + %26 = icmp ult i32 %25, 10 + %27 = trunc i32 %25 to i8 + %28 = or i8 %27, 48 + %29 = add i8 %27, 87 + %iftmp.5.0.6 = select i1 %26, i8 %28, i8 %29 + store i8 %iftmp.5.0.6, i8* undef, align 1 + ; CHECK: umull [[REGISTER:lr|r[0-9]+]], + ; CHECK-NOT: [[REGISTER]], + ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} + ; CHECK: umull [[REGISTER:lr|r[0-9]+]], + ; CHECK-NOT: [[REGISTER]], + ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} + %30 = udiv i32 %2, 10000000 + %31 = urem i32 %30, 10 + %32 = icmp ult i32 %31, 10 + %33 = trunc i32 %31 to i8 + %34 = or i8 %33, 48 + %35 = add i8 %33, 87 + %iftmp.5.0.7 = select i1 %32, i8 %34, i8 %35 + store i8 %iftmp.5.0.7, i8* undef, align 1 + ; CHECK: umull [[REGISTER:lr|r[0-9]+]], + ; CHECK-NOT: [[REGISTER]], + ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} + ; CHECK: umull [[REGISTER:lr|r[0-9]+]], + ; CHECK-NOT: [[REGISTER]], + ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} + %36 = udiv i32 %2, 100000000 + %37 = urem i32 %36, 10 + %38 = icmp ult i32 %37, 10 + %39 = trunc i32 %37 to i8 + %40 = or i8 %39, 48 + %41 = add i8 %39, 87 + %iftmp.5.0.8 = select i1 %38, i8 %40, i8 %41 + store i8 %iftmp.5.0.8, i8* null, align 1 + unreachable + +bb46: ; preds = %bb3 + ret void +} + +declare noalias i8* @malloc() nounwind + +declare i32 @ptou() diff --git a/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll b/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll new file mode 100644 index 0000000..f3d7888 --- /dev/null +++ b/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll @@ -0,0 +1,89 @@ +; RUN: llc < %s -asm-verbose=false -O3 -mtriple=armv5e-none-linux-gnueabi | FileCheck %s +; PR8986: PostRA antidependence breaker must respect "earlyclobber". +; armv5e generates mulv5 that cannot used the same reg for src/dest. + +; ModuleID = '' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32" +target triple = "armv5e-none-linux-gnueabi" + +define hidden fastcc void @storeAtts() nounwind { +entry: + %.SV116 = alloca i8** + br i1 undef, label %meshBB520, label %meshBB464 + +bb15: ; preds = %meshBB424 + br i1 undef, label %bb216, label %meshBB396 + +bb22: ; preds = %meshBB396 + br label %cBB564 + +cBB564: ; preds = %cBB564, %bb22 + br label %cBB564 + +poolStoreString.exit.thread: ; preds = %meshBB424 + ret void + +bb78: ; preds = %meshBB412 + unreachable + +bb129: ; preds = %meshBB540 + br i1 undef, label %bb131.loopexit, label %meshBB540 + +bb131.loopexit: ; preds = %bb129 + br label %bb131 + +bb131: ; preds = %bb135, %bb131.loopexit + br i1 undef, label %bb134, label %meshBB396 + +bb134: ; preds = %bb131 + unreachable + +bb135: ; preds = %meshBB396 + %uriHash.1.phi.load = load i32* undef + %.load120 = load i8*** %.SV116 + %.phi24 = load i8* null + %.phi26 = load i8** null + store i8 %.phi24, i8* %.phi26, align 1 + %0 = getelementptr inbounds i8* %.phi26, i32 1 + store i8* %0, i8** %.load120, align 4 + ; CHECK: mul [[REGISTER:lr|r[0-9]+]], + ; CHECK-NOT: [[REGISTER]], + ; CHECK: {{(lr|r[0-9]+)$}} + %1 = mul i32 %uriHash.1.phi.load, 1000003 + %2 = xor i32 0, %1 + store i32 %2, i32* null + %3 = load i8* null, align 1 + %4 = icmp eq i8 %3, 0 + store i8* %0, i8** undef + br i1 %4, label %meshBB472, label %bb131 + +bb212: ; preds = %meshBB540 + unreachable + +bb216: ; preds = %bb15 + ret void + +meshBB396: ; preds = %bb131, %bb15 + br i1 undef, label %bb135, label %bb22 + +meshBB412: ; preds = %meshBB464 + br i1 undef, label %meshBB504, label %bb78 + +meshBB424: ; preds = %meshBB464 + br i1 undef, label %poolStoreString.exit.thread, label %bb15 + +meshBB464: ; preds = %entry + br i1 undef, label %meshBB424, label %meshBB412 + +meshBB472: ; preds = %meshBB504, %bb135 + unreachable + +meshBB504: ; preds = %meshBB412 + br label %meshBB472 + +meshBB520: ; preds = %entry + br label %meshBB540 + +meshBB540: ; preds = %meshBB520, %bb129 + br i1 undef, label %bb212, label %bb129 +} diff --git a/test/CodeGen/ARM/align.ll b/test/CodeGen/ARM/align.ll index d4d0128..d57c159 100644 --- a/test/CodeGen/ARM/align.ll +++ b/test/CodeGen/ARM/align.ll @@ -22,7 +22,7 @@ @e = global i64 4 ;ELF: .align 3 ;ELF: e -;DARWIN: .align 2 +;DARWIN: .align 3 ;DARWIN: _e: @f = global float 5.0 @@ -34,7 +34,7 @@ @g = global double 6.0 ;ELF: .align 3 ;ELF: g: -;DARWIN: .align 2 +;DARWIN: .align 3 ;DARWIN: _g: @bar = common global [75 x i8] zeroinitializer, align 128 diff --git a/test/CodeGen/ARM/arguments.ll b/test/CodeGen/ARM/arguments.ll index bb7853e..c7fcb97 100644 --- a/test/CodeGen/ARM/arguments.ll +++ b/test/CodeGen/ARM/arguments.ll @@ -13,8 +13,8 @@ define i32 @f1(i32 %a, i64 %b) { ; test that allocating the double to r2/r3 makes r1 unavailable on gnueabi. define i32 @f2() nounwind optsize { ; ELF: f2: -; ELF: mov r0, #128 -; ELF: str r0, [sp] +; ELF: mov [[REGISTER:(r[0-9]+)]], #128 +; ELF: str [[REGISTER]], [sp] ; DARWIN: f2: ; DARWIN: mov r3, #128 entry: diff --git a/test/CodeGen/ARM/arm-and-tst-peephole.ll b/test/CodeGen/ARM/arm-and-tst-peephole.ll new file mode 100644 index 0000000..50c638b --- /dev/null +++ b/test/CodeGen/ARM/arm-and-tst-peephole.ll @@ -0,0 +1,112 @@ +; RUN: llc < %s -march=arm | FileCheck -check-prefix=ARM %s +; RUN: llc < %s -march=thumb | FileCheck -check-prefix=THUMB %s +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck -check-prefix=T2 %s + +; FIXME: The -march=thumb test doesn't change if -disable-peephole is specified. + +%struct.Foo = type { i8* } + +; ARM: foo +; THUMB: foo +; T2: foo +define %struct.Foo* @foo(%struct.Foo* %this, i32 %acc) nounwind readonly align 2 { +entry: + %scevgep = getelementptr %struct.Foo* %this, i32 1 + br label %tailrecurse + +tailrecurse: ; preds = %sw.bb, %entry + %lsr.iv2 = phi %struct.Foo* [ %scevgep3, %sw.bb ], [ %scevgep, %entry ] + %lsr.iv = phi i32 [ %lsr.iv.next, %sw.bb ], [ 1, %entry ] + %acc.tr = phi i32 [ %or, %sw.bb ], [ %acc, %entry ] + %lsr.iv24 = bitcast %struct.Foo* %lsr.iv2 to i8** + %scevgep5 = getelementptr i8** %lsr.iv24, i32 -1 + %tmp2 = load i8** %scevgep5 + %0 = ptrtoint i8* %tmp2 to i32 + +; ARM: ands r12, r12, #3 +; ARM-NEXT: beq + +; THUMB: movs r5, #3 +; THUMB-NEXT: ands r5, r4 +; THUMB-NEXT: cmp r5, #0 +; THUMB-NEXT: beq + +; T2: ands r12, r12, #3 +; T2-NEXT: beq + + %and = and i32 %0, 3 + %tst = icmp eq i32 %and, 0 + br i1 %tst, label %sw.bb, label %tailrecurse.switch + +tailrecurse.switch: ; preds = %tailrecurse + switch i32 %and, label %sw.epilog [ + i32 1, label %sw.bb + i32 3, label %sw.bb6 + i32 2, label %sw.bb8 + ] + +sw.bb: ; preds = %tailrecurse.switch, %tailrecurse + %shl = shl i32 %acc.tr, 1 + %or = or i32 %and, %shl + %lsr.iv.next = add i32 %lsr.iv, 1 + %scevgep3 = getelementptr %struct.Foo* %lsr.iv2, i32 1 + br label %tailrecurse + +sw.bb6: ; preds = %tailrecurse.switch + ret %struct.Foo* %lsr.iv2 + +sw.bb8: ; preds = %tailrecurse.switch + %tmp1 = add i32 %acc.tr, %lsr.iv + %add.ptr11 = getelementptr inbounds %struct.Foo* %this, i32 %tmp1 + ret %struct.Foo* %add.ptr11 + +sw.epilog: ; preds = %tailrecurse.switch + ret %struct.Foo* undef +} + +; Another test that exercises the AND/TST peephole optimization and also +; generates a predicated ANDS instruction. Check that the predicate is printed +; after the "S" modifier on the instruction. + +%struct.S = type { i8* (i8*)*, [1 x i8] } + +; ARM: bar +; THUMB: bar +; T2: bar +define internal zeroext i8 @bar(%struct.S* %x, %struct.S* nocapture %y) nounwind readonly { +entry: + %0 = getelementptr inbounds %struct.S* %x, i32 0, i32 1, i32 0 + %1 = load i8* %0, align 1 + %2 = zext i8 %1 to i32 +; ARM: ands +; THUMB: ands +; T2: ands + %3 = and i32 %2, 112 + %4 = icmp eq i32 %3, 0 + br i1 %4, label %return, label %bb + +bb: ; preds = %entry + %5 = getelementptr inbounds %struct.S* %y, i32 0, i32 1, i32 0 + %6 = load i8* %5, align 1 + %7 = zext i8 %6 to i32 +; ARM: andsne +; THUMB: ands +; T2: andsne + %8 = and i32 %7, 112 + %9 = icmp eq i32 %8, 0 + br i1 %9, label %return, label %bb2 + +bb2: ; preds = %bb + %10 = icmp eq i32 %3, 16 + %11 = icmp eq i32 %8, 16 + %or.cond = or i1 %10, %11 + br i1 %or.cond, label %bb4, label %return + +bb4: ; preds = %bb2 + %12 = ptrtoint %struct.S* %x to i32 + %phitmp = trunc i32 %12 to i8 + ret i8 %phitmp + +return: ; preds = %bb2, %bb, %entry + ret i8 1 +} diff --git a/test/CodeGen/ARM/atomic-cmp.ll b/test/CodeGen/ARM/atomic-cmp.ll new file mode 100644 index 0000000..f31aa7b --- /dev/null +++ b/test/CodeGen/ARM/atomic-cmp.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s -check-prefix=T2 +; rdar://8964854 + +define i8 @t(i8* %a, i8 %b, i8 %c) nounwind { +; ARM: t: +; ARM: ldrexb +; ARM: strexb + +; T2: t: +; T2: ldrexb +; T2: strexb + %tmp0 = tail call i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* %a, i8 %b, i8 %c) + ret i8 %tmp0 +} + +declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* nocapture, i8, i8) nounwind diff --git a/test/CodeGen/ARM/bfi.ll b/test/CodeGen/ARM/bfi.ll index 59e2b43..946db19 100644 --- a/test/CodeGen/ARM/bfi.ll +++ b/test/CodeGen/ARM/bfi.ll @@ -16,10 +16,10 @@ entry: ret void } -define i32 @f2(i32 %A, i32 %B) nounwind readnone optsize { +define i32 @f2(i32 %A, i32 %B) nounwind { entry: ; CHECK: f2 -; CHECK: mov r1, r1, lsr #7 +; CHECK: lsr{{.*}}#7 ; CHECK: bfi r0, r1, #7, #16 %and = and i32 %A, -8388481 ; [#uses=1] %and2 = and i32 %B, 8388480 ; [#uses=1] @@ -27,10 +27,10 @@ entry: ret i32 %or } -define i32 @f3(i32 %A, i32 %B) nounwind readnone optsize { +define i32 @f3(i32 %A, i32 %B) nounwind { entry: ; CHECK: f3 -; CHECK: mov r2, r0, lsr #7 +; CHECK: lsr{{.*}} #7 ; CHECK: mov r0, r1 ; CHECK: bfi r0, r2, #7, #16 %and = and i32 %A, 8388480 ; [#uses=1] @@ -38,3 +38,27 @@ entry: %or = or i32 %and2, %and ; [#uses=1] ret i32 %or } + +; rdar://8752056 +define i32 @f4(i32 %a) nounwind { +; CHECK: f4 +; CHECK: movw r1, #3137 +; CHECK: bfi r1, r0, #15, #5 + %1 = shl i32 %a, 15 + %ins7 = and i32 %1, 1015808 + %ins12 = or i32 %ins7, 3137 + ret i32 %ins12 +} + +; rdar://8458663 +define i32 @f5(i32 %a, i32 %b) nounwind { +entry: +; CHECK: f5: +; CHECK-NOT: bfc +; CHECK: bfi r0, r1, #20, #4 + %0 = and i32 %a, -15728641 + %1 = shl i32 %b, 20 + %2 = and i32 %1, 15728640 + %3 = or i32 %2, %0 + ret i32 %3 +} diff --git a/test/CodeGen/ARM/bits.ll b/test/CodeGen/ARM/bits.ll index 9e94efe..ce1b2ad 100644 --- a/test/CodeGen/ARM/bits.ll +++ b/test/CodeGen/ARM/bits.ll @@ -1,36 +1,41 @@ -; RUN: llc < %s -march=arm > %t -; RUN: grep and %t | count 1 -; RUN: grep orr %t | count 1 -; RUN: grep eor %t | count 1 -; RUN: grep mov.*lsl %t | count 1 -; RUN: grep mov.*asr %t | count 1 +; RUN: llc < %s -march=arm | FileCheck %s define i32 @f1(i32 %a, i32 %b) { entry: +; CHECK: f1 +; CHECK: and r0, r1, r0 %tmp2 = and i32 %b, %a ; [#uses=1] ret i32 %tmp2 } define i32 @f2(i32 %a, i32 %b) { entry: +; CHECK: f2 +; CHECK: orr r0, r1, r0 %tmp2 = or i32 %b, %a ; [#uses=1] ret i32 %tmp2 } define i32 @f3(i32 %a, i32 %b) { entry: +; CHECK: f3 +; CHECK: eor r0, r1, r0 %tmp2 = xor i32 %b, %a ; [#uses=1] ret i32 %tmp2 } define i32 @f4(i32 %a, i32 %b) { entry: +; CHECK: f4 +; CHECK: lsl %tmp3 = shl i32 %a, %b ; [#uses=1] ret i32 %tmp3 } define i32 @f5(i32 %a, i32 %b) { entry: +; CHECK: f5 +; CHECK: asr %tmp3 = ashr i32 %a, %b ; [#uses=1] ret i32 %tmp3 } diff --git a/test/CodeGen/ARM/bswap-inline-asm.ll b/test/CodeGen/ARM/bswap-inline-asm.ll new file mode 100644 index 0000000..472213d --- /dev/null +++ b/test/CodeGen/ARM/bswap-inline-asm.ll @@ -0,0 +1,9 @@ +; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6 | FileCheck %s + +define i32 @t1(i32 %x) nounwind { +; CHECK: t1: +; CHECK-NOT: InlineAsm +; CHECK: rev + %asmtmp = tail call i32 asm "rev $0, $1\0A", "=l,l"(i32 %x) nounwind + ret i32 %asmtmp +} diff --git a/test/CodeGen/ARM/bx_fold.ll b/test/CodeGen/ARM/bx_fold.ll index 0e3e070..09f1aae 100644 --- a/test/CodeGen/ARM/bx_fold.ll +++ b/test/CodeGen/ARM/bx_fold.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=arm -; RUN: llc < %s -march=arm | not grep bx +; RUN: llc < %s -mtriple=armv5t-apple-darwin | FileCheck %s define void @test(i32 %Ptr, i8* %L) { entry: @@ -24,6 +23,8 @@ bb1: ; preds = %bb, %entry br i1 %bothcond, label %bb, label %bb18 bb18: ; preds = %bb1 +; CHECK-NOT: bx +; CHECK: ldmia sp! ret void } diff --git a/test/CodeGen/ARM/call-tc.ll b/test/CodeGen/ARM/call-tc.ll index db5afe3..a77aba0 100644 --- a/test/CodeGen/ARM/call-tc.ll +++ b/test/CodeGen/ARM/call-tc.ll @@ -1,8 +1,6 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin -march=arm | FileCheck %s -check-prefix=CHECKV4 -; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin -mattr=+v5t | FileCheck %s -check-prefix=CHECKV5 -; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi\ -; RUN: -relocation-model=pic | FileCheck %s -check-prefix=CHECKELF -; XFAIL: * +; RUN: llc < %s -mtriple=armv6-apple-darwin -mattr=+vfp2 -arm-tail-calls | FileCheck %s -check-prefix=CHECKV6 +; RUN: llc < %s -mtriple=armv6-linux-gnueabi -relocation-model=pic -mattr=+vfp2 -arm-tail-calls | FileCheck %s -check-prefix=CHECKELF +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -arm-tail-calls | FileCheck %s -check-prefix=CHECKT2 @t = weak global i32 ()* null ; [#uses=1] @@ -10,40 +8,80 @@ declare void @g(i32, i32, i32, i32) define void @t1() { ; CHECKELF: t1: -; CHECKELF: PLT +; CHECKELF: bl g(PLT) call void @g( i32 1, i32 2, i32 3, i32 4 ) ret void } define void @t2() { -; CHECKV4: t2: -; CHECKV4: bx r0 @ TAILCALL -; CHECKV5: t2: -; CHECKV5: bx r0 @ TAILCALL +; CHECKV6: t2: +; CHECKV6: bx r0 @ TAILCALL %tmp = load i32 ()** @t ; [#uses=1] %tmp.upgrd.2 = tail call i32 %tmp( ) ; [#uses=0] ret void } -define i32* @t3(i32, i32, i32*, i32*, i32*) nounwind { -; CHECKV4: t3: -; CHECKV4: bx r{{.*}} -BB0: - %5 = inttoptr i32 %0 to i32* ; [#uses=1] - %t35 = volatile load i32* %5 ; [#uses=1] - %6 = inttoptr i32 %t35 to i32** ; [#uses=1] - %7 = getelementptr i32** %6, i32 86 ; [#uses=1] - %8 = load i32** %7 ; [#uses=1] - %9 = bitcast i32* %8 to i32* (i32, i32*, i32, i32*, i32*, i32*)* ; [#uses=1] - %10 = call i32* %9(i32 %0, i32* null, i32 %1, i32* %2, i32* %3, i32* %4) ; [#uses=1] - ret i32* %10 -} - -define void @t4() { -; CHECKV4: t4: -; CHECKV4: b _t2 @ TAILCALL -; CHECKV5: t4: -; CHECKV5: b _t2 @ TAILCALL +define void @t3() { +; CHECKV6: t3: +; CHECKV6: b _t2 @ TAILCALL +; CHECKELF: t3: +; CHECKELF: b t2(PLT) @ TAILCALL tail call void @t2( ) ; [#uses=0] ret void } + +; Sibcall optimization of expanded libcalls. rdar://8707777 +define double @t4(double %a) nounwind readonly ssp { +entry: +; CHECKV6: t4: +; CHECKV6: b _sin @ TAILCALL +; CHECKELF: t4: +; CHECKELF: b sin(PLT) @ TAILCALL + %0 = tail call double @sin(double %a) nounwind readonly ; [#uses=1] + ret double %0 +} + +define float @t5(float %a) nounwind readonly ssp { +entry: +; CHECKV6: t5: +; CHECKV6: b _sinf @ TAILCALL +; CHECKELF: t5: +; CHECKELF: b sinf(PLT) @ TAILCALL + %0 = tail call float @sinf(float %a) nounwind readonly ; [#uses=1] + ret float %0 +} + +declare float @sinf(float) nounwind readonly + +declare double @sin(double) nounwind readonly + +define i32 @t6(i32 %a, i32 %b) nounwind readnone { +entry: +; CHECKV6: t6: +; CHECKV6: b ___divsi3 @ TAILCALL +; CHECKELF: t6: +; CHECKELF: b __aeabi_idiv(PLT) @ TAILCALL + %0 = sdiv i32 %a, %b + ret i32 %0 +} + +; Make sure the tail call instruction isn't deleted +; rdar://8309338 +declare void @foo() nounwind + +define void @t7() nounwind { +entry: +; CHECKT2: t7: +; CHECKT2: blxeq _foo +; CHECKT2-NEXT: pop.w +; CHECKT2-NEXT: b.w _foo + br i1 undef, label %bb, label %bb1.lr.ph + +bb1.lr.ph: + tail call void @foo() nounwind + unreachable + +bb: + tail call void @foo() nounwind + ret void +} diff --git a/test/CodeGen/ARM/clz.ll b/test/CodeGen/ARM/clz.ll index d2235c9..e381e00 100644 --- a/test/CodeGen/ARM/clz.ll +++ b/test/CodeGen/ARM/clz.ll @@ -1,8 +1,10 @@ -; RUN: llc < %s -march=arm -mattr=+v5t | grep clz +; RUN: llc < %s -march=arm -mattr=+v5t | FileCheck %s declare i32 @llvm.ctlz.i32(i32) define i32 @test(i32 %x) { - %tmp.1 = call i32 @llvm.ctlz.i32( i32 %x ) ; [#uses=1] +; CHECK: test +; CHECK: clz r0, r0 + %tmp.1 = call i32 @llvm.ctlz.i32( i32 %x ) ret i32 %tmp.1 } diff --git a/test/CodeGen/ARM/code-placement.ll b/test/CodeGen/ARM/code-placement.ll index 25c5568..845be8c 100644 --- a/test/CodeGen/ARM/code-placement.ll +++ b/test/CodeGen/ARM/code-placement.ll @@ -1,12 +1,13 @@ -; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=armv7-apple-darwin -cgp-critical-edge-splitting=0 | FileCheck %s ; PHI elimination shouldn't break backedge. ; rdar://8263994 %struct.list_data_s = type { i16, i16 } %struct.list_head = type { %struct.list_head*, %struct.list_data_s* } -define arm_apcscc %struct.list_head* @t(%struct.list_head* %list) nounwind { +define arm_apcscc %struct.list_head* @t1(%struct.list_head* %list) nounwind { entry: +; CHECK: t1: %0 = icmp eq %struct.list_head* %list, null br i1 %0, label %bb2, label %bb @@ -27,3 +28,52 @@ bb2: %next.0.lcssa = phi %struct.list_head* [ null, %entry ], [ %list_addr.05, %bb ] ret %struct.list_head* %next.0.lcssa } + +; Optimize loop entry, eliminate intra loop branches +; rdar://8117827 +define i32 @t2(i32 %passes, i32* nocapture %src, i32 %size) nounwind readonly { +entry: +; CHECK: t2: +; CHECK: beq LBB1_[[RET:.]] + %0 = icmp eq i32 %passes, 0 ; [#uses=1] + br i1 %0, label %bb5, label %bb.nph15 + +; CHECK: LBB1_[[PREHDR:.]]: @ %bb2.preheader +bb1: ; preds = %bb2.preheader, %bb1 +; CHECK: LBB1_[[BB1:.]]: @ %bb1 +; CHECK: bne LBB1_[[BB1]] + %indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %bb2.preheader ] ; [#uses=2] + %sum.08 = phi i32 [ %2, %bb1 ], [ %sum.110, %bb2.preheader ] ; [#uses=1] + %tmp17 = sub i32 %i.07, %indvar ; [#uses=1] + %scevgep = getelementptr i32* %src, i32 %tmp17 ; [#uses=1] + %1 = load i32* %scevgep, align 4 ; [#uses=1] + %2 = add nsw i32 %1, %sum.08 ; [#uses=2] + %indvar.next = add i32 %indvar, 1 ; [#uses=2] + %exitcond = icmp eq i32 %indvar.next, %size ; [#uses=1] + br i1 %exitcond, label %bb3, label %bb1 + +bb3: ; preds = %bb1, %bb2.preheader +; CHECK: LBB1_[[BB3:.]]: @ %bb3 +; CHECK: bne LBB1_[[PREHDR]] +; CHECK-NOT: b LBB1_ + %sum.0.lcssa = phi i32 [ %sum.110, %bb2.preheader ], [ %2, %bb1 ] ; [#uses=2] + %3 = add i32 %pass.011, 1 ; [#uses=2] + %exitcond18 = icmp eq i32 %3, %passes ; [#uses=1] + br i1 %exitcond18, label %bb5, label %bb2.preheader + +bb.nph15: ; preds = %entry + %i.07 = add i32 %size, -1 ; [#uses=2] + %4 = icmp sgt i32 %i.07, -1 ; [#uses=1] + br label %bb2.preheader + +bb2.preheader: ; preds = %bb3, %bb.nph15 + %pass.011 = phi i32 [ 0, %bb.nph15 ], [ %3, %bb3 ] ; [#uses=1] + %sum.110 = phi i32 [ 0, %bb.nph15 ], [ %sum.0.lcssa, %bb3 ] ; [#uses=2] + br i1 %4, label %bb1, label %bb3 + +; CHECK: LBB1_[[RET]]: @ %bb5 +; CHECK: ldmia sp! +bb5: ; preds = %bb3, %entry + %sum.1.lcssa = phi i32 [ 0, %entry ], [ %sum.0.lcssa, %bb3 ] ; [#uses=1] + ret i32 %sum.1.lcssa +} diff --git a/test/CodeGen/ARM/constants.ll b/test/CodeGen/ARM/constants.ll index ce91936..542cf02 100644 --- a/test/CodeGen/ARM/constants.ll +++ b/test/CodeGen/ARM/constants.ll @@ -14,34 +14,33 @@ define i32 @f2() { define i32 @f3() { ; CHECK: f3 -; CHECK: mov r0{{.*}}256 +; CHECK: mov r0, #1, 24 ret i32 256 } define i32 @f4() { ; CHECK: f4 -; CHECK: orr{{.*}}256 +; CHECK: orr{{.*}}#1, 24 ret i32 257 } define i32 @f5() { ; CHECK: f5 -; CHECK: mov r0, {{.*}}-1073741761 +; CHECK: mov r0, #255, 2 ret i32 -1073741761 } define i32 @f6() { ; CHECK: f6 -; CHECK: mov r0, {{.*}}1008 +; CHECK: mov r0, #63, 28 ret i32 1008 } define void @f7(i32 %a) { ; CHECK: f7 ; CHECK: cmp r0, #1, 16 - %b = icmp ugt i32 %a, 65536 ; [#uses=1] + %b = icmp ugt i32 %a, 65536 br i1 %b, label %r, label %r - -r: ; preds = %0, %0 +r: ret void } diff --git a/test/CodeGen/ARM/crash.ll b/test/CodeGen/ARM/crash.ll new file mode 100644 index 0000000..4b6876d --- /dev/null +++ b/test/CodeGen/ARM/crash.ll @@ -0,0 +1,29 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 + +; +%struct.foo = type { i32, i32 } + +define void @func() nounwind { +entry: + %tmp = load i32* undef, align 4 + br label %bb1 + +bb1: + %tmp1 = and i32 %tmp, 16 + %tmp2 = icmp eq i32 %tmp1, 0 + %invok.1.i = select i1 %tmp2, i32 undef, i32 0 + %tmp119 = add i32 %invok.1.i, 0 + br i1 undef, label %bb2, label %exit + +bb2: + %tmp120 = add i32 %tmp119, 0 + %scevgep810.i = getelementptr %struct.foo* null, i32 %tmp120, i32 1 + store i32 undef, i32* %scevgep810.i, align 4 + br i1 undef, label %bb2, label %bb3 + +bb3: + br i1 %tmp2, label %bb2, label %bb2 + +exit: + ret void +} diff --git a/test/CodeGen/ARM/div.ll b/test/CodeGen/ARM/div.ll index 448b437..3d29e05 100644 --- a/test/CodeGen/ARM/div.ll +++ b/test/CodeGen/ARM/div.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=CHECK-ARM +; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=CHECK-ARM define i32 @f1(i32 %a, i32 %b) { entry: diff --git a/test/CodeGen/ARM/fabss.ll b/test/CodeGen/ARM/fabss.ll index dfc1e0a..f03282b 100644 --- a/test/CodeGen/ARM/fabss.ll +++ b/test/CodeGen/ARM/fabss.ll @@ -24,4 +24,4 @@ declare float @fabsf(float) ; CORTEXA8: test: ; CORTEXA8: vabs.f32 d1, d1 ; CORTEXA9: test: -; CORTEXA9: vabs.f32 s0, s0 +; CORTEXA9: vabs.f32 s1, s1 diff --git a/test/CodeGen/ARM/fadds.ll b/test/CodeGen/ARM/fadds.ll index 113f0e2..749690e 100644 --- a/test/CodeGen/ARM/fadds.ll +++ b/test/CodeGen/ARM/fadds.ll @@ -20,4 +20,4 @@ entry: ; CORTEXA8: test: ; CORTEXA8: vadd.f32 d0, d1, d0 ; CORTEXA9: test: -; CORTEXA9: vadd.f32 s0, s0, s1 +; CORTEXA9: vadd.f32 s0, s1, s0 diff --git a/test/CodeGen/ARM/fast-isel-crash.ll b/test/CodeGen/ARM/fast-isel-crash.ll new file mode 100644 index 0000000..370c70f --- /dev/null +++ b/test/CodeGen/ARM/fast-isel-crash.ll @@ -0,0 +1,21 @@ +; RUN: llc < %s -O0 -mtriple=thumbv7-apple-darwin + +%union.anon = type { <16 x i32> } + +@__md0 = external global [137 x i8] + +define internal void @stretch(<4 x i8> addrspace(1)* %src, <4 x i8> addrspace(1)* %dst, i32 %width, i32 %height, i32 %iLS, i32 %oLS, <2 x float> %c, <4 x float> %param) nounwind { +entry: + ret void +} + +define internal i32 @_Z13get_global_idj(i32 %dim) nounwind ssp { +entry: + ret i32 undef +} + +define void @wrap(i8 addrspace(1)* addrspace(1)* %arglist, i32 addrspace(1)* %gtid) nounwind ssp { +entry: + call void @stretch(<4 x i8> addrspace(1)* undef, <4 x i8> addrspace(1)* undef, i32 undef, i32 undef, i32 undef, i32 undef, <2 x float> undef, <4 x float> undef) + ret void +} diff --git a/test/CodeGen/ARM/fast-isel-static.ll b/test/CodeGen/ARM/fast-isel-static.ll new file mode 100644 index 0000000..8f58480 --- /dev/null +++ b/test/CodeGen/ARM/fast-isel-static.ll @@ -0,0 +1,30 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -relocation-model=static -arm-long-calls | FileCheck -check-prefix=LONG %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -relocation-model=static | FileCheck -check-prefix=NORM %s + +define void @myadd(float* %sum, float* %addend) nounwind { +entry: + %sum.addr = alloca float*, align 4 + %addend.addr = alloca float*, align 4 + store float* %sum, float** %sum.addr, align 4 + store float* %addend, float** %addend.addr, align 4 + %tmp = load float** %sum.addr, align 4 + %tmp1 = load float* %tmp + %tmp2 = load float** %addend.addr, align 4 + %tmp3 = load float* %tmp2 + %add = fadd float %tmp1, %tmp3 + %tmp4 = load float** %sum.addr, align 4 + store float %add, float* %tmp4 + ret void +} + +define i32 @main(i32 %argc, i8** %argv) nounwind { +entry: + %ztot = alloca float, align 4 + %z = alloca float, align 4 + store float 0.000000e+00, float* %ztot, align 4 + store float 1.000000e+00, float* %z, align 4 +; CHECK-LONG: blx r2 +; CHECK-NORM: blx _myadd + call void @myadd(float* %ztot, float* %z) + ret i32 0 +} diff --git a/test/CodeGen/ARM/fast-isel.ll b/test/CodeGen/ARM/fast-isel.ll index 3bee84d..dd806ec 100644 --- a/test/CodeGen/ARM/fast-isel.ll +++ b/test/CodeGen/ARM/fast-isel.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -O0 -arm-fast-isel -fast-isel-abort -mtriple=armv7-apple-darwin -; RUN: llc < %s -O0 -arm-fast-isel -fast-isel-abort -mtriple=thumbv7-apple-darwin +; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-apple-darwin +; RUN: llc < %s -O0 -fast-isel-abort -mtriple=thumbv7-apple-darwin ; Very basic fast-isel functionality. -define i32 @add(i32 %a, i32 %b) nounwind ssp { +define i32 @add(i32 %a, i32 %b) nounwind { entry: %a.addr = alloca i32, align 4 %b.addr = alloca i32, align 4 @@ -13,27 +13,4 @@ entry: %tmp1 = load i32* %b.addr %add = add nsw i32 %tmp, %tmp1 ret i32 %add -} - -define i32* @foo(i32* %p, i32* %q, i32** %z) nounwind { -entry: - %r = load i32* %p - %s = load i32* %q - %y = load i32** %z - br label %fast - -fast: - %t0 = add i32 %r, %s - %t1 = mul i32 %t0, %s - %t2 = sub i32 %t1, %s - %t3 = and i32 %t2, %s - %t4 = xor i32 %t3, 3 - %t5 = xor i32 %t4, %s - %t6 = add i32 %t5, 2 - %t7 = getelementptr i32* %y, i32 1 - %t8 = getelementptr i32* %t7, i32 %t6 - br label %exit - -exit: - ret i32* %t8 -} +} \ No newline at end of file diff --git a/test/CodeGen/ARM/fcopysign.ll b/test/CodeGen/ARM/fcopysign.ll index a6d7410..1050cd2 100644 --- a/test/CodeGen/ARM/fcopysign.ll +++ b/test/CodeGen/ARM/fcopysign.ll @@ -1,18 +1,45 @@ -; RUN: llc < %s -march=arm | grep bic | count 2 -; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | \ -; RUN: grep vneg | count 2 +; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=SOFT +; RUN: llc < %s -mtriple=armv7-gnueabi -float-abi=hard -mcpu=cortex-a8 | FileCheck %s -check-prefix=HARD -define float @test1(float %x, double %y) { - %tmp = fpext float %x to double - %tmp2 = tail call double @copysign( double %tmp, double %y ) - %tmp3 = fptrunc double %tmp2 to float - ret float %tmp3 +; rdar://8984306 +define float @test1(float %x, float %y) nounwind { +entry: +; SOFT: test1: +; SOFT: lsr r1, r1, #31 +; SOFT: bfi r0, r1, #31, #1 + +; HARD: test1: +; HARD: vabs.f32 d0, d0 +; HARD: cmp r0, #0 +; HARD: vneglt.f32 s0, s0 + %0 = tail call float @copysignf(float %x, float %y) nounwind + ret float %0 +} + +define double @test2(double %x, double %y) nounwind { +entry: +; SOFT: test2: +; SOFT: lsr r2, r3, #31 +; SOFT: bfi r1, r2, #31, #1 + +; HARD: test2: +; HARD: vabs.f64 d0, d0 +; HARD: cmp r1, #0 +; HARD: vneglt.f64 d0, d0 + %0 = tail call double @copysign(double %x, double %y) nounwind + ret double %0 } -define double @test2(double %x, float %y) { - %tmp = fpext float %y to double - %tmp2 = tail call double @copysign( double %x, double %tmp ) - ret double %tmp2 +define double @test3(double %x, double %y, double %z) nounwind { +entry: +; SOFT: test3: +; SOFT: vabs.f64 +; SOFT: cmp {{.*}}, #0 +; SOFT: vneglt.f64 + %0 = fmul double %x, %y + %1 = tail call double @copysign(double %0, double %z) nounwind + ret double %1 } -declare double @copysign(double, double) +declare double @copysign(double, double) nounwind +declare float @copysignf(float, float) nounwind diff --git a/test/CodeGen/ARM/fdivs.ll b/test/CodeGen/ARM/fdivs.ll index 9af1217..0c31495 100644 --- a/test/CodeGen/ARM/fdivs.ll +++ b/test/CodeGen/ARM/fdivs.ll @@ -20,4 +20,4 @@ entry: ; CORTEXA8: test: ; CORTEXA8: vdiv.f32 s0, s1, s0 ; CORTEXA9: test: -; CORTEXA9: vdiv.f32 s0, s0, s1 +; CORTEXA9: vdiv.f32 s0, s1, s0 diff --git a/test/CodeGen/ARM/fmacs.ll b/test/CodeGen/ARM/fmacs.ll index c4ceca9..fb83ef6 100644 --- a/test/CodeGen/ARM/fmacs.ll +++ b/test/CodeGen/ARM/fmacs.ll @@ -1,24 +1,51 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8 -define float @test(float %acc, float %a, float %b) { +define float @t1(float %acc, float %a, float %b) { entry: +; VFP2: t1: +; VFP2: vmla.f32 + +; NEON: t1: +; NEON: vmla.f32 + +; A8: t1: +; A8: vmul.f32 +; A8: vadd.f32 %0 = fmul float %a, %b %1 = fadd float %acc, %0 ret float %1 } -; VFP2: test: -; VFP2: vmla.f32 s2, s1, s0 +define double @t2(double %acc, double %a, double %b) { +entry: +; VFP2: t2: +; VFP2: vmla.f64 + +; NEON: t2: +; NEON: vmla.f64 -; NFP1: test: -; NFP1: vmul.f32 d0, d1, d0 -; NFP0: test: -; NFP0: vmla.f32 s2, s1, s0 +; A8: t2: +; A8: vmul.f64 +; A8: vadd.f64 + %0 = fmul double %a, %b + %1 = fadd double %acc, %0 + ret double %1 +} -; CORTEXA8: test: -; CORTEXA8: vmul.f32 d0, d1, d0 -; CORTEXA9: test: -; CORTEXA9: vmla.f32 s0, s1, s2 +define float @t3(float %acc, float %a, float %b) { +entry: +; VFP2: t3: +; VFP2: vmla.f32 + +; NEON: t3: +; NEON: vmla.f32 + +; A8: t3: +; A8: vmul.f32 +; A8: vadd.f32 + %0 = fmul float %a, %b + %1 = fadd float %0, %acc + ret float %1 +} diff --git a/test/CodeGen/ARM/fmscs.ll b/test/CodeGen/ARM/fmscs.ll index 103ce33..a182833 100644 --- a/test/CodeGen/ARM/fmscs.ll +++ b/test/CodeGen/ARM/fmscs.ll @@ -1,24 +1,35 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8 -define float @test(float %acc, float %a, float %b) { +define float @t1(float %acc, float %a, float %b) { entry: +; VFP2: t1: +; VFP2: vnmls.f32 + +; NEON: t1: +; NEON: vnmls.f32 + +; A8: t1: +; A8: vmul.f32 +; A8: vsub.f32 %0 = fmul float %a, %b %1 = fsub float %0, %acc ret float %1 } -; VFP2: test: -; VFP2: vnmls.f32 s2, s1, s0 +define double @t2(double %acc, double %a, double %b) { +entry: +; VFP2: t2: +; VFP2: vnmls.f64 -; NFP1: test: -; NFP1: vnmls.f32 s2, s1, s0 -; NFP0: test: -; NFP0: vnmls.f32 s2, s1, s0 +; NEON: t2: +; NEON: vnmls.f64 -; CORTEXA8: test: -; CORTEXA8: vnmls.f32 s2, s1, s0 -; CORTEXA9: test: -; CORTEXA9: vnmls.f32 s0, s1, s2 +; A8: t2: +; A8: vmul.f64 +; A8: vsub.f64 + %0 = fmul double %a, %b + %1 = fsub double %0, %acc + ret double %1 +} diff --git a/test/CodeGen/ARM/fmuls.ll b/test/CodeGen/ARM/fmuls.ll index bfafd20..ef4e3e5 100644 --- a/test/CodeGen/ARM/fmuls.ll +++ b/test/CodeGen/ARM/fmuls.ll @@ -20,4 +20,4 @@ entry: ; CORTEXA8: test: ; CORTEXA8: vmul.f32 d0, d1, d0 ; CORTEXA9: test: -; CORTEXA9: vmul.f32 s0, s0, s1 +; CORTEXA9: vmul.f32 s0, s1, s0 diff --git a/test/CodeGen/ARM/fnegs.ll b/test/CodeGen/ARM/fnegs.ll index c15005e..418b598 100644 --- a/test/CodeGen/ARM/fnegs.ll +++ b/test/CodeGen/ARM/fnegs.ll @@ -13,19 +13,19 @@ entry: ret float %retval } ; VFP2: test1: -; VFP2: vneg.f32 s1, s0 +; VFP2: vneg.f32 s{{.*}}, s{{.*}} ; NFP1: test1: -; NFP1: vneg.f32 d1, d0 +; NFP1: vneg.f32 d{{.*}}, d{{.*}} ; NFP0: test1: -; NFP0: vneg.f32 s1, s0 +; NFP0: vneg.f32 s{{.*}}, s{{.*}} ; CORTEXA8: test1: -; CORTEXA8: vneg.f32 d1, d0 +; CORTEXA8: vneg.f32 d{{.*}}, d{{.*}} ; CORTEXA9: test1: -; CORTEXA9: vneg.f32 s1, s0 +; CORTEXA9: vneg.f32 s{{.*}}, s{{.*}} define float @test2(float* %a) { entry: @@ -37,17 +37,17 @@ entry: ret float %retval } ; VFP2: test2: -; VFP2: vneg.f32 s1, s0 +; VFP2: vneg.f32 s{{.*}}, s{{.*}} ; NFP1: test2: -; NFP1: vneg.f32 d1, d0 +; NFP1: vneg.f32 d{{.*}}, d{{.*}} ; NFP0: test2: -; NFP0: vneg.f32 s1, s0 +; NFP0: vneg.f32 s{{.*}}, s{{.*}} ; CORTEXA8: test2: -; CORTEXA8: vneg.f32 d1, d0 +; CORTEXA8: vneg.f32 d{{.*}}, d{{.*}} ; CORTEXA9: test2: -; CORTEXA9: vneg.f32 s1, s0 +; CORTEXA9: vneg.f32 s{{.*}}, s{{.*}} diff --git a/test/CodeGen/ARM/fnmacs.ll b/test/CodeGen/ARM/fnmacs.ll index 1d1d06a..1763d46 100644 --- a/test/CodeGen/ARM/fnmacs.ll +++ b/test/CodeGen/ARM/fnmacs.ll @@ -1,20 +1,35 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=NEONFP +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8 -define float @test(float %acc, float %a, float %b) { +define float @t1(float %acc, float %a, float %b) { entry: +; VFP2: t1: ; VFP2: vmls.f32 -; NEON: vmls.f32 -; NEONFP-NOT: vmls -; NEONFP-NOT: vmov.f32 -; NEONFP: vmul.f32 -; NEONFP: vsub.f32 -; NEONFP: vmov +; NEON: t1: +; NEON: vmls.f32 +; A8: t1: +; A8: vmul.f32 +; A8: vsub.f32 %0 = fmul float %a, %b %1 = fsub float %acc, %0 ret float %1 } +define double @t2(double %acc, double %a, double %b) { +entry: +; VFP2: t2: +; VFP2: vmls.f64 + +; NEON: t2: +; NEON: vmls.f64 + +; A8: t2: +; A8: vmul.f64 +; A8: vsub.f64 + %0 = fmul double %a, %b + %1 = fsub double %acc, %0 + ret double %1 +} diff --git a/test/CodeGen/ARM/fnmscs.ll b/test/CodeGen/ARM/fnmscs.ll index 0b47edd..76c8067 100644 --- a/test/CodeGen/ARM/fnmscs.ll +++ b/test/CodeGen/ARM/fnmscs.ll @@ -1,23 +1,71 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8 -define float @test1(float %acc, float %a, float %b) nounwind { -; CHECK: vnmla.f32 s{{.*}}, s{{.*}}, s{{.*}} +define float @t1(float %acc, float %a, float %b) nounwind { entry: +; VFP2: t1: +; VFP2: vnmla.f32 + +; NEON: t1: +; NEON: vnmla.f32 + +; A8: t1: +; A8: vnmul.f32 s0, s{{[01]}}, s{{[01]}} +; A8: vsub.f32 d0, d0, d1 %0 = fmul float %a, %b %1 = fsub float -0.0, %0 %2 = fsub float %1, %acc ret float %2 } -define float @test2(float %acc, float %a, float %b) nounwind { -; CHECK: vnmla.f32 s{{.*}}, s{{.*}}, s{{.*}} +define float @t2(float %acc, float %a, float %b) nounwind { entry: +; VFP2: t2: +; VFP2: vnmla.f32 + +; NEON: t2: +; NEON: vnmla.f32 + +; A8: t2: +; A8: vnmul.f32 s0, s{{[01]}}, s{{[01]}} +; A8: vsub.f32 d0, d0, d1 %0 = fmul float %a, %b %1 = fmul float -1.0, %0 %2 = fsub float %1, %acc ret float %2 } +define double @t3(double %acc, double %a, double %b) nounwind { +entry: +; VFP2: t3: +; VFP2: vnmla.f64 + +; NEON: t3: +; NEON: vnmla.f64 + +; A8: t3: +; A8: vnmul.f64 d16, d1{{[67]}}, d1{{[67]}} +; A8: vsub.f64 d16, d16, d17 + %0 = fmul double %a, %b + %1 = fsub double -0.0, %0 + %2 = fsub double %1, %acc + ret double %2 +} + +define double @t4(double %acc, double %a, double %b) nounwind { +entry: +; VFP2: t4: +; VFP2: vnmla.f64 + +; NEON: t4: +; NEON: vnmla.f64 + +; A8: t4: +; A8: vnmul.f64 d16, d1{{[67]}}, d1{{[67]}} +; A8: vsub.f64 d16, d16, d17 + %0 = fmul double %a, %b + %1 = fmul double -1.0, %0 + %2 = fsub double %1, %acc + ret double %2 +} diff --git a/test/CodeGen/ARM/fp.ll b/test/CodeGen/ARM/fp.ll index 8fbd45b..b6e9c3c 100644 --- a/test/CodeGen/ARM/fp.ll +++ b/test/CodeGen/ARM/fp.ll @@ -51,7 +51,7 @@ entry: define float @h2() { ;CHECK: h2: -;CHECK: 1065353216 +;CHECK: mov r0, #254, 10 entry: ret float 1.000000e+00 } diff --git a/test/CodeGen/ARM/fpcmp-opt.ll b/test/CodeGen/ARM/fpcmp-opt.ll index 6435059..65b921b 100644 --- a/test/CodeGen/ARM/fpcmp-opt.ll +++ b/test/CodeGen/ARM/fpcmp-opt.ll @@ -38,6 +38,7 @@ entry: ; FINITE: t2: ; FINITE-NOT: vldr ; FINITE: ldrd r0, [r0] +; FINITE-NOT: b LBB ; FINITE: cmp r0, #0 ; FINITE: cmpeq r1, #0 ; FINITE-NOT: vcmpe.f32 diff --git a/test/CodeGen/ARM/fpcmp_ueq.ll b/test/CodeGen/ARM/fpcmp_ueq.ll index 67f70e9..2e6b3e3 100644 --- a/test/CodeGen/ARM/fpcmp_ueq.ll +++ b/test/CodeGen/ARM/fpcmp_ueq.ll @@ -1,8 +1,14 @@ -; RUN: llc < %s -march=arm | grep moveq -; RUN: llc < %s -march=arm -mattr=+vfp2 | grep movvs +; RUN: llc < %s -mtriple=arm-apple-darwin | grep moveq +; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s define i32 @f7(float %a, float %b) { entry: +; CHECK: f7: +; CHECK: vcmpe.f32 +; CHECK: vmrs apsr_nzcv, fpscr +; CHECK: movweq +; CHECK-NOT: vmrs +; CHECK: movwvs %tmp = fcmp ueq float %a,%b %retval = select i1 %tmp, i32 666, i32 42 ret i32 %retval diff --git a/test/CodeGen/ARM/fpconsts.ll b/test/CodeGen/ARM/fpconsts.ll index f1d6a16..638dde9 100644 --- a/test/CodeGen/ARM/fpconsts.ll +++ b/test/CodeGen/ARM/fpconsts.ll @@ -3,7 +3,7 @@ define float @t1(float %x) nounwind readnone optsize { entry: ; CHECK: t1: -; CHECK: vmov.f32 s1, #4.000000e+00 +; CHECK: vmov.f32 s{{.*}}, #4.000000e+00 %0 = fadd float %x, 4.000000e+00 ret float %0 } @@ -11,7 +11,7 @@ entry: define double @t2(double %x) nounwind readnone optsize { entry: ; CHECK: t2: -; CHECK: vmov.f64 d1, #3.000000e+00 +; CHECK: vmov.f64 d{{.*}}, #3.000000e+00 %0 = fadd double %x, 3.000000e+00 ret double %0 } @@ -19,7 +19,7 @@ entry: define double @t3(double %x) nounwind readnone optsize { entry: ; CHECK: t3: -; CHECK: vmov.f64 d1, #-1.300000e+01 +; CHECK: vmov.f64 d{{.*}}, #-1.300000e+01 %0 = fmul double %x, -1.300000e+01 ret double %0 } @@ -27,7 +27,7 @@ entry: define float @t4(float %x) nounwind readnone optsize { entry: ; CHECK: t4: -; CHECK: vmov.f32 s1, #-2.400000e+01 +; CHECK: vmov.f32 s{{.*}}, #-2.400000e+01 %0 = fmul float %x, -2.400000e+01 ret float %0 } diff --git a/test/CodeGen/ARM/fpconv.ll b/test/CodeGen/ARM/fpconv.ll index bf197a4..1b4c008b 100644 --- a/test/CodeGen/ARM/fpconv.ll +++ b/test/CodeGen/ARM/fpconv.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s --check-prefix=CHECK-VFP -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s define float @f1(double %x) { ;CHECK-VFP: f1: diff --git a/test/CodeGen/ARM/global-merge.ll b/test/CodeGen/ARM/global-merge.ll new file mode 100644 index 0000000..28bf221 --- /dev/null +++ b/test/CodeGen/ARM/global-merge.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s +; Test the ARMGlobalMerge pass. Use -march=thumb because it has a small +; value for the maximum offset (127). + +; A local array that exceeds the maximum offset should not be merged. +; CHECK: g0: +@g0 = internal global [32 x i32] [ i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 1, i32 2 ] + +; CHECK: _MergedGlobals: +@g1 = internal global i32 1 +@g2 = internal global i32 2 + +; Make sure that the complete variable fits within the range of the maximum +; offset. Having the starting offset in range is not sufficient. +; When this works properly, @g3 is placed in a separate chunk of merged globals. +; CHECK: _MergedGlobals1: +@g3 = internal global [30 x i32] [ i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10 ] + +; Global variables that can be placed in BSS should be kept together in a +; separate pool of merged globals. +; CHECK: _MergedGlobals2 +@g4 = internal global i32 0 +@g5 = internal global i32 0 diff --git a/test/CodeGen/ARM/hello.ll b/test/CodeGen/ARM/hello.ll index ccdc7bf..bfed7a6 100644 --- a/test/CodeGen/ARM/hello.ll +++ b/test/CodeGen/ARM/hello.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm ; RUN: llc < %s -mtriple=arm-linux-gnueabi | grep mov | count 1 ; RUN: llc < %s -mtriple=arm-linux-gnu --disable-fp-elim | \ -; RUN: grep mov | count 3 +; RUN: grep mov | count 2 ; RUN: llc < %s -mtriple=arm-apple-darwin | grep mov | count 2 @str = internal constant [12 x i8] c"Hello World\00" diff --git a/test/CodeGen/ARM/ifcvt10.ll b/test/CodeGen/ARM/ifcvt10.ll new file mode 100644 index 0000000..75428ac --- /dev/null +++ b/test/CodeGen/ARM/ifcvt10.ll @@ -0,0 +1,43 @@ +; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a9 | FileCheck %s +; rdar://8402126 +; Make sure if-converter is not predicating vldmia and ldmia. These are +; micro-coded and would have long issue latency even if predicated on +; false predicate. + +define void @t(double %a, double %b, double %c, double %d, i32* nocapture %solutions, double* nocapture %x) nounwind { +entry: +; CHECK: t: +; CHECK: vpop {d8} +; CHECK-NOT: vpopne +; CHECK: ldmia sp!, {r7, pc} +; CHECK: vpop {d8} +; CHECK: ldmia sp!, {r7, pc} + br i1 undef, label %if.else, label %if.then + +if.then: ; preds = %entry + %mul73 = fmul double undef, 0.000000e+00 + %sub76 = fsub double %mul73, undef + store double %sub76, double* undef, align 4 + %call88 = tail call double @cos(double 0.000000e+00) nounwind + %mul89 = fmul double undef, %call88 + %sub92 = fsub double %mul89, undef + store double %sub92, double* undef, align 4 + ret void + +if.else: ; preds = %entry + %tmp101 = tail call double @llvm.pow.f64(double undef, double 0x3FD5555555555555) + %add112 = fadd double %tmp101, undef + %mul118 = fmul double %add112, undef + store double 0.000000e+00, double* %x, align 4 + ret void +} + +declare double @acos(double) + +declare double @sqrt(double) readnone + +declare double @cos(double) readnone + +declare double @fabs(double) + +declare double @llvm.pow.f64(double, double) nounwind readonly diff --git a/test/CodeGen/ARM/ifcvt11.ll b/test/CodeGen/ARM/ifcvt11.ll new file mode 100644 index 0000000..63f8557 --- /dev/null +++ b/test/CodeGen/ARM/ifcvt11.ll @@ -0,0 +1,59 @@ +; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 | FileCheck %s +; rdar://8598427 +; Adjust if-converter heuristics to avoid predicating vmrs which can cause +; significant regression. + +%struct.xyz_t = type { double, double, double } + +define i32 @effie(i32 %tsets, %struct.xyz_t* nocapture %p, i32 %a, i32 %b, i32 %c) nounwind readonly noinline { +; CHECK: effie: +entry: + %0 = icmp sgt i32 %tsets, 0 + br i1 %0, label %bb.nph, label %bb6 + +bb.nph: ; preds = %entry + %1 = add nsw i32 %b, %a + %2 = add nsw i32 %1, %c + br label %bb + +bb: ; preds = %bb4, %bb.nph +; CHECK: vcmpe.f64 +; CHECK: vmrs apsr_nzcv, fpscr + %r.19 = phi i32 [ 0, %bb.nph ], [ %r.0, %bb4 ] + %n.08 = phi i32 [ 0, %bb.nph ], [ %10, %bb4 ] + %scevgep10 = getelementptr inbounds %struct.xyz_t* %p, i32 %n.08, i32 0 + %scevgep11 = getelementptr %struct.xyz_t* %p, i32 %n.08, i32 1 + %3 = load double* %scevgep10, align 4 + %4 = load double* %scevgep11, align 4 + %5 = fcmp uge double %3, %4 + br i1 %5, label %bb3, label %bb1 + +bb1: ; preds = %bb +; CHECK-NOT: it +; CHECK-NOT: vcmpemi +; CHECK-NOT: vmrsmi +; CHECK: vcmpe.f64 +; CHECK: vmrs apsr_nzcv, fpscr + %scevgep12 = getelementptr %struct.xyz_t* %p, i32 %n.08, i32 2 + %6 = load double* %scevgep12, align 4 + %7 = fcmp uge double %3, %6 + br i1 %7, label %bb3, label %bb2 + +bb2: ; preds = %bb1 + %8 = add nsw i32 %2, %r.19 + br label %bb4 + +bb3: ; preds = %bb1, %bb + %9 = add nsw i32 %r.19, 1 + br label %bb4 + +bb4: ; preds = %bb3, %bb2 + %r.0 = phi i32 [ %9, %bb3 ], [ %8, %bb2 ] + %10 = add nsw i32 %n.08, 1 + %exitcond = icmp eq i32 %10, %tsets + br i1 %exitcond, label %bb6, label %bb + +bb6: ; preds = %bb4, %entry + %r.1.lcssa = phi i32 [ 0, %entry ], [ %r.0, %bb4 ] + ret i32 %r.1.lcssa +} diff --git a/test/CodeGen/ARM/ifcvt6.ll b/test/CodeGen/ARM/ifcvt6.ll index e2c0ba3..5edf32f 100644 --- a/test/CodeGen/ARM/ifcvt6.ll +++ b/test/CodeGen/ARM/ifcvt6.ll @@ -1,10 +1,9 @@ -; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \ -; RUN: grep cmpne | count 1 -; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \ -; RUN: grep ldmiahi | count 1 +; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s define void @foo(i32 %X, i32 %Y) { entry: +; CHECK: cmpne +; CHECK: ldmiahi sp! %tmp1 = icmp ult i32 %X, 4 ; [#uses=1] %tmp4 = icmp eq i32 %Y, 0 ; [#uses=1] %tmp7 = or i1 %tmp4, %tmp1 ; [#uses=1] diff --git a/test/CodeGen/ARM/ifcvt7.ll b/test/CodeGen/ARM/ifcvt7.ll index eb97085..62e1355 100644 --- a/test/CodeGen/ARM/ifcvt7.ll +++ b/test/CodeGen/ARM/ifcvt7.ll @@ -1,14 +1,12 @@ -; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \ -; RUN: grep cmpeq | count 1 -; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \ -; RUN: grep moveq | count 1 -; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \ -; RUN: grep ldmiaeq | count 1 +; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s ; FIXME: Need post-ifcvt branch folding to get rid of the extra br at end of BB1. %struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* } define fastcc i32 @CountTree(%struct.quad_struct* %tree) { +; CHECK: cmpeq +; CHECK: moveq +; CHECK: ldmiaeq sp! entry: br label %tailrecurse diff --git a/test/CodeGen/ARM/ifcvt8.ll b/test/CodeGen/ARM/ifcvt8.ll index 1e39060..5fdfc4e 100644 --- a/test/CodeGen/ARM/ifcvt8.ll +++ b/test/CodeGen/ARM/ifcvt8.ll @@ -1,11 +1,11 @@ -; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \ -; RUN: grep ldmiane | count 1 +; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s %struct.SString = type { i8*, i32, i32 } declare void @abort() define fastcc void @t(%struct.SString* %word, i8 signext %c) { +; CHECK: ldmiane sp! entry: %tmp1 = icmp eq %struct.SString* %word, null ; [#uses=1] br i1 %tmp1, label %cond_true, label %cond_false diff --git a/test/CodeGen/ARM/inlineasm3.ll b/test/CodeGen/ARM/inlineasm3.ll index 687e138..9f77ad1 100644 --- a/test/CodeGen/ARM/inlineasm3.ll +++ b/test/CodeGen/ARM/inlineasm3.ll @@ -7,7 +7,7 @@ define void @t() nounwind { entry: ; CHECK: vmov.I64 q15, #0 ; CHECK: vmov.32 d30[0], r0 -; CHECK: vmov q0, q15 +; CHECK: vmov q8, q15 %tmp = alloca %struct.int32x4_t, align 16 call void asm sideeffect "vmov.I64 q15, #0\0Avmov.32 d30[0], $1\0Avmov ${0:q}, q15\0A", "=*w,r,~{d31},~{d30}"(%struct.int32x4_t* %tmp, i32 8192) nounwind ret void @@ -18,7 +18,7 @@ entry: define void @t2() nounwind { entry: -; CHECK: vmov d30, d0 +; CHECK: vmov d30, d16 ; CHECK: vmov.32 r0, d30[0] %asmtmp2 = tail call i32 asm sideeffect "vmov d30, $1\0Avmov.32 $0, d30[0]\0A", "=r,w,~{d30}"(<2 x i32> undef) nounwind ret void diff --git a/test/CodeGen/ARM/ispositive.ll b/test/CodeGen/ARM/ispositive.ll index 245ed51..2f1a2cf 100644 --- a/test/CodeGen/ARM/ispositive.ll +++ b/test/CodeGen/ARM/ispositive.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm | FileCheck %s define i32 @test1(i32 %X) { -; CHECK: mov r0, r0, lsr #31 +; CHECK: lsr{{.*}}#31 entry: icmp slt i32 %X, 0 ; :0 [#uses=1] zext i1 %0 to i32 ; :1 [#uses=1] diff --git a/test/CodeGen/ARM/ldm.ll b/test/CodeGen/ARM/ldm.ll index 78201a6..2f1b85e 100644 --- a/test/CodeGen/ARM/ldm.ll +++ b/test/CodeGen/ARM/ldm.ll @@ -1,10 +1,13 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=armv4t-apple-darwin | FileCheck %s -check-prefix=V4T @X = external global [0 x i32] ; <[0 x i32]*> [#uses=5] define i32 @t1() { ; CHECK: t1: ; CHECK: ldmia +; V4T: t1: +; V4T: ldmia %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0) ; [#uses=1] %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; [#uses=1] %tmp4 = tail call i32 @f1( i32 %tmp, i32 %tmp3 ) ; [#uses=1] @@ -14,6 +17,8 @@ define i32 @t1() { define i32 @t2() { ; CHECK: t2: ; CHECK: ldmia +; V4T: t2: +; V4T: ldmia %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; [#uses=1] %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; [#uses=1] %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 4) ; [#uses=1] @@ -25,6 +30,10 @@ define i32 @t3() { ; CHECK: t3: ; CHECK: ldmib ; CHECK: ldmia sp! +; V4T: t3: +; V4T: ldmib +; V4T: pop +; V4T-NEXT: bx lr %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; [#uses=1] %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; [#uses=1] %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; [#uses=1] diff --git a/test/CodeGen/ARM/ldst-f32-2-i32.ll b/test/CodeGen/ARM/ldst-f32-2-i32.ll new file mode 100644 index 0000000..2d016f6 --- /dev/null +++ b/test/CodeGen/ARM/ldst-f32-2-i32.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s +; Check if the f32 load / store pair are optimized to i32 load / store. +; rdar://8944252 + +define void @t(i32 %width, float* nocapture %src, float* nocapture %dst, i32 %index) nounwind { +; CHECK: t: +entry: + %src6 = bitcast float* %src to i8* + %0 = icmp eq i32 %width, 0 + br i1 %0, label %return, label %bb + +bb: +; CHECK: ldr [[REGISTER:(r[0-9]+)]], [r1], r3 +; CHECK: str [[REGISTER]], [r2], #4 + %j.05 = phi i32 [ %2, %bb ], [ 0, %entry ] + %tmp = mul i32 %j.05, %index + %uglygep = getelementptr i8* %src6, i32 %tmp + %src_addr.04 = bitcast i8* %uglygep to float* + %dst_addr.03 = getelementptr float* %dst, i32 %j.05 + %1 = load float* %src_addr.04, align 4 + store float %1, float* %dst_addr.03, align 4 + %2 = add i32 %j.05, 1 + %exitcond = icmp eq i32 %2, %width + br i1 %exitcond, label %return, label %bb + +return: + ret void +} diff --git a/test/CodeGen/ARM/load-global.ll b/test/CodeGen/ARM/load-global.ll new file mode 100644 index 0000000..15a415d --- /dev/null +++ b/test/CodeGen/ARM/load-global.ll @@ -0,0 +1,50 @@ +; RUN: llc < %s -mtriple=armv6-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=STATIC +; RUN: llc < %s -mtriple=armv6-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DYNAMIC +; RUN: llc < %s -mtriple=armv6-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=PIC +; RUN: llc < %s -mtriple=thumbv6-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=PIC_T +; RUN: llc < %s -mtriple=armv7-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=PIC_V7 +; RUN: llc < %s -mtriple=armv6-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LINUX + +@G = external global i32 + +define i32 @test1() { +; STATIC: _test1: +; STATIC: ldr r0, LCPI0_0 +; STATIC: ldr r0, [r0] +; STATIC: .long _G + +; DYNAMIC: _test1: +; DYNAMIC: ldr r0, LCPI0_0 +; DYNAMIC: ldr r0, [r0] +; DYNAMIC: ldr r0, [r0] +; DYNAMIC: .long L_G$non_lazy_ptr + +; PIC: _test1 +; PIC: ldr r0, LCPI0_0 +; PIC: ldr r0, [pc, r0] +; PIC: ldr r0, [r0] +; PIC: .long L_G$non_lazy_ptr-(LPC0_0+8) + +; PIC_T: _test1 +; PIC_T: ldr.n r0, LCPI0_0 +; PIC_T: add r0, pc +; PIC_T: ldr r0, [r0] +; PIC_T: ldr r0, [r0] +; PIC_T: .long L_G$non_lazy_ptr-(LPC0_0+4) + +; PIC_V7: _test1 +; PIC_V7: movw r0, :lower16:(L_G$non_lazy_ptr-(LPC0_0+8)) +; PIC_V7: movt r0, :upper16:(L_G$non_lazy_ptr-(LPC0_0+8)) +; PIC_V7: ldr r0, [pc, r0] +; PIC_V7: ldr r0, [r0] + +; LINUX: test1 +; LINUX: ldr r0, .LCPI0_0 +; LINUX: ldr r1, .LCPI0_1 +; LINUX: add r0, pc, r0 +; LINUX: ldr r0, [r1, r0] +; LINUX: ldr r0, [r0] +; LINUX: .long G(GOT) + %tmp = load i32* @G + ret i32 %tmp +} diff --git a/test/CodeGen/ARM/long.ll b/test/CodeGen/ARM/long.ll index 16ef7cc..74f8d78 100644 --- a/test/CodeGen/ARM/long.ll +++ b/test/CodeGen/ARM/long.ll @@ -14,22 +14,22 @@ entry: define i64 @f3() { ; CHECK: f3: -; CHECK: mvn{{.*}}-2147483648 +; CHECK: mvn r0, #2, 2 entry: ret i64 2147483647 } define i64 @f4() { ; CHECK: f4: -; CHECK: -2147483648 +; CHECK: mov r0, #2, 2 entry: ret i64 2147483648 } define i64 @f5() { ; CHECK: f5: -; CHECK: mvn -; CHECK: mvn{{.*}}-2147483648 +; CHECK: mvn r0, #0 +; CHECK: mvn r1, #2, 2 entry: ret i64 9223372036854775807 } diff --git a/test/CodeGen/ARM/long_shift.ll b/test/CodeGen/ARM/long_shift.ll index 1ec4d15..5e4f573 100644 --- a/test/CodeGen/ARM/long_shift.ll +++ b/test/CodeGen/ARM/long_shift.ll @@ -2,8 +2,8 @@ define i64 @f0(i64 %A, i64 %B) { ; CHECK: f0 -; CHECK: movs r3, r3, lsr #1 -; CHECK-NEXT: mov r2, r2, rrx +; CHECK: lsrs r3, r3, #1 +; CHECK-NEXT: rrx r2, r2 ; CHECK-NEXT: subs r0, r0, r2 ; CHECK-NEXT: sbc r1, r1, r3 %tmp = bitcast i64 %A to i64 @@ -14,7 +14,7 @@ define i64 @f0(i64 %A, i64 %B) { define i32 @f1(i64 %x, i64 %y) { ; CHECK: f1 -; CHECK: mov r0, r0, lsl r2 +; CHECK: lsl{{.*}}r2 %a = shl i64 %x, %y %b = trunc i64 %a to i32 ret i32 %b @@ -22,7 +22,7 @@ define i32 @f1(i64 %x, i64 %y) { define i32 @f2(i64 %x, i64 %y) { ; CHECK: f2 -; CHECK: mov r0, r0, lsr r2 +; CHECK: lsr{{.*}}r2 ; CHECK-NEXT: rsb r3, r2, #32 ; CHECK-NEXT: subs r2, r2, #32 ; CHECK-NEXT: orr r0, r0, r1, lsl r3 @@ -34,7 +34,7 @@ define i32 @f2(i64 %x, i64 %y) { define i32 @f3(i64 %x, i64 %y) { ; CHECK: f3 -; CHECK: mov r0, r0, lsr r2 +; CHECK: lsr{{.*}}r2 ; CHECK-NEXT: rsb r3, r2, #32 ; CHECK-NEXT: subs r2, r2, #32 ; CHECK-NEXT: orr r0, r0, r1, lsl r3 diff --git a/test/CodeGen/ARM/lsr-code-insertion.ll b/test/CodeGen/ARM/lsr-code-insertion.ll index b8c543b..1bbb96d 100644 --- a/test/CodeGen/ARM/lsr-code-insertion.ll +++ b/test/CodeGen/ARM/lsr-code-insertion.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -stats |& grep {38.*Number of machine instrs printed} +; RUN: llc < %s -stats |& grep {39.*Number of machine instrs printed} ; RUN: llc < %s -stats |& not grep {.*Number of re-materialization} ; This test really wants to check that the resultant "cond_true" block only ; has a single store in it, and that cond_true55 only has code to materialize diff --git a/test/CodeGen/ARM/lsr-on-unrolled-loops.ll b/test/CodeGen/ARM/lsr-on-unrolled-loops.ll index 866be42..9882690 100644 --- a/test/CodeGen/ARM/lsr-on-unrolled-loops.ll +++ b/test/CodeGen/ARM/lsr-on-unrolled-loops.ll @@ -4,14 +4,14 @@ ; constant offset addressing, so that each of the following stores ; uses the same register. -; CHECK: vstr.32 s{{.*}}, [r{{.*}}, #-128] -; CHECK: vstr.32 s{{.*}}, [r{{.*}}, #-96] -; CHECK: vstr.32 s{{.*}}, [r{{.*}}, #-64] -; CHECK: vstr.32 s{{.*}}, [r{{.*}}, #-32] -; CHECK: vstr.32 s{{.*}}, [r{{.*}}] -; CHECK: vstr.32 s{{.*}}, [r{{.*}}, #32] -; CHECK: vstr.32 s{{.*}}, [r{{.*}}, #64] -; CHECK: vstr.32 s{{.*}}, [r{{.*}}, #96] +; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #-128] +; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #-96] +; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #-64] +; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #-32] +; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}] +; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #32] +; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #64] +; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #96] target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" @@ -624,12 +624,11 @@ bb23: ; preds = %bb22, %bb20, %bb9, bb24: ; preds = %bb23 ; LSR should use count-down iteration to avoid requiring the trip count -; in a register, and it shouldn't require any reloads here. +; in a register. ; CHECK: @ %bb24 -; CHECK-NEXT: @ in Loop: Header=BB1_1 Depth=1 -; CHECK-NEXT: sub{{.*}} [[REGISTER:(r[0-9]+)|(lr)]], #1 -; CHECK-NEXT: bne.w +; CHECK: subs{{.*}} {{(r[0-9]+)|(lr)}}, #1 +; CHECK: bne.w %92 = icmp eq i32 %tmp81, %indvar78 ; [#uses=1] %indvar.next79 = add i32 %indvar78, 1 ; [#uses=1] diff --git a/test/CodeGen/ARM/machine-licm.ll b/test/CodeGen/ARM/machine-licm.ll new file mode 100644 index 0000000..8656c5b --- /dev/null +++ b/test/CodeGen/ARM/machine-licm.ll @@ -0,0 +1,66 @@ +; RUN: llc < %s -mtriple=thumb-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s -check-prefix=THUMB +; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic -disable-fp-elim -mattr=+v6t2 | FileCheck %s -check-prefix=MOVT +; rdar://7353541 +; rdar://7354376 +; rdar://8887598 + +; The generated code is no where near ideal. It's not recognizing the two +; constantpool entries being loaded can be merged into one. + +@GV = external global i32 ; [#uses=2] + +define void @t(i32* nocapture %vals, i32 %c) nounwind { +entry: +; ARM: t: +; ARM: ldr [[REGISTER_1:r[0-9]+]], LCPI0_0 +; Unfortunately currently ARM codegen doesn't cse the ldr from constantpool. +; The issue is it can be read by an "add pc" or a "ldr [pc]" so it's messy +; to add the pseudo instructions to make sure they are CSE'ed at the same +; time as the "ldr cp". +; ARM: ldr r{{[0-9]+}}, LCPI0_1 +; ARM: LPC0_0: +; ARM: ldr r{{[0-9]+}}, [pc, [[REGISTER_1]]] +; ARM: ldr r{{[0-9]+}}, [r{{[0-9]+}}] + +; MOVT: t: +; MOVT: movw [[REGISTER_2:r[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+8)) +; MOVT: movt [[REGISTER_2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+8)) +; MOVT: LPC0_0: +; MOVT: ldr r{{[0-9]+}}, [pc, [[REGISTER_2]]] +; MOVT: ldr r{{[0-9]+}}, [r{{[0-9]+}}] + +; THUMB: t: + %0 = icmp eq i32 %c, 0 ; [#uses=1] + br i1 %0, label %return, label %bb.nph + +bb.nph: ; preds = %entry +; ARM: LCPI0_0: +; ARM: LCPI0_1: +; ARM: .section + +; THUMB: BB#1 +; THUMB: ldr.n r2, LCPI0_0 +; THUMB: add r2, pc +; THUMB: ldr r{{[0-9]+}}, [r2] +; THUMB: LBB0_2 +; THUMB: LCPI0_0: +; THUMB-NOT: LCPI0_1: +; THUMB: .section + %.pre = load i32* @GV, align 4 ; [#uses=1] + br label %bb + +bb: ; preds = %bb, %bb.nph + %1 = phi i32 [ %.pre, %bb.nph ], [ %3, %bb ] ; [#uses=1] + %i.03 = phi i32 [ 0, %bb.nph ], [ %4, %bb ] ; [#uses=2] + %scevgep = getelementptr i32* %vals, i32 %i.03 ; [#uses=1] + %2 = load i32* %scevgep, align 4 ; [#uses=1] + %3 = add nsw i32 %1, %2 ; [#uses=2] + store i32 %3, i32* @GV, align 4 + %4 = add i32 %i.03, 1 ; [#uses=2] + %exitcond = icmp eq i32 %4, %c ; [#uses=1] + br i1 %exitcond, label %return, label %bb + +return: ; preds = %bb, %entry + ret void +} diff --git a/test/CodeGen/ARM/mul_const.ll b/test/CodeGen/ARM/mul_const.ll index 8c10246..3cb8a8e 100644 --- a/test/CodeGen/ARM/mul_const.ll +++ b/test/CodeGen/ARM/mul_const.ll @@ -36,7 +36,7 @@ define i32 @t12288(i32 %v) nounwind readnone { entry: ; CHECK: t12288: ; CHECK: add r0, r0, r0, lsl #1 -; CHECK: mov r0, r0, lsl #12 +; CHECK: lsl{{.*}}#12 %0 = mul i32 %v, 12288 ret i32 %0 } diff --git a/test/CodeGen/ARM/mult-alt-generic-arm.ll b/test/CodeGen/ARM/mult-alt-generic-arm.ll new file mode 100644 index 0000000..a8104db --- /dev/null +++ b/test/CodeGen/ARM/mult-alt-generic-arm.ll @@ -0,0 +1,323 @@ +; RUN: llc < %s -march=arm +; ModuleID = 'mult-alt-generic.c' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32" +target triple = "arm" + +@mout0 = common global i32 0, align 4 +@min1 = common global i32 0, align 4 +@marray = common global [2 x i32] zeroinitializer, align 4 + +define arm_aapcscc void @single_m() nounwind { +entry: + call void asm "foo $1,$0", "=*m,*m"(i32* @mout0, i32* @min1) nounwind + ret void +} + +define arm_aapcscc void @single_o() nounwind { +entry: + %out0 = alloca i32, align 4 + %index = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %index, align 4 + ret void +} + +define arm_aapcscc void @single_V() nounwind { +entry: + ret void +} + +define arm_aapcscc void @single_lt() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* %in1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,r>"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @single_r() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @single_i() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,i"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @single_n() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,n"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @single_E() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r,E"(double 1.000000e+001) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define arm_aapcscc void @single_F() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r,F"(double 1.000000e+000) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define arm_aapcscc void @single_s() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @single_g() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r,imr"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @single_X() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r,X"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + %3 = call i32 asm "foo $1,$0", "=r,X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %3, i32* %out0, align 4 +; No lowering support. +; %4 = call i32 asm "foo $1,$0", "=r,X"(double 1.000000e+001) nounwind +; store i32 %4, i32* %out0, align 4 +; %5 = call i32 asm "foo $1,$0", "=r,X"(double 1.000000e+000) nounwind +; store i32 %5, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @single_p() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @multi_m() nounwind { +entry: + %tmp = load i32* @min1, align 4 + call void asm "foo $1,$0", "=*m|r,m|r"(i32* @mout0, i32 %tmp) nounwind + ret void +} + +define arm_aapcscc void @multi_o() nounwind { +entry: + %out0 = alloca i32, align 4 + %index = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %index, align 4 + ret void +} + +define arm_aapcscc void @multi_V() nounwind { +entry: + ret void +} + +define arm_aapcscc void @multi_lt() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* %in1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|r>"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @multi_r() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|m"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @multi_i() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|i"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @multi_n() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|n"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @multi_E() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r|r,r|E"(double 1.000000e+001) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define arm_aapcscc void @multi_F() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r|r,r|F"(double 1.000000e+000) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define arm_aapcscc void @multi_s() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @multi_g() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @multi_X() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + %3 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %3, i32* %out0, align 4 +; No lowering support. +; %4 = call i32 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+001) nounwind +; store i32 %4, i32* %out0, align 4 +; %5 = call i32 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+000) nounwind +; store i32 %5, i32* %out0, align 4 + ret void +} + +define arm_aapcscc void @multi_p() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} diff --git a/test/CodeGen/ARM/neon_div.ll b/test/CodeGen/ARM/neon_div.ll new file mode 100644 index 0000000..e337970 --- /dev/null +++ b/test/CodeGen/ARM/neon_div.ll @@ -0,0 +1,48 @@ +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s + +define <8 x i8> @sdivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { +;CHECK: vrecpe.f32 +;CHECK: vrecpe.f32 +;CHECK: vmovn.i32 +;CHECK: vmovn.i32 +;CHECK: vmovn.i16 + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = sdiv <8 x i8> %tmp1, %tmp2 + ret <8 x i8> %tmp3 +} + +define <8 x i8> @udivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { +;CHECK: vrecpe.f32 +;CHECK: vrecps.f32 +;CHECK: vrecpe.f32 +;CHECK: vrecps.f32 +;CHECK: vmovn.i32 +;CHECK: vmovn.i32 +;CHECK: vqmovun.s16 + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = udiv <8 x i8> %tmp1, %tmp2 + ret <8 x i8> %tmp3 +} + +define <4 x i16> @sdivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { +;CHECK: vrecpe.f32 +;CHECK: vrecps.f32 +;CHECK: vmovn.i32 + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = sdiv <4 x i16> %tmp1, %tmp2 + ret <4 x i16> %tmp3 +} + +define <4 x i16> @udivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { +;CHECK: vrecpe.f32 +;CHECK: vrecps.f32 +;CHECK: vrecps.f32 +;CHECK: vmovn.i32 + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = udiv <4 x i16> %tmp1, %tmp2 + ret <4 x i16> %tmp3 +} diff --git a/test/CodeGen/ARM/pack.ll b/test/CodeGen/ARM/pack.ll index 4905dc2..9015176 100644 --- a/test/CodeGen/ARM/pack.ll +++ b/test/CodeGen/ARM/pack.ll @@ -3,87 +3,78 @@ ; CHECK: test1 ; CHECK: pkhbt r0, r0, r1, lsl #16 define i32 @test1(i32 %X, i32 %Y) { - %tmp1 = and i32 %X, 65535 ; [#uses=1] - %tmp4 = shl i32 %Y, 16 ; [#uses=1] - %tmp5 = or i32 %tmp4, %tmp1 ; [#uses=1] - ret i32 %tmp5 -} - -; CHECK: test1a -; CHECK: pkhbt r0, r0, r1, lsl #16 -define i32 @test1a(i32 %X, i32 %Y) { - %tmp19 = and i32 %X, 65535 ; [#uses=1] - %tmp37 = shl i32 %Y, 16 ; [#uses=1] - %tmp5 = or i32 %tmp37, %tmp19 ; [#uses=1] + %tmp1 = and i32 %X, 65535 + %tmp4 = shl i32 %Y, 16 + %tmp5 = or i32 %tmp4, %tmp1 ret i32 %tmp5 } ; CHECK: test2 ; CHECK: pkhbt r0, r0, r1, lsl #12 define i32 @test2(i32 %X, i32 %Y) { - %tmp1 = and i32 %X, 65535 ; [#uses=1] - %tmp3 = shl i32 %Y, 12 ; [#uses=1] - %tmp4 = and i32 %tmp3, -65536 ; [#uses=1] - %tmp57 = or i32 %tmp4, %tmp1 ; [#uses=1] + %tmp1 = and i32 %X, 65535 + %tmp3 = shl i32 %Y, 12 + %tmp4 = and i32 %tmp3, -65536 + %tmp57 = or i32 %tmp4, %tmp1 ret i32 %tmp57 } ; CHECK: test3 ; CHECK: pkhbt r0, r0, r1, lsl #18 define i32 @test3(i32 %X, i32 %Y) { - %tmp19 = and i32 %X, 65535 ; [#uses=1] - %tmp37 = shl i32 %Y, 18 ; [#uses=1] - %tmp5 = or i32 %tmp37, %tmp19 ; [#uses=1] + %tmp19 = and i32 %X, 65535 + %tmp37 = shl i32 %Y, 18 + %tmp5 = or i32 %tmp37, %tmp19 ret i32 %tmp5 } ; CHECK: test4 ; CHECK: pkhbt r0, r0, r1 define i32 @test4(i32 %X, i32 %Y) { - %tmp1 = and i32 %X, 65535 ; [#uses=1] - %tmp3 = and i32 %Y, -65536 ; [#uses=1] - %tmp46 = or i32 %tmp3, %tmp1 ; [#uses=1] + %tmp1 = and i32 %X, 65535 + %tmp3 = and i32 %Y, -65536 + %tmp46 = or i32 %tmp3, %tmp1 ret i32 %tmp46 } ; CHECK: test5 ; CHECK: pkhtb r0, r0, r1, asr #16 define i32 @test5(i32 %X, i32 %Y) { - %tmp17 = and i32 %X, -65536 ; [#uses=1] - %tmp2 = bitcast i32 %Y to i32 ; [#uses=1] - %tmp4 = lshr i32 %tmp2, 16 ; [#uses=2] - %tmp5 = or i32 %tmp4, %tmp17 ; [#uses=1] + %tmp17 = and i32 %X, -65536 + %tmp2 = bitcast i32 %Y to i32 + %tmp4 = lshr i32 %tmp2, 16 + %tmp5 = or i32 %tmp4, %tmp17 ret i32 %tmp5 } ; CHECK: test5a ; CHECK: pkhtb r0, r0, r1, asr #16 define i32 @test5a(i32 %X, i32 %Y) { - %tmp110 = and i32 %X, -65536 ; [#uses=1] - %tmp37 = lshr i32 %Y, 16 ; [#uses=1] - %tmp39 = bitcast i32 %tmp37 to i32 ; [#uses=1] - %tmp5 = or i32 %tmp39, %tmp110 ; [#uses=1] + %tmp110 = and i32 %X, -65536 + %tmp37 = lshr i32 %Y, 16 + %tmp39 = bitcast i32 %tmp37 to i32 + %tmp5 = or i32 %tmp39, %tmp110 ret i32 %tmp5 } ; CHECK: test6 ; CHECK: pkhtb r0, r0, r1, asr #12 define i32 @test6(i32 %X, i32 %Y) { - %tmp1 = and i32 %X, -65536 ; [#uses=1] - %tmp37 = lshr i32 %Y, 12 ; [#uses=1] - %tmp38 = bitcast i32 %tmp37 to i32 ; [#uses=1] - %tmp4 = and i32 %tmp38, 65535 ; [#uses=1] - %tmp59 = or i32 %tmp4, %tmp1 ; [#uses=1] + %tmp1 = and i32 %X, -65536 + %tmp37 = lshr i32 %Y, 12 + %tmp38 = bitcast i32 %tmp37 to i32 + %tmp4 = and i32 %tmp38, 65535 + %tmp59 = or i32 %tmp4, %tmp1 ret i32 %tmp59 } ; CHECK: test7 ; CHECK: pkhtb r0, r0, r1, asr #18 define i32 @test7(i32 %X, i32 %Y) { - %tmp1 = and i32 %X, -65536 ; [#uses=1] - %tmp3 = ashr i32 %Y, 18 ; [#uses=1] - %tmp4 = and i32 %tmp3, 65535 ; [#uses=1] - %tmp57 = or i32 %tmp4, %tmp1 ; [#uses=1] + %tmp1 = and i32 %X, -65536 + %tmp3 = ashr i32 %Y, 18 + %tmp4 = and i32 %tmp3, 65535 + %tmp57 = or i32 %tmp4, %tmp1 ret i32 %tmp57 } diff --git a/test/CodeGen/ARM/phi.ll b/test/CodeGen/ARM/phi.ll new file mode 100644 index 0000000..29e17c0 --- /dev/null +++ b/test/CodeGen/ARM/phi.ll @@ -0,0 +1,23 @@ +; RUN: llc -march=arm < %s | FileCheck %s +; + +define i32 @test1(i1 %a, i32* %b) { +; CHECK: test1 +entry: + br i1 %a, label %lblock, label %rblock + +lblock: + %lbranch = getelementptr i32* %b, i32 1 + br label %end + +rblock: + %rbranch = getelementptr i32* %b, i32 1 + br label %end + +end: +; CHECK: ldr r0, [r1, #4] + %gep = phi i32* [%lbranch, %lblock], [%rbranch, %rblock] + %r = load i32* %gep +; CHECK-NEXT: bx lr + ret i32 %r +} \ No newline at end of file diff --git a/test/CodeGen/ARM/prefetch.ll b/test/CodeGen/ARM/prefetch.ll new file mode 100644 index 0000000..895b27b --- /dev/null +++ b/test/CodeGen/ARM/prefetch.ll @@ -0,0 +1,61 @@ +; RUN: llc < %s -march=thumb -mattr=-thumb2 | not grep pld +; RUN: llc < %s -march=thumb -mattr=+v7a | FileCheck %s -check-prefix=THUMB2 +; RUN: llc < %s -march=arm -mattr=+v7a,+mp | FileCheck %s -check-prefix=ARM-MP +; rdar://8601536 + +define void @t1(i8* %ptr) nounwind { +entry: +; ARM-MP: t1: +; ARM-MP: pldw [r0] +; ARM-MP: pld [r0] + +; THUMB2: t1: +; THUMB2-NOT: pldw [r0] +; THUMB2: pld [r0] + tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3 ) + tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3 ) + ret void +} + +define void @t2(i8* %ptr) nounwind { +entry: +; ARM-MP: t2: +; ARM-MP: pld [r0, #1023] + +; THUMB2: t2: +; THUMB2: pld [r0, #1023] + %tmp = getelementptr i8* %ptr, i32 1023 + tail call void @llvm.prefetch( i8* %tmp, i32 0, i32 3 ) + ret void +} + +define void @t3(i32 %base, i32 %offset) nounwind { +entry: +; ARM-MP: t3: +; ARM-MP: pld [r0, r1, lsr #2] + +; THUMB2: t3: +; THUMB2: lsrs r1, r1, #2 +; THUMB2: pld [r0, r1] + %tmp1 = lshr i32 %offset, 2 + %tmp2 = add i32 %base, %tmp1 + %tmp3 = inttoptr i32 %tmp2 to i8* + tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3 ) + ret void +} + +define void @t4(i32 %base, i32 %offset) nounwind { +entry: +; ARM-MP: t4: +; ARM-MP: pld [r0, r1, lsl #2] + +; THUMB2: t4: +; THUMB2: pld [r0, r1, lsl #2] + %tmp1 = shl i32 %offset, 2 + %tmp2 = add i32 %base, %tmp1 + %tmp3 = inttoptr i32 %tmp2 to i8* + tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3 ) + ret void +} + +declare void @llvm.prefetch(i8*, i32, i32) nounwind diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll index 2e4f10d..53214fd 100644 --- a/test/CodeGen/ARM/reg_sequence.ll +++ b/test/CodeGen/ARM/reg_sequence.ll @@ -46,8 +46,8 @@ entry: ; CHECK: t2: ; CHECK: vld1.16 ; CHECK-NOT: vmov -; CHECK: vld1.16 ; CHECK: vmul.i16 +; CHECK: vld1.16 ; CHECK: vmul.i16 ; CHECK-NOT: vmov ; CHECK: vst1.16 @@ -75,7 +75,8 @@ define <8 x i8> @t3(i8* %A, i8* %B) nounwind { ; CHECK: t3: ; CHECK: vld3.8 ; CHECK: vmul.i8 -; CHECK-NOT: vmov +; CHECK: vmov r +; CHECK-NOT: vmov d ; CHECK: vst3.8 %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2] %tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0 ; <<8 x i8>> [#uses=1] @@ -122,9 +123,9 @@ return1: return2: ; CHECK: %return2 ; CHECK: vadd.i32 -; CHECK: vmov q1, q3 +; CHECK: vmov q9, q11 ; CHECK-NOT: vmov -; CHECK: vst2.32 {d0, d1, d2, d3} +; CHECK: vst2.32 {d16, d17, d18, d19} %tmp100 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 ; <<4 x i32>> [#uses=1] %tmp101 = extractvalue %struct.__neon_int32x4x2_t %tmp5, 1 ; <<4 x i32>> [#uses=1] %tmp102 = add <4 x i32> %tmp100, %tmp101 ; <<4 x i32>> [#uses=1] @@ -136,9 +137,9 @@ return2: define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind { ; CHECK: t5: ; CHECK: vldmia -; CHECK: vmov q1, q0 +; CHECK: vmov q9, q8 ; CHECK-NOT: vmov -; CHECK: vld2.16 {d0[1], d2[1]}, [r0] +; CHECK: vld2.16 {d16[1], d18[1]}, [r0] ; CHECK-NOT: vmov ; CHECK: vadd.i16 %tmp0 = bitcast i16* %A to i8* ; [#uses=1] @@ -153,8 +154,8 @@ define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind { define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind { ; CHECK: t6: ; CHECK: vldr.64 -; CHECK: vmov d1, d0 -; CHECK-NEXT: vld2.8 {d0[1], d1[1]} +; CHECK: vmov d17, d16 +; CHECK-NEXT: vld2.8 {d16[1], d17[1]} %tmp1 = load <8 x i8>* %B ; <<8 x i8>> [#uses=2] %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) ; <%struct.__neon_int8x8x2_t> [#uses=2] %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0 ; <<8 x i8>> [#uses=1] @@ -168,10 +169,10 @@ entry: ; CHECK: t7: ; CHECK: vld2.32 ; CHECK: vst2.32 -; CHECK: vld1.32 {d0, d1}, -; CHECK: vmov q1, q0 +; CHECK: vld1.32 {d16, d17}, +; CHECK: vmov q9, q8 ; CHECK-NOT: vmov -; CHECK: vuzp.32 q0, q1 +; CHECK: vuzp.32 q8, q9 ; CHECK: vst1.32 %0 = bitcast i32* %iptr to i8* ; [#uses=2] %1 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %0, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2] @@ -188,7 +189,7 @@ entry: ; PR7156 define arm_aapcs_vfpcc i32 @t8() nounwind { ; CHECK: t8: -; CHECK: vrsqrte.f32 q0, q0 +; CHECK: vrsqrte.f32 q8, q8 bb.nph55.bb.nph55.split_crit_edge: br label %bb3 @@ -238,10 +239,10 @@ bb14: ; preds = %bb6 define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind { ; CHECK: t9: ; CHECK: vldr.64 -; CHECK-NOT: vmov d{{.*}}, d0 -; CHECK: vmov.i32 d1 -; CHECK-NEXT: vstmia r0, {d0, d1} -; CHECK-NEXT: vstmia r0, {d0, d1} +; CHECK-NOT: vmov d{{.*}}, d16 +; CHECK: vmov.i32 d17 +; CHECK-NEXT: vstmia r0, {d16, d17} +; CHECK-NEXT: vstmia r0, {d16, d17} %3 = bitcast double 0.000000e+00 to <2 x float> ; <<2 x float>> [#uses=2] %4 = shufflevector <2 x float> %3, <2 x float> undef, <4 x i32> ; <<4 x float>> [#uses=1] store <4 x float> %4, <4 x float>* undef, align 16 @@ -269,9 +270,9 @@ define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind { define arm_aapcs_vfpcc i32 @t10() nounwind { entry: ; CHECK: t10: -; CHECK: vmov.i32 q1, #0x3F000000 -; CHECK: vmov d0, d1 -; CHECK: vmla.f32 q0, q0, d0[0] +; CHECK: vmul.f32 q8, q8, d0[0] +; CHECK: vmov.i32 q9, #0x3F000000 +; CHECK: vadd.f32 q8, q8, q8 %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] %1 = insertelement <4 x float> %0, float undef, i32 1 ; <<4 x float>> [#uses=1] %2 = insertelement <4 x float> %1, float undef, i32 2 ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/ARM/remat.ll b/test/CodeGen/ARM/remat.ll deleted file mode 100644 index 6b86f1a..0000000 --- a/test/CodeGen/ARM/remat.ll +++ /dev/null @@ -1,65 +0,0 @@ -; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 -o /dev/null -stats -info-output-file - | grep "Number of re-materialization" - -define i32 @main(i32 %argc, i8** nocapture %argv, double %d1, double %d2) nounwind { -entry: - br i1 undef, label %smvp.exit, label %bb.i3 - -bb.i3: ; preds = %bb.i3, %bb134 - br i1 undef, label %smvp.exit, label %bb.i3 - -smvp.exit: ; preds = %bb.i3 - %0 = fmul double %d1, 2.400000e-03 ; [#uses=2] - br i1 undef, label %bb138.preheader, label %bb159 - -bb138.preheader: ; preds = %smvp.exit - br label %bb138 - -bb138: ; preds = %bb138, %bb138.preheader - br i1 undef, label %bb138, label %bb145.loopexit - -bb142: ; preds = %bb.nph218.bb.nph218.split_crit_edge, %phi0.exit - %1 = fmul double %d1, -1.200000e-03 ; [#uses=1] - %2 = fadd double %d2, %1 ; [#uses=1] - %3 = fmul double %2, %d2 ; [#uses=1] - %4 = fsub double 0.000000e+00, %3 ; [#uses=1] - br i1 %14, label %phi1.exit, label %bb.i35 - -bb.i35: ; preds = %bb142 - %5 = call double @sin(double %15) nounwind readonly ; [#uses=1] - %6 = fmul double %5, 0x4031740AFA84AD8A ; [#uses=1] - %7 = fsub double 1.000000e+00, undef ; [#uses=1] - %8 = fdiv double %7, 6.000000e-01 ; [#uses=1] - br label %phi1.exit - -phi1.exit: ; preds = %bb.i35, %bb142 - %.pn = phi double [ %6, %bb.i35 ], [ 0.000000e+00, %bb142 ] ; [#uses=1] - %9 = phi double [ %8, %bb.i35 ], [ 0.000000e+00, %bb142 ] ; [#uses=1] - %10 = fmul double %.pn, %9 ; [#uses=1] - br i1 %14, label %phi0.exit, label %bb.i - -bb.i: ; preds = %phi1.exit - unreachable - -phi0.exit: ; preds = %phi1.exit - %11 = fsub double %4, %10 ; [#uses=1] - %12 = fadd double 0.000000e+00, %11 ; [#uses=1] - store double %12, double* undef, align 4 - br label %bb142 - -bb145.loopexit: ; preds = %bb138 - br i1 undef, label %bb.nph218.bb.nph218.split_crit_edge, label %bb159 - -bb.nph218.bb.nph218.split_crit_edge: ; preds = %bb145.loopexit - %13 = fmul double %0, 0x401921FB54442D18 ; [#uses=1] - %14 = fcmp ugt double %0, 6.000000e-01 ; [#uses=2] - %15 = fdiv double %13, 6.000000e-01 ; [#uses=1] - br label %bb142 - -bb159: ; preds = %bb145.loopexit, %smvp.exit, %bb134 - unreachable - -bb166: ; preds = %bb127 - unreachable -} - -declare double @sin(double) nounwind readonly diff --git a/test/CodeGen/ARM/rev.ll b/test/CodeGen/ARM/rev.ll index 1c12268..687bf88 100644 --- a/test/CodeGen/ARM/rev.ll +++ b/test/CodeGen/ARM/rev.ll @@ -1,27 +1,30 @@ -; RUN: llc < %s -march=arm -mattr=+v6 | grep rev16 -; RUN: llc < %s -march=arm -mattr=+v6 | grep revsh +; RUN: llc < %s -march=arm -mattr=+v6 | FileCheck %s define i32 @test1(i32 %X) { - %tmp1 = lshr i32 %X, 8 ; [#uses=3] - %X15 = bitcast i32 %X to i32 ; [#uses=1] - %tmp4 = shl i32 %X15, 8 ; [#uses=2] - %tmp2 = and i32 %tmp1, 16711680 ; [#uses=1] - %tmp5 = and i32 %tmp4, -16777216 ; [#uses=1] - %tmp9 = and i32 %tmp1, 255 ; [#uses=1] - %tmp13 = and i32 %tmp4, 65280 ; [#uses=1] - %tmp6 = or i32 %tmp5, %tmp2 ; [#uses=1] - %tmp10 = or i32 %tmp6, %tmp13 ; [#uses=1] - %tmp14 = or i32 %tmp10, %tmp9 ; [#uses=1] +; CHECK: test1 +; CHECK: rev16 r0, r0 + %tmp1 = lshr i32 %X, 8 + %X15 = bitcast i32 %X to i32 + %tmp4 = shl i32 %X15, 8 + %tmp2 = and i32 %tmp1, 16711680 + %tmp5 = and i32 %tmp4, -16777216 + %tmp9 = and i32 %tmp1, 255 + %tmp13 = and i32 %tmp4, 65280 + %tmp6 = or i32 %tmp5, %tmp2 + %tmp10 = or i32 %tmp6, %tmp13 + %tmp14 = or i32 %tmp10, %tmp9 ret i32 %tmp14 } define i32 @test2(i32 %X) { - %tmp1 = lshr i32 %X, 8 ; [#uses=1] - %tmp1.upgrd.1 = trunc i32 %tmp1 to i16 ; [#uses=1] - %tmp3 = trunc i32 %X to i16 ; [#uses=1] - %tmp2 = and i16 %tmp1.upgrd.1, 255 ; [#uses=1] - %tmp4 = shl i16 %tmp3, 8 ; [#uses=1] - %tmp5 = or i16 %tmp2, %tmp4 ; [#uses=1] - %tmp5.upgrd.2 = sext i16 %tmp5 to i32 ; [#uses=1] +; CHECK: test2 +; CHECK: revsh r0, r0 + %tmp1 = lshr i32 %X, 8 + %tmp1.upgrd.1 = trunc i32 %tmp1 to i16 + %tmp3 = trunc i32 %X to i16 + %tmp2 = and i16 %tmp1.upgrd.1, 255 + %tmp4 = shl i16 %tmp3, 8 + %tmp5 = or i16 %tmp2, %tmp4 + %tmp5.upgrd.2 = sext i16 %tmp5 to i32 ret i32 %tmp5.upgrd.2 } diff --git a/test/CodeGen/ARM/select-imm.ll b/test/CodeGen/ARM/select-imm.ll index 6e15fde..578834e 100644 --- a/test/CodeGen/ARM/select-imm.ll +++ b/test/CodeGen/ARM/select-imm.ll @@ -1,5 +1,6 @@ -; RUN: llc < %s -march=arm | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -march=arm -mattr=+thumb2 | FileCheck %s --check-prefix=T2 +; RUN: llc < %s -march=arm | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -march=arm -mattr=+thumb2 | FileCheck %s --check-prefix=ARMT2 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s --check-prefix=THUMB2 define i32 @t1(i32 %c) nounwind readnone { entry: @@ -8,9 +9,13 @@ entry: ; ARM: orr r1, r1, #1, 24 ; ARM: movgt r0, #123 -; T2: t1: -; T2: movw r0, #357 -; T2: movgt r0, #123 +; ARMT2: t1: +; ARMT2: movw r0, #357 +; ARMT2: movgt r0, #123 + +; THUMB2: t1: +; THUMB2: movw r0, #357 +; THUMB2: movgt r0, #123 %0 = icmp sgt i32 %c, 1 %1 = select i1 %0, i32 123, i32 357 @@ -20,13 +25,17 @@ entry: define i32 @t2(i32 %c) nounwind readnone { entry: ; ARM: t2: -; ARM: mov r1, #101 -; ARM: orr r1, r1, #1, 24 -; ARM: movle r0, #123 +; ARM: mov r0, #123 +; ARM: movgt r0, #101 +; ARM: orrgt r0, r0, #1, 24 -; T2: t2: -; T2: movw r0, #357 -; T2: movle r0, #123 +; ARMT2: t2: +; ARMT2: mov r0, #123 +; ARMT2: movwgt r0, #357 + +; THUMB2: t2: +; THUMB2: mov.w r0, #123 +; THUMB2: movwgt r0, #357 %0 = icmp sgt i32 %c, 1 %1 = select i1 %0, i32 357, i32 123 @@ -39,10 +48,31 @@ entry: ; ARM: mov r0, #0 ; ARM: moveq r0, #1 -; T2: t3: -; T2: mov r0, #0 -; T2: moveq r0, #1 +; ARMT2: t3: +; ARMT2: mov r0, #0 +; ARMT2: moveq r0, #1 + +; THUMB2: t3: +; THUMB2: mov.w r0, #0 +; THUMB2: moveq r0, #1 %0 = icmp eq i32 %a, 160 %1 = zext i1 %0 to i32 ret i32 %1 } + +define i32 @t4(i32 %a, i32 %b, i32 %x) nounwind { +entry: +; ARM: t4: +; ARM: ldr +; ARM: movlt + +; ARMT2: t4: +; ARMT2: movwlt r0, #65365 +; ARMT2: movtlt r0, #65365 + +; THUMB2: t4: +; THUMB2: mvnlt.w r0, #11141290 + %0 = icmp slt i32 %a, %b + %1 = select i1 %0, i32 4283826005, i32 %x + ret i32 %1 +} diff --git a/test/CodeGen/ARM/select.ll b/test/CodeGen/ARM/select.ll index 7413bed..1aa0d39 100644 --- a/test/CodeGen/ARM/select.ll +++ b/test/CodeGen/ARM/select.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s --check-prefix=CHECK-VFP ; RUN: llc < %s -mattr=+neon,+thumb2 -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=CHECK-NEON @@ -79,9 +79,9 @@ define double @f7(double %a, double %b) { ; CHECK-NEON: movw [[REGISTER_1:r[0-9]+]], #1123 ; CHECK-NEON-NEXT: movs [[REGISTER_2:r[0-9]+]], #0 ; CHECK-NEON-NEXT: cmp r0, [[REGISTER_1]] -; CHECK-NEON-NEXT: adr [[REGISTER_3:r[0-9]+]], #LCPI ; CHECK-NEON-NEXT: it eq ; CHECK-NEON-NEXT: moveq [[REGISTER_2]], #4 +; CHECK-NEON-NEXT: adr [[REGISTER_3:r[0-9]+]], #LCPI ; CHECK-NEON-NEXT: ldr ; CHECK-NEON: bx diff --git a/test/CodeGen/ARM/select_xform.ll b/test/CodeGen/ARM/select_xform.ll index 7fd91ce..5dabfc3 100644 --- a/test/CodeGen/ARM/select_xform.ll +++ b/test/CodeGen/ARM/select_xform.ll @@ -1,15 +1,60 @@ -; RUN: llc < %s -march=arm | grep mov | count 2 +; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -mtriple=thumb-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=T2 +; rdar://8662825 define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind { - %tmp1 = icmp sgt i32 %c, 10 - %tmp2 = select i1 %tmp1, i32 0, i32 2147483647 - %tmp3 = add i32 %tmp2, %b - ret i32 %tmp3 +; ARM: t1: +; ARM: sub r0, r1, #6, 2 +; ARM: movgt r0, r1 + +; T2: t1: +; T2: mvn r0, #-2147483648 +; T2: add r0, r1 +; T2: movgt r0, r1 + %tmp1 = icmp sgt i32 %c, 10 + %tmp2 = select i1 %tmp1, i32 0, i32 2147483647 + %tmp3 = add i32 %tmp2, %b + ret i32 %tmp3 } define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { - %tmp1 = icmp sgt i32 %c, 10 - %tmp2 = select i1 %tmp1, i32 0, i32 10 - %tmp3 = sub i32 %b, %tmp2 - ret i32 %tmp3 +; ARM: t2: +; ARM: sub r0, r1, #10 +; ARM: movgt r0, r1 + +; T2: t2: +; T2: sub.w r0, r1, #10 +; T2: movgt r0, r1 + %tmp1 = icmp sgt i32 %c, 10 + %tmp2 = select i1 %tmp1, i32 0, i32 10 + %tmp3 = sub i32 %b, %tmp2 + ret i32 %tmp3 +} + +define i32 @t3(i32 %a, i32 %b, i32 %x, i32 %y) nounwind { +; ARM: t3: +; ARM: mvnlt r2, #0 +; ARM: and r0, r2, r3 + +; T2: t3: +; T2: movlt.w r2, #-1 +; T2: and.w r0, r2, r3 + %cond = icmp slt i32 %a, %b + %z = select i1 %cond, i32 -1, i32 %x + %s = and i32 %z, %y + ret i32 %s +} + +define i32 @t4(i32 %a, i32 %b, i32 %x, i32 %y) nounwind { +; ARM: t4: +; ARM: movlt r2, #0 +; ARM: orr r0, r2, r3 + +; T2: t4: +; T2: movlt r2, #0 +; T2: orr.w r0, r2, r3 + %cond = icmp slt i32 %a, %b + %z = select i1 %cond, i32 0, i32 %x + %s = or i32 %z, %y + ret i32 %s } diff --git a/test/CodeGen/ARM/shifter_operand.ll b/test/CodeGen/ARM/shifter_operand.ll index 2bbe9fd..01e3a92 100644 --- a/test/CodeGen/ARM/shifter_operand.ll +++ b/test/CodeGen/ARM/shifter_operand.ll @@ -1,18 +1,72 @@ -; RUN: llc < %s -march=arm | grep add | grep lsl -; RUN: llc < %s -march=arm | grep bic | grep asr +; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8 +; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s -check-prefix=A9 +; rdar://8576755 define i32 @test1(i32 %X, i32 %Y, i8 %sh) { - %shift.upgrd.1 = zext i8 %sh to i32 ; [#uses=1] - %A = shl i32 %Y, %shift.upgrd.1 ; [#uses=1] - %B = add i32 %X, %A ; [#uses=1] +; A8: test1: +; A8: add r0, r0, r1, lsl r2 + +; A9: test1: +; A9: add r0, r0, r1, lsl r2 + %shift.upgrd.1 = zext i8 %sh to i32 + %A = shl i32 %Y, %shift.upgrd.1 + %B = add i32 %X, %A ret i32 %B } define i32 @test2(i32 %X, i32 %Y, i8 %sh) { - %shift.upgrd.2 = zext i8 %sh to i32 ; [#uses=1] - %A = ashr i32 %Y, %shift.upgrd.2 ; [#uses=1] - %B = xor i32 %A, -1 ; [#uses=1] - %C = and i32 %X, %B ; [#uses=1] +; A8: test2: +; A8: bic r0, r0, r1, asr r2 + +; A9: test2: +; A9: bic r0, r0, r1, asr r2 + %shift.upgrd.2 = zext i8 %sh to i32 + %A = ashr i32 %Y, %shift.upgrd.2 + %B = xor i32 %A, -1 + %C = and i32 %X, %B ret i32 %C } + +define i32 @test3(i32 %base, i32 %base2, i32 %offset) { +entry: +; A8: test3: +; A8: ldr r0, [r0, r2, lsl #2] +; A8: ldr r1, [r1, r2, lsl #2] + +; lsl #2 is free +; A9: test3: +; A9: ldr r0, [r0, r2, lsl #2] +; A9: ldr r1, [r1, r2, lsl #2] + %tmp1 = shl i32 %offset, 2 + %tmp2 = add i32 %base, %tmp1 + %tmp3 = inttoptr i32 %tmp2 to i32* + %tmp4 = add i32 %base2, %tmp1 + %tmp5 = inttoptr i32 %tmp4 to i32* + %tmp6 = load i32* %tmp3 + %tmp7 = load i32* %tmp5 + %tmp8 = add i32 %tmp7, %tmp6 + ret i32 %tmp8 +} + +declare i8* @malloc(...) + +define fastcc void @test4() nounwind { +entry: +; A8: test4: +; A8: ldr r1, [r0, r0, lsl #2] +; A8: str r1, [r0, r0, lsl #2] + +; A9: test4: +; A9: add r0, r0, r0, lsl #2 +; A9: ldr r1, [r0] +; A9: str r1, [r0] + %0 = tail call i8* (...)* @malloc(i32 undef) nounwind + %1 = bitcast i8* %0 to i32* + %2 = sext i16 undef to i32 + %3 = getelementptr inbounds i32* %1, i32 %2 + %4 = load i32* %3, align 4 + %5 = add nsw i32 %4, 1 + store i32 %5, i32* %3, align 4 + ret void +} diff --git a/test/CodeGen/ARM/spill-q.ll b/test/CodeGen/ARM/spill-q.ll index ae1ba2f..bf4e55c 100644 --- a/test/CodeGen/ARM/spill-q.ll +++ b/test/CodeGen/ARM/spill-q.ll @@ -15,11 +15,34 @@ define void @aaa(%quuz* %this, i8* %block) { ; CHECK: vst1.64 {{.*}}sp, :128 ; CHECK: vld1.64 {{.*}}sp, :128 entry: - %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1] + %aligned_vec = alloca <4 x float>, align 16 + %"alloca point" = bitcast i32 0 to i32 + %vecptr = bitcast <4 x float>* %aligned_vec to i8* + %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %vecptr, i32 1) nounwind ; <<4 x float>> [#uses=1] store float 6.300000e+01, float* undef, align 4 %1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1] store float 0.000000e+00, float* undef, align 4 %2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1] + %ld3 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + store float 0.000000e+00, float* undef, align 4 + %ld4 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + store float 0.000000e+00, float* undef, align 4 + %ld5 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + store float 0.000000e+00, float* undef, align 4 + %ld6 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + store float 0.000000e+00, float* undef, align 4 + %ld7 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + store float 0.000000e+00, float* undef, align 4 + %ld8 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + store float 0.000000e+00, float* undef, align 4 + %ld9 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + store float 0.000000e+00, float* undef, align 4 + %ld10 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + store float 0.000000e+00, float* undef, align 4 + %ld11 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + store float 0.000000e+00, float* undef, align 4 + %ld12 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind + store float 0.000000e+00, float* undef, align 4 %val173 = load <4 x float>* undef ; <<4 x float>> [#uses=1] br label %bb4 @@ -44,7 +67,16 @@ bb4: ; preds = %bb193, %entry %18 = fmul <4 x float> %17, %val173 ; <<4 x float>> [#uses=1] %19 = shufflevector <4 x float> %18, <4 x float> undef, <2 x i32> ; <<2 x float>> [#uses=1] %20 = shufflevector <2 x float> %19, <2 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] - %21 = fadd <4 x float> zeroinitializer, %20 ; <<4 x float>> [#uses=2] + %tmp1 = fadd <4 x float> %20, %ld3 + %tmp2 = fadd <4 x float> %tmp1, %ld4 + %tmp3 = fadd <4 x float> %tmp2, %ld5 + %tmp4 = fadd <4 x float> %tmp3, %ld6 + %tmp5 = fadd <4 x float> %tmp4, %ld7 + %tmp6 = fadd <4 x float> %tmp5, %ld8 + %tmp7 = fadd <4 x float> %tmp6, %ld9 + %tmp8 = fadd <4 x float> %tmp7, %ld10 + %tmp9 = fadd <4 x float> %tmp8, %ld11 + %21 = fadd <4 x float> %tmp9, %ld12 %22 = fcmp ogt <4 x float> %besterror.0.2264, %21 ; <<4 x i1>> [#uses=0] %tmp = extractelement <4 x i1> %22, i32 0 br i1 %tmp, label %bb193, label %bb186 diff --git a/test/CodeGen/ARM/stm.ll b/test/CodeGen/ARM/stm.ll index 22a7ecb..2f5fadb 100644 --- a/test/CodeGen/ARM/stm.ll +++ b/test/CodeGen/ARM/stm.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2 | grep stm | count 2 +; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2 | FileCheck %s @"\01LC" = internal constant [32 x i8] c"Boolean Not: %d %d %d %d %d %d\0A\00", section "__TEXT,__cstring,cstring_literals" ; <[32 x i8]*> [#uses=1] @"\01LC1" = internal constant [26 x i8] c"Bitwise Not: %d %d %d %d\0A\00", section "__TEXT,__cstring,cstring_literals" ; <[26 x i8]*> [#uses=1] @@ -7,6 +7,9 @@ declare i32 @printf(i8* nocapture, ...) nounwind define i32 @main() nounwind { entry: +; CHECK: main +; CHECK: push +; CHECK: stmib %0 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([26 x i8]* @"\01LC1", i32 0, i32 0), i32 -2, i32 -3, i32 2, i32 -6) nounwind ; [#uses=0] %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([32 x i8]* @"\01LC", i32 0, i32 0), i32 0, i32 1, i32 0, i32 1, i32 0, i32 1) nounwind ; [#uses=0] ret i32 0 diff --git a/test/CodeGen/ARM/str_pre-2.ll b/test/CodeGen/ARM/str_pre-2.ll index 553cd64..465c7e6 100644 --- a/test/CodeGen/ARM/str_pre-2.ll +++ b/test/CodeGen/ARM/str_pre-2.ll @@ -1,10 +1,11 @@ -; RUN: llc < %s -mtriple=arm-linux-gnu | grep {str.*\\!} -; RUN: llc < %s -mtriple=arm-linux-gnu | grep {ldr.*\\\[.*\], #4} +; RUN: llc < %s -mtriple=armv6-linux-gnu | FileCheck %s @b = external global i64* define i64 @t(i64 %a) nounwind readonly { entry: +; CHECK: str lr, [sp, #-4]! +; CHECK: ldr lr, [sp], #4 %0 = load i64** @b, align 4 %1 = load i64* %0, align 4 %2 = mul i64 %1, %a diff --git a/test/CodeGen/ARM/tail-opts.ll b/test/CodeGen/ARM/tail-opts.ll index 17c8bae..5b3dce3 100644 --- a/test/CodeGen/ARM/tail-opts.ll +++ b/test/CodeGen/ARM/tail-opts.ll @@ -17,13 +17,16 @@ declare i8* @choose(i8*, i8*) ; CHECK: tail_duplicate_me: ; CHECK: qux ; CHECK: qux -; CHECK: ldr r{{.}}, LCPI +; CHECK: movw r{{[0-9]+}}, :lower16:_GHJK +; CHECK: movt r{{[0-9]+}}, :upper16:_GHJK ; CHECK: str r ; CHECK-NEXT: bx r -; CHECK: ldr r{{.}}, LCPI +; CHECK: movw r{{[0-9]+}}, :lower16:_GHJK +; CHECK: movt r{{[0-9]+}}, :upper16:_GHJK ; CHECK: str r ; CHECK-NEXT: bx r -; CHECK: ldr r{{.}}, LCPI +; CHECK: movw r{{[0-9]+}}, :lower16:_GHJK +; CHECK: movt r{{[0-9]+}}, :upper16:_GHJK ; CHECK: str r ; CHECK-NEXT: bx r diff --git a/test/CodeGen/ARM/thumb1-varalloc.ll b/test/CodeGen/ARM/thumb1-varalloc.ll new file mode 100644 index 0000000..25093fe --- /dev/null +++ b/test/CodeGen/ARM/thumb1-varalloc.ll @@ -0,0 +1,40 @@ +; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s +; rdar://8819685 + +@__bar = external hidden global i8* +@__baz = external hidden global i8* + +define i8* @_foo() { +entry: +; CHECK: foo: + + %size = alloca i32, align 4 + %0 = load i8** @__bar, align 4 + %1 = icmp eq i8* %0, null + br i1 %1, label %bb1, label %bb3 + +bb1: + store i32 1026, i32* %size, align 4 + %2 = alloca [1026 x i8], align 1 +; CHECK: mov r0, sp +; CHECK: adds r4, r0, r4 + %3 = getelementptr inbounds [1026 x i8]* %2, i32 0, i32 0 + %4 = call i32 @_called_func(i8* %3, i32* %size) nounwind + %5 = icmp eq i32 %4, 0 + br i1 %5, label %bb2, label %bb3 + +bb2: + %6 = call i8* @strdup(i8* %3) nounwind + store i8* %6, i8** @__baz, align 4 + br label %bb3 + +bb3: + %.0 = phi i8* [ %0, %entry ], [ %6, %bb2 ], [ %3, %bb1 ] +; CHECK: subs r4, #5 +; CHECK-NEXT: mov sp, r4 +; CHECK-NEXT: pop {r4, r5, r6, r7, pc} + ret i8* %.0 +} + +declare noalias i8* @strdup(i8* nocapture) nounwind +declare i32 @_called_func(i8*, i32*) nounwind \ No newline at end of file diff --git a/test/CodeGen/ARM/umulo-32.ll b/test/CodeGen/ARM/umulo-32.ll new file mode 100644 index 0000000..aa7d28a --- /dev/null +++ b/test/CodeGen/ARM/umulo-32.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s + +%umul.ty = type { i32, i1 } + +define i32 @func(i32 %a) nounwind { +; CHECK: func +; CHECK: muldi3 + %tmp0 = tail call %umul.ty @llvm.umul.with.overflow.i32(i32 %a, i32 37) + %tmp1 = extractvalue %umul.ty %tmp0, 0 + %tmp2 = select i1 undef, i32 -1, i32 %tmp1 + ret i32 %tmp2 +} + +declare %umul.ty @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone diff --git a/test/CodeGen/ARM/unaligned_load_store.ll b/test/CodeGen/ARM/unaligned_load_store.ll index e279491..b42e11f 100644 --- a/test/CodeGen/ARM/unaligned_load_store.ll +++ b/test/CodeGen/ARM/unaligned_load_store.ll @@ -1,5 +1,6 @@ -; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=GENERIC +; RUN: llc < %s -march=arm -pre-RA-sched=source | FileCheck %s -check-prefix=GENERIC ; RUN: llc < %s -mtriple=armv6-apple-darwin | FileCheck %s -check-prefix=DARWIN_V6 +; RUN: llc < %s -mtriple=armv6-apple-darwin -arm-strict-align | FileCheck %s -check-prefix=GENERIC ; RUN: llc < %s -mtriple=armv6-linux | FileCheck %s -check-prefix=GENERIC ; rdar://7113725 diff --git a/test/CodeGen/ARM/vbits.ll b/test/CodeGen/ARM/vbits.ll index 293d229..51f9bdf 100644 --- a/test/CodeGen/ARM/vbits.ll +++ b/test/CodeGen/ARM/vbits.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+neon -mcpu=cortex-a8 | FileCheck %s define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: v_andi8: @@ -505,3 +505,43 @@ define <4 x i32> @vtstQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { %tmp5 = sext <4 x i1> %tmp4 to <4 x i32> ret <4 x i32> %tmp5 } + +define <8 x i8> @v_orrimm(<8 x i8>* %A) nounwind { +; CHECK: v_orrimm: +; CHECK-NOT: vmov +; CHECK-NOT: vmvn +; CHECK: vorr + %tmp1 = load <8 x i8>* %A + %tmp3 = or <8 x i8> %tmp1, + ret <8 x i8> %tmp3 +} + +define <16 x i8> @v_orrimmQ(<16 x i8>* %A) nounwind { +; CHECK: v_orrimmQ +; CHECK-NOT: vmov +; CHECK-NOT: vmvn +; CHECK: vorr + %tmp1 = load <16 x i8>* %A + %tmp3 = or <16 x i8> %tmp1, + ret <16 x i8> %tmp3 +} + +define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind { +; CHECK: v_bicimm: +; CHECK-NOT: vmov +; CHECK-NOT: vmvn +; CHECK: vbic + %tmp1 = load <8 x i8>* %A + %tmp3 = and <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 > + ret <8 x i8> %tmp3 +} + +define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind { +; CHECK: v_bicimmQ: +; CHECK-NOT: vmov +; CHECK-NOT: vmvn +; CHECK: vbic + %tmp1 = load <16 x i8>* %A + %tmp3 = and <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 > + ret <16 x i8> %tmp3 +} diff --git a/test/CodeGen/ARM/vceq.ll b/test/CodeGen/ARM/vceq.ll index e478751..051c349 100644 --- a/test/CodeGen/ARM/vceq.ll +++ b/test/CodeGen/ARM/vceq.ll @@ -79,3 +79,14 @@ define <4 x i32> @vceqQf32(<4 x float>* %A, <4 x float>* %B) nounwind { %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 } + +define <8 x i8> @vceqi8Z(<8 x i8>* %A) nounwind { +;CHECK: vceqi8Z: +;CHECK-NOT: vmov +;CHECK-NOT: vmvn +;CHECK: vceq.i8 + %tmp1 = load <8 x i8>* %A + %tmp3 = icmp eq <8 x i8> %tmp1, + %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> + ret <8 x i8> %tmp4 +} diff --git a/test/CodeGen/ARM/vcge.ll b/test/CodeGen/ARM/vcge.ll index 2c16111..bf5f0b9 100644 --- a/test/CodeGen/ARM/vcge.ll +++ b/test/CodeGen/ARM/vcge.ll @@ -160,3 +160,44 @@ define <4 x i32> @vacgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind { declare <2 x i32> @llvm.arm.neon.vacged(<2 x float>, <2 x float>) nounwind readnone declare <4 x i32> @llvm.arm.neon.vacgeq(<4 x float>, <4 x float>) nounwind readnone + +define <8 x i8> @vcgei8Z(<8 x i8>* %A) nounwind { +;CHECK: vcgei8Z: +;CHECK-NOT: vmov +;CHECK-NOT: vmvn +;CHECK: vcge.s8 + %tmp1 = load <8 x i8>* %A + %tmp3 = icmp sge <8 x i8> %tmp1, + %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> + ret <8 x i8> %tmp4 +} + +define <8 x i8> @vclei8Z(<8 x i8>* %A) nounwind { +;CHECK: vclei8Z: +;CHECK-NOT: vmov +;CHECK-NOT: vmvn +;CHECK: vcle.s8 + %tmp1 = load <8 x i8>* %A + %tmp3 = icmp sle <8 x i8> %tmp1, + %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> + ret <8 x i8> %tmp4 +} + +; Radar 8782191 +; Floating-point comparisons against zero produce results with integer +; elements, not floating-point elements. +define void @test_vclez_fp() nounwind optsize { +;CHECK: test_vclez_fp +;CHECK: vcle.f32 +entry: + %0 = fcmp ole <4 x float> undef, zeroinitializer + %1 = sext <4 x i1> %0 to <4 x i16> + %2 = add <4 x i16> %1, zeroinitializer + %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <8 x i32> + %4 = add <8 x i16> %3, + %5 = trunc <8 x i16> %4 to <8 x i8> + tail call void @llvm.arm.neon.vst1.v8i8(i8* undef, <8 x i8> %5, i32 1) + unreachable +} + +declare void @llvm.arm.neon.vst1.v8i8(i8*, <8 x i8>, i32) nounwind diff --git a/test/CodeGen/ARM/vcgt.ll b/test/CodeGen/ARM/vcgt.ll index 194093c..c3c4cb3 100644 --- a/test/CodeGen/ARM/vcgt.ll +++ b/test/CodeGen/ARM/vcgt.ll @@ -161,9 +161,9 @@ define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind { ; rdar://7923010 define <4 x i32> @vcgt_zext(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK: vcgt_zext: -;CHECK: vcgt.f32 q0 -;CHECK: vmov.i32 q1, #0x1 -;CHECK: vand q0, q0, q1 +;CHECK: vmov.i32 q10, #0x1 +;CHECK: vcgt.f32 q8 +;CHECK: vand q8, q8, q10 %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B %tmp3 = fcmp ogt <4 x float> %tmp1, %tmp2 @@ -173,3 +173,25 @@ define <4 x i32> @vcgt_zext(<4 x float>* %A, <4 x float>* %B) nounwind { declare <2 x i32> @llvm.arm.neon.vacgtd(<2 x float>, <2 x float>) nounwind readnone declare <4 x i32> @llvm.arm.neon.vacgtq(<4 x float>, <4 x float>) nounwind readnone + +define <8 x i8> @vcgti8Z(<8 x i8>* %A) nounwind { +;CHECK: vcgti8Z: +;CHECK-NOT: vmov +;CHECK-NOT: vmvn +;CHECK: vcgt.s8 + %tmp1 = load <8 x i8>* %A + %tmp3 = icmp sgt <8 x i8> %tmp1, + %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> + ret <8 x i8> %tmp4 +} + +define <8 x i8> @vclti8Z(<8 x i8>* %A) nounwind { +;CHECK: vclti8Z: +;CHECK-NOT: vmov +;CHECK-NOT: vmvn +;CHECK: vclt.s8 + %tmp1 = load <8 x i8>* %A + %tmp3 = icmp slt <8 x i8> %tmp1, + %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> + ret <8 x i8> %tmp4 +} diff --git a/test/CodeGen/ARM/vcombine.ll b/test/CodeGen/ARM/vcombine.ll index e673305..527f93b 100644 --- a/test/CodeGen/ARM/vcombine.ll +++ b/test/CodeGen/ARM/vcombine.ll @@ -1,6 +1,9 @@ -; RUN: llc < %s -march=arm -mattr=+neon +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <16 x i8> @vcombine8(<8 x i8>* %A, <8 x i8>* %B) nounwind { +; CHECK: vcombine8 +; CHECK: vmov r0, r1, d16 +; CHECK: vmov r2, r3, d17 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> @@ -8,6 +11,9 @@ define <16 x i8> @vcombine8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <8 x i16> @vcombine16(<4 x i16>* %A, <4 x i16>* %B) nounwind { +; CHECK: vcombine16 +; CHECK: vmov r0, r1, d16 +; CHECK: vmov r2, r3, d17 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> @@ -15,6 +21,9 @@ define <8 x i16> @vcombine16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <4 x i32> @vcombine32(<2 x i32>* %A, <2 x i32>* %B) nounwind { +; CHECK: vcombine32 +; CHECK: vmov r0, r1, d16 +; CHECK: vmov r2, r3, d17 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B %tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32> @@ -22,6 +31,9 @@ define <4 x i32> @vcombine32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <4 x float> @vcombinefloat(<2 x float>* %A, <2 x float>* %B) nounwind { +; CHECK: vcombinefloat +; CHECK: vmov r0, r1, d16 +; CHECK: vmov r2, r3, d17 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B %tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <4 x i32> @@ -29,8 +41,32 @@ define <4 x float> @vcombinefloat(<2 x float>* %A, <2 x float>* %B) nounwind { } define <2 x i64> @vcombine64(<1 x i64>* %A, <1 x i64>* %B) nounwind { +; CHECK: vcombine64 +; CHECK: vmov r0, r1, d16 +; CHECK: vmov r2, r3, d17 %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B %tmp3 = shufflevector <1 x i64> %tmp1, <1 x i64> %tmp2, <2 x i32> ret <2 x i64> %tmp3 } + +; Check for vget_low and vget_high implemented with shufflevector. PR8411. +; They should not require storing to the stack. + +define <4 x i16> @vget_low16(<8 x i16>* %A) nounwind { +; CHECK: vget_low16 +; CHECK-NOT: vst +; CHECK: vmov r0, r1, d16 + %tmp1 = load <8 x i16>* %A + %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> + ret <4 x i16> %tmp2 +} + +define <8 x i8> @vget_high8(<16 x i8>* %A) nounwind { +; CHECK: vget_high8 +; CHECK-NOT: vst +; CHECK: vmov r0, r1, d17 + %tmp1 = load <16 x i8>* %A + %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <8 x i32> + ret <8 x i8> %tmp2 +} diff --git a/test/CodeGen/ARM/vcvt.ll b/test/CodeGen/ARM/vcvt.ll index f4cc536..c078f49 100644 --- a/test/CodeGen/ARM/vcvt.ll +++ b/test/CodeGen/ARM/vcvt.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+neon,+fp16 | FileCheck %s define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind { ;CHECK: vcvt_f32tos32: @@ -138,3 +138,21 @@ declare <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float>, i32) nounwi declare <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone +define <4 x float> @vcvt_f16tof32(<4 x i16>* %A) nounwind { +;CHECK: vcvt_f16tof32: +;CHECK: vcvt.f32.f16 + %tmp1 = load <4 x i16>* %A + %tmp2 = call <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16> %tmp1) + ret <4 x float> %tmp2 +} + +define <4 x i16> @vcvt_f32tof16(<4 x float>* %A) nounwind { +;CHECK: vcvt_f32tof16: +;CHECK: vcvt.f16.f32 + %tmp1 = load <4 x float>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float> %tmp1) + ret <4 x i16> %tmp2 +} + +declare <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float>) nounwind readnone diff --git a/test/CodeGen/ARM/vdup.ll b/test/CodeGen/ARM/vdup.ll index a545f6c..e99fac1 100644 --- a/test/CodeGen/ARM/vdup.ll +++ b/test/CodeGen/ARM/vdup.ll @@ -162,24 +162,6 @@ define <4 x float> @v_shuffledupQfloat(float %A) nounwind { ret <4 x float> %tmp2 } -define <2 x float> @v_shuffledupfloat2(float* %A) nounwind { -;CHECK: v_shuffledupfloat2: -;CHECK: vdup.32 - %tmp0 = load float* %A - %tmp1 = insertelement <2 x float> undef, float %tmp0, i32 0 - %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer - ret <2 x float> %tmp2 -} - -define <4 x float> @v_shuffledupQfloat2(float* %A) nounwind { -;CHECK: v_shuffledupQfloat2: -;CHECK: vdup.32 - %tmp0 = load float* %A - %tmp1 = insertelement <4 x float> undef, float %tmp0, i32 0 - %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer - ret <4 x float> %tmp2 -} - define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind { ;CHECK: vduplane8: ;CHECK: vdup.8 diff --git a/test/CodeGen/ARM/vector-DAGCombine.ll b/test/CodeGen/ARM/vector-DAGCombine.ll new file mode 100644 index 0000000..3ab0cfc --- /dev/null +++ b/test/CodeGen/ARM/vector-DAGCombine.ll @@ -0,0 +1,107 @@ +; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s + +; PR7158 +define i32 @test_pr7158() nounwind { +bb.nph55.bb.nph55.split_crit_edge: + br label %bb3 + +bb3: ; preds = %bb3, %bb.nph55.bb.nph55.split_crit_edge + br i1 undef, label %bb.i19, label %bb3 + +bb.i19: ; preds = %bb.i19, %bb3 + %0 = insertelement <4 x float> undef, float undef, i32 3 ; <<4 x float>> [#uses=3] + %1 = fmul <4 x float> %0, %0 ; <<4 x float>> [#uses=1] + %2 = bitcast <4 x float> %1 to <2 x double> ; <<2 x double>> [#uses=0] + %3 = fmul <4 x float> %0, undef ; <<4 x float>> [#uses=0] + br label %bb.i19 +} + +; Check that the DAG combiner does not arbitrarily modify BUILD_VECTORs +; after legalization. +define void @test_illegal_build_vector() nounwind { +entry: + store <2 x i64> undef, <2 x i64>* undef, align 16 + %0 = load <16 x i8>* undef, align 16 ; <<16 x i8>> [#uses=1] + %1 = or <16 x i8> zeroinitializer, %0 ; <<16 x i8>> [#uses=1] + store <16 x i8> %1, <16 x i8>* undef, align 16 + ret void +} + +; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is +; converted back to be used as a vector type. +; CHECK: test_vmovrrd_combine +define <4 x i32> @test_vmovrrd_combine() nounwind { +entry: + br i1 undef, label %bb1, label %bb2 + +bb1: + %0 = bitcast <2 x i64> zeroinitializer to <2 x double> + %1 = extractelement <2 x double> %0, i32 0 + %2 = bitcast double %1 to i64 + %3 = insertelement <1 x i64> undef, i64 %2, i32 0 +; CHECK-NOT: vmov s +; CHECK: vext.8 + %4 = shufflevector <1 x i64> %3, <1 x i64> undef, <2 x i32> + %tmp2006.3 = bitcast <2 x i64> %4 to <16 x i8> + %5 = shufflevector <16 x i8> %tmp2006.3, <16 x i8> undef, <16 x i32> + %tmp2004.3 = bitcast <16 x i8> %5 to <4 x i32> + br i1 undef, label %bb2, label %bb1 + +bb2: + %result = phi <4 x i32> [ undef, %entry ], [ %tmp2004.3, %bb1 ] + ret <4 x i32> %result +} + +; Test trying to do a ShiftCombine on illegal types. +; The vector should be split first. +define void @lshrIllegalType(<8 x i32>* %A) nounwind { + %tmp1 = load <8 x i32>* %A + %tmp2 = lshr <8 x i32> %tmp1, < i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3> + store <8 x i32> %tmp2, <8 x i32>* %A + ret void +} + +; Test folding a binary vector operation with constant BUILD_VECTOR +; operands with i16 elements. +define void @test_i16_constant_fold() nounwind optsize { +entry: + %0 = sext <4 x i1> zeroinitializer to <4 x i16> + %1 = add <4 x i16> %0, zeroinitializer + %2 = shufflevector <4 x i16> %1, <4 x i16> undef, <8 x i32> + %3 = add <8 x i16> %2, + %4 = trunc <8 x i16> %3 to <8 x i8> + tail call void @llvm.arm.neon.vst1.v8i8(i8* undef, <8 x i8> %4, i32 1) + unreachable +} + +declare void @llvm.arm.neon.vst1.v8i8(i8*, <8 x i8>, i32) nounwind + +; Test that loads and stores of i64 vector elements are handled as f64 values +; so they are not split up into i32 values. Radar 8755338. +define void @i64_buildvector(i64* %ptr, <2 x i64>* %vp) nounwind { +; CHECK: i64_buildvector +; CHECK: vldr.64 + %t0 = load i64* %ptr, align 4 + %t1 = insertelement <2 x i64> undef, i64 %t0, i32 0 + store <2 x i64> %t1, <2 x i64>* %vp + ret void +} + +define void @i64_insertelement(i64* %ptr, <2 x i64>* %vp) nounwind { +; CHECK: i64_insertelement +; CHECK: vldr.64 + %t0 = load i64* %ptr, align 4 + %vec = load <2 x i64>* %vp + %t1 = insertelement <2 x i64> %vec, i64 %t0, i32 0 + store <2 x i64> %t1, <2 x i64>* %vp + ret void +} + +define void @i64_extractelement(i64* %ptr, <2 x i64>* %vp) nounwind { +; CHECK: i64_extractelement +; CHECK: vstr.64 + %vec = load <2 x i64>* %vp + %t1 = extractelement <2 x i64> %vec, i32 0 + store i64 %t1, i64* %ptr + ret void +} diff --git a/test/CodeGen/ARM/vext.ll b/test/CodeGen/ARM/vext.ll index e460a84..55abefe 100644 --- a/test/CodeGen/ARM/vext.ll +++ b/test/CodeGen/ARM/vext.ll @@ -74,3 +74,62 @@ define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind { ret <16 x i8> %tmp3 } +; Tests for ReconstructShuffle function. Indices have to be carefully +; chosen to reach lowering phase as a BUILD_VECTOR. + +; One vector needs vext, the other can be handled by extract_subvector +; Also checks interleaving of sources is handled correctly. +; Essence: a vext is used on %A and something saner than stack load/store for final result. +define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind { +;CHECK: test_interleaved: +;CHECK: vext.16 +;CHECK-NOT: vext.16 +;CHECK: vzip.16 + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> + ret <4 x i16> %tmp3 +} + +; An undef in the shuffle list should still be optimizable +define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind { +;CHECK: test_undef: +;CHECK: vzip.16 + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> + ret <4 x i16> %tmp3 +} + +; We should ignore a build_vector with more than two sources. +; Use illegal <32 x i16> type to produce such a shuffle after legalizing types. +; Try to look for fallback to stack expansion. +define <4 x i16> @test_multisource(<32 x i16>* %B) nounwind { +;CHECK: test_multisource: +;CHECK: vst1.16 + %tmp1 = load <32 x i16>* %B + %tmp2 = shufflevector <32 x i16> %tmp1, <32 x i16> undef, <4 x i32> + ret <4 x i16> %tmp2 +} + +; We don't handle shuffles using more than half of a 128-bit vector. +; Again, test for fallback to stack expansion +define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind { +;CHECK: test_largespan: +;CHECK: vst1.16 + %tmp1 = load <8 x i16>* %B + %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> + ret <4 x i16> %tmp2 +} + +; The actual shuffle code only handles some cases, make sure we check +; this rather than blindly emitting a VECTOR_SHUFFLE (infinite +; lowering loop can result otherwise). +define <8 x i8> @test_illegal(<16 x i8>* %A, <16 x i8>* %B) nounwind { +;CHECK: test_illegal: +;CHECK: vst1.8 + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <8 x i32> + ret <8 x i8> %tmp3 +} diff --git a/test/CodeGen/ARM/vget_lane.ll b/test/CodeGen/ARM/vget_lane.ll index 05e7f50..1fc885d 100644 --- a/test/CodeGen/ARM/vget_lane.ll +++ b/test/CodeGen/ARM/vget_lane.ll @@ -96,13 +96,14 @@ define i32 @vgetQ_lanei32(<4 x i32>* %A) nounwind { define arm_aapcs_vfpcc void @test_vget_laneu16() nounwind { entry: -; CHECK: vmov.u16 r0, d0[1] +; CHECK: vmov.u16 r0, d{{.*}}[1] %arg0_uint16x4_t = alloca <4 x i16> ; <<4 x i16>*> [#uses=1] %out_uint16_t = alloca i16 ; [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] %0 = load <4 x i16>* %arg0_uint16x4_t, align 8 ; <<4 x i16>> [#uses=1] %1 = extractelement <4 x i16> %0, i32 1 ; [#uses=1] - store i16 %1, i16* %out_uint16_t, align 2 + %2 = add i16 %1, %1 + store i16 %2, i16* %out_uint16_t, align 2 br label %return return: ; preds = %entry @@ -111,13 +112,14 @@ return: ; preds = %entry define arm_aapcs_vfpcc void @test_vget_laneu8() nounwind { entry: -; CHECK: vmov.u8 r0, d0[1] +; CHECK: vmov.u8 r0, d{{.*}}[1] %arg0_uint8x8_t = alloca <8 x i8> ; <<8 x i8>*> [#uses=1] %out_uint8_t = alloca i8 ; [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] %0 = load <8 x i8>* %arg0_uint8x8_t, align 8 ; <<8 x i8>> [#uses=1] %1 = extractelement <8 x i8> %0, i32 1 ; [#uses=1] - store i8 %1, i8* %out_uint8_t, align 1 + %2 = add i8 %1, %1 + store i8 %2, i8* %out_uint8_t, align 1 br label %return return: ; preds = %entry @@ -126,13 +128,14 @@ return: ; preds = %entry define arm_aapcs_vfpcc void @test_vgetQ_laneu16() nounwind { entry: -; CHECK: vmov.u16 r0, d0[1] +; CHECK: vmov.u16 r0, d{{.*}}[1] %arg0_uint16x8_t = alloca <8 x i16> ; <<8 x i16>*> [#uses=1] %out_uint16_t = alloca i16 ; [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] %0 = load <8 x i16>* %arg0_uint16x8_t, align 16 ; <<8 x i16>> [#uses=1] %1 = extractelement <8 x i16> %0, i32 1 ; [#uses=1] - store i16 %1, i16* %out_uint16_t, align 2 + %2 = add i16 %1, %1 + store i16 %2, i16* %out_uint16_t, align 2 br label %return return: ; preds = %entry @@ -141,13 +144,14 @@ return: ; preds = %entry define arm_aapcs_vfpcc void @test_vgetQ_laneu8() nounwind { entry: -; CHECK: vmov.u8 r0, d0[1] +; CHECK: vmov.u8 r0, d{{.*}}[1] %arg0_uint8x16_t = alloca <16 x i8> ; <<16 x i8>*> [#uses=1] %out_uint8_t = alloca i8 ; [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] %0 = load <16 x i8>* %arg0_uint8x16_t, align 16 ; <<16 x i8>> [#uses=1] %1 = extractelement <16 x i8> %0, i32 1 ; [#uses=1] - store i8 %1, i8* %out_uint8_t, align 1 + %2 = add i8 %1, %1 + store i8 %2, i8* %out_uint8_t, align 1 br label %return return: ; preds = %entry @@ -210,3 +214,20 @@ entry: %0 = insertelement <2 x float> %arg1_float32x2_t, float %arg0_float32_t, i32 1 ; <<2 x float>> [#uses=1] ret <2 x float> %0 } + +; The llvm extractelement instruction does not require that the lane number +; be an immediate constant. Make sure a variable lane number is handled. + +define i32 @vget_variable_lanes8(<8 x i8>* %A, i32 %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = extractelement <8 x i8> %tmp1, i32 %B + %tmp3 = sext i8 %tmp2 to i32 + ret i32 %tmp3 +} + +define i32 @vgetQ_variable_lanei32(<4 x i32>* %A, i32 %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = add <4 x i32> %tmp1, %tmp1 + %tmp3 = extractelement <4 x i32> %tmp2, i32 %B + ret i32 %tmp3 +} diff --git a/test/CodeGen/ARM/vld1.ll b/test/CodeGen/ARM/vld1.ll index 2488e8a..c886125 100644 --- a/test/CodeGen/ARM/vld1.ll +++ b/test/CodeGen/ARM/vld1.ll @@ -2,8 +2,9 @@ define <8 x i8> @vld1i8(i8* %A) nounwind { ;CHECK: vld1i8: -;CHECK: vld1.8 - %tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %A, i32 1) +;Check the alignment value. Max for this instruction is 64 bits: +;CHECK: vld1.8 {d16}, [r0, :64] + %tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %A, i32 16) ret <8 x i8> %tmp1 } @@ -15,6 +16,18 @@ define <4 x i16> @vld1i16(i16* %A) nounwind { ret <4 x i16> %tmp1 } +;Check for a post-increment updating load. +define <4 x i16> @vld1i16_update(i16** %ptr) nounwind { +;CHECK: vld1i16_update: +;CHECK: vld1.16 {d16}, [r1]! + %A = load i16** %ptr + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 1) + %tmp2 = getelementptr i16* %A, i32 4 + store i16* %tmp2, i16** %ptr + ret <4 x i16> %tmp1 +} + define <2 x i32> @vld1i32(i32* %A) nounwind { ;CHECK: vld1i32: ;CHECK: vld1.32 @@ -23,6 +36,18 @@ define <2 x i32> @vld1i32(i32* %A) nounwind { ret <2 x i32> %tmp1 } +;Check for a post-increment updating load with register increment. +define <2 x i32> @vld1i32_update(i32** %ptr, i32 %inc) nounwind { +;CHECK: vld1i32_update: +;CHECK: vld1.32 {d16}, [r2], r1 + %A = load i32** %ptr + %tmp0 = bitcast i32* %A to i8* + %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 1) + %tmp2 = getelementptr i32* %A, i32 %inc + store i32* %tmp2, i32** %ptr + ret <2 x i32> %tmp1 +} + define <2 x float> @vld1f(float* %A) nounwind { ;CHECK: vld1f: ;CHECK: vld1.32 @@ -41,16 +66,29 @@ define <1 x i64> @vld1i64(i64* %A) nounwind { define <16 x i8> @vld1Qi8(i8* %A) nounwind { ;CHECK: vld1Qi8: -;CHECK: vld1.8 - %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 1) +;Check the alignment value. Max for this instruction is 128 bits: +;CHECK: vld1.8 {d16, d17}, [r0, :64] + %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8) + ret <16 x i8> %tmp1 +} + +;Check for a post-increment updating load. +define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind { +;CHECK: vld1Qi8_update: +;CHECK: vld1.8 {d16, d17}, [r1, :64]! + %A = load i8** %ptr + %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8) + %tmp2 = getelementptr i8* %A, i32 16 + store i8* %tmp2, i8** %ptr ret <16 x i8> %tmp1 } define <8 x i16> @vld1Qi16(i16* %A) nounwind { ;CHECK: vld1Qi16: -;CHECK: vld1.16 +;Check the alignment value. Max for this instruction is 128 bits: +;CHECK: vld1.16 {d16, d17}, [r0, :128] %tmp0 = bitcast i16* %A to i8* - %tmp1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %tmp0, i32 1) + %tmp1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %tmp0, i32 32) ret <8 x i16> %tmp1 } diff --git a/test/CodeGen/ARM/vld2.ll b/test/CodeGen/ARM/vld2.ll index 811f6e6..29b3794 100644 --- a/test/CodeGen/ARM/vld2.ll +++ b/test/CodeGen/ARM/vld2.ll @@ -13,8 +13,9 @@ define <8 x i8> @vld2i8(i8* %A) nounwind { ;CHECK: vld2i8: -;CHECK: vld2.8 - %tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8(i8* %A, i32 1) +;Check the alignment value. Max for this instruction is 128 bits: +;CHECK: vld2.8 {d16, d17}, [r0, :64] + %tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8(i8* %A, i32 8) %tmp2 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 1 %tmp4 = add <8 x i8> %tmp2, %tmp3 @@ -23,9 +24,10 @@ define <8 x i8> @vld2i8(i8* %A) nounwind { define <4 x i16> @vld2i16(i16* %A) nounwind { ;CHECK: vld2i16: -;CHECK: vld2.16 +;Check the alignment value. Max for this instruction is 128 bits: +;CHECK: vld2.16 {d16, d17}, [r0, :128] %tmp0 = bitcast i16* %A to i8* - %tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16(i8* %tmp0, i32 1) + %tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16(i8* %tmp0, i32 32) %tmp2 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 1 %tmp4 = add <4 x i16> %tmp2, %tmp3 @@ -54,11 +56,27 @@ define <2 x float> @vld2f(float* %A) nounwind { ret <2 x float> %tmp4 } +;Check for a post-increment updating load. +define <2 x float> @vld2f_update(float** %ptr) nounwind { +;CHECK: vld2f_update: +;CHECK: vld2.32 {d16, d17}, [r1]! + %A = load float** %ptr + %tmp0 = bitcast float* %A to i8* + %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32(i8* %tmp0, i32 1) + %tmp2 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 0 + %tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 1 + %tmp4 = fadd <2 x float> %tmp2, %tmp3 + %tmp5 = getelementptr float* %A, i32 4 + store float* %tmp5, float** %ptr + ret <2 x float> %tmp4 +} + define <1 x i64> @vld2i64(i64* %A) nounwind { ;CHECK: vld2i64: -;CHECK: vld1.64 +;Check the alignment value. Max for this instruction is 128 bits: +;CHECK: vld1.64 {d16, d17}, [r0, :128] %tmp0 = bitcast i64* %A to i8* - %tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64(i8* %tmp0, i32 1) + %tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64(i8* %tmp0, i32 32) %tmp2 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 1 %tmp4 = add <1 x i64> %tmp2, %tmp3 @@ -67,19 +85,35 @@ define <1 x i64> @vld2i64(i64* %A) nounwind { define <16 x i8> @vld2Qi8(i8* %A) nounwind { ;CHECK: vld2Qi8: -;CHECK: vld2.8 - %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 1) +;Check the alignment value. Max for this instruction is 256 bits: +;CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64] + %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 8) + %tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0 + %tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1 + %tmp4 = add <16 x i8> %tmp2, %tmp3 + ret <16 x i8> %tmp4 +} + +;Check for a post-increment updating load with register increment. +define <16 x i8> @vld2Qi8_update(i8** %ptr, i32 %inc) nounwind { +;CHECK: vld2Qi8_update: +;CHECK: vld2.8 {d16, d17, d18, d19}, [r2, :128], r1 + %A = load i8** %ptr + %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 16) %tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1 %tmp4 = add <16 x i8> %tmp2, %tmp3 + %tmp5 = getelementptr i8* %A, i32 %inc + store i8* %tmp5, i8** %ptr ret <16 x i8> %tmp4 } define <8 x i16> @vld2Qi16(i16* %A) nounwind { ;CHECK: vld2Qi16: -;CHECK: vld2.16 +;Check the alignment value. Max for this instruction is 256 bits: +;CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] %tmp0 = bitcast i16* %A to i8* - %tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16(i8* %tmp0, i32 1) + %tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16(i8* %tmp0, i32 16) %tmp2 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 1 %tmp4 = add <8 x i16> %tmp2, %tmp3 @@ -88,9 +122,10 @@ define <8 x i16> @vld2Qi16(i16* %A) nounwind { define <4 x i32> @vld2Qi32(i32* %A) nounwind { ;CHECK: vld2Qi32: -;CHECK: vld2.32 +;Check the alignment value. Max for this instruction is 256 bits: +;CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256] %tmp0 = bitcast i32* %A to i8* - %tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp0, i32 1) + %tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp0, i32 64) %tmp2 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 1 %tmp4 = add <4 x i32> %tmp2, %tmp3 diff --git a/test/CodeGen/ARM/vld3.ll b/test/CodeGen/ARM/vld3.ll index 92538c3..dde530f 100644 --- a/test/CodeGen/ARM/vld3.ll +++ b/test/CodeGen/ARM/vld3.ll @@ -13,8 +13,9 @@ define <8 x i8> @vld3i8(i8* %A) nounwind { ;CHECK: vld3i8: -;CHECK: vld3.8 - %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 1) +;Check the alignment value. Max for this instruction is 64 bits: +;CHECK: vld3.8 {d16, d17, d18}, [r0, :64] + %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 32) %tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 2 %tmp4 = add <8 x i8> %tmp2, %tmp3 @@ -32,6 +33,21 @@ define <4 x i16> @vld3i16(i16* %A) nounwind { ret <4 x i16> %tmp4 } +;Check for a post-increment updating load with register increment. +define <4 x i16> @vld3i16_update(i16** %ptr, i32 %inc) nounwind { +;CHECK: vld3i16_update: +;CHECK: vld3.16 {d16, d17, d18}, [r2], r1 + %A = load i16** %ptr + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 1) + %tmp2 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 0 + %tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 2 + %tmp4 = add <4 x i16> %tmp2, %tmp3 + %tmp5 = getelementptr i16* %A, i32 %inc + store i16* %tmp5, i16** %ptr + ret <4 x i16> %tmp4 +} + define <2 x i32> @vld3i32(i32* %A) nounwind { ;CHECK: vld3i32: ;CHECK: vld3.32 @@ -56,9 +72,10 @@ define <2 x float> @vld3f(float* %A) nounwind { define <1 x i64> @vld3i64(i64* %A) nounwind { ;CHECK: vld3i64: -;CHECK: vld1.64 +;Check the alignment value. Max for this instruction is 64 bits: +;CHECK: vld1.64 {d16, d17, d18}, [r0, :64] %tmp0 = bitcast i64* %A to i8* - %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64(i8* %tmp0, i32 1) + %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64(i8* %tmp0, i32 16) %tmp2 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 2 %tmp4 = add <1 x i64> %tmp2, %tmp3 @@ -67,9 +84,10 @@ define <1 x i64> @vld3i64(i64* %A) nounwind { define <16 x i8> @vld3Qi8(i8* %A) nounwind { ;CHECK: vld3Qi8: -;CHECK: vld3.8 -;CHECK: vld3.8 - %tmp1 = call %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8(i8* %A, i32 1) +;Check the alignment value. Max for this instruction is 64 bits: +;CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! +;CHECK: vld3.8 {d17, d19, d21}, [r0, :64] + %tmp1 = call %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8(i8* %A, i32 32) %tmp2 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 2 %tmp4 = add <16 x i8> %tmp2, %tmp3 @@ -100,6 +118,22 @@ define <4 x i32> @vld3Qi32(i32* %A) nounwind { ret <4 x i32> %tmp4 } +;Check for a post-increment updating load. +define <4 x i32> @vld3Qi32_update(i32** %ptr) nounwind { +;CHECK: vld3Qi32_update: +;CHECK: vld3.32 {d16, d18, d20}, [r1]! +;CHECK: vld3.32 {d17, d19, d21}, [r1]! + %A = load i32** %ptr + %tmp0 = bitcast i32* %A to i8* + %tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32(i8* %tmp0, i32 1) + %tmp2 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 0 + %tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 2 + %tmp4 = add <4 x i32> %tmp2, %tmp3 + %tmp5 = getelementptr i32* %A, i32 12 + store i32* %tmp5, i32** %ptr + ret <4 x i32> %tmp4 +} + define <4 x float> @vld3Qf(float* %A) nounwind { ;CHECK: vld3Qf: ;CHECK: vld3.32 diff --git a/test/CodeGen/ARM/vld4.ll b/test/CodeGen/ARM/vld4.ll index d1bf957..59a73db 100644 --- a/test/CodeGen/ARM/vld4.ll +++ b/test/CodeGen/ARM/vld4.ll @@ -13,19 +13,35 @@ define <8 x i8> @vld4i8(i8* %A) nounwind { ;CHECK: vld4i8: -;CHECK: vld4.8 - %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 1) +;Check the alignment value. Max for this instruction is 256 bits: +;CHECK: vld4.8 {d16, d17, d18, d19}, [r0, :64] + %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 8) %tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 2 %tmp4 = add <8 x i8> %tmp2, %tmp3 ret <8 x i8> %tmp4 } +;Check for a post-increment updating load with register increment. +define <8 x i8> @vld4i8_update(i8** %ptr, i32 %inc) nounwind { +;CHECK: vld4i8_update: +;CHECK: vld4.8 {d16, d17, d18, d19}, [r2, :128], r1 + %A = load i8** %ptr + %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 16) + %tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0 + %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 2 + %tmp4 = add <8 x i8> %tmp2, %tmp3 + %tmp5 = getelementptr i8* %A, i32 %inc + store i8* %tmp5, i8** %ptr + ret <8 x i8> %tmp4 +} + define <4 x i16> @vld4i16(i16* %A) nounwind { ;CHECK: vld4i16: -;CHECK: vld4.16 +;Check the alignment value. Max for this instruction is 256 bits: +;CHECK: vld4.16 {d16, d17, d18, d19}, [r0, :128] %tmp0 = bitcast i16* %A to i8* - %tmp1 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16(i8* %tmp0, i32 1) + %tmp1 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16(i8* %tmp0, i32 16) %tmp2 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 2 %tmp4 = add <4 x i16> %tmp2, %tmp3 @@ -34,9 +50,10 @@ define <4 x i16> @vld4i16(i16* %A) nounwind { define <2 x i32> @vld4i32(i32* %A) nounwind { ;CHECK: vld4i32: -;CHECK: vld4.32 +;Check the alignment value. Max for this instruction is 256 bits: +;CHECK: vld4.32 {d16, d17, d18, d19}, [r0, :256] %tmp0 = bitcast i32* %A to i8* - %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8* %tmp0, i32 1) + %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8* %tmp0, i32 32) %tmp2 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 2 %tmp4 = add <2 x i32> %tmp2, %tmp3 @@ -56,9 +73,10 @@ define <2 x float> @vld4f(float* %A) nounwind { define <1 x i64> @vld4i64(i64* %A) nounwind { ;CHECK: vld4i64: -;CHECK: vld1.64 +;Check the alignment value. Max for this instruction is 256 bits: +;CHECK: vld1.64 {d16, d17, d18, d19}, [r0, :256] %tmp0 = bitcast i64* %A to i8* - %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i8* %tmp0, i32 1) + %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i8* %tmp0, i32 64) %tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 2 %tmp4 = add <1 x i64> %tmp2, %tmp3 @@ -67,9 +85,10 @@ define <1 x i64> @vld4i64(i64* %A) nounwind { define <16 x i8> @vld4Qi8(i8* %A) nounwind { ;CHECK: vld4Qi8: -;CHECK: vld4.8 -;CHECK: vld4.8 - %tmp1 = call %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8(i8* %A, i32 1) +;Check the alignment value. Max for this instruction is 256 bits: +;CHECK: vld4.8 {d16, d18, d20, d22}, [r0, :256]! +;CHECK: vld4.8 {d17, d19, d21, d23}, [r0, :256] + %tmp1 = call %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8(i8* %A, i32 64) %tmp2 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 2 %tmp4 = add <16 x i8> %tmp2, %tmp3 @@ -78,8 +97,9 @@ define <16 x i8> @vld4Qi8(i8* %A) nounwind { define <8 x i16> @vld4Qi16(i16* %A) nounwind { ;CHECK: vld4Qi16: -;CHECK: vld4.16 -;CHECK: vld4.16 +;Check for no alignment specifier. +;CHECK: vld4.16 {d16, d18, d20, d22}, [r0]! +;CHECK: vld4.16 {d17, d19, d21, d23}, [r0] %tmp0 = bitcast i16* %A to i8* %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8* %tmp0, i32 1) %tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0 @@ -88,6 +108,22 @@ define <8 x i16> @vld4Qi16(i16* %A) nounwind { ret <8 x i16> %tmp4 } +;Check for a post-increment updating load. +define <8 x i16> @vld4Qi16_update(i16** %ptr) nounwind { +;CHECK: vld4Qi16_update: +;CHECK: vld4.16 {d16, d18, d20, d22}, [r1, :64]! +;CHECK: vld4.16 {d17, d19, d21, d23}, [r1, :64]! + %A = load i16** %ptr + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8* %tmp0, i32 8) + %tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0 + %tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 2 + %tmp4 = add <8 x i16> %tmp2, %tmp3 + %tmp5 = getelementptr i16* %A, i32 32 + store i16* %tmp5, i16** %ptr + ret <8 x i16> %tmp4 +} + define <4 x i32> @vld4Qi32(i32* %A) nounwind { ;CHECK: vld4Qi32: ;CHECK: vld4.32 diff --git a/test/CodeGen/ARM/vlddup.ll b/test/CodeGen/ARM/vlddup.ll new file mode 100644 index 0000000..d0e9ac3 --- /dev/null +++ b/test/CodeGen/ARM/vlddup.ll @@ -0,0 +1,212 @@ +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s + +define <8 x i8> @vld1dupi8(i8* %A) nounwind { +;CHECK: vld1dupi8: +;Check the (default) alignment value. +;CHECK: vld1.8 {d16[]}, [r0] + %tmp1 = load i8* %A, align 8 + %tmp2 = insertelement <8 x i8> undef, i8 %tmp1, i32 0 + %tmp3 = shufflevector <8 x i8> %tmp2, <8 x i8> undef, <8 x i32> zeroinitializer + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vld1dupi16(i16* %A) nounwind { +;CHECK: vld1dupi16: +;Check the alignment value. Max for this instruction is 16 bits: +;CHECK: vld1.16 {d16[]}, [r0, :16] + %tmp1 = load i16* %A, align 8 + %tmp2 = insertelement <4 x i16> undef, i16 %tmp1, i32 0 + %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> undef, <4 x i32> zeroinitializer + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vld1dupi32(i32* %A) nounwind { +;CHECK: vld1dupi32: +;Check the alignment value. Max for this instruction is 32 bits: +;CHECK: vld1.32 {d16[]}, [r0, :32] + %tmp1 = load i32* %A, align 8 + %tmp2 = insertelement <2 x i32> undef, i32 %tmp1, i32 0 + %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> undef, <2 x i32> zeroinitializer + ret <2 x i32> %tmp3 +} + +define <2 x float> @vld1dupf(float* %A) nounwind { +;CHECK: vld1dupf: +;CHECK: vld1.32 {d16[]}, [r0] + %tmp0 = load float* %A + %tmp1 = insertelement <2 x float> undef, float %tmp0, i32 0 + %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer + ret <2 x float> %tmp2 +} + +define <16 x i8> @vld1dupQi8(i8* %A) nounwind { +;CHECK: vld1dupQi8: +;Check the (default) alignment value. +;CHECK: vld1.8 {d16[], d17[]}, [r0] + %tmp1 = load i8* %A, align 8 + %tmp2 = insertelement <16 x i8> undef, i8 %tmp1, i32 0 + %tmp3 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <16 x i32> zeroinitializer + ret <16 x i8> %tmp3 +} + +define <4 x float> @vld1dupQf(float* %A) nounwind { +;CHECK: vld1dupQf: +;CHECK: vld1.32 {d16[], d17[]}, [r0] + %tmp0 = load float* %A + %tmp1 = insertelement <4 x float> undef, float %tmp0, i32 0 + %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer + ret <4 x float> %tmp2 +} + +%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> } +%struct.__neon_int4x16x2_t = type { <4 x i16>, <4 x i16> } +%struct.__neon_int2x32x2_t = type { <2 x i32>, <2 x i32> } + +define <8 x i8> @vld2dupi8(i8* %A) nounwind { +;CHECK: vld2dupi8: +;Check the (default) alignment value. +;CHECK: vld2.8 {d16[], d17[]}, [r0] + %tmp0 = tail call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1) + %tmp1 = extractvalue %struct.__neon_int8x8x2_t %tmp0, 0 + %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer + %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp0, 1 + %tmp4 = shufflevector <8 x i8> %tmp3, <8 x i8> undef, <8 x i32> zeroinitializer + %tmp5 = add <8 x i8> %tmp2, %tmp4 + ret <8 x i8> %tmp5 +} + +define <4 x i16> @vld2dupi16(i16* %A) nounwind { +;CHECK: vld2dupi16: +;Check that a power-of-two alignment smaller than the total size of the memory +;being loaded is ignored. +;CHECK: vld2.16 {d16[], d17[]}, [r0] + %tmp0 = tail call %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16(i16* %A, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2) + %tmp1 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 0 + %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer + %tmp3 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 1 + %tmp4 = shufflevector <4 x i16> %tmp3, <4 x i16> undef, <4 x i32> zeroinitializer + %tmp5 = add <4 x i16> %tmp2, %tmp4 + ret <4 x i16> %tmp5 +} + +;Check for a post-increment updating load. +define <4 x i16> @vld2dupi16_update(i16** %ptr) nounwind { +;CHECK: vld2dupi16_update: +;CHECK: vld2.16 {d16[], d17[]}, [r1]! + %A = load i16** %ptr + %tmp0 = tail call %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16(i16* %A, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2) + %tmp1 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 0 + %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer + %tmp3 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 1 + %tmp4 = shufflevector <4 x i16> %tmp3, <4 x i16> undef, <4 x i32> zeroinitializer + %tmp5 = add <4 x i16> %tmp2, %tmp4 + %tmp6 = getelementptr i16* %A, i32 2 + store i16* %tmp6, i16** %ptr + ret <4 x i16> %tmp5 +} + +define <2 x i32> @vld2dupi32(i32* %A) nounwind { +;CHECK: vld2dupi32: +;Check the alignment value. Max for this instruction is 64 bits: +;CHECK: vld2.32 {d16[], d17[]}, [r0, :64] + %tmp0 = tail call %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32(i32* %A, <2 x i32> undef, <2 x i32> undef, i32 0, i32 16) + %tmp1 = extractvalue %struct.__neon_int2x32x2_t %tmp0, 0 + %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer + %tmp3 = extractvalue %struct.__neon_int2x32x2_t %tmp0, 1 + %tmp4 = shufflevector <2 x i32> %tmp3, <2 x i32> undef, <2 x i32> zeroinitializer + %tmp5 = add <2 x i32> %tmp2, %tmp4 + ret <2 x i32> %tmp5 +} + +declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly +declare %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16(i16*, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly +declare %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32(i32*, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly + +%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> } +%struct.__neon_int16x4x3_t = type { <4 x i16>, <4 x i16>, <4 x i16> } + +;Check for a post-increment updating load with register increment. +define <8 x i8> @vld3dupi8_update(i8** %ptr, i32 %inc) nounwind { +;CHECK: vld3dupi8_update: +;CHECK: vld3.8 {d16[], d17[], d18[]}, [r2], r1 + %A = load i8** %ptr + %tmp0 = tail call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8* %A, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, i32 0, i32 8) + %tmp1 = extractvalue %struct.__neon_int8x8x3_t %tmp0, 0 + %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer + %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp0, 1 + %tmp4 = shufflevector <8 x i8> %tmp3, <8 x i8> undef, <8 x i32> zeroinitializer + %tmp5 = extractvalue %struct.__neon_int8x8x3_t %tmp0, 2 + %tmp6 = shufflevector <8 x i8> %tmp5, <8 x i8> undef, <8 x i32> zeroinitializer + %tmp7 = add <8 x i8> %tmp2, %tmp4 + %tmp8 = add <8 x i8> %tmp7, %tmp6 + %tmp9 = getelementptr i8* %A, i32 %inc + store i8* %tmp9, i8** %ptr + ret <8 x i8> %tmp8 +} + +define <4 x i16> @vld3dupi16(i16* %A) nounwind { +;CHECK: vld3dupi16: +;Check the (default) alignment value. VLD3 does not support alignment. +;CHECK: vld3.16 {d16[], d17[], d18[]}, [r0] + %tmp0 = tail call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i16* %A, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 8) + %tmp1 = extractvalue %struct.__neon_int16x4x3_t %tmp0, 0 + %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer + %tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp0, 1 + %tmp4 = shufflevector <4 x i16> %tmp3, <4 x i16> undef, <4 x i32> zeroinitializer + %tmp5 = extractvalue %struct.__neon_int16x4x3_t %tmp0, 2 + %tmp6 = shufflevector <4 x i16> %tmp5, <4 x i16> undef, <4 x i32> zeroinitializer + %tmp7 = add <4 x i16> %tmp2, %tmp4 + %tmp8 = add <4 x i16> %tmp7, %tmp6 + ret <4 x i16> %tmp8 +} + +declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly +declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i16*, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly + +%struct.__neon_int16x4x4_t = type { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } +%struct.__neon_int32x2x4_t = type { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } + +;Check for a post-increment updating load. +define <4 x i16> @vld4dupi16_update(i16** %ptr) nounwind { +;CHECK: vld4dupi16_update: +;CHECK: vld4.16 {d16[], d17[], d18[], d19[]}, [r1]! + %A = load i16** %ptr + %tmp0 = tail call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16(i16* %A, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 1) + %tmp1 = extractvalue %struct.__neon_int16x4x4_t %tmp0, 0 + %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer + %tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp0, 1 + %tmp4 = shufflevector <4 x i16> %tmp3, <4 x i16> undef, <4 x i32> zeroinitializer + %tmp5 = extractvalue %struct.__neon_int16x4x4_t %tmp0, 2 + %tmp6 = shufflevector <4 x i16> %tmp5, <4 x i16> undef, <4 x i32> zeroinitializer + %tmp7 = extractvalue %struct.__neon_int16x4x4_t %tmp0, 3 + %tmp8 = shufflevector <4 x i16> %tmp7, <4 x i16> undef, <4 x i32> zeroinitializer + %tmp9 = add <4 x i16> %tmp2, %tmp4 + %tmp10 = add <4 x i16> %tmp6, %tmp8 + %tmp11 = add <4 x i16> %tmp9, %tmp10 + %tmp12 = getelementptr i16* %A, i32 4 + store i16* %tmp12, i16** %ptr + ret <4 x i16> %tmp11 +} + +define <2 x i32> @vld4dupi32(i32* %A) nounwind { +;CHECK: vld4dupi32: +;Check the alignment value. An 8-byte alignment is allowed here even though +;it is smaller than the total size of the memory being loaded. +;CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, [r0, :64] + %tmp0 = tail call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i32* %A, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, i32 0, i32 8) + %tmp1 = extractvalue %struct.__neon_int32x2x4_t %tmp0, 0 + %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer + %tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp0, 1 + %tmp4 = shufflevector <2 x i32> %tmp3, <2 x i32> undef, <2 x i32> zeroinitializer + %tmp5 = extractvalue %struct.__neon_int32x2x4_t %tmp0, 2 + %tmp6 = shufflevector <2 x i32> %tmp5, <2 x i32> undef, <2 x i32> zeroinitializer + %tmp7 = extractvalue %struct.__neon_int32x2x4_t %tmp0, 3 + %tmp8 = shufflevector <2 x i32> %tmp7, <2 x i32> undef, <2 x i32> zeroinitializer + %tmp9 = add <2 x i32> %tmp2, %tmp4 + %tmp10 = add <2 x i32> %tmp6, %tmp8 + %tmp11 = add <2 x i32> %tmp9, %tmp10 + ret <2 x i32> %tmp11 +} + +declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16(i16*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly +declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i32*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly diff --git a/test/CodeGen/ARM/vldlane.ll b/test/CodeGen/ARM/vldlane.ll index 31ee64f..770ed07 100644 --- a/test/CodeGen/ARM/vldlane.ll +++ b/test/CodeGen/ARM/vldlane.ll @@ -1,5 +1,80 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind { +;CHECK: vld1lanei8: +;Check the (default) alignment value. +;CHECK: vld1.8 {d16[3]}, [r0] + %tmp1 = load <8 x i8>* %B + %tmp2 = load i8* %A, align 8 + %tmp3 = insertelement <8 x i8> %tmp1, i8 %tmp2, i32 3 + ret <8 x i8> %tmp3 +} + +define <4 x i16> @vld1lanei16(i16* %A, <4 x i16>* %B) nounwind { +;CHECK: vld1lanei16: +;Check the alignment value. Max for this instruction is 16 bits: +;CHECK: vld1.16 {d16[2]}, [r0, :16] + %tmp1 = load <4 x i16>* %B + %tmp2 = load i16* %A, align 8 + %tmp3 = insertelement <4 x i16> %tmp1, i16 %tmp2, i32 2 + ret <4 x i16> %tmp3 +} + +define <2 x i32> @vld1lanei32(i32* %A, <2 x i32>* %B) nounwind { +;CHECK: vld1lanei32: +;Check the alignment value. Max for this instruction is 32 bits: +;CHECK: vld1.32 {d16[1]}, [r0, :32] + %tmp1 = load <2 x i32>* %B + %tmp2 = load i32* %A, align 8 + %tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1 + ret <2 x i32> %tmp3 +} + +define <2 x float> @vld1lanef(float* %A, <2 x float>* %B) nounwind { +;CHECK: vld1lanef: +;CHECK: vld1.32 {d16[1]}, [r0] + %tmp1 = load <2 x float>* %B + %tmp2 = load float* %A, align 4 + %tmp3 = insertelement <2 x float> %tmp1, float %tmp2, i32 1 + ret <2 x float> %tmp3 +} + +define <16 x i8> @vld1laneQi8(i8* %A, <16 x i8>* %B) nounwind { +;CHECK: vld1laneQi8: +;CHECK: vld1.8 {d17[1]}, [r0] + %tmp1 = load <16 x i8>* %B + %tmp2 = load i8* %A, align 8 + %tmp3 = insertelement <16 x i8> %tmp1, i8 %tmp2, i32 9 + ret <16 x i8> %tmp3 +} + +define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind { +;CHECK: vld1laneQi16: +;CHECK: vld1.16 {d17[1]}, [r0, :16] + %tmp1 = load <8 x i16>* %B + %tmp2 = load i16* %A, align 8 + %tmp3 = insertelement <8 x i16> %tmp1, i16 %tmp2, i32 5 + ret <8 x i16> %tmp3 +} + +define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind { +;CHECK: vld1laneQi32: +;CHECK: vld1.32 {d17[1]}, [r0, :32] + %tmp1 = load <4 x i32>* %B + %tmp2 = load i32* %A, align 8 + %tmp3 = insertelement <4 x i32> %tmp1, i32 %tmp2, i32 3 + ret <4 x i32> %tmp3 +} + +define <4 x float> @vld1laneQf(float* %A, <4 x float>* %B) nounwind { +;CHECK: vld1laneQf: +;CHECK: vld1.32 {d16[0]}, [r0] + %tmp1 = load <4 x float>* %B + %tmp2 = load float* %A + %tmp3 = insertelement <4 x float> %tmp1, float %tmp2, i32 0 + ret <4 x float> %tmp3 +} + %struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> } %struct.__neon_int16x4x2_t = type { <4 x i16>, <4 x i16> } %struct.__neon_int32x2x2_t = type { <2 x i32>, <2 x i32> } @@ -11,9 +86,10 @@ define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK: vld2lanei8: -;CHECK: vld2.8 +;Check the alignment value. Max for this instruction is 16 bits: +;CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] %tmp1 = load <8 x i8>* %B - %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) + %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4) %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1 %tmp5 = add <8 x i8> %tmp3, %tmp4 @@ -22,10 +98,11 @@ define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vld2lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vld2lanei16: -;CHECK: vld2.16 +;Check the alignment value. Max for this instruction is 32 bits: +;CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - %tmp2 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 1) + %tmp2 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8) %tmp3 = extractvalue %struct.__neon_int16x4x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x4x2_t %tmp2, 1 %tmp5 = add <4 x i16> %tmp3, %tmp4 @@ -44,6 +121,22 @@ define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind { ret <2 x i32> %tmp5 } +;Check for a post-increment updating load. +define <2 x i32> @vld2lanei32_update(i32** %ptr, <2 x i32>* %B) nounwind { +;CHECK: vld2lanei32_update: +;CHECK: vld2.32 {d16[1], d17[1]}, [r1]! + %A = load i32** %ptr + %tmp0 = bitcast i32* %A to i8* + %tmp1 = load <2 x i32>* %B + %tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1) + %tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 0 + %tmp4 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 1 + %tmp5 = add <2 x i32> %tmp3, %tmp4 + %tmp6 = getelementptr i32* %A, i32 2 + store i32* %tmp6, i32** %ptr + ret <2 x i32> %tmp5 +} + define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK: vld2lanef: ;CHECK: vld2.32 @@ -58,10 +151,11 @@ define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind { define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vld2laneQi16: -;CHECK: vld2.16 +;Check the (default) alignment. +;CHECK: vld2.16 {d17[1], d19[1]}, [r0] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 1) + %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 5, i32 1) %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 1 %tmp5 = add <8 x i16> %tmp3, %tmp4 @@ -70,10 +164,11 @@ define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vld2laneQi32: -;CHECK: vld2.32 +;Check the alignment value. Max for this instruction is 64 bits: +;CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B - %tmp2 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 1) + %tmp2 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16) %tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 1 %tmp5 = add <4 x i32> %tmp3, %tmp4 @@ -125,10 +220,11 @@ define <8 x i8> @vld3lanei8(i8* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vld3lanei16: -;CHECK: vld3.16 +;Check the (default) alignment value. VLD3 does not support alignment. +;CHECK: vld3.16 {d16[1], d17[1], d18[1]}, [r0] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - %tmp2 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 1) + %tmp2 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8) %tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 2 @@ -167,10 +263,11 @@ define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind { define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vld3laneQi16: -;CHECK: vld3.16 +;Check the (default) alignment value. VLD3 does not support alignment. +;CHECK: vld3.16 {d16[1], d18[1], d20[1]}, [r0] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 1) + %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 8) %tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 2 @@ -179,6 +276,24 @@ define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind { ret <8 x i16> %tmp7 } +;Check for a post-increment updating load with register increment. +define <8 x i16> @vld3laneQi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind { +;CHECK: vld3laneQi16_update: +;CHECK: vld3.16 {d16[1], d18[1], d20[1]}, [r2], r1 + %A = load i16** %ptr + %tmp0 = bitcast i16* %A to i8* + %tmp1 = load <8 x i16>* %B + %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 8) + %tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 0 + %tmp4 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 1 + %tmp5 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 2 + %tmp6 = add <8 x i16> %tmp3, %tmp4 + %tmp7 = add <8 x i16> %tmp5, %tmp6 + %tmp8 = getelementptr i16* %A, i32 %inc + store i16* %tmp8, i16** %ptr + ret <8 x i16> %tmp7 +} + define <4 x i32> @vld3laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vld3laneQi32: ;CHECK: vld3.32 @@ -227,9 +342,10 @@ declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(i8*, <4 x flo define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK: vld4lanei8: -;CHECK: vld4.8 +;Check the alignment value. Max for this instruction is 32 bits: +;CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] %tmp1 = load <8 x i8>* %B - %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) + %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8) %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2 @@ -240,12 +356,33 @@ define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind { ret <8 x i8> %tmp9 } +;Check for a post-increment updating load. +define <8 x i8> @vld4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind { +;CHECK: vld4lanei8_update: +;CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32]! + %A = load i8** %ptr + %tmp1 = load <8 x i8>* %B + %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8) + %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0 + %tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1 + %tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2 + %tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3 + %tmp7 = add <8 x i8> %tmp3, %tmp4 + %tmp8 = add <8 x i8> %tmp5, %tmp6 + %tmp9 = add <8 x i8> %tmp7, %tmp8 + %tmp10 = getelementptr i8* %A, i32 4 + store i8* %tmp10, i8** %ptr + ret <8 x i8> %tmp9 +} + define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vld4lanei16: -;CHECK: vld4.16 +;Check that a power-of-two alignment smaller than the total size of the memory +;being loaded is ignored. +;CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - %tmp2 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 1) + %tmp2 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 4) %tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 2 @@ -258,10 +395,12 @@ define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vld4lanei32: -;CHECK: vld4.32 +;Check the alignment value. An 8-byte alignment is allowed here even though +;it is smaller than the total size of the memory being loaded. +;CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :64] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B - %tmp2 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1) + %tmp2 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 8) %tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 2 @@ -290,10 +429,11 @@ define <2 x float> @vld4lanef(float* %A, <2 x float>* %B) nounwind { define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vld4laneQi16: -;CHECK: vld4.16 +;Check the alignment value. Max for this instruction is 64 bits: +;CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - %tmp2 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 1) + %tmp2 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 16) %tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 2 @@ -306,10 +446,11 @@ define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vld4laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vld4laneQi32: -;CHECK: vld4.32 +;Check the (default) alignment. +;CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B - %tmp2 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 1, i32 1) + %tmp2 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 1) %tmp3 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 2 @@ -344,3 +485,22 @@ declare %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4lane.v2f32(i8*, <2 x flo declare %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly declare %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind readonly declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind readonly + +; Radar 8776599: If one of the operands to a QQQQ REG_SEQUENCE is a register +; in the QPR_VFP2 regclass, it needs to be copied to a QPR regclass because +; we don't currently have a QQQQ_VFP2 super-regclass. (The "0" for the low +; part of %ins67 is supposed to be loaded by a VLDRS instruction in this test.) +define void @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind { +;CHECK: test_qqqq_regsequence_subreg +;CHECK: vld3.16 + %tmp63 = extractvalue [6 x i64] %b, 5 + %tmp64 = zext i64 %tmp63 to i128 + %tmp65 = shl i128 %tmp64, 64 + %ins67 = or i128 %tmp65, 0 + %tmp78 = bitcast i128 %ins67 to <8 x i16> + %vld3_lane = tail call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> %tmp78, i32 1, i32 2) + call void @llvm.trap() + unreachable +} + +declare void @llvm.trap() nounwind diff --git a/test/CodeGen/ARM/vmov.ll b/test/CodeGen/ARM/vmov.ll index 8cd9457..a86be32b 100644 --- a/test/CodeGen/ARM/vmov.ll +++ b/test/CodeGen/ARM/vmov.ll @@ -2,169 +2,169 @@ define <8 x i8> @v_movi8() nounwind { ;CHECK: v_movi8: -;CHECK: vmov.i8 d0, #0x8 +;CHECK: vmov.i8 d{{.*}}, #0x8 ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > } define <4 x i16> @v_movi16a() nounwind { ;CHECK: v_movi16a: -;CHECK: vmov.i16 d0, #0x10 +;CHECK: vmov.i16 d{{.*}}, #0x10 ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 > } define <4 x i16> @v_movi16b() nounwind { ;CHECK: v_movi16b: -;CHECK: vmov.i16 d0, #0x1000 +;CHECK: vmov.i16 d{{.*}}, #0x1000 ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 > } define <4 x i16> @v_mvni16a() nounwind { ;CHECK: v_mvni16a: -;CHECK: vmvn.i16 d0, #0x10 +;CHECK: vmvn.i16 d{{.*}}, #0x10 ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 > } define <4 x i16> @v_mvni16b() nounwind { ;CHECK: v_mvni16b: -;CHECK: vmvn.i16 d0, #0x1000 +;CHECK: vmvn.i16 d{{.*}}, #0x1000 ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 > } define <2 x i32> @v_movi32a() nounwind { ;CHECK: v_movi32a: -;CHECK: vmov.i32 d0, #0x20 +;CHECK: vmov.i32 d{{.*}}, #0x20 ret <2 x i32> < i32 32, i32 32 > } define <2 x i32> @v_movi32b() nounwind { ;CHECK: v_movi32b: -;CHECK: vmov.i32 d0, #0x2000 +;CHECK: vmov.i32 d{{.*}}, #0x2000 ret <2 x i32> < i32 8192, i32 8192 > } define <2 x i32> @v_movi32c() nounwind { ;CHECK: v_movi32c: -;CHECK: vmov.i32 d0, #0x200000 +;CHECK: vmov.i32 d{{.*}}, #0x200000 ret <2 x i32> < i32 2097152, i32 2097152 > } define <2 x i32> @v_movi32d() nounwind { ;CHECK: v_movi32d: -;CHECK: vmov.i32 d0, #0x20000000 +;CHECK: vmov.i32 d{{.*}}, #0x20000000 ret <2 x i32> < i32 536870912, i32 536870912 > } define <2 x i32> @v_movi32e() nounwind { ;CHECK: v_movi32e: -;CHECK: vmov.i32 d0, #0x20FF +;CHECK: vmov.i32 d{{.*}}, #0x20FF ret <2 x i32> < i32 8447, i32 8447 > } define <2 x i32> @v_movi32f() nounwind { ;CHECK: v_movi32f: -;CHECK: vmov.i32 d0, #0x20FFFF +;CHECK: vmov.i32 d{{.*}}, #0x20FFFF ret <2 x i32> < i32 2162687, i32 2162687 > } define <2 x i32> @v_mvni32a() nounwind { ;CHECK: v_mvni32a: -;CHECK: vmvn.i32 d0, #0x20 +;CHECK: vmvn.i32 d{{.*}}, #0x20 ret <2 x i32> < i32 4294967263, i32 4294967263 > } define <2 x i32> @v_mvni32b() nounwind { ;CHECK: v_mvni32b: -;CHECK: vmvn.i32 d0, #0x2000 +;CHECK: vmvn.i32 d{{.*}}, #0x2000 ret <2 x i32> < i32 4294959103, i32 4294959103 > } define <2 x i32> @v_mvni32c() nounwind { ;CHECK: v_mvni32c: -;CHECK: vmvn.i32 d0, #0x200000 +;CHECK: vmvn.i32 d{{.*}}, #0x200000 ret <2 x i32> < i32 4292870143, i32 4292870143 > } define <2 x i32> @v_mvni32d() nounwind { ;CHECK: v_mvni32d: -;CHECK: vmvn.i32 d0, #0x20000000 +;CHECK: vmvn.i32 d{{.*}}, #0x20000000 ret <2 x i32> < i32 3758096383, i32 3758096383 > } define <2 x i32> @v_mvni32e() nounwind { ;CHECK: v_mvni32e: -;CHECK: vmvn.i32 d0, #0x20FF +;CHECK: vmvn.i32 d{{.*}}, #0x20FF ret <2 x i32> < i32 4294958848, i32 4294958848 > } define <2 x i32> @v_mvni32f() nounwind { ;CHECK: v_mvni32f: -;CHECK: vmvn.i32 d0, #0x20FFFF +;CHECK: vmvn.i32 d{{.*}}, #0x20FFFF ret <2 x i32> < i32 4292804608, i32 4292804608 > } define <1 x i64> @v_movi64() nounwind { ;CHECK: v_movi64: -;CHECK: vmov.i64 d0, #0xFF0000FF0000FFFF +;CHECK: vmov.i64 d{{.*}}, #0xFF0000FF0000FFFF ret <1 x i64> < i64 18374687574888349695 > } define <16 x i8> @v_movQi8() nounwind { ;CHECK: v_movQi8: -;CHECK: vmov.i8 q0, #0x8 +;CHECK: vmov.i8 q{{.*}}, #0x8 ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > } define <8 x i16> @v_movQi16a() nounwind { ;CHECK: v_movQi16a: -;CHECK: vmov.i16 q0, #0x10 +;CHECK: vmov.i16 q{{.*}}, #0x10 ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 > } define <8 x i16> @v_movQi16b() nounwind { ;CHECK: v_movQi16b: -;CHECK: vmov.i16 q0, #0x1000 +;CHECK: vmov.i16 q{{.*}}, #0x1000 ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 > } define <4 x i32> @v_movQi32a() nounwind { ;CHECK: v_movQi32a: -;CHECK: vmov.i32 q0, #0x20 +;CHECK: vmov.i32 q{{.*}}, #0x20 ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 > } define <4 x i32> @v_movQi32b() nounwind { ;CHECK: v_movQi32b: -;CHECK: vmov.i32 q0, #0x2000 +;CHECK: vmov.i32 q{{.*}}, #0x2000 ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 > } define <4 x i32> @v_movQi32c() nounwind { ;CHECK: v_movQi32c: -;CHECK: vmov.i32 q0, #0x200000 +;CHECK: vmov.i32 q{{.*}}, #0x200000 ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 > } define <4 x i32> @v_movQi32d() nounwind { ;CHECK: v_movQi32d: -;CHECK: vmov.i32 q0, #0x20000000 +;CHECK: vmov.i32 q{{.*}}, #0x20000000 ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 > } define <4 x i32> @v_movQi32e() nounwind { ;CHECK: v_movQi32e: -;CHECK: vmov.i32 q0, #0x20FF +;CHECK: vmov.i32 q{{.*}}, #0x20FF ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 > } define <4 x i32> @v_movQi32f() nounwind { ;CHECK: v_movQi32f: -;CHECK: vmov.i32 q0, #0x20FFFF +;CHECK: vmov.i32 q{{.*}}, #0x20FFFF ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 > } define <2 x i64> @v_movQi64() nounwind { ;CHECK: v_movQi64: -;CHECK: vmov.i64 q0, #0xFF0000FF0000FFFF +;CHECK: vmov.i64 q{{.*}}, #0xFF0000FF0000FFFF ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 > } @@ -173,7 +173,7 @@ define <2 x i64> @v_movQi64() nounwind { define void @vdupn128(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { entry: ;CHECK: vdupn128: -;CHECK: vmov.i8 d0, #0x80 +;CHECK: vmov.i8 d{{.*}}, #0x80 %0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1] store <8 x i8> , <8 x i8>* %0, align 8 ret void @@ -182,7 +182,7 @@ entry: define void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { entry: ;CHECK: vdupnneg75: -;CHECK: vmov.i8 d0, #0xB5 +;CHECK: vmov.i8 d{{.*}}, #0xB5 %0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1] store <8 x i8> , <8 x i8>* %0, align 8 ret void @@ -343,3 +343,13 @@ declare <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64>) nounwind readnone declare <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16>) nounwind readnone declare <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32>) nounwind readnone declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone + +; Truncating vector stores are not supported. The following should not crash. +; Radar 8598391. +define void @noTruncStore(<4 x i32>* %a, <4 x i16>* %b) nounwind { +;CHECK: vmovn + %tmp1 = load <4 x i32>* %a, align 16 + %tmp2 = trunc <4 x i32> %tmp1 to <4 x i16> + store <4 x i16> %tmp2, <4 x i16>* %b, align 8 + ret void +} diff --git a/test/CodeGen/ARM/vmul.ll b/test/CodeGen/ARM/vmul.ll index 5383425..ee033ca 100644 --- a/test/CodeGen/ARM/vmul.ll +++ b/test/CodeGen/ARM/vmul.ll @@ -267,3 +267,75 @@ entry: } declare <8 x i16> @llvm.arm.neon.vmullp.v8i16(<8 x i8>, <8 x i8>) nounwind readnone + + +; Radar 8687140 +; VMULL needs to recognize BUILD_VECTORs with sign/zero-extended elements. + +define <8 x i16> @vmull_extvec_s8(<8 x i8> %arg) nounwind { +; CHECK: vmull_extvec_s8 +; CHECK: vmull.s8 + %tmp3 = sext <8 x i8> %arg to <8 x i16> + %tmp4 = mul <8 x i16> %tmp3, + ret <8 x i16> %tmp4 +} + +define <8 x i16> @vmull_extvec_u8(<8 x i8> %arg) nounwind { +; CHECK: vmull_extvec_u8 +; CHECK: vmull.u8 + %tmp3 = zext <8 x i8> %arg to <8 x i16> + %tmp4 = mul <8 x i16> %tmp3, + ret <8 x i16> %tmp4 +} + +define <8 x i16> @vmull_noextvec_s8(<8 x i8> %arg) nounwind { +; Do not use VMULL if the BUILD_VECTOR element values are too big. +; CHECK: vmull_noextvec_s8 +; CHECK: vmovl.s8 +; CHECK: vmul.i16 + %tmp3 = sext <8 x i8> %arg to <8 x i16> + %tmp4 = mul <8 x i16> %tmp3, + ret <8 x i16> %tmp4 +} + +define <8 x i16> @vmull_noextvec_u8(<8 x i8> %arg) nounwind { +; Do not use VMULL if the BUILD_VECTOR element values are too big. +; CHECK: vmull_noextvec_u8 +; CHECK: vmovl.u8 +; CHECK: vmul.i16 + %tmp3 = zext <8 x i8> %arg to <8 x i16> + %tmp4 = mul <8 x i16> %tmp3, + ret <8 x i16> %tmp4 +} + +define <4 x i32> @vmull_extvec_s16(<4 x i16> %arg) nounwind { +; CHECK: vmull_extvec_s16 +; CHECK: vmull.s16 + %tmp3 = sext <4 x i16> %arg to <4 x i32> + %tmp4 = mul <4 x i32> %tmp3, + ret <4 x i32> %tmp4 +} + +define <4 x i32> @vmull_extvec_u16(<4 x i16> %arg) nounwind { +; CHECK: vmull_extvec_u16 +; CHECK: vmull.u16 + %tmp3 = zext <4 x i16> %arg to <4 x i32> + %tmp4 = mul <4 x i32> %tmp3, + ret <4 x i32> %tmp4 +} + +define <2 x i64> @vmull_extvec_s32(<2 x i32> %arg) nounwind { +; CHECK: vmull_extvec_s32 +; CHECK: vmull.s32 + %tmp3 = sext <2 x i32> %arg to <2 x i64> + %tmp4 = mul <2 x i64> %tmp3, + ret <2 x i64> %tmp4 +} + +define <2 x i64> @vmull_extvec_u32(<2 x i32> %arg) nounwind { +; CHECK: vmull_extvec_u32 +; CHECK: vmull.u32 + %tmp3 = zext <2 x i32> %arg to <2 x i64> + %tmp4 = mul <2 x i64> %tmp3, + ret <2 x i64> %tmp4 +} diff --git a/test/CodeGen/ARM/vrev.ll b/test/CodeGen/ARM/vrev.ll index e1fe64b..f0f9e4e 100644 --- a/test/CodeGen/ARM/vrev.ll +++ b/test/CodeGen/ARM/vrev.ll @@ -129,3 +129,21 @@ define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind { %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> ret <8 x i16> %tmp2 } + +; A vcombine feeding a VREV should not obscure things. Radar 8597007. + +define void @test_with_vcombine(<4 x float>* %v) nounwind { +;CHECK: test_with_vcombine: +;CHECK-NOT: vext +;CHECK: vrev64.32 + %tmp1 = load <4 x float>* %v, align 16 + %tmp2 = bitcast <4 x float> %tmp1 to <2 x double> + %tmp3 = extractelement <2 x double> %tmp2, i32 0 + %tmp4 = bitcast double %tmp3 to <2 x float> + %tmp5 = extractelement <2 x double> %tmp2, i32 1 + %tmp6 = bitcast double %tmp5 to <2 x float> + %tmp7 = fadd <2 x float> %tmp6, %tmp6 + %tmp8 = shufflevector <2 x float> %tmp4, <2 x float> %tmp7, <4 x i32> + store <4 x float> %tmp8, <4 x float>* %v, align 16 + ret void +} diff --git a/test/CodeGen/ARM/vst1.ll b/test/CodeGen/ARM/vst1.ll index 2b535ad..364d44b 100644 --- a/test/CodeGen/ARM/vst1.ll +++ b/test/CodeGen/ARM/vst1.ll @@ -2,9 +2,10 @@ define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK: vst1i8: -;CHECK: vst1.8 +;Check the alignment value. Max for this instruction is 64 bits: +;CHECK: vst1.8 {d16}, [r0, :64] %tmp1 = load <8 x i8>* %B - call void @llvm.arm.neon.vst1.v8i8(i8* %A, <8 x i8> %tmp1, i32 1) + call void @llvm.arm.neon.vst1.v8i8(i8* %A, <8 x i8> %tmp1, i32 16) ret void } @@ -35,6 +36,19 @@ define void @vst1f(float* %A, <2 x float>* %B) nounwind { ret void } +;Check for a post-increment updating store. +define void @vst1f_update(float** %ptr, <2 x float>* %B) nounwind { +;CHECK: vst1f_update: +;CHECK: vst1.32 {d16}, [r1]! + %A = load float** %ptr + %tmp0 = bitcast float* %A to i8* + %tmp1 = load <2 x float>* %B + call void @llvm.arm.neon.vst1.v2f32(i8* %tmp0, <2 x float> %tmp1, i32 1) + %tmp2 = getelementptr float* %A, i32 2 + store float* %tmp2, float** %ptr + ret void +} + define void @vst1i64(i64* %A, <1 x i64>* %B) nounwind { ;CHECK: vst1i64: ;CHECK: vst1.64 @@ -46,18 +60,33 @@ define void @vst1i64(i64* %A, <1 x i64>* %B) nounwind { define void @vst1Qi8(i8* %A, <16 x i8>* %B) nounwind { ;CHECK: vst1Qi8: -;CHECK: vst1.8 +;Check the alignment value. Max for this instruction is 128 bits: +;CHECK: vst1.8 {d16, d17}, [r0, :64] %tmp1 = load <16 x i8>* %B - call void @llvm.arm.neon.vst1.v16i8(i8* %A, <16 x i8> %tmp1, i32 1) + call void @llvm.arm.neon.vst1.v16i8(i8* %A, <16 x i8> %tmp1, i32 8) ret void } define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst1Qi16: -;CHECK: vst1.16 +;Check the alignment value. Max for this instruction is 128 bits: +;CHECK: vst1.16 {d16, d17}, [r0, :128] + %tmp0 = bitcast i16* %A to i8* + %tmp1 = load <8 x i16>* %B + call void @llvm.arm.neon.vst1.v8i16(i8* %tmp0, <8 x i16> %tmp1, i32 32) + ret void +} + +;Check for a post-increment updating store with register increment. +define void @vst1Qi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind { +;CHECK: vst1Qi16_update: +;CHECK: vst1.16 {d16, d17}, [r1, :64], r2 + %A = load i16** %ptr %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - call void @llvm.arm.neon.vst1.v8i16(i8* %tmp0, <8 x i16> %tmp1, i32 1) + call void @llvm.arm.neon.vst1.v8i16(i8* %tmp0, <8 x i16> %tmp1, i32 8) + %tmp2 = getelementptr i16* %A, i32 %inc + store i16* %tmp2, i16** %ptr ret void } diff --git a/test/CodeGen/ARM/vst2.ll b/test/CodeGen/ARM/vst2.ll index aed15fd..915a84b 100644 --- a/test/CodeGen/ARM/vst2.ll +++ b/test/CodeGen/ARM/vst2.ll @@ -2,18 +2,32 @@ define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK: vst2i8: -;CHECK: vst2.8 +;Check the alignment value. Max for this instruction is 128 bits: +;CHECK: vst2.8 {d16, d17}, [r0, :64] %tmp1 = load <8 x i8>* %B - call void @llvm.arm.neon.vst2.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1) + call void @llvm.arm.neon.vst2.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 8) + ret void +} + +;Check for a post-increment updating store with register increment. +define void @vst2i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind { +;CHECK: vst2i8_update: +;CHECK: vst2.8 {d16, d17}, [r1], r2 + %A = load i8** %ptr + %tmp1 = load <8 x i8>* %B + call void @llvm.arm.neon.vst2.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 4) + %tmp2 = getelementptr i8* %A, i32 %inc + store i8* %tmp2, i8** %ptr ret void } define void @vst2i16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst2i16: -;CHECK: vst2.16 +;Check the alignment value. Max for this instruction is 128 bits: +;CHECK: vst2.16 {d16, d17}, [r0, :128] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - call void @llvm.arm.neon.vst2.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) + call void @llvm.arm.neon.vst2.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 32) ret void } @@ -37,36 +51,53 @@ define void @vst2f(float* %A, <2 x float>* %B) nounwind { define void @vst2i64(i64* %A, <1 x i64>* %B) nounwind { ;CHECK: vst2i64: -;CHECK: vst1.64 +;Check the alignment value. Max for this instruction is 128 bits: +;CHECK: vst1.64 {d16, d17}, [r0, :128] + %tmp0 = bitcast i64* %A to i8* + %tmp1 = load <1 x i64>* %B + call void @llvm.arm.neon.vst2.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 32) + ret void +} + +;Check for a post-increment updating store. +define void @vst2i64_update(i64** %ptr, <1 x i64>* %B) nounwind { +;CHECK: vst2i64_update: +;CHECK: vst1.64 {d16, d17}, [r1, :64]! + %A = load i64** %ptr %tmp0 = bitcast i64* %A to i8* %tmp1 = load <1 x i64>* %B - call void @llvm.arm.neon.vst2.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 1) + call void @llvm.arm.neon.vst2.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 8) + %tmp2 = getelementptr i64* %A, i32 2 + store i64* %tmp2, i64** %ptr ret void } define void @vst2Qi8(i8* %A, <16 x i8>* %B) nounwind { ;CHECK: vst2Qi8: -;CHECK: vst2.8 +;Check the alignment value. Max for this instruction is 256 bits: +;CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64] %tmp1 = load <16 x i8>* %B - call void @llvm.arm.neon.vst2.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 1) + call void @llvm.arm.neon.vst2.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 8) ret void } define void @vst2Qi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst2Qi16: -;CHECK: vst2.16 +;Check the alignment value. Max for this instruction is 256 bits: +;CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - call void @llvm.arm.neon.vst2.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) + call void @llvm.arm.neon.vst2.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 16) ret void } define void @vst2Qi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst2Qi32: -;CHECK: vst2.32 +;Check the alignment value. Max for this instruction is 256 bits: +;CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B - call void @llvm.arm.neon.vst2.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 1) + call void @llvm.arm.neon.vst2.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 64) ret void } diff --git a/test/CodeGen/ARM/vst3.ll b/test/CodeGen/ARM/vst3.ll index 1feaed5..d262303 100644 --- a/test/CodeGen/ARM/vst3.ll +++ b/test/CodeGen/ARM/vst3.ll @@ -2,9 +2,11 @@ define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK: vst3i8: -;CHECK: vst3.8 +;Check the alignment value. Max for this instruction is 64 bits: +;This test runs at -O0 so do not check for specific register numbers. +;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}, :64] %tmp1 = load <8 x i8>* %B - call void @llvm.arm.neon.vst3.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1) + call void @llvm.arm.neon.vst3.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 32) ret void } @@ -26,6 +28,19 @@ define void @vst3i32(i32* %A, <2 x i32>* %B) nounwind { ret void } +;Check for a post-increment updating store. +define void @vst3i32_update(i32** %ptr, <2 x i32>* %B) nounwind { +;CHECK: vst3i32_update: +;CHECK: vst3.32 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]! + %A = load i32** %ptr + %tmp0 = bitcast i32* %A to i8* + %tmp1 = load <2 x i32>* %B + call void @llvm.arm.neon.vst3.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) + %tmp2 = getelementptr i32* %A, i32 6 + store i32* %tmp2, i32** %ptr + ret void +} + define void @vst3f(float* %A, <2 x float>* %B) nounwind { ;CHECK: vst3f: ;CHECK: vst3.32 @@ -37,19 +52,23 @@ define void @vst3f(float* %A, <2 x float>* %B) nounwind { define void @vst3i64(i64* %A, <1 x i64>* %B) nounwind { ;CHECK: vst3i64: -;CHECK: vst1.64 +;Check the alignment value. Max for this instruction is 64 bits: +;This test runs at -O0 so do not check for specific register numbers. +;CHECK: vst1.64 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}, :64] %tmp0 = bitcast i64* %A to i8* %tmp1 = load <1 x i64>* %B - call void @llvm.arm.neon.vst3.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 1) + call void @llvm.arm.neon.vst3.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 16) ret void } define void @vst3Qi8(i8* %A, <16 x i8>* %B) nounwind { ;CHECK: vst3Qi8: -;CHECK: vst3.8 -;CHECK: vst3.8 +;Check the alignment value. Max for this instruction is 64 bits: +;This test runs at -O0 so do not check for specific register numbers. +;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}, :64]! +;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}, :64] %tmp1 = load <16 x i8>* %B - call void @llvm.arm.neon.vst3.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 1) + call void @llvm.arm.neon.vst3.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 32) ret void } @@ -63,6 +82,20 @@ define void @vst3Qi16(i16* %A, <8 x i16>* %B) nounwind { ret void } +;Check for a post-increment updating store. +define void @vst3Qi16_update(i16** %ptr, <8 x i16>* %B) nounwind { +;CHECK: vst3Qi16_update: +;CHECK: vst3.16 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]! +;CHECK: vst3.16 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]! + %A = load i16** %ptr + %tmp0 = bitcast i16* %A to i8* + %tmp1 = load <8 x i16>* %B + call void @llvm.arm.neon.vst3.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) + %tmp2 = getelementptr i16* %A, i32 24 + store i16* %tmp2, i16** %ptr + ret void +} + define void @vst3Qi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst3Qi32: ;CHECK: vst3.32 diff --git a/test/CodeGen/ARM/vst4.ll b/test/CodeGen/ARM/vst4.ll index d302f09..e94acb6 100644 --- a/test/CodeGen/ARM/vst4.ll +++ b/test/CodeGen/ARM/vst4.ll @@ -2,27 +2,42 @@ define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK: vst4i8: -;CHECK: vst4.8 +;Check the alignment value. Max for this instruction is 256 bits: +;CHECK: vst4.8 {d16, d17, d18, d19}, [r0, :64] %tmp1 = load <8 x i8>* %B - call void @llvm.arm.neon.vst4.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1) + call void @llvm.arm.neon.vst4.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 8) + ret void +} + +;Check for a post-increment updating store with register increment. +define void @vst4i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind { +;CHECK: vst4i8_update: +;CHECK: vst4.8 {d16, d17, d18, d19}, [r1, :128], r2 + %A = load i8** %ptr + %tmp1 = load <8 x i8>* %B + call void @llvm.arm.neon.vst4.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 16) + %tmp2 = getelementptr i8* %A, i32 %inc + store i8* %tmp2, i8** %ptr ret void } define void @vst4i16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst4i16: -;CHECK: vst4.16 +;Check the alignment value. Max for this instruction is 256 bits: +;CHECK: vst4.16 {d16, d17, d18, d19}, [r0, :128] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - call void @llvm.arm.neon.vst4.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) + call void @llvm.arm.neon.vst4.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 16) ret void } define void @vst4i32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst4i32: -;CHECK: vst4.32 +;Check the alignment value. Max for this instruction is 256 bits: +;CHECK: vst4.32 {d16, d17, d18, d19}, [r0, :256] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B - call void @llvm.arm.neon.vst4.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) + call void @llvm.arm.neon.vst4.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 32) ret void } @@ -37,26 +52,29 @@ define void @vst4f(float* %A, <2 x float>* %B) nounwind { define void @vst4i64(i64* %A, <1 x i64>* %B) nounwind { ;CHECK: vst4i64: -;CHECK: vst1.64 +;Check the alignment value. Max for this instruction is 256 bits: +;CHECK: vst1.64 {d16, d17, d18, d19}, [r0, :256] %tmp0 = bitcast i64* %A to i8* %tmp1 = load <1 x i64>* %B - call void @llvm.arm.neon.vst4.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 1) + call void @llvm.arm.neon.vst4.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 64) ret void } define void @vst4Qi8(i8* %A, <16 x i8>* %B) nounwind { ;CHECK: vst4Qi8: -;CHECK: vst4.8 -;CHECK: vst4.8 +;Check the alignment value. Max for this instruction is 256 bits: +;CHECK: vst4.8 {d16, d18, d20, d22}, [r0, :256]! +;CHECK: vst4.8 {d17, d19, d21, d23}, [r0, :256] %tmp1 = load <16 x i8>* %B - call void @llvm.arm.neon.vst4.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 1) + call void @llvm.arm.neon.vst4.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 64) ret void } define void @vst4Qi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst4Qi16: -;CHECK: vst4.16 -;CHECK: vst4.16 +;Check for no alignment specifier. +;CHECK: vst4.16 {d16, d18, d20, d22}, [r0]! +;CHECK: vst4.16 {d17, d19, d21, d23}, [r0] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B call void @llvm.arm.neon.vst4.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) @@ -83,6 +101,20 @@ define void @vst4Qf(float* %A, <4 x float>* %B) nounwind { ret void } +;Check for a post-increment updating store. +define void @vst4Qf_update(float** %ptr, <4 x float>* %B) nounwind { +;CHECK: vst4Qf_update: +;CHECK: vst4.32 {d16, d18, d20, d22}, [r1]! +;CHECK: vst4.32 {d17, d19, d21, d23}, [r1]! + %A = load float** %ptr + %tmp0 = bitcast float* %A to i8* + %tmp1 = load <4 x float>* %B + call void @llvm.arm.neon.vst4.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) + %tmp2 = getelementptr float* %A, i32 16 + store float* %tmp2, float** %ptr + ret void +} + declare void @llvm.arm.neon.vst4.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind declare void @llvm.arm.neon.vst4.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32) nounwind declare void @llvm.arm.neon.vst4.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind diff --git a/test/CodeGen/ARM/vstlane.ll b/test/CodeGen/ARM/vstlane.ll index 30ec52a..6cc052b 100644 --- a/test/CodeGen/ARM/vstlane.ll +++ b/test/CodeGen/ARM/vstlane.ll @@ -1,19 +1,109 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind { +;CHECK: vst1lanei8: +;Check the (default) alignment. +;CHECK: vst1.8 {d16[3]}, [r0] + %tmp1 = load <8 x i8>* %B + %tmp2 = extractelement <8 x i8> %tmp1, i32 3 + store i8 %tmp2, i8* %A, align 8 + ret void +} + +define void @vst1lanei16(i16* %A, <4 x i16>* %B) nounwind { +;CHECK: vst1lanei16: +;Check the alignment value. Max for this instruction is 16 bits: +;CHECK: vst1.16 {d16[2]}, [r0, :16] + %tmp1 = load <4 x i16>* %B + %tmp2 = extractelement <4 x i16> %tmp1, i32 2 + store i16 %tmp2, i16* %A, align 8 + ret void +} + +define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind { +;CHECK: vst1lanei32: +;Check the alignment value. Max for this instruction is 32 bits: +;CHECK: vst1.32 {d16[1]}, [r0, :32] + %tmp1 = load <2 x i32>* %B + %tmp2 = extractelement <2 x i32> %tmp1, i32 1 + store i32 %tmp2, i32* %A, align 8 + ret void +} + +define void @vst1lanef(float* %A, <2 x float>* %B) nounwind { +;CHECK: vst1lanef: +;CHECK: vst1.32 {d16[1]}, [r0] + %tmp1 = load <2 x float>* %B + %tmp2 = extractelement <2 x float> %tmp1, i32 1 + store float %tmp2, float* %A + ret void +} + +define void @vst1laneQi8(i8* %A, <16 x i8>* %B) nounwind { +;CHECK: vst1laneQi8: +;CHECK: vst1.8 {d17[1]}, [r0] + %tmp1 = load <16 x i8>* %B + %tmp2 = extractelement <16 x i8> %tmp1, i32 9 + store i8 %tmp2, i8* %A, align 8 + ret void +} + +define void @vst1laneQi16(i16* %A, <8 x i16>* %B) nounwind { +;CHECK: vst1laneQi16: +;CHECK: vst1.16 {d17[1]}, [r0, :16] + %tmp1 = load <8 x i16>* %B + %tmp2 = extractelement <8 x i16> %tmp1, i32 5 + store i16 %tmp2, i16* %A, align 8 + ret void +} + +define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind { +;CHECK: vst1laneQi32: +;CHECK: vst1.32 {d17[1]}, [r0, :32] + %tmp1 = load <4 x i32>* %B + %tmp2 = extractelement <4 x i32> %tmp1, i32 3 + store i32 %tmp2, i32* %A, align 8 + ret void +} + +define void @vst1laneQf(float* %A, <4 x float>* %B) nounwind { +;CHECK: vst1laneQf: +;CHECK: vst1.32 {d17[1]}, [r0] + %tmp1 = load <4 x float>* %B + %tmp2 = extractelement <4 x float> %tmp1, i32 3 + store float %tmp2, float* %A + ret void +} + define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK: vst2lanei8: -;CHECK: vst2.8 +;Check the alignment value. Max for this instruction is 16 bits: +;CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] %tmp1 = load <8 x i8>* %B - call void @llvm.arm.neon.vst2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) + call void @llvm.arm.neon.vst2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4) ret void } define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst2lanei16: -;CHECK: vst2.16 +;Check the alignment value. Max for this instruction is 32 bits: +;CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - call void @llvm.arm.neon.vst2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 1) + call void @llvm.arm.neon.vst2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8) + ret void +} + +;Check for a post-increment updating store with register increment. +define void @vst2lanei16_update(i16** %ptr, <4 x i16>* %B, i32 %inc) nounwind { +;CHECK: vst2lanei16_update: +;CHECK: vst2.16 {d16[1], d17[1]}, [r1], r2 + %A = load i16** %ptr + %tmp0 = bitcast i16* %A to i8* + %tmp1 = load <4 x i16>* %B + call void @llvm.arm.neon.vst2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 2) + %tmp2 = getelementptr i16* %A, i32 %inc + store i16* %tmp2, i16** %ptr ret void } @@ -37,19 +127,21 @@ define void @vst2lanef(float* %A, <2 x float>* %B) nounwind { define void @vst2laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst2laneQi16: -;CHECK: vst2.16 +;Check the (default) alignment. +;CHECK: vst2.16 {d17[1], d19[1]}, [r0] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - call void @llvm.arm.neon.vst2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 1) + call void @llvm.arm.neon.vst2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 5, i32 1) ret void } define void @vst2laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst2laneQi32: -;CHECK: vst2.32 +;Check the alignment value. Max for this instruction is 64 bits: +;CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B - call void @llvm.arm.neon.vst2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 1) + call void @llvm.arm.neon.vst2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16) ret void } @@ -81,10 +173,11 @@ define void @vst3lanei8(i8* %A, <8 x i8>* %B) nounwind { define void @vst3lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst3lanei16: -;CHECK: vst3.16 +;Check the (default) alignment value. VST3 does not support alignment. +;CHECK: vst3.16 {d16[1], d17[1], d18[1]}, [r0] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - call void @llvm.arm.neon.vst3lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 1) + call void @llvm.arm.neon.vst3lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8) ret void } @@ -108,10 +201,11 @@ define void @vst3lanef(float* %A, <2 x float>* %B) nounwind { define void @vst3laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst3laneQi16: -;CHECK: vst3.16 +;Check the (default) alignment value. VST3 does not support alignment. +;CHECK: vst3.16 {d17[2], d19[2], d21[2]}, [r0] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - call void @llvm.arm.neon.vst3lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 6, i32 1) + call void @llvm.arm.neon.vst3lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 6, i32 8) ret void } @@ -124,6 +218,19 @@ define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind { ret void } +;Check for a post-increment updating store. +define void @vst3laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind { +;CHECK: vst3laneQi32_update: +;CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r1]! + %A = load i32** %ptr + %tmp0 = bitcast i32* %A to i8* + %tmp1 = load <4 x i32>* %B + call void @llvm.arm.neon.vst3lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0, i32 1) + %tmp2 = getelementptr i32* %A, i32 3 + store i32* %tmp2, i32** %ptr + ret void +} + define void @vst3laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst3laneQf: ;CHECK: vst3.32 @@ -145,9 +252,22 @@ declare void @llvm.arm.neon.vst3lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x f define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK: vst4lanei8: -;CHECK: vst4.8 +;Check the alignment value. Max for this instruction is 32 bits: +;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] + %tmp1 = load <8 x i8>* %B + call void @llvm.arm.neon.vst4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8) + ret void +} + +;Check for a post-increment updating store. +define void @vst4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind { +;CHECK: vst4lanei8_update: +;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32]! + %A = load i8** %ptr %tmp1 = load <8 x i8>* %B - call void @llvm.arm.neon.vst4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) + call void @llvm.arm.neon.vst4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8) + %tmp2 = getelementptr i8* %A, i32 4 + store i8* %tmp2, i8** %ptr ret void } @@ -162,10 +282,11 @@ define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind { define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst4lanei32: -;CHECK: vst4.32 +;Check the alignment value. Max for this instruction is 128 bits: +;CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B - call void @llvm.arm.neon.vst4lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1) + call void @llvm.arm.neon.vst4lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 16) ret void } @@ -180,16 +301,18 @@ define void @vst4lanef(float* %A, <2 x float>* %B) nounwind { define void @vst4laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst4laneQi16: -;CHECK: vst4.16 +;Check the alignment value. Max for this instruction is 64 bits: +;CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - call void @llvm.arm.neon.vst4lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 7, i32 1) + call void @llvm.arm.neon.vst4lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 7, i32 16) ret void } define void @vst4laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst4laneQi32: -;CHECK: vst4.32 +;Check the (default) alignment. +;CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B call void @llvm.arm.neon.vst4lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 1) diff --git a/test/CodeGen/Alpha/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/Alpha/2010-04-07-DbgValueOtherTargets.ll index cf3f0b9..4590f12 100644 --- a/test/CodeGen/Alpha/2010-04-07-DbgValueOtherTargets.ll +++ b/test/CodeGen/Alpha/2010-04-07-DbgValueOtherTargets.ll @@ -1,33 +1,28 @@ ; RUN: llc -O0 -march=alpha -asm-verbose < %s | FileCheck %s ; Check that DEBUG_VALUE comments come through on a variety of targets. -%tart.reflect.ComplexType = type { double, double } - -@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } - -define i32 @"main(tart.core.String[])->int32"(i32 %args) { +define i32 @main() nounwind ssp { entry: ; CHECK: DEBUG_VALUE - tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) - tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] - ret i32 3 + call void @llvm.dbg.value(metadata !6, i64 0, metadata !7), !dbg !9 + ret i32 0, !dbg !10 } +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone -declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone -!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] -!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] -!3 = metadata !{metadata !4, metadata !6, metadata !7} -!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] -!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] -!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] -!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] -!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] -!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] -!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] -!12 = metadata !{metadata !13} -!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} +!llvm.dbg.sp = !{!0} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !"clang version 2.9 (trunk 120996)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 589860, metadata !2, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 0} +!7 = metadata !{i32 590080, metadata !8, metadata !"i", metadata !1, i32 3, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!8 = metadata !{i32 589835, metadata !0, i32 2, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!9 = metadata !{i32 3, i32 11, metadata !8, null} +!10 = metadata !{i32 4, i32 2, metadata !8, null} + diff --git a/test/CodeGen/CellSPU/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/CellSPU/2010-04-07-DbgValueOtherTargets.ll index 45d53c8..401399f 100644 --- a/test/CodeGen/CellSPU/2010-04-07-DbgValueOtherTargets.ll +++ b/test/CodeGen/CellSPU/2010-04-07-DbgValueOtherTargets.ll @@ -1,33 +1,28 @@ ; RUN: llc -O0 -march=cellspu -asm-verbose < %s | FileCheck %s ; Check that DEBUG_VALUE comments come through on a variety of targets. -%tart.reflect.ComplexType = type { double, double } - -@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } - -define i32 @"main(tart.core.String[])->int32"(i32 %args) { +define i32 @main() nounwind ssp { entry: ; CHECK: DEBUG_VALUE - tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) - tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] - ret i32 3 + call void @llvm.dbg.value(metadata !6, i64 0, metadata !7), !dbg !9 + ret i32 0, !dbg !10 } +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone -declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone -!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] -!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] -!3 = metadata !{metadata !4, metadata !6, metadata !7} -!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] -!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] -!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] -!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] -!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] -!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] -!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] -!12 = metadata !{metadata !13} -!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} +!llvm.dbg.sp = !{!0} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !"clang version 2.9 (trunk 120996)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 589860, metadata !2, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 0} +!7 = metadata !{i32 590080, metadata !8, metadata !"i", metadata !1, i32 3, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!8 = metadata !{i32 589835, metadata !0, i32 2, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!9 = metadata !{i32 3, i32 11, metadata !8, null} +!10 = metadata !{i32 4, i32 2, metadata !8, null} + diff --git a/test/CodeGen/CellSPU/arg_ret.ll b/test/CodeGen/CellSPU/arg_ret.ll index 743292a..7410b72 100644 --- a/test/CodeGen/CellSPU/arg_ret.ll +++ b/test/CodeGen/CellSPU/arg_ret.ll @@ -26,7 +26,8 @@ define ccc i32 @test_regs_and_stack( %paramstruct %prm, i32 %stackprm ) define ccc %paramstruct @test_return( i32 %param, %paramstruct %prm ) { -;CHECK: lqd $75, 80($sp) +;CHECK: lqd {{\$[0-9]+}}, 80($sp) +;CHECK-NOT: ori {{\$[0-9]+, \$[0-9]+, 0}} ;CHECK: lr $3, $4 ret %paramstruct %prm } diff --git a/test/CodeGen/CellSPU/div_ops.ll b/test/CodeGen/CellSPU/div_ops.ll new file mode 100644 index 0000000..0c93d83 --- /dev/null +++ b/test/CodeGen/CellSPU/div_ops.ll @@ -0,0 +1,22 @@ +; RUN: llc --march=cellspu %s -o - | FileCheck %s + +; signed division rounds towards zero, rotma don't. +define i32 @sdivide (i32 %val ) +{ +; CHECK: rotmai +; CHECK: rotmi +; CHECK: a +; CHECK: rotmai +; CHECK: bi $lr + %rv = sdiv i32 %val, 4 + ret i32 %rv +} + +define i32 @udivide (i32 %val ) +{ +; CHECK: rotmi +; CHECK: bi $lr + %rv = udiv i32 %val, 4 + ret i32 %rv +} + diff --git a/test/CodeGen/CellSPU/fcmp32.ll b/test/CodeGen/CellSPU/fcmp32.ll index f07fe6f..c14fd7b 100644 --- a/test/CodeGen/CellSPU/fcmp32.ll +++ b/test/CodeGen/CellSPU/fcmp32.ll @@ -1,9 +1,4 @@ -; RUN: llc < %s -march=cellspu > %t1.s -; RUN: grep fceq %t1.s | count 1 -; RUN: grep fcmeq %t1.s | count 1 - -target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" -target triple = "spu" +; RUN: llc --march=cellspu %s -o - | FileCheck %s ; Exercise the floating point comparison operators for f32: @@ -11,13 +6,31 @@ declare double @fabs(double) declare float @fabsf(float) define i1 @fcmp_eq(float %arg1, float %arg2) { +; CHECK: fceq +; CHECK: bi $lr %A = fcmp oeq float %arg1, %arg2 ret i1 %A } define i1 @fcmp_mag_eq(float %arg1, float %arg2) { +; CHECK: fcmeq +; CHECK: bi $lr %1 = call float @fabsf(float %arg1) %2 = call float @fabsf(float %arg2) %3 = fcmp oeq float %1, %2 ret i1 %3 } + +define i1 @test_ogt(float %a, float %b) { +; CHECK: fcgt +; CHECK: bi $lr + %cmp = fcmp ogt float %a, %b + ret i1 %cmp +} + +define i1 @test_ugt(float %a, float %b) { +; CHECK: fcgt +; CHECK: bi $lr + %cmp = fcmp ugt float %a, %b + ret i1 %cmp +} diff --git a/test/CodeGen/CellSPU/immed32.ll b/test/CodeGen/CellSPU/immed32.ll index 119f526..8e48f0b 100644 --- a/test/CodeGen/CellSPU/immed32.ll +++ b/test/CodeGen/CellSPU/immed32.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=cellspu > %t1.s -; RUN: grep ilhu %t1.s | count 8 -; RUN: grep iohl %t1.s | count 6 +; RUN: grep ilhu %t1.s | count 9 +; RUN: grep iohl %t1.s | count 7 ; RUN: grep -w il %t1.s | count 3 ; RUN: grep 16429 %t1.s | count 1 ; RUN: grep 63572 %t1.s | count 1 @@ -12,6 +12,7 @@ ; RUN: grep 49077 %t1.s | count 1 ; RUN: grep 1267 %t1.s | count 2 ; RUN: grep 16309 %t1.s | count 1 +; RUN: cat %t1.s | FileCheck %s target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" @@ -31,6 +32,16 @@ define i32 @test_4() { ret i32 -512 ;; IL via pattern } +define i32 @test_5() +{ +;CHECK: test_5: +;CHECK-NOT: ila $3, 40000 +;CHECK: ilhu +;CHECK: iohl +;CHECK: bi $lr + ret i32 400000 +} + ;; double float floatval ;; 0x4005bf0a80000000 0x402d|f854 2.718282 define float @float_const_1() { diff --git a/test/CodeGen/CellSPU/loads.ll b/test/CodeGen/CellSPU/loads.ll index d40217d..03d7ad1 100644 --- a/test/CodeGen/CellSPU/loads.ll +++ b/test/CodeGen/CellSPU/loads.ll @@ -38,3 +38,15 @@ define <4 x float> @load_undef(){ %val = load <4 x float>* undef ret <4 x float> %val } + +;check that 'misaligned' loads that may span two memory chunks +;have two loads. Don't check for the bitmanipulation, as that +;might change with improved algorithms or scheduling +define i32 @load_misaligned( i32* %ptr ){ +;CHECK: load_misaligned +;CHECK: lqd +;CHECK: lqd +;CHECK: bi $lr + %rv = load i32* %ptr, align 2 + ret i32 %rv +} diff --git a/test/CodeGen/CellSPU/rotate_ops.ll b/test/CodeGen/CellSPU/rotate_ops.ll index a504c00..e117208 100644 --- a/test/CodeGen/CellSPU/rotate_ops.ll +++ b/test/CodeGen/CellSPU/rotate_ops.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=cellspu -o %t1.s -; RUN: grep rot %t1.s | count 85 +; RUN: grep rot %t1.s | count 86 ; RUN: grep roth %t1.s | count 8 ; RUN: grep roti.*5 %t1.s | count 1 ; RUN: grep roti.*27 %t1.s | count 1 @@ -8,6 +8,7 @@ ; RUN grep rothi.*,.3 %t1.s | count 1 ; RUN: grep andhi %t1.s | count 4 ; RUN: grep shlhi %t1.s | count 4 +; RUN: cat %t1.s | FileCheck %s target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" @@ -158,3 +159,14 @@ define i8 @rotri8(i8 %A) { %D = or i8 %B, %C ; [#uses=1] ret i8 %D } + +define <2 x float> @test1(<4 x float> %param ) +{ +; CHECK: test1 +; CHECK: rotqbyi + %el = extractelement <4 x float> %param, i32 1 + %vec1 = insertelement <1 x float> undef, float %el, i32 0 + %rv = shufflevector <1 x float> %vec1, <1 x float> undef, <2 x i32> +; CHECK: bi $lr + ret <2 x float> %rv +} diff --git a/test/CodeGen/CellSPU/sext128.ll b/test/CodeGen/CellSPU/sext128.ll index 0c0b359..6ae9aa5 100644 --- a/test/CodeGen/CellSPU/sext128.ll +++ b/test/CodeGen/CellSPU/sext128.ll @@ -12,8 +12,9 @@ entry: ; CHECK: long 269488144 ; CHECK: long 66051 ; CHECK: long 67438087 -; CHECK: rotmai +; CHECK-NOT: rotqmbyi ; CHECK: lqa +; CHECK: rotmai ; CHECK: shufb } @@ -25,8 +26,9 @@ entry: ; CHECK: long 269488144 ; CHECK: long 269488144 ; CHECK: long 66051 -; CHECK: rotmai +; CHECK-NOT: rotqmbyi ; CHECK: lqa +; CHECK: rotmai ; CHECK: shufb } @@ -39,9 +41,31 @@ entry: ; CHECK: long 269488144 ; CHECK: long 269488144 ; CHECK: long 66051 -; CHECK: rotmai +; CHECK-NOT: rotqmbyi ; CHECK: lqa +; CHECK: rotmai ; CHECK: shufb } declare i32 @myfunc(float) + +define i128 @func1(i8 %u) { +entry: +; CHECK: xsbh +; CHECK: xshw +; CHECK: rotmai +; CHECK: shufb +; CHECK: bi $lr + %0 = sext i8 %u to i128 + ret i128 %0 +} + +define i128 @func2(i16 %u) { +entry: +; CHECK: xshw +; CHECK: rotmai +; CHECK: shufb +; CHECK: bi $lr + %0 = sext i16 %u to i128 + ret i128 %0 +} diff --git a/test/CodeGen/CellSPU/shift_ops.ll b/test/CodeGen/CellSPU/shift_ops.ll index 0264fc8..92390ab 100644 --- a/test/CodeGen/CellSPU/shift_ops.ll +++ b/test/CodeGen/CellSPU/shift_ops.ll @@ -4,17 +4,18 @@ ; RUN: grep {shl } %t1.s | count 9 ; RUN: grep {shli } %t1.s | count 3 ; RUN: grep {xshw } %t1.s | count 5 -; RUN: grep {and } %t1.s | count 5 +; RUN: grep {and } %t1.s | count 14 ; RUN: grep {andi } %t1.s | count 2 ; RUN: grep {rotmi } %t1.s | count 2 ; RUN: grep {rotqmbyi } %t1.s | count 1 ; RUN: grep {rotqmbii } %t1.s | count 2 ; RUN: grep {rotqmby } %t1.s | count 1 -; RUN: grep {rotqmbi } %t1.s | count 1 +; RUN: grep {rotqmbi } %t1.s | count 2 ; RUN: grep {rotqbyi } %t1.s | count 1 ; RUN: grep {rotqbii } %t1.s | count 2 ; RUN: grep {rotqbybi } %t1.s | count 1 -; RUN: grep {sfi } %t1.s | count 3 +; RUN: grep {sfi } %t1.s | count 4 +; RUN: cat %t1.s | FileCheck %s target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" @@ -281,3 +282,14 @@ define i32 @hi32_i64(i64 %arg) { %2 = trunc i64 %1 to i32 ret i32 %2 } + +; some random tests +define i128 @test_lshr_i128( i128 %val ) { + ;CHECK: test_lshr_i128 + ;CHECK: sfi + ;CHECK: rotqmbi + ;CHECK: rotqmbybi + ;CHECK: bi $lr + %rv = lshr i128 %val, 64 + ret i128 %rv +} diff --git a/test/CodeGen/CellSPU/shuffles.ll b/test/CodeGen/CellSPU/shuffles.ll index f37d2ae..c88a258 100644 --- a/test/CodeGen/CellSPU/shuffles.ll +++ b/test/CodeGen/CellSPU/shuffles.ll @@ -1,4 +1,4 @@ -; RUN: llc --march=cellspu < %s | FileCheck %s +; RUN: llc -O1 --march=cellspu < %s | FileCheck %s define <4 x float> @shuffle(<4 x float> %param1, <4 x float> %param2) { ; CHECK: cwd {{\$.}}, 0($sp) @@ -39,3 +39,29 @@ define <4 x float> @test_insert_1(<4 x float> %vparam, float %eltparam) { ret <4 x float> %rv } +define <2 x i32> @test_v2i32(<4 x i32>%vec) +{ +;CHECK: rotqbyi $3, $3, 4 +;CHECK: bi $lr + %rv = shufflevector <4 x i32> %vec, <4 x i32> undef, <2 x i32> + ret <2 x i32> %rv +} + +define <4 x i32> @test_v4i32_rot8(<4 x i32>%vec) +{ +;CHECK: rotqbyi $3, $3, 8 +;CHECK: bi $lr + %rv = shufflevector <4 x i32> %vec, <4 x i32> undef, + <4 x i32> + ret <4 x i32> %rv +} + +define <4 x i32> @test_v4i32_rot4(<4 x i32>%vec) +{ +;CHECK: rotqbyi $3, $3, 4 +;CHECK: bi $lr + %rv = shufflevector <4 x i32> %vec, <4 x i32> undef, + <4 x i32> + ret <4 x i32> %rv +} + diff --git a/test/CodeGen/CellSPU/stores.ll b/test/CodeGen/CellSPU/stores.ll index 05f44f4..7e0bf06 100644 --- a/test/CodeGen/CellSPU/stores.ll +++ b/test/CodeGen/CellSPU/stores.ll @@ -14,6 +14,7 @@ ; RUN: grep iohl %t1.s | count 8 ; RUN: grep shufb %t1.s | count 15 ; RUN: grep frds %t1.s | count 1 +; RUN: llc < %s -march=cellspu | FileCheck %s ; ModuleID = 'stores.bc' target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" @@ -149,3 +150,24 @@ entry: store float %conv, float* %dest ret float %conv } + +;Check stores that might span two 16 byte memory blocks +define void @store_misaligned( i32 %val, i32* %ptr) { +;CHECK: store_misaligned +;CHECK: lqd +;CHECK: lqd +;CHECK: stqd +;CHECK: stqd +;CHECK: bi $lr + store i32 %val, i32*%ptr, align 2 + ret void +} + +define void @store_v8( <8 x float> %val, <8 x float>* %ptr ) +{ +;CHECK: stq +;CHECK: stq +;CHECK: bi $lr + store <8 x float> %val, <8 x float>* %ptr + ret void +} diff --git a/test/CodeGen/CellSPU/v2f32.ll b/test/CodeGen/CellSPU/v2f32.ll index b81c0cd..efd0320 100644 --- a/test/CodeGen/CellSPU/v2f32.ll +++ b/test/CodeGen/CellSPU/v2f32.ll @@ -62,8 +62,7 @@ define %vec @test_insert(){ } define void @test_unaligned_store() { -;CHECK: cdd $3, 8($3) -;CHECK: lqd +;CHECK: cdd ;CHECK: shufb ;CHECK: stqd %data = alloca [4 x float], align 16 ; <[4 x float]*> [#uses=1] diff --git a/test/CodeGen/CellSPU/v2i32.ll b/test/CodeGen/CellSPU/v2i32.ll index dd51be5..71d4aba 100644 --- a/test/CodeGen/CellSPU/v2i32.ll +++ b/test/CodeGen/CellSPU/v2i32.ll @@ -37,9 +37,8 @@ define %vec @test_mul(%vec %param) } define <2 x i32> @test_splat(i32 %param ) { -;TODO insertelement transforms to a PREFSLOT2VEC, that trasforms to the -; somewhat redundant: -;CHECK-NOT or $3, $3, $3 +;see svn log for why this is here... +;CHECK-NOT: or $3, $3, $3 ;CHECK: lqa ;CHECK: shufb %sv = insertelement <1 x i32> undef, i32 %param, i32 0 @@ -62,3 +61,17 @@ define void @test_store( %vec %val, %vec* %ptr) store %vec %val, %vec* %ptr ret void } + +;Alignment of <2 x i32> is not *directly* defined in the ABI +;It probably is safe to interpret it as an array, thus having 8 byte +;alignment (according to ABI). This tests that the size of +;[2 x <2 x i32>] is 16 bytes, i.e. there is no padding between the +;two arrays +define <2 x i32>* @test_alignment( [2 x <2 x i32>]* %ptr) +{ +; CHECK-NOT: ai $3, $3, 16 +; CHECK: ai $3, $3, 8 +; CHECK: bi $lr + %rv = getelementptr [2 x <2 x i32>]* %ptr, i32 0, i32 1 + ret <2 x i32>* %rv +} diff --git a/test/CodeGen/Generic/2010-11-04-BigByval.ll b/test/CodeGen/Generic/2010-11-04-BigByval.ll new file mode 100644 index 0000000..df2ca4c --- /dev/null +++ b/test/CodeGen/Generic/2010-11-04-BigByval.ll @@ -0,0 +1,11 @@ +; RUN: llc < %s +; PR7170 + +%big = type [131072 x i8] + +declare void @foo(%big* byval align 1) + +define void @bar(%big* byval align 1 %x) { + call void @foo(%big* byval align 1 %x) + ret void +} diff --git a/test/CodeGen/Generic/2011-01-06-BigNumberCrash.ll b/test/CodeGen/Generic/2011-01-06-BigNumberCrash.ll new file mode 100644 index 0000000..05fdf4c --- /dev/null +++ b/test/CodeGen/Generic/2011-01-06-BigNumberCrash.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s +; PR8582 + +define void @uint82() nounwind { +entry: + %tmp3 = select i1 undef, i960 4872657003430991806293355221650511486142000513558154090491761976385142772940676648094983476628187266917101386048750715027104076737938178423519545241493072038894065019132638919037781494702597609951702322267198307200588774905587225212622510286498675097141625012190497682454879271766334636032, i960 0 + br i1 undef, label %for.body25.for.body25_crit_edge, label %if.end + +for.body25.for.body25_crit_edge: ; preds = %entry + %ins = or i960 %tmp3, undef + ret void + +if.end: ; preds = %entry + ret void +} diff --git a/test/CodeGen/Generic/2011-02-12-shuffle.ll b/test/CodeGen/Generic/2011-02-12-shuffle.ll new file mode 100644 index 0000000..b4d56d1 --- /dev/null +++ b/test/CodeGen/Generic/2011-02-12-shuffle.ll @@ -0,0 +1,32 @@ +; RUN: llc < %s +; PR9165 + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" +target triple = "i686-pc-win32" + +define void @m_387() nounwind { +entry: + br i1 undef, label %if.end, label %UnifiedReturnBlock + +if.end: ; preds = %entry + %tmp1067 = load <16 x i32> addrspace(1)* null, align 64 + %tmp1082 = shufflevector <16 x i32> , + <16 x i32> %tmp1067, + <16 x i32> + + %tmp1100 = shufflevector <16 x i32> %tmp1082, + <16 x i32> %tmp1067, + <16 x i32> + + %tmp1112 = shufflevector <16 x i32> %tmp1100, + <16 x i32> %tmp1067, + <16 x i32> + + store <16 x i32> %tmp1112, <16 x i32> addrspace(1)* undef, align 64 + + ret void + +UnifiedReturnBlock: ; preds = %entry + ret void +} + diff --git a/test/CodeGen/Generic/add-with-overflow-128.ll b/test/CodeGen/Generic/add-with-overflow-128.ll index c46c820..33f44d6 100644 --- a/test/CodeGen/Generic/add-with-overflow-128.ll +++ b/test/CodeGen/Generic/add-with-overflow-128.ll @@ -3,22 +3,7 @@ @ok = internal constant [4 x i8] c"%d\0A\00" @no = internal constant [4 x i8] c"no\0A\00" -define i1 @func1(i128 signext %v1, i128 signext %v2) nounwind { -entry: - %t = call {i128, i1} @llvm.sadd.with.overflow.i128(i128 %v1, i128 %v2) - %sum = extractvalue {i128, i1} %t, 0 - %sum32 = trunc i128 %sum to i32 - %obit = extractvalue {i128, i1} %t, 1 - br i1 %obit, label %overflow, label %normal - -normal: - %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum32 ) nounwind - ret i1 true -overflow: - %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind - ret i1 false -} define i1 @func2(i128 zeroext %v1, i128 zeroext %v2) nounwind { entry: @@ -38,5 +23,12 @@ carry: } declare i32 @printf(i8*, ...) nounwind -declare {i128, i1} @llvm.sadd.with.overflow.i128(i128, i128) +declare {i96, i1} @llvm.sadd.with.overflow.i96(i96, i96) declare {i128, i1} @llvm.uadd.with.overflow.i128(i128, i128) + +define i1 @func1(i96 signext %v1, i96 signext %v2) nounwind { +entry: + %t = call {i96, i1} @llvm.sadd.with.overflow.i96(i96 %v1, i96 %v2) + %obit = extractvalue {i96, i1} %t, 1 + ret i1 %obit +} diff --git a/test/CodeGen/Generic/crash.ll b/test/CodeGen/Generic/crash.ll index 7218565..04273988 100644 --- a/test/CodeGen/Generic/crash.ll +++ b/test/CodeGen/Generic/crash.ll @@ -6,3 +6,35 @@ @tags = global [1 x %struct.AVCodecTag*] [%struct.AVCodecTag* getelementptr inbounds ([0 x %struct.AVCodecTag]* @ff_codec_bmp_tags, i32 0, i32 0)] + +; rdar://8878965 + +%struct.CAMERA = type { [3 x double], [3 x double], [3 x double], [3 x double], [3 x double], [3 x double], double, double, i32, double, double, i32, double, i32* } + +define void @Parse_Camera(%struct.CAMERA** nocapture %Camera_Ptr) nounwind { +entry: +%.pre = load %struct.CAMERA** %Camera_Ptr, align 4 +%0 = getelementptr inbounds %struct.CAMERA* %.pre, i32 0, i32 1, i32 0 +%1 = getelementptr inbounds %struct.CAMERA* %.pre, i32 0, i32 1, i32 2 +br label %bb32 + +bb32: ; preds = %bb6 +%2 = load double* %0, align 4 +%3 = load double* %1, align 4 +%4 = load double* %0, align 4 +call void @Parse_Vector(double* %0) nounwind +%5 = call i32 @llvm.objectsize.i32(i8* undef, i1 false) +%6 = icmp eq i32 %5, -1 +br i1 %6, label %bb34, label %bb33 + +bb33: ; preds = %bb32 +unreachable + +bb34: ; preds = %bb32 +unreachable + +} + +declare void @Parse_Vector(double*) +declare i32 @llvm.objectsize.i32(i8*, i1) + diff --git a/test/CodeGen/Generic/overflow.ll b/test/CodeGen/Generic/overflow.ll new file mode 100644 index 0000000..4196855 --- /dev/null +++ b/test/CodeGen/Generic/overflow.ll @@ -0,0 +1,220 @@ +; RUN: llc < %s +; Verify codegen's don't crash on overflow intrinsics. + +;; SADD + +define zeroext i8 @sadd_i8(i8 signext %a, i8 signext %b) nounwind ssp { +entry: + %sadd = tail call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 %a, i8 %b) + %cmp = extractvalue { i8, i1 } %sadd, 1 + %sadd.result = extractvalue { i8, i1 } %sadd, 0 + %X = select i1 %cmp, i8 %sadd.result, i8 42 + ret i8 %X +} + +declare { i8, i1 } @llvm.sadd.with.overflow.i8(i8, i8) nounwind readnone + +define zeroext i16 @sadd_i16(i16 signext %a, i16 signext %b) nounwind ssp { +entry: + %sadd = tail call { i16, i1 } @llvm.sadd.with.overflow.i16(i16 %a, i16 %b) + %cmp = extractvalue { i16, i1 } %sadd, 1 + %sadd.result = extractvalue { i16, i1 } %sadd, 0 + %X = select i1 %cmp, i16 %sadd.result, i16 42 + ret i16 %X +} + +declare { i16, i1 } @llvm.sadd.with.overflow.i16(i16, i16) nounwind readnone + +define zeroext i32 @sadd_i32(i32 signext %a, i32 signext %b) nounwind ssp { +entry: + %sadd = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 %b) + %cmp = extractvalue { i32, i1 } %sadd, 1 + %sadd.result = extractvalue { i32, i1 } %sadd, 0 + %X = select i1 %cmp, i32 %sadd.result, i32 42 + ret i32 %X +} + +declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone + + +;; UADD + +define zeroext i8 @uadd_i8(i8 signext %a, i8 signext %b) nounwind ssp { +entry: + %uadd = tail call { i8, i1 } @llvm.uadd.with.overflow.i8(i8 %a, i8 %b) + %cmp = extractvalue { i8, i1 } %uadd, 1 + %uadd.result = extractvalue { i8, i1 } %uadd, 0 + %X = select i1 %cmp, i8 %uadd.result, i8 42 + ret i8 %X +} + +declare { i8, i1 } @llvm.uadd.with.overflow.i8(i8, i8) nounwind readnone + +define zeroext i16 @uadd_i16(i16 signext %a, i16 signext %b) nounwind ssp { +entry: + %uadd = tail call { i16, i1 } @llvm.uadd.with.overflow.i16(i16 %a, i16 %b) + %cmp = extractvalue { i16, i1 } %uadd, 1 + %uadd.result = extractvalue { i16, i1 } %uadd, 0 + %X = select i1 %cmp, i16 %uadd.result, i16 42 + ret i16 %X +} + +declare { i16, i1 } @llvm.uadd.with.overflow.i16(i16, i16) nounwind readnone + +define zeroext i32 @uadd_i32(i32 signext %a, i32 signext %b) nounwind ssp { +entry: + %uadd = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b) + %cmp = extractvalue { i32, i1 } %uadd, 1 + %uadd.result = extractvalue { i32, i1 } %uadd, 0 + %X = select i1 %cmp, i32 %uadd.result, i32 42 + ret i32 %X +} + +declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone + + + +;; ssub + +define zeroext i8 @ssub_i8(i8 signext %a, i8 signext %b) nounwind ssp { +entry: + %ssub = tail call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %a, i8 %b) + %cmp = extractvalue { i8, i1 } %ssub, 1 + %ssub.result = extractvalue { i8, i1 } %ssub, 0 + %X = select i1 %cmp, i8 %ssub.result, i8 42 + ret i8 %X +} + +declare { i8, i1 } @llvm.ssub.with.overflow.i8(i8, i8) nounwind readnone + +define zeroext i16 @ssub_i16(i16 signext %a, i16 signext %b) nounwind ssp { +entry: + %ssub = tail call { i16, i1 } @llvm.ssub.with.overflow.i16(i16 %a, i16 %b) + %cmp = extractvalue { i16, i1 } %ssub, 1 + %ssub.result = extractvalue { i16, i1 } %ssub, 0 + %X = select i1 %cmp, i16 %ssub.result, i16 42 + ret i16 %X +} + +declare { i16, i1 } @llvm.ssub.with.overflow.i16(i16, i16) nounwind readnone + +define zeroext i32 @ssub_i32(i32 signext %a, i32 signext %b) nounwind ssp { +entry: + %ssub = tail call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 %b) + %cmp = extractvalue { i32, i1 } %ssub, 1 + %ssub.result = extractvalue { i32, i1 } %ssub, 0 + %X = select i1 %cmp, i32 %ssub.result, i32 42 + ret i32 %X +} + +declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32) nounwind readnone + + +;; usub + +define zeroext i8 @usub_i8(i8 signext %a, i8 signext %b) nounwind ssp { +entry: + %usub = tail call { i8, i1 } @llvm.usub.with.overflow.i8(i8 %a, i8 %b) + %cmp = extractvalue { i8, i1 } %usub, 1 + %usub.result = extractvalue { i8, i1 } %usub, 0 + %X = select i1 %cmp, i8 %usub.result, i8 42 + ret i8 %X +} + +declare { i8, i1 } @llvm.usub.with.overflow.i8(i8, i8) nounwind readnone + +define zeroext i16 @usub_i16(i16 signext %a, i16 signext %b) nounwind ssp { +entry: + %usub = tail call { i16, i1 } @llvm.usub.with.overflow.i16(i16 %a, i16 %b) + %cmp = extractvalue { i16, i1 } %usub, 1 + %usub.result = extractvalue { i16, i1 } %usub, 0 + %X = select i1 %cmp, i16 %usub.result, i16 42 + ret i16 %X +} + +declare { i16, i1 } @llvm.usub.with.overflow.i16(i16, i16) nounwind readnone + +define zeroext i32 @usub_i32(i32 signext %a, i32 signext %b) nounwind ssp { +entry: + %usub = tail call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b) + %cmp = extractvalue { i32, i1 } %usub, 1 + %usub.result = extractvalue { i32, i1 } %usub, 0 + %X = select i1 %cmp, i32 %usub.result, i32 42 + ret i32 %X +} + +declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) nounwind readnone + + + +;; smul + +define zeroext i8 @smul_i8(i8 signext %a, i8 signext %b) nounwind ssp { +entry: + %smul = tail call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %a, i8 %b) + %cmp = extractvalue { i8, i1 } %smul, 1 + %smul.result = extractvalue { i8, i1 } %smul, 0 + %X = select i1 %cmp, i8 %smul.result, i8 42 + ret i8 %X +} + +declare { i8, i1 } @llvm.smul.with.overflow.i8(i8, i8) nounwind readnone + +define zeroext i16 @smul_i16(i16 signext %a, i16 signext %b) nounwind ssp { +entry: + %smul = tail call { i16, i1 } @llvm.smul.with.overflow.i16(i16 %a, i16 %b) + %cmp = extractvalue { i16, i1 } %smul, 1 + %smul.result = extractvalue { i16, i1 } %smul, 0 + %X = select i1 %cmp, i16 %smul.result, i16 42 + ret i16 %X +} + +declare { i16, i1 } @llvm.smul.with.overflow.i16(i16, i16) nounwind readnone + +define zeroext i32 @smul_i32(i32 signext %a, i32 signext %b) nounwind ssp { +entry: + %smul = tail call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %a, i32 %b) + %cmp = extractvalue { i32, i1 } %smul, 1 + %smul.result = extractvalue { i32, i1 } %smul, 0 + %X = select i1 %cmp, i32 %smul.result, i32 42 + ret i32 %X +} + +declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32) nounwind readnone + + +;; umul + +define zeroext i8 @umul_i8(i8 signext %a, i8 signext %b) nounwind ssp { +entry: + %umul = tail call { i8, i1 } @llvm.umul.with.overflow.i8(i8 %a, i8 %b) + %cmp = extractvalue { i8, i1 } %umul, 1 + %umul.result = extractvalue { i8, i1 } %umul, 0 + %X = select i1 %cmp, i8 %umul.result, i8 42 + ret i8 %X +} + +declare { i8, i1 } @llvm.umul.with.overflow.i8(i8, i8) nounwind readnone + +define zeroext i16 @umul_i16(i16 signext %a, i16 signext %b) nounwind ssp { +entry: + %umul = tail call { i16, i1 } @llvm.umul.with.overflow.i16(i16 %a, i16 %b) + %cmp = extractvalue { i16, i1 } %umul, 1 + %umul.result = extractvalue { i16, i1 } %umul, 0 + %X = select i1 %cmp, i16 %umul.result, i16 42 + ret i16 %X +} + +declare { i16, i1 } @llvm.umul.with.overflow.i16(i16, i16) nounwind readnone + +define zeroext i32 @umul_i32(i32 signext %a, i32 signext %b) nounwind ssp { +entry: + %umul = tail call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %a, i32 %b) + %cmp = extractvalue { i32, i1 } %umul, 1 + %umul.result = extractvalue { i32, i1 } %umul, 0 + %X = select i1 %cmp, i32 %umul.result, i32 42 + ret i32 %X +} + +declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone + diff --git a/test/CodeGen/MBlaze/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/MBlaze/2010-04-07-DbgValueOtherTargets.ll index 854352a..d8970ea 100644 --- a/test/CodeGen/MBlaze/2010-04-07-DbgValueOtherTargets.ll +++ b/test/CodeGen/MBlaze/2010-04-07-DbgValueOtherTargets.ll @@ -1,33 +1,28 @@ ; RUN: llc -O0 -march=mblaze -asm-verbose < %s | FileCheck %s ; Check that DEBUG_VALUE comments come through on a variety of targets. -%tart.reflect.ComplexType = type { double, double } - -@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } - -define i32 @"main(tart.core.String[])->int32"(i32 %args) { +define i32 @main() nounwind ssp { entry: ; CHECK: DEBUG_VALUE - tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) - tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] - ret i32 3 + call void @llvm.dbg.value(metadata !6, i64 0, metadata !7), !dbg !9 + ret i32 0, !dbg !10 } +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone -declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone -!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] -!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] -!3 = metadata !{metadata !4, metadata !6, metadata !7} -!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] -!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] -!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] -!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] -!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] -!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] -!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] -!12 = metadata !{metadata !13} -!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} +!llvm.dbg.sp = !{!0} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !"clang version 2.9 (trunk 120996)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 589860, metadata !2, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 0} +!7 = metadata !{i32 590080, metadata !8, metadata !"i", metadata !1, i32 3, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!8 = metadata !{i32 589835, metadata !0, i32 2, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!9 = metadata !{i32 3, i32 11, metadata !8, null} +!10 = metadata !{i32 4, i32 2, metadata !8, null} + diff --git a/test/CodeGen/MBlaze/brind.ll b/test/CodeGen/MBlaze/brind.ll index 7798e0f..2229a87 100644 --- a/test/CodeGen/MBlaze/brind.ll +++ b/test/CodeGen/MBlaze/brind.ll @@ -28,32 +28,31 @@ loop: label %L3, label %L4, label %L5 ] - ; CHECK: br {{r[0-9]*}} + ; CHECK: brad {{r[0-9]*}} L1: %tmp.1 = add i32 %a, %b br label %finish - ; CHECK: br + ; CHECK: brid L2: %tmp.2 = sub i32 %a, %b br label %finish - ; CHECK: br + ; CHECK: brid L3: %tmp.3 = mul i32 %a, %b br label %finish - ; CHECK: br + ; CHECK: brid L4: %tmp.4 = sdiv i32 %a, %b br label %finish - ; CHECK: br + ; CHECK: brid L5: %tmp.5 = srem i32 %a, %b br label %finish - ; CHECK: br finish: %tmp.6 = phi i32 [ %tmp.1, %L1 ], @@ -69,5 +68,5 @@ finish: %tmp.8 = urem i32 %tmp.7, 5 br label %loop - ; CHECK: br + ; CHECK: brad {{r[0-9]*}} } diff --git a/test/CodeGen/MBlaze/cc.ll b/test/CodeGen/MBlaze/cc.ll index aaa918f..b1eb22a 100644 --- a/test/CodeGen/MBlaze/cc.ll +++ b/test/CodeGen/MBlaze/cc.ll @@ -12,7 +12,7 @@ declare i32 @printf(i8*, ...) define void @params0_noret() { ; CHECK: params0_noret: ret void - ; CHECK-NOT: {{.* r3, r0, 1}} + ; CHECK-NOT: {{.* r3, .*, .*}} ; CHECK-NOT: {{.* r4, .*, .*}} ; CHECK: rtsd } @@ -20,81 +20,88 @@ define void @params0_noret() { define i8 @params0_8bitret() { ; CHECK: params0_8bitret: ret i8 1 - ; CHECK: {{.* r3, r0, 1}} + ; CHECK-NOT: {{.* r3, .*, .*}} ; CHECK-NOT: {{.* r4, .*, .*}} ; CHECK: rtsd + ; CHECK: {{.* r3, r0, 1}} } define i16 @params0_16bitret() { ; CHECK: params0_16bitret: ret i16 1 + ; CHECK: rtsd ; CHECK: {{.* r3, r0, 1}} ; CHECK-NOT: {{.* r4, .*, .*}} - ; CHECK: rtsd } define i32 @params0_32bitret() { ; CHECK: params0_32bitret: ret i32 1 - ; CHECK: {{.* r3, r0, 1}} ; CHECK-NOT: {{.* r4, .*, .*}} ; CHECK: rtsd + ; CHECK: {{.* r3, r0, 1}} } define i64 @params0_64bitret() { ; CHECK: params0_64bitret: ret i64 1 ; CHECK: {{.* r3, r0, .*}} - ; CHECK: {{.* r4, r0, 1}} ; CHECK: rtsd + ; CHECK: {{.* r4, r0, 1}} } define i32 @params1_32bitret(i32 %a) { ; CHECK: params1_32bitret: ret i32 %a - ; CHECK: {{.* r3, r5, r0}} + ; CHECK-NOT: {{.* r3, .*, .*}} ; CHECK-NOT: {{.* r4, .*, .*}} ; CHECK: rtsd + ; CHECK: {{.* r3, r5, r0}} } define i32 @params2_32bitret(i32 %a, i32 %b) { ; CHECK: params2_32bitret: ret i32 %b - ; CHECK: {{.* r3, r6, r0}} + ; CHECK-NOT: {{.* r3, .*, .*}} ; CHECK-NOT: {{.* r4, .*, .*}} ; CHECK: rtsd + ; CHECK: {{.* r3, r6, r0}} } define i32 @params3_32bitret(i32 %a, i32 %b, i32 %c) { ; CHECK: params3_32bitret: ret i32 %c - ; CHECK: {{.* r3, r7, r0}} + ; CHECK-NOT: {{.* r3, .*, .*}} ; CHECK-NOT: {{.* r4, .*, .*}} ; CHECK: rtsd + ; CHECK: {{.* r3, r7, r0}} } define i32 @params4_32bitret(i32 %a, i32 %b, i32 %c, i32 %d) { ; CHECK: params4_32bitret: ret i32 %d - ; CHECK: {{.* r3, r8, r0}} + ; CHECK-NOT: {{.* r3, .*, .*}} ; CHECK-NOT: {{.* r4, .*, .*}} ; CHECK: rtsd + ; CHECK: {{.* r3, r8, r0}} } define i32 @params5_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) { ; CHECK: params5_32bitret: ret i32 %e - ; CHECK: {{.* r3, r9, r0}} + ; CHECK-NOT: {{.* r3, .*, .*}} ; CHECK-NOT: {{.* r4, .*, .*}} ; CHECK: rtsd + ; CHECK: {{.* r3, r9, r0}} } define i32 @params6_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f) { ; CHECK: params6_32bitret: ret i32 %f - ; CHECK: {{.* r3, r10, r0}} + ; CHECK-NOT: {{.* r3, .*, .*}} ; CHECK-NOT: {{.* r4, .*, .*}} ; CHECK: rtsd + ; CHECK: {{.* r3, r10, r0}} } define i32 @params7_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, @@ -142,53 +149,29 @@ define void @testing() { %tmp.1 = call i8 @params0_8bitret() ; CHECK: brlid call i32 (i8*,...)* @printf(i8* %MSG.1, i8 %tmp.1) - ; CHECK: {{.* r5, .*, .*}} - ; CHECK: {{.* r6, r3, r0}} - ; CHECK-NOT: {{.* r7, .*, .*}} - ; CHECK: brlid %tmp.2 = call i16 @params0_16bitret() ; CHECK: brlid call i32 (i8*,...)* @printf(i8* %MSG.1, i16 %tmp.2) - ; CHECK: {{.* r5, .*, .*}} - ; CHECK: {{.* r6, r3, r0}} - ; CHECK-NOT: {{.* r7, .*, .*}} - ; CHECK: brlid %tmp.3 = call i32 @params0_32bitret() ; CHECK: brlid call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.3) - ; CHECK: {{.* r5, .*, .*}} - ; CHECK: {{.* r6, r3, r0}} - ; CHECK-NOT: {{.* r7, .*, .*}} - ; CHECK: brlid %tmp.4 = call i64 @params0_64bitret() ; CHECK: brlid call i32 (i8*,...)* @printf(i8* %MSG.1, i64 %tmp.4) - ; CHECK: {{.* r5, .*, .*}} - ; CHECK: {{.* r6, r3, r0}} - ; CHECK: {{.* r7, r4, r0}} - ; CHECK: brlid %tmp.5 = call i32 @params1_32bitret(i32 1) ; CHECK: {{.* r5, .*, .*}} ; CHECK: brlid call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.5) - ; CHECK: {{.* r5, .*, .*}} - ; CHECK: {{.* r6, r3, r0}} - ; CHECK-NOT: {{.* r7, .*, .*}} - ; CHECK: brlid %tmp.6 = call i32 @params2_32bitret(i32 1, i32 2) ; CHECK: {{.* r5, .*, .*}} ; CHECK: {{.* r6, .*, .*}} ; CHECK: brlid call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.6) - ; CHECK: {{.* r5, .*, .*}} - ; CHECK: {{.* r6, r3, r0}} - ; CHECK-NOT: {{.* r7, .*, .*}} - ; CHECK: brlid %tmp.7 = call i32 @params3_32bitret(i32 1, i32 2, i32 3) ; CHECK: {{.* r5, .*, .*}} @@ -196,10 +179,6 @@ define void @testing() { ; CHECK: {{.* r7, .*, .*}} ; CHECK: brlid call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.7) - ; CHECK: {{.* r5, .*, .*}} - ; CHECK: {{.* r6, r3, r0}} - ; CHECK-NOT: {{.* r7, .*, .*}} - ; CHECK: brlid %tmp.8 = call i32 @params4_32bitret(i32 1, i32 2, i32 3, i32 4) ; CHECK: {{.* r5, .*, .*}} @@ -208,10 +187,6 @@ define void @testing() { ; CHECK: {{.* r8, .*, .*}} ; CHECK: brlid call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.8) - ; CHECK: {{.* r5, .*, .*}} - ; CHECK: {{.* r6, r3, r0}} - ; CHECK-NOT: {{.* r7, .*, .*}} - ; CHECK: brlid %tmp.9 = call i32 @params5_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5) ; CHECK: {{.* r5, .*, .*}} @@ -221,10 +196,6 @@ define void @testing() { ; CHECK: {{.* r9, .*, .*}} ; CHECK: brlid call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.9) - ; CHECK: {{.* r5, .*, .*}} - ; CHECK: {{.* r6, r3, r0}} - ; CHECK-NOT: {{.* r7, .*, .*}} - ; CHECK: brlid %tmp.10 = call i32 @params6_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6) @@ -236,10 +207,6 @@ define void @testing() { ; CHECK: {{.* r10, .*, .*}} ; CHECK: brlid call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.10) - ; CHECK: {{.* r5, .*, .*}} - ; CHECK: {{.* r6, r3, r0}} - ; CHECK-NOT: {{.* r7, .*, .*}} - ; CHECK: brlid %tmp.11 = call i32 @params7_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7) @@ -252,10 +219,6 @@ define void @testing() { ; CHECK: {{.* r10, .*, .*}} ; CHECK: brlid call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.11) - ; CHECK: {{.* r5, .*, .*}} - ; CHECK: {{.* r6, r3, r0}} - ; CHECK-NOT: {{.* r7, .*, .*}} - ; CHECK: brlid %tmp.12 = call i32 @params8_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8) @@ -269,10 +232,6 @@ define void @testing() { ; CHECK: {{.* r10, .*, .*}} ; CHECK: brlid call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.12) - ; CHECK: {{.* r5, .*, .*}} - ; CHECK: {{.* r6, r3, r0}} - ; CHECK-NOT: {{.* r7, .*, .*}} - ; CHECK: brlid %tmp.13 = call i32 @params9_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9) @@ -287,10 +246,6 @@ define void @testing() { ; CHECK: {{.* r10, .*, .*}} ; CHECK: brlid call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.13) - ; CHECK: {{.* r5, .*, .*}} - ; CHECK: {{.* r6, r3, r0}} - ; CHECK-NOT: {{.* r7, .*, .*}} - ; CHECK: brlid %tmp.14 = call i32 @params10_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10) @@ -306,10 +261,6 @@ define void @testing() { ; CHECK: {{.* r10, .*, .*}} ; CHECK: brlid call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.14) - ; CHECK: {{.* r5, .*, .*}} - ; CHECK: {{.* r6, r3, r0}} - ; CHECK-NOT: {{.* r7, .*, .*}} - ; CHECK: brlid ret void } diff --git a/test/CodeGen/MBlaze/fpu.ll b/test/CodeGen/MBlaze/fpu.ll index 83f4d83..2aef4fd 100644 --- a/test/CodeGen/MBlaze/fpu.ll +++ b/test/CodeGen/MBlaze/fpu.ll @@ -10,14 +10,14 @@ define float @test_add(float %a, float %b) { ; FPU: test_add: %tmp.1 = fadd float %a, %b - ; FUN-NOT: fadd ; FUN: brlid ; FPU-NOT: brlid - ; FPU: fadd ret float %tmp.1 ; FUN: rtsd ; FPU: rtsd + ; FUN-NOT: fadd + ; FPU-NEXT: fadd } define float @test_sub(float %a, float %b) { @@ -25,14 +25,14 @@ define float @test_sub(float %a, float %b) { ; FPU: test_sub: %tmp.1 = fsub float %a, %b - ; FUN-NOT: frsub ; FUN: brlid ; FPU-NOT: brlid - ; FPU: frsub ret float %tmp.1 ; FUN: rtsd ; FPU: rtsd + ; FUN-NOT: frsub + ; FPU-NEXT: frsub } define float @test_mul(float %a, float %b) { @@ -40,14 +40,14 @@ define float @test_mul(float %a, float %b) { ; FPU: test_mul: %tmp.1 = fmul float %a, %b - ; FUN-NOT: fmul ; FUN: brlid ; FPU-NOT: brlid - ; FPU: fmul ret float %tmp.1 ; FUN: rtsd ; FPU: rtsd + ; FUN-NOT: fmul + ; FPU-NEXT: fmul } define float @test_div(float %a, float %b) { @@ -55,12 +55,12 @@ define float @test_div(float %a, float %b) { ; FPU: test_div: %tmp.1 = fdiv float %a, %b - ; FUN-NOT: fdiv ; FUN: brlid ; FPU-NOT: brlid - ; FPU: fdiv ret float %tmp.1 ; FUN: rtsd ; FPU: rtsd + ; FUN-NOT: fdiv + ; FPU-NEXT: fdiv } diff --git a/test/CodeGen/MBlaze/imm.ll b/test/CodeGen/MBlaze/imm.ll index 85fad17..6effd3e 100644 --- a/test/CodeGen/MBlaze/imm.ll +++ b/test/CodeGen/MBlaze/imm.ll @@ -7,22 +7,22 @@ define i8 @retimm_i8() { ; CHECK: retimm_i8: - ; CHECK: add - ; CHECK-NEXT: rtsd + ; CHECK: rtsd + ; CHECK-NEXT: add ; FPU: retimm_i8: - ; FPU: add - ; FPU-NEXT: rtsd + ; FPU: rtsd + ; FPU-NEXT: add ret i8 123 } define i16 @retimm_i16() { ; CHECK: retimm_i16: - ; CHECK: add - ; CHECK-NEXT: rtsd + ; CHECK: rtsd + ; CHECK-NEXT: add ; FPU: retimm_i16: - ; FPU: add - ; FPU-NEXT: rtsd - ret i16 38212 + ; FPU: rtsd + ; FPU-NEXT: add + ret i16 31212 } define i32 @retimm_i32() { @@ -38,12 +38,12 @@ define i32 @retimm_i32() { define i64 @retimm_i64() { ; CHECK: retimm_i64: ; CHECK: add - ; CHECK-NEXT: add ; CHECK-NEXT: rtsd + ; CHECK-NEXT: add ; FPU: retimm_i64: ; FPU: add - ; FPU-NEXT: add ; FPU-NEXT: rtsd + ; FPU-NEXT: add ret i64 94581823 } @@ -53,7 +53,7 @@ define float @retimm_float() { ; CHECK-NEXT: rtsd ; FPU: retimm_float: ; FPU: or - ; FPU: rtsd + ; FPU-NEXT: rtsd ret float 12.0 } diff --git a/test/CodeGen/MBlaze/intr.ll b/test/CodeGen/MBlaze/intr.ll new file mode 100644 index 0000000..79c6bff --- /dev/null +++ b/test/CodeGen/MBlaze/intr.ll @@ -0,0 +1,48 @@ +; Ensure that the MBlaze interrupt_handler calling convention (cc73) is handled +; correctly correctly by the MBlaze backend. +; +; RUN: llc < %s -march=mblaze | FileCheck %s + +@.str = private constant [28 x i8] c"The interrupt has gone off\0A\00" +@_interrupt_handler = alias void ()* @myintr + +define cc73 void @myintr() nounwind noinline { + ; CHECK: myintr: + ; CHECK: swi r3, r1 + ; CHECK: swi r4, r1 + ; CHECK: swi r5, r1 + ; CHECK: swi r6, r1 + ; CHECK: swi r7, r1 + ; CHECK: swi r8, r1 + ; CHECK: swi r9, r1 + ; CHECK: swi r10, r1 + ; CHECK: swi r11, r1 + ; CHECK: swi r12, r1 + ; CHECK: swi r17, r1 + ; CHECK: swi r18, r1 + ; CHECK: mfs r11, rmsr + ; CHECK: swi r11, r1 + entry: + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([28 x i8]* @.str, i32 0, i32 0)) + ret void + + ; CHECK: lwi r11, r1 + ; CHECK: mts rmsr, r11 + ; CHECK: lwi r18, r1 + ; CHECK: lwi r17, r1 + ; CHECK: lwi r12, r1 + ; CHECK: lwi r11, r1 + ; CHECK: lwi r10, r1 + ; CHECK: lwi r9, r1 + ; CHECK: lwi r8, r1 + ; CHECK: lwi r7, r1 + ; CHECK: lwi r6, r1 + ; CHECK: lwi r5, r1 + ; CHECK: lwi r4, r1 + ; CHECK: lwi r3, r1 + ; CHECK: rtid r14, 0 +} + + ; CHECK: .globl _interrupt_handler + ; CHECK: _interrupt_handler = myintr +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/MBlaze/jumptable.ll b/test/CodeGen/MBlaze/jumptable.ll index 3f27c12..299084d 100644 --- a/test/CodeGen/MBlaze/jumptable.ll +++ b/test/CodeGen/MBlaze/jumptable.ll @@ -18,8 +18,8 @@ define i32 @jmptable(i32 %arg) i32 8, label %L8 i32 9, label %L9 ] - ; CHECK: lw [[REG:r[0-9]*]] - ; CHECK: br [[REG]] + ; CHECK: lw [[REG:r[0-9]*]] + ; CHECK: brad [[REG]] L0: %var0 = add i32 %arg, 0 br label %DONE diff --git a/test/CodeGen/MBlaze/loop.ll b/test/CodeGen/MBlaze/loop.ll index b473020..8973f75 100644 --- a/test/CodeGen/MBlaze/loop.ll +++ b/test/CodeGen/MBlaze/loop.ll @@ -27,11 +27,10 @@ loop_inner: loop_inner_finish: %inner.5 = add i32 %inner.2, 1 - ; CHECK: addi {{.*, 1}} - call i32 (i8*,...)* @printf( i8* getelementptr([19 x i8]* @MSG,i32 0,i32 0), i32 %inner.0, i32 %inner.1, i32 %inner.2 ) ; CHECK: brlid + ; CHECK: addik {{.*, 1}} %inner.6 = icmp eq i32 %inner.5, 100 ; CHECK: cmp diff --git a/test/CodeGen/MBlaze/mul.ll b/test/CodeGen/MBlaze/mul.ll index 65d3e22..cefdb8d 100644 --- a/test/CodeGen/MBlaze/mul.ll +++ b/test/CodeGen/MBlaze/mul.ll @@ -13,11 +13,11 @@ define i8 @test_i8(i8 %a, i8 %b) { ; FUN-NOT: mul ; FUN: brlid ; MUL-NOT: brlid - ; MUL: mul ret i8 %tmp.1 ; FUN: rtsd ; MUL: rtsd + ; MUL: mul } define i16 @test_i16(i16 %a, i16 %b) { @@ -28,11 +28,11 @@ define i16 @test_i16(i16 %a, i16 %b) { ; FUN-NOT: mul ; FUN: brlid ; MUL-NOT: brlid - ; MUL: mul ret i16 %tmp.1 ; FUN: rtsd ; MUL: rtsd + ; MUL: mul } define i32 @test_i32(i32 %a, i32 %b) { @@ -43,9 +43,9 @@ define i32 @test_i32(i32 %a, i32 %b) { ; FUN-NOT: mul ; FUN: brlid ; MUL-NOT: brlid - ; MUL: mul ret i32 %tmp.1 ; FUN: rtsd ; MUL: rtsd + ; MUL: mul } diff --git a/test/CodeGen/MBlaze/shift.ll b/test/CodeGen/MBlaze/shift.ll index 186115e..99f0519 100644 --- a/test/CodeGen/MBlaze/shift.ll +++ b/test/CodeGen/MBlaze/shift.ll @@ -10,17 +10,16 @@ define i8 @test_i8(i8 %a, i8 %b) { ; SHT: test_i8: %tmp.1 = shl i8 %a, %b - ; FUN-NOT: bsll ; FUN: andi ; FUN: add ; FUN: bnei - ; SHT-NOT: andi ; SHT-NOT: bnei - ; SHT: bsll ret i8 %tmp.1 ; FUN: rtsd ; SHT: rtsd + ; FUN-NOT: bsll + ; SHT-NEXT: bsll } define i8 @testc_i8(i8 %a, i8 %b) { @@ -28,18 +27,18 @@ define i8 @testc_i8(i8 %a, i8 %b) { ; SHT: testc_i8: %tmp.1 = shl i8 %a, 5 - ; FUN-NOT: bsll ; FUN: andi ; FUN: add ; FUN: bnei ; SHT-NOT: andi ; SHT-NOT: add ; SHT-NOT: bnei - ; SHT: bslli ret i8 %tmp.1 ; FUN: rtsd ; SHT: rtsd + ; FUN-NOT: bsll + ; SHT-NEXT: bslli } define i16 @test_i16(i16 %a, i16 %b) { @@ -47,17 +46,16 @@ define i16 @test_i16(i16 %a, i16 %b) { ; SHT: test_i16: %tmp.1 = shl i16 %a, %b - ; FUN-NOT: bsll ; FUN: andi ; FUN: add ; FUN: bnei - ; SHT-NOT: andi ; SHT-NOT: bnei - ; SHT: bsll ret i16 %tmp.1 ; FUN: rtsd ; SHT: rtsd + ; FUN-NOT: bsll + ; SHT-NEXT: bsll } define i16 @testc_i16(i16 %a, i16 %b) { @@ -65,18 +63,18 @@ define i16 @testc_i16(i16 %a, i16 %b) { ; SHT: testc_i16: %tmp.1 = shl i16 %a, 5 - ; FUN-NOT: bsll ; FUN: andi ; FUN: add ; FUN: bnei ; SHT-NOT: andi ; SHT-NOT: add ; SHT-NOT: bnei - ; SHT: bslli ret i16 %tmp.1 ; FUN: rtsd ; SHT: rtsd + ; FUN-NOT: bsll + ; SHT-NEXT: bslli } define i32 @test_i32(i32 %a, i32 %b) { @@ -84,17 +82,17 @@ define i32 @test_i32(i32 %a, i32 %b) { ; SHT: test_i32: %tmp.1 = shl i32 %a, %b - ; FUN-NOT: bsll ; FUN: andi ; FUN: add ; FUN: bnei ; SHT-NOT: andi ; SHT-NOT: bnei - ; SHT: bsll ret i32 %tmp.1 ; FUN: rtsd ; SHT: rtsd + ; FUN-NOT: bsll + ; SHT-NEXT: bsll } define i32 @testc_i32(i32 %a, i32 %b) { @@ -102,16 +100,16 @@ define i32 @testc_i32(i32 %a, i32 %b) { ; SHT: testc_i32: %tmp.1 = shl i32 %a, 5 - ; FUN-NOT: bsll ; FUN: andi ; FUN: add ; FUN: bnei ; SHT-NOT: andi ; SHT-NOT: add ; SHT-NOT: bnei - ; SHT: bslli ret i32 %tmp.1 ; FUN: rtsd ; SHT: rtsd + ; FUN-NOT: bsll + ; SHT-NEXT: bslli } diff --git a/test/CodeGen/MBlaze/svol.ll b/test/CodeGen/MBlaze/svol.ll new file mode 100644 index 0000000..c1e9620 --- /dev/null +++ b/test/CodeGen/MBlaze/svol.ll @@ -0,0 +1,80 @@ +; Ensure that the MBlaze save_volatiles calling convention (cc74) is handled +; correctly correctly by the MBlaze backend. +; +; RUN: llc < %s -march=mblaze | FileCheck %s + +@.str = private constant [28 x i8] c"The interrupt has gone off\0A\00" + +define cc74 void @mysvol() nounwind noinline { + ; CHECK: mysvol: + ; CHECK: swi r3, r1 + ; CHECK: swi r4, r1 + ; CHECK: swi r5, r1 + ; CHECK: swi r6, r1 + ; CHECK: swi r7, r1 + ; CHECK: swi r8, r1 + ; CHECK: swi r9, r1 + ; CHECK: swi r10, r1 + ; CHECK: swi r11, r1 + ; CHECK: swi r12, r1 + ; CHECK: swi r17, r1 + ; CHECK: swi r18, r1 + ; CHECK-NOT: mfs r11, rmsr + entry: + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([28 x i8]* @.str, i32 0, i32 0)) + ret void + + ; CHECK-NOT: mts rmsr, r11 + ; CHECK: lwi r18, r1 + ; CHECK: lwi r17, r1 + ; CHECK: lwi r12, r1 + ; CHECK: lwi r11, r1 + ; CHECK: lwi r10, r1 + ; CHECK: lwi r9, r1 + ; CHECK: lwi r8, r1 + ; CHECK: lwi r7, r1 + ; CHECK: lwi r6, r1 + ; CHECK: lwi r5, r1 + ; CHECK: lwi r4, r1 + ; CHECK: lwi r3, r1 + ; CHECK: rtsd r15, 8 +} + +define cc74 void @mysvol2() nounwind noinline { + ; CHECK: mysvol2: + ; CHECK-NOT: swi r3, r1 + ; CHECK-NOT: swi r4, r1 + ; CHECK-NOT: swi r5, r1 + ; CHECK-NOT: swi r6, r1 + ; CHECK-NOT: swi r7, r1 + ; CHECK-NOT: swi r8, r1 + ; CHECK-NOT: swi r9, r1 + ; CHECK-NOT: swi r10, r1 + ; CHECK-NOT: swi r11, r1 + ; CHECK-NOT: swi r12, r1 + ; CHECK: swi r17, r1 + ; CHECK: swi r18, r1 + ; CHECK-NOT: mfs r11, rmsr +entry: + + ; CHECK-NOT: mts rmsr, r11 + ; CHECK: lwi r18, r1 + ; CHECK: lwi r17, r1 + ; CHECK-NOT: lwi r12, r1 + ; CHECK-NOT: lwi r11, r1 + ; CHECK-NOT: lwi r10, r1 + ; CHECK-NOT: lwi r9, r1 + ; CHECK-NOT: lwi r8, r1 + ; CHECK-NOT: lwi r7, r1 + ; CHECK-NOT: lwi r6, r1 + ; CHECK-NOT: lwi r5, r1 + ; CHECK-NOT: lwi r4, r1 + ; CHECK-NOT: lwi r3, r1 + ; CHECK: rtsd r15, 8 + ret void +} + + ; CHECK-NOT: .globl _interrupt_handler + ; CHECK-NOT: _interrupt_handler = mysvol + ; CHECK-NOT: _interrupt_handler = mysvol2 +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/MSP430/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/MSP430/2010-04-07-DbgValueOtherTargets.ll index 8de044c..9d549da 100644 --- a/test/CodeGen/MSP430/2010-04-07-DbgValueOtherTargets.ll +++ b/test/CodeGen/MSP430/2010-04-07-DbgValueOtherTargets.ll @@ -1,33 +1,28 @@ ; RUN: llc -O0 -march=msp430 -asm-verbose < %s | FileCheck %s ; Check that DEBUG_VALUE comments come through on a variety of targets. -%tart.reflect.ComplexType = type { double, double } - -@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } - -define i32 @"main(tart.core.String[])->int32"(i32 %args) { +define i32 @main() nounwind ssp { entry: ; CHECK: DEBUG_VALUE - tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) - tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] - ret i32 3 + call void @llvm.dbg.value(metadata !6, i64 0, metadata !7), !dbg !9 + ret i32 0, !dbg !10 } +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone -declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone -!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] -!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] -!3 = metadata !{metadata !4, metadata !6, metadata !7} -!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] -!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] -!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] -!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] -!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] -!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] -!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] -!12 = metadata !{metadata !13} -!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} +!llvm.dbg.sp = !{!0} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !"clang version 2.9 (trunk 120996)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 589860, metadata !2, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 0} +!7 = metadata !{i32 590080, metadata !8, metadata !"i", metadata !1, i32 3, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!8 = metadata !{i32 589835, metadata !0, i32 2, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!9 = metadata !{i32 3, i32 11, metadata !8, null} +!10 = metadata !{i32 4, i32 2, metadata !8, null} + diff --git a/test/CodeGen/MSP430/mult-alt-generic-msp430.ll b/test/CodeGen/MSP430/mult-alt-generic-msp430.ll new file mode 100644 index 0000000..342afed --- /dev/null +++ b/test/CodeGen/MSP430/mult-alt-generic-msp430.ll @@ -0,0 +1,323 @@ +; RUN: llc < %s -march=msp430 +; ModuleID = 'mult-alt-generic.c' +target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16" +target triple = "msp430" + +@mout0 = common global i16 0, align 2 +@min1 = common global i16 0, align 2 +@marray = common global [2 x i16] zeroinitializer, align 2 + +define void @single_m() nounwind { +entry: + call void asm "foo $1,$0", "=*m,*m"(i16* @mout0, i16* @min1) nounwind + ret void +} + +define void @single_o() nounwind { +entry: + %out0 = alloca i16, align 2 + %index = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + store i16 1, i16* %index, align 2 + ret void +} + +define void @single_V() nounwind { +entry: + ret void +} + +define void @single_lt() nounwind { +entry: + %out0 = alloca i16, align 2 + %in1 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + store i16 1, i16* %in1, align 2 + %tmp = load i16* %in1, align 2 + %0 = call i16 asm "foo $1,$0", "=r,r"(i16 %tmp) nounwind + store i16 %0, i16* %out0, align 2 + %tmp1 = load i16* %in1, align 2 + %1 = call i16 asm "foo $1,$0", "=r,r>"(i16 %tmp1) nounwind + store i16 %1, i16* %out0, align 2 + ret void +} + +define void @single_r() nounwind { +entry: + %out0 = alloca i16, align 2 + %in1 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + store i16 1, i16* %in1, align 2 + %tmp = load i16* %in1, align 2 + %0 = call i16 asm "foo $1,$0", "=r,r"(i16 %tmp) nounwind + store i16 %0, i16* %out0, align 2 + ret void +} + +define void @single_i() nounwind { +entry: + %out0 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + %0 = call i16 asm "foo $1,$0", "=r,i"(i16 1) nounwind + store i16 %0, i16* %out0, align 2 + ret void +} + +define void @single_n() nounwind { +entry: + %out0 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + %0 = call i16 asm "foo $1,$0", "=r,n"(i16 1) nounwind + store i16 %0, i16* %out0, align 2 + ret void +} + +define void @single_E() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r,E"(double 1.000000e+001) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @single_F() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r,F"(double 1.000000e+000) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @single_s() nounwind { +entry: + %out0 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + ret void +} + +define void @single_g() nounwind { +entry: + %out0 = alloca i16, align 2 + %in1 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + store i16 1, i16* %in1, align 2 + %tmp = load i16* %in1, align 2 + %0 = call i16 asm "foo $1,$0", "=r,imr"(i16 %tmp) nounwind + store i16 %0, i16* %out0, align 2 + %tmp1 = load i16* @min1, align 2 + %1 = call i16 asm "foo $1,$0", "=r,imr"(i16 %tmp1) nounwind + store i16 %1, i16* %out0, align 2 + %2 = call i16 asm "foo $1,$0", "=r,imr"(i16 1) nounwind + store i16 %2, i16* %out0, align 2 + ret void +} + +define void @single_X() nounwind { +entry: + %out0 = alloca i16, align 2 + %in1 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + store i16 1, i16* %in1, align 2 + %tmp = load i16* %in1, align 2 + %0 = call i16 asm "foo $1,$0", "=r,X"(i16 %tmp) nounwind + store i16 %0, i16* %out0, align 2 + %tmp1 = load i16* @min1, align 2 + %1 = call i16 asm "foo $1,$0", "=r,X"(i16 %tmp1) nounwind + store i16 %1, i16* %out0, align 2 + %2 = call i16 asm "foo $1,$0", "=r,X"(i16 1) nounwind + store i16 %2, i16* %out0, align 2 + %3 = call i16 asm "foo $1,$0", "=r,X"(i16* getelementptr inbounds ([2 x i16]* @marray, i32 0, i32 0)) nounwind + store i16 %3, i16* %out0, align 2 +; No lowering support. +; %4 = call i16 asm "foo $1,$0", "=r,X"(double 1.000000e+001) nounwind +; store i16 %4, i16* %out0, align 2 +; %5 = call i16 asm "foo $1,$0", "=r,X"(double 1.000000e+000) nounwind +; store i16 %5, i16* %out0, align 2 + ret void +} + +define void @single_p() nounwind { +entry: + %out0 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + %0 = call i16 asm "foo $1,$0", "=r,r"(i16* getelementptr inbounds ([2 x i16]* @marray, i32 0, i32 0)) nounwind + store i16 %0, i16* %out0, align 2 + ret void +} + +define void @multi_m() nounwind { +entry: + %tmp = load i16* @min1, align 2 + call void asm "foo $1,$0", "=*m|r,m|r"(i16* @mout0, i16 %tmp) nounwind + ret void +} + +define void @multi_o() nounwind { +entry: + %out0 = alloca i16, align 2 + %index = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + store i16 1, i16* %index, align 2 + ret void +} + +define void @multi_V() nounwind { +entry: + ret void +} + +define void @multi_lt() nounwind { +entry: + %out0 = alloca i16, align 2 + %in1 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + store i16 1, i16* %in1, align 2 + %tmp = load i16* %in1, align 2 + %0 = call i16 asm "foo $1,$0", "=r|r,r|r"(i16 %tmp) nounwind + store i16 %0, i16* %out0, align 2 + %tmp1 = load i16* %in1, align 2 + %1 = call i16 asm "foo $1,$0", "=r|r,r|r>"(i16 %tmp1) nounwind + store i16 %1, i16* %out0, align 2 + ret void +} + +define void @multi_r() nounwind { +entry: + %out0 = alloca i16, align 2 + %in1 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + store i16 1, i16* %in1, align 2 + %tmp = load i16* %in1, align 2 + %0 = call i16 asm "foo $1,$0", "=r|r,r|m"(i16 %tmp) nounwind + store i16 %0, i16* %out0, align 2 + ret void +} + +define void @multi_i() nounwind { +entry: + %out0 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + %0 = call i16 asm "foo $1,$0", "=r|r,r|i"(i16 1) nounwind + store i16 %0, i16* %out0, align 2 + ret void +} + +define void @multi_n() nounwind { +entry: + %out0 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + %0 = call i16 asm "foo $1,$0", "=r|r,r|n"(i16 1) nounwind + store i16 %0, i16* %out0, align 2 + ret void +} + +define void @multi_E() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r|r,r|E"(double 1.000000e+001) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @multi_F() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r|r,r|F"(double 1.000000e+000) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @multi_s() nounwind { +entry: + %out0 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + ret void +} + +define void @multi_g() nounwind { +entry: + %out0 = alloca i16, align 2 + %in1 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + store i16 1, i16* %in1, align 2 + %tmp = load i16* %in1, align 2 + %0 = call i16 asm "foo $1,$0", "=r|r,r|imr"(i16 %tmp) nounwind + store i16 %0, i16* %out0, align 2 + %tmp1 = load i16* @min1, align 2 + %1 = call i16 asm "foo $1,$0", "=r|r,r|imr"(i16 %tmp1) nounwind + store i16 %1, i16* %out0, align 2 + %2 = call i16 asm "foo $1,$0", "=r|r,r|imr"(i16 1) nounwind + store i16 %2, i16* %out0, align 2 + ret void +} + +define void @multi_X() nounwind { +entry: + %out0 = alloca i16, align 2 + %in1 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + store i16 1, i16* %in1, align 2 + %tmp = load i16* %in1, align 2 + %0 = call i16 asm "foo $1,$0", "=r|r,r|X"(i16 %tmp) nounwind + store i16 %0, i16* %out0, align 2 + %tmp1 = load i16* @min1, align 2 + %1 = call i16 asm "foo $1,$0", "=r|r,r|X"(i16 %tmp1) nounwind + store i16 %1, i16* %out0, align 2 + %2 = call i16 asm "foo $1,$0", "=r|r,r|X"(i16 1) nounwind + store i16 %2, i16* %out0, align 2 + %3 = call i16 asm "foo $1,$0", "=r|r,r|X"(i16* getelementptr inbounds ([2 x i16]* @marray, i32 0, i32 0)) nounwind + store i16 %3, i16* %out0, align 2 +; No lowering support. +; %4 = call i16 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+001) nounwind +; store i16 %4, i16* %out0, align 2 +; %5 = call i16 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+000) nounwind +; store i16 %5, i16* %out0, align 2 + ret void +} + +define void @multi_p() nounwind { +entry: + %out0 = alloca i16, align 2 + store i16 0, i16* %out0, align 2 + %0 = call i16 asm "foo $1,$0", "=r|r,r|r"(i16* getelementptr inbounds ([2 x i16]* @marray, i32 0, i32 0)) nounwind + store i16 %0, i16* %out0, align 2 + ret void +} diff --git a/test/CodeGen/Mips/2008-07-15-InternalConstant.ll b/test/CodeGen/Mips/2008-07-15-InternalConstant.ll index bda4a31..c3db638 100644 --- a/test/CodeGen/Mips/2008-07-15-InternalConstant.ll +++ b/test/CodeGen/Mips/2008-07-15-InternalConstant.ll @@ -7,8 +7,8 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" target triple = "mipsallegrexel-unknown-psp-elf" -@.str = internal constant [10 x i8] c"AAAAAAAAA\00" -@i0 = internal constant [5 x i32] [ i32 0, i32 1, i32 2, i32 3, i32 4 ] +@.str = internal unnamed_addr constant [10 x i8] c"AAAAAAAAA\00" +@i0 = internal unnamed_addr constant [5 x i32] [ i32 0, i32 1, i32 2, i32 3, i32 4 ] define i8* @foo() nounwind { entry: diff --git a/test/CodeGen/Mips/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/Mips/2010-04-07-DbgValueOtherTargets.ll index 4161c1d..994e19a 100644 --- a/test/CodeGen/Mips/2010-04-07-DbgValueOtherTargets.ll +++ b/test/CodeGen/Mips/2010-04-07-DbgValueOtherTargets.ll @@ -1,33 +1,28 @@ ; RUN: llc -O0 -march=mips -asm-verbose < %s | FileCheck %s ; Check that DEBUG_VALUE comments come through on a variety of targets. -%tart.reflect.ComplexType = type { double, double } - -@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } - -define i32 @"main(tart.core.String[])->int32"(i32 %args) { +define i32 @main() nounwind ssp { entry: ; CHECK: DEBUG_VALUE - tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) - tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] - ret i32 3 + call void @llvm.dbg.value(metadata !6, i64 0, metadata !7), !dbg !9 + ret i32 0, !dbg !10 } +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone -declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone -!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] -!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] -!3 = metadata !{metadata !4, metadata !6, metadata !7} -!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] -!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] -!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] -!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] -!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] -!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] -!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] -!12 = metadata !{metadata !13} -!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} +!llvm.dbg.sp = !{!0} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !"clang version 2.9 (trunk 120996)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 589860, metadata !2, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 0} +!7 = metadata !{i32 590080, metadata !8, metadata !"i", metadata !1, i32 3, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!8 = metadata !{i32 589835, metadata !0, i32 2, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!9 = metadata !{i32 3, i32 11, metadata !8, null} +!10 = metadata !{i32 4, i32 2, metadata !8, null} + diff --git a/test/CodeGen/Mips/2010-07-20-Select.ll b/test/CodeGen/Mips/2010-07-20-Select.ll index 8b7f9a9..891b5d9 100644 --- a/test/CodeGen/Mips/2010-07-20-Select.ll +++ b/test/CodeGen/Mips/2010-07-20-Select.ll @@ -9,12 +9,12 @@ entry: volatile store i32 0, i32* %c, align 4 %0 = volatile load i32* %a, align 4 ; [#uses=1] %1 = icmp eq i32 %0, 0 ; [#uses=1] -; CHECK: addiu $4, $zero, 3 +; CHECK: addiu $3, $zero, 0 %iftmp.0.0 = select i1 %1, i32 3, i32 0 ; [#uses=1] %2 = volatile load i32* %c, align 4 ; [#uses=1] %3 = icmp eq i32 %2, 0 ; [#uses=1] -; CHECK: addu $4, $zero, $3 -; CHECK: addu $2, $5, $4 +; CHECK: addiu $3, $zero, 3 +; CHECK: addu $2, $5, $3 %iftmp.2.0 = select i1 %3, i32 0, i32 5 ; [#uses=1] %4 = add nsw i32 %iftmp.2.0, %iftmp.0.0 ; [#uses=1] ret i32 %4 diff --git a/test/CodeGen/Mips/2010-11-09-CountLeading.ll b/test/CodeGen/Mips/2010-11-09-CountLeading.ll new file mode 100644 index 0000000..d592fef --- /dev/null +++ b/test/CodeGen/Mips/2010-11-09-CountLeading.ll @@ -0,0 +1,33 @@ +; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s + +; CHECK: clz $2, $4 +define i32 @t1(i32 %X) nounwind readnone { +entry: + %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X) + ret i32 %tmp1 +} + +declare i32 @llvm.ctlz.i32(i32) nounwind readnone + +; CHECK: clz $2, $4 +define i32 @t2(i32 %X) nounwind readnone { +entry: + %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X) + ret i32 %tmp1 +} + +; CHECK: clo $2, $4 +define i32 @t3(i32 %X) nounwind readnone { +entry: + %neg = xor i32 %X, -1 + %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg) + ret i32 %tmp1 +} + +; CHECK: clo $2, $4 +define i32 @t4(i32 %X) nounwind readnone { +entry: + %neg = xor i32 %X, -1 + %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg) + ret i32 %tmp1 +} diff --git a/test/CodeGen/Mips/2010-11-09-Mul.ll b/test/CodeGen/Mips/2010-11-09-Mul.ll new file mode 100644 index 0000000..65a10b5 --- /dev/null +++ b/test/CodeGen/Mips/2010-11-09-Mul.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s + +; CHECK: mul $2, $5, $4 +define i32 @mul1(i32 %a, i32 %b) nounwind readnone { +entry: + %mul = mul i32 %b, %a + ret i32 %mul +} + +; CHECK: mul $2, $5, $4 +define i32 @mul2(i32 %a, i32 %b) nounwind readnone { +entry: + %mul = mul nsw i32 %b, %a + ret i32 %mul +} diff --git a/test/CodeGen/Mips/cmov.ll b/test/CodeGen/Mips/cmov.ll new file mode 100755 index 0000000..7d3e025 --- /dev/null +++ b/test/CodeGen/Mips/cmov.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s + +@i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4 +@i3 = common global i32* null, align 4 + +; CHECK: lw $3, %got(i3)($gp) +; CHECK: addiu $5, $gp, %got(i1) +define i32* @cmov1(i32 %s) nounwind readonly { +entry: + %tobool = icmp ne i32 %s, 0 + %tmp1 = load i32** @i3, align 4 + %cond = select i1 %tobool, i32* getelementptr inbounds ([3 x i32]* @i1, i32 0, i32 0), i32* %tmp1 + ret i32* %cond +} + diff --git a/test/CodeGen/Mips/madd-msub.ll b/test/CodeGen/Mips/madd-msub.ll new file mode 100644 index 0000000..4a205b1 --- /dev/null +++ b/test/CodeGen/Mips/madd-msub.ll @@ -0,0 +1,65 @@ +; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s + +; CHECK: madd $5, $4 +define i64 @madd1(i32 %a, i32 %b, i32 %c) nounwind readnone { +entry: + %conv = sext i32 %a to i64 + %conv2 = sext i32 %b to i64 + %mul = mul nsw i64 %conv2, %conv + %conv4 = sext i32 %c to i64 + %add = add nsw i64 %mul, %conv4 + ret i64 %add +} + +; CHECK: maddu $5, $4 +define i64 @madd2(i32 %a, i32 %b, i32 %c) nounwind readnone { +entry: + %conv = zext i32 %a to i64 + %conv2 = zext i32 %b to i64 + %mul = mul nsw i64 %conv2, %conv + %conv4 = zext i32 %c to i64 + %add = add nsw i64 %mul, %conv4 + ret i64 %add +} + +; CHECK: madd $5, $4 +define i64 @madd3(i32 %a, i32 %b, i64 %c) nounwind readnone { +entry: + %conv = sext i32 %a to i64 + %conv2 = sext i32 %b to i64 + %mul = mul nsw i64 %conv2, %conv + %add = add nsw i64 %mul, %c + ret i64 %add +} + +; CHECK: msub $5, $4 +define i64 @msub1(i32 %a, i32 %b, i32 %c) nounwind readnone { +entry: + %conv = sext i32 %c to i64 + %conv2 = sext i32 %a to i64 + %conv4 = sext i32 %b to i64 + %mul = mul nsw i64 %conv4, %conv2 + %sub = sub nsw i64 %conv, %mul + ret i64 %sub +} + +; CHECK: msubu $5, $4 +define i64 @msub2(i32 %a, i32 %b, i32 %c) nounwind readnone { +entry: + %conv = zext i32 %c to i64 + %conv2 = zext i32 %a to i64 + %conv4 = zext i32 %b to i64 + %mul = mul nsw i64 %conv4, %conv2 + %sub = sub nsw i64 %conv, %mul + ret i64 %sub +} + +; CHECK: msub $5, $4 +define i64 @msub3(i32 %a, i32 %b, i64 %c) nounwind readnone { +entry: + %conv = sext i32 %a to i64 + %conv3 = sext i32 %b to i64 + %mul = mul nsw i64 %conv3, %conv + %sub = sub nsw i64 %c, %mul + ret i64 %sub +} diff --git a/test/CodeGen/Mips/o32_cc.ll b/test/CodeGen/Mips/o32_cc.ll new file mode 100644 index 0000000..b6df62b --- /dev/null +++ b/test/CodeGen/Mips/o32_cc.ll @@ -0,0 +1,325 @@ +; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s + +; FIXME: Disabled because it unpredictably fails on certain platforms. +; REQUIRES: disabled + +; $f12, $f14 +; CHECK: ldc1 $f12, %lo +; CHECK: ldc1 $f14, %lo +define void @testlowercall0() nounwind { +entry: + tail call void @f0(double 5.000000e+00, double 6.000000e+00) nounwind + ret void +} + +declare void @f0(double, double) + +; $f12, $f14 +; CHECK: lwc1 $f12, %lo +; CHECK: lwc1 $f14, %lo +define void @testlowercall1() nounwind { +entry: + tail call void @f1(float 8.000000e+00, float 9.000000e+00) nounwind + ret void +} + +declare void @f1(float, float) + +; $f12, $f14 +; CHECK: lwc1 $f12, %lo +; CHECK: ldc1 $f14, %lo +define void @testlowercall2() nounwind { +entry: + tail call void @f2(float 8.000000e+00, double 6.000000e+00) nounwind + ret void +} + +declare void @f2(float, double) + +; $f12, $f14 +; CHECK: ldc1 $f12, %lo +; CHECK: lwc1 $f14, %lo +define void @testlowercall3() nounwind { +entry: + tail call void @f3(double 5.000000e+00, float 9.000000e+00) nounwind + ret void +} + +declare void @f3(double, float) + +; $4, $5, $6, $7 +; CHECK: addiu $4, $zero, 12 +; CHECK: addiu $5, $zero, 13 +; CHECK: addiu $6, $zero, 14 +; CHECK: addiu $7, $zero, 15 +define void @testlowercall4() nounwind { +entry: + tail call void @f4(i32 12, i32 13, i32 14, i32 15) nounwind + ret void +} + +declare void @f4(i32, i32, i32, i32) + +; $f12, $6, stack +; CHECK: sw $2, 16($sp) +; CHECK: sw $zero, 20($sp) +; CHECK: ldc1 $f12, %lo +; CHECK: addiu $6, $zero, 23 +define void @testlowercall5() nounwind { +entry: + tail call void @f5(double 1.500000e+01, i32 23, double 1.700000e+01) nounwind + ret void +} + +declare void @f5(double, i32, double) + +; $f12, $6, $7 +; CHECK: ldc1 $f12, %lo +; CHECK: addiu $6, $zero, 33 +; CHECK: addiu $7, $zero, 24 +define void @testlowercall6() nounwind { +entry: + tail call void @f6(double 2.500000e+01, i32 33, i32 24) nounwind + ret void +} + +declare void @f6(double, i32, i32) + +; $f12, $5, $6 +; CHECK: lwc1 $f12, %lo +; CHECK: addiu $5, $zero, 43 +; CHECK: addiu $6, $zero, 34 +define void @testlowercall7() nounwind { +entry: + tail call void @f7(float 1.800000e+01, i32 43, i32 34) nounwind + ret void +} + +declare void @f7(float, i32, i32) + +; $4, $5, $6, stack +; CHECK: sw $2, 16($sp) +; CHECK: sw $zero, 20($sp) +; CHECK: addiu $4, $zero, 22 +; CHECK: addiu $5, $zero, 53 +; CHECK: addiu $6, $zero, 44 +define void @testlowercall8() nounwind { +entry: + tail call void @f8(i32 22, i32 53, i32 44, double 4.000000e+00) nounwind + ret void +} + +declare void @f8(i32, i32, i32, double) + +; $4, $5, $6, $7 +; CHECK: addiu $4, $zero, 32 +; CHECK: addiu $5, $zero, 63 +; CHECK: addiu $6, $zero, 54 +; CHECK: ori $7, $2, 0 +define void @testlowercall9() nounwind { +entry: + tail call void @f9(i32 32, i32 63, i32 54, float 1.100000e+01) nounwind + ret void +} + +declare void @f9(i32, i32, i32, float) + +; $4, $5, ($6, $7) +; CHECK: addiu $4, $zero, 42 +; CHECK: addiu $5, $zero, 73 +; CHECK: addiu $6, $zero, 0 +; CHECK: ori $7, $2, 0 +define void @testlowercall10() nounwind { +entry: + tail call void @f10(i32 42, i32 73, double 2.700000e+01) nounwind + ret void +} + +declare void @f10(i32, i32, double) + +; $4, ($6, $7) +; CHECK: addiu $4, $zero, 52 +; CHECK: addiu $6, $zero, 0 +; CHECK: ori $7, $2, 0 +define void @testlowercall11() nounwind { +entry: + tail call void @f11(i32 52, double 1.600000e+01) nounwind + ret void +} + +declare void @f11(i32, double) + +; $f12, $f14, $6, $7 +; CHECK: lwc1 $f12, %lo +; CHECK: lwc1 $f14, %lo +; CHECK: ori $6, $4, 0 +; CHECK: ori $7, $5, 0 +define void @testlowercall12() nounwind { +entry: + tail call void @f12(float 2.800000e+01, float 1.900000e+01, float 1.000000e+01, float 2.100000e+01) nounwind + ret void +} + +declare void @f12(float, float, float, float) + +; $f12, $5, $6, $7 +; CHECK: lwc1 $f12, %lo +; CHECK: addiu $5, $zero, 83 +; CHECK: ori $6, $3, 0 +; CHECK: addiu $7, $zero, 25 +define void @testlowercall13() nounwind { +entry: + tail call void @f13(float 3.800000e+01, i32 83, float 2.000000e+01, i32 25) nounwind + ret void +} + + +declare void @f13(float, i32, float, i32) + +; $f12, $f14, $7 +; CHECK: ldc1 $f12, %lo +; CHECK: lwc1 $f14, %lo +; CHECK: ori $7, $4, 0 +define void @testlowercall14() nounwind { +entry: + tail call void @f14(double 3.500000e+01, float 2.900000e+01, float 3.000000e+01) nounwind + ret void +} + +declare void @f14(double, float, float) + +; $f12, $f14, ($6, $7) +; CHECK: lwc1 $f12, %lo +; CHECK: lwc1 $f14, %lo +; CHECK: addiu $6, $zero, 0 +; CHECK: ori $7, $4, 32768 +define void @testlowercall15() nounwind { +entry: + tail call void @f15(float 4.800000e+01, float 3.900000e+01, double 3.700000e+01) nounwind + ret void +} + +declare void @f15(float, float, double) + +; $4, $5, $6, $7 +; CHECK: addiu $4, $zero, 62 +; CHECK: ori $5, $2, 0 +; CHECK: addiu $6, $zero, 64 +; CHECK: ori $7, $3, 0 +define void @testlowercall16() nounwind { +entry: + tail call void @f16(i32 62, float 4.900000e+01, i32 64, float 3.100000e+01) nounwind + ret void +} + +declare void @f16(i32, float, i32, float) + +; $4, $5, $6, $7 +; CHECK: addiu $4, $zero, 72 +; CHECK: ori $5, $2, 0 +; CHECK: addiu $6, $zero, 74 +; CHECK: addiu $7, $zero, 35 +define void @testlowercall17() nounwind { +entry: + tail call void @f17(i32 72, float 5.900000e+01, i32 74, i32 35) nounwind + ret void +} + +declare void @f17(i32, float, i32, i32) + +; $4, $5, $6, $7 +; CHECK: addiu $4, $zero, 82 +; CHECK: addiu $5, $zero, 93 +; CHECK: ori $6, $2, 0 +; CHECK: addiu $7, $zero, 45 +define void @testlowercall18() nounwind { +entry: + tail call void @f18(i32 82, i32 93, float 4.000000e+01, i32 45) nounwind + ret void +} + +declare void @f18(i32, i32, float, i32) + + +; $4, ($6, $7), stack +; CHECK: sw $2, 16($sp) +; CHECK: sw $zero, 20($sp) +; CHECK: addiu $4, $zero, 92 +; CHECK: addiu $6, $zero, 0 +; CHECK: ori $7, $3, 0 +define void @testlowercall20() nounwind { +entry: + tail call void @f20(i32 92, double 2.600000e+01, double 4.700000e+01) nounwind + ret void +} + +declare void @f20(i32, double, double) + +; $f12, $5 +; CHECK: lwc1 $f12, %lo +; CHECK: addiu $5, $zero, 103 +define void @testlowercall21() nounwind { +entry: + tail call void @f21(float 5.800000e+01, i32 103) nounwind + ret void +} + +declare void @f21(float, i32) + +; $f12, $5, ($6, $7) +; CHECK: lwc1 $f12, %lo +; CHECK: addiu $5, $zero, 113 +; CHECK: addiu $6, $zero, 0 +; CHECK: ori $7, $3, 32768 +define void @testlowercall22() nounwind { +entry: + tail call void @f22(float 6.800000e+01, i32 113, double 5.700000e+01) nounwind + ret void +} + +declare void @f22(float, i32, double) + +; $f12, f6 +; CHECK: ldc1 $f12, %lo +; CHECK: addiu $6, $zero, 123 +define void @testlowercall23() nounwind { +entry: + tail call void @f23(double 4.500000e+01, i32 123) nounwind + ret void +} + +declare void @f23(double, i32) + +; $f12,$6, stack +; CHECK: sw $2, 16($sp) +; CHECK: sw $zero, 20($sp) +; CHECK: ldc1 $f12, %lo +; CHECK: addiu $6, $zero, 133 +define void @testlowercall24() nounwind { +entry: + tail call void @f24(double 5.500000e+01, i32 133, double 6.700000e+01) nounwind + ret void +} + +declare void @f24(double, i32, double) + +; CHECK: lwc1 $f12, %lo +; lwc1 $f12, %lo +; CHECK: lwc1 $f14, %lo +; CHECK: ori $6, $4, 0 +; CHECK: ori $7, $5, 0 +; CHECK: lwc1 $f12, %lo +; CHECK: addiu $5, $zero, 83 +; CHECK: ori $6, $3, 0 +; CHECK: addiu $7, $zero, 25 +; CHECK: addiu $4, $zero, 82 +; CHECK: addiu $5, $zero, 93 +; CHECK: ori $6, $2, 0 +; CHECK: addiu $7, $zero, 45 +define void @testlowercall25() nounwind { +entry: + tail call void @f12(float 2.800000e+01, float 1.900000e+01, float 1.000000e+01, float 2.100000e+01) nounwind + tail call void @f13(float 3.800000e+01, i32 83, float 2.000000e+01, i32 25) nounwind + tail call void @f18(i32 82, i32 93, float 4.000000e+01, i32 45) nounwind + ret void +} diff --git a/test/CodeGen/Mips/rotate.ll b/test/CodeGen/Mips/rotate.ll new file mode 100644 index 0000000..e7dc309 --- /dev/null +++ b/test/CodeGen/Mips/rotate.ll @@ -0,0 +1,40 @@ +; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s + +; CHECK: rotrv $2, $4, $2 +define i32 @rot0(i32 %a, i32 %b) nounwind readnone { +entry: + %shl = shl i32 %a, %b + %sub = sub i32 32, %b + %shr = lshr i32 %a, %sub + %or = or i32 %shr, %shl + ret i32 %or +} + +; CHECK: rotr $2, $4, 22 +define i32 @rot1(i32 %a) nounwind readnone { +entry: + %shl = shl i32 %a, 10 + %shr = lshr i32 %a, 22 + %or = or i32 %shl, %shr + ret i32 %or +} + +; CHECK: rotrv $2, $4, $5 +define i32 @rot2(i32 %a, i32 %b) nounwind readnone { +entry: + %shr = lshr i32 %a, %b + %sub = sub i32 32, %b + %shl = shl i32 %a, %sub + %or = or i32 %shl, %shr + ret i32 %or +} + +; CHECK: rotr $2, $4, 10 +define i32 @rot3(i32 %a) nounwind readnone { +entry: + %shr = lshr i32 %a, 10 + %shl = shl i32 %a, 22 + %or = or i32 %shr, %shl + ret i32 %or +} + diff --git a/test/CodeGen/PIC16/2009-07-17-PR4566-pic16.ll b/test/CodeGen/PIC16/2009-07-17-PR4566-pic16.ll deleted file mode 100644 index 5b5e11f..0000000 --- a/test/CodeGen/PIC16/2009-07-17-PR4566-pic16.ll +++ /dev/null @@ -1,32 +0,0 @@ -; RUN: llc < %s -march=pic16 | FileCheck %s -; XFAIL: vg_leak - -target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8-f32:32:32" -target triple = "pic16-" -@i = global i32 -10, align 1 ; [#uses=1] -@j = global i32 -20, align 1 ; [#uses=1] -@pc = global i8* inttoptr (i64 160 to i8*), align 1 ; [#uses=3] -@main.auto.k = internal global i32 0 ; [#uses=2] - -define void @main() nounwind { -entry: - %tmp = load i32* @i ; [#uses=1] - %tmp1 = load i32* @j ; [#uses=1] - %add = add i32 %tmp, %tmp1 ; [#uses=1] - store i32 %add, i32* @main.auto.k - %tmp2 = load i32* @main.auto.k ; [#uses=1] - %add3 = add i32 %tmp2, 32 ; [#uses=1] - %conv = trunc i32 %add3 to i8 ; [#uses=1] - %tmp4 = load i8** @pc ; [#uses=1] - store i8 %conv, i8* %tmp4 - %tmp5 = load i8** @pc ; [#uses=1] - %tmp6 = load i8* %tmp5 ; [#uses=1] - %conv7 = sext i8 %tmp6 to i16 ; [#uses=1] - %sub = sub i16 %conv7, 1 ; [#uses=1] - %conv8 = trunc i16 %sub to i8 ; [#uses=1] - %tmp9 = load i8** @pc ; [#uses=1] - store i8 %conv8, i8* %tmp9 - ret void -} - -; CHECK: movf @i + 0, W diff --git a/test/CodeGen/PIC16/2009-11-20-NewNode.ll b/test/CodeGen/PIC16/2009-11-20-NewNode.ll deleted file mode 100644 index d68f0f4..0000000 --- a/test/CodeGen/PIC16/2009-11-20-NewNode.ll +++ /dev/null @@ -1,36 +0,0 @@ -; RUN: llc -march=pic16 < %s -; PR5558 - -define i64 @_strtoll_r(i16 %base) nounwind { -entry: - br i1 undef, label %if.then, label %if.end27 - -if.then: ; preds = %do.end - br label %if.end27 - -if.end27: ; preds = %if.then, %do.end - %cond66 = select i1 undef, i64 -9223372036854775808, i64 9223372036854775807 ; [#uses=3] - %conv69 = sext i16 %base to i64 ; [#uses=1] - %div = udiv i64 %cond66, %conv69 ; [#uses=1] - br label %for.cond - -for.cond: ; preds = %if.end116, %if.end27 - br i1 undef, label %if.then152, label %if.then93 - -if.then93: ; preds = %for.cond - br i1 undef, label %if.end116, label %if.then152 - -if.end116: ; preds = %if.then93 - %cmp123 = icmp ugt i64 undef, %div ; [#uses=1] - %or.cond = or i1 undef, %cmp123 ; [#uses=0] - br label %for.cond - -if.then152: ; preds = %if.then93, %for.cond - br i1 undef, label %if.end182, label %if.then172 - -if.then172: ; preds = %if.then152 - ret i64 %cond66 - -if.end182: ; preds = %if.then152 - ret i64 %cond66 -} diff --git a/test/CodeGen/PIC16/C16-11.ll b/test/CodeGen/PIC16/C16-11.ll deleted file mode 100644 index 8a5a0ac..0000000 --- a/test/CodeGen/PIC16/C16-11.ll +++ /dev/null @@ -1,40 +0,0 @@ -; RUN: llc < %s -march=pic16 -; XFAIL: * -; This fails because PIC16 doesn't define a (xor reg, reg) pattern. -; - -@c612.auto.a.b = internal global i1 false ; [#uses=2] -@c612.auto.A.b = internal global i1 false ; [#uses=2] - -define void @c612() nounwind { -entry: - %tmp3.b = load i1* @c612.auto.a.b ; [#uses=1] - %tmp3 = zext i1 %tmp3.b to i16 ; [#uses=1] - %tmp4.b = load i1* @c612.auto.A.b ; [#uses=1] - %tmp4 = select i1 %tmp4.b, i16 2, i16 0 ; [#uses=1] - %cmp5 = icmp ne i16 %tmp3, %tmp4 ; [#uses=1] - %conv7 = zext i1 %cmp5 to i8 ; [#uses=1] - tail call void @expectWrap(i8 %conv7, i8 2) - ret void -} - -define void @expectWrap(i8 %boolresult, i8 %errCode) nounwind { -entry: - %tobool = icmp eq i8 %boolresult, 0 ; [#uses=1] - br i1 %tobool, label %if.then, label %if.end - -if.then: ; preds = %entry - tail call void @exit(i16 1) - unreachable - -if.end: ; preds = %entry - ret void -} - -define i16 @main() nounwind { -entry: - tail call void @c612() - ret i16 0 -} - -declare void @exit(i16) noreturn nounwind diff --git a/test/CodeGen/PIC16/C16-15.ll b/test/CodeGen/PIC16/C16-15.ll deleted file mode 100644 index 020b0dd..0000000 --- a/test/CodeGen/PIC16/C16-15.ll +++ /dev/null @@ -1,45 +0,0 @@ -; RUN: llc < %s -march=pic16 | grep "extern" | grep "@.lib.unordered.f32" | count 3 -; XFAIL: vg_leak - -@pc = global i8* inttoptr (i64 160 to i8*), align 1 ; [#uses=2] -@aa = common global i16 0, align 1 ; [#uses=0] -@c6214.auto.d = internal global float 0.000000e+00, align 4 ; [#uses=1] -@c6214.auto.l = internal global float 0.000000e+00, align 4 ; [#uses=1] - -define float @dvalue(float %f) nounwind { -entry: - ret float %f -} - -define void @_assert(i16 %line, i16 %result) nounwind { -entry: - %add = add i16 %line, %result ; [#uses=1] - %conv = trunc i16 %add to i8 ; [#uses=1] - %tmp2 = load i8** @pc ; [#uses=1] - store i8 %conv, i8* %tmp2 - ret void -} - -define i16 @main() nounwind { -entry: - %retval = alloca i16, align 1 ; [#uses=2] - store i16 0, i16* %retval - call void @c6214() - %0 = load i16* %retval ; [#uses=1] - ret i16 %0 -} - -define internal void @c6214() nounwind { -entry: - %call = call float @dvalue(float 0x3FF3C0CA40000000) ; [#uses=3] - store float %call, float* @c6214.auto.d - store float %call, float* @c6214.auto.l - %cmp = fcmp ord float %call, 0.000000e+00 ; [#uses=1] - %conv = zext i1 %cmp to i16 ; [#uses=1] - call void @_assert(i16 10, i16 %conv) - %tmp3 = load i8** @pc ; [#uses=2] - %tmp4 = load i8* %tmp3 ; [#uses=1] - %sub = add i8 %tmp4, -10 ; [#uses=1] - store i8 %sub, i8* %tmp3 - ret void -} diff --git a/test/CodeGen/PIC16/C16-49.ll b/test/CodeGen/PIC16/C16-49.ll deleted file mode 100644 index e59800b..0000000 --- a/test/CodeGen/PIC16/C16-49.ll +++ /dev/null @@ -1,15 +0,0 @@ -;RUN: llvm-as < %s | llc -march=pic16 - -@aa = global i16 55, align 1 ; [#uses=1] -@bb = global i16 44, align 1 ; [#uses=1] -@PORTD = external global i8 ; [#uses=1] - -define void @foo() nounwind { -entry: - %tmp = volatile load i16* @aa ; [#uses=1] - %tmp1 = volatile load i16* @bb ; [#uses=1] - %sub = sub i16 %tmp, %tmp1 ; [#uses=1] - %conv = trunc i16 %sub to i8 ; [#uses=1] - store i8 %conv, i8* @PORTD - ret void -} diff --git a/test/CodeGen/PIC16/check_inc_files.ll b/test/CodeGen/PIC16/check_inc_files.ll deleted file mode 100644 index 436d416..0000000 --- a/test/CodeGen/PIC16/check_inc_files.ll +++ /dev/null @@ -1,9 +0,0 @@ -; RUN: llvm-as < %s | llc -march=pic16 | FileCheck %s - -;CHECK: #include p16f1xxx.inc -;CHECK: #include stdmacros.inc - -define void @foo() nounwind { -entry: - ret void -} diff --git a/test/CodeGen/PIC16/dg.exp b/test/CodeGen/PIC16/dg.exp deleted file mode 100644 index b08b985..0000000 --- a/test/CodeGen/PIC16/dg.exp +++ /dev/null @@ -1,5 +0,0 @@ -load_lib llvm.exp - -if { [llvm_supports_target PIC16] } { - RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]] -} diff --git a/test/CodeGen/PIC16/global-in-user-section.ll b/test/CodeGen/PIC16/global-in-user-section.ll deleted file mode 100644 index 6cdb648..0000000 --- a/test/CodeGen/PIC16/global-in-user-section.ll +++ /dev/null @@ -1,6 +0,0 @@ -; RUN: llc < %s -march=pic16 | FileCheck %s -; XFAIL: vg_leak - -@G1 = common global i16 0, section "usersection", align 1 -; CHECK: usersection UDATA -; CHECK: @G1 RES 2 diff --git a/test/CodeGen/PIC16/globals.ll b/test/CodeGen/PIC16/globals.ll deleted file mode 100644 index 3ee2e25..0000000 --- a/test/CodeGen/PIC16/globals.ll +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: llc < %s -march=pic16 | FileCheck %s -; XFAIL: vg_leak - -@G1 = global i32 4712, section "Address=412" -; CHECK: @G1.412..user_section.# IDATA 412 -; CHECK: @G1 -; CHECK: dl 4712 - -@G2 = global i32 0, section "Address=412" -; CHECK: @G2.412..user_section.# UDATA 412 -; CHECK: @G2 RES 4 - -@G3 = addrspace(1) constant i32 4712, section "Address=412" -; CHECK: @G3.412..user_section.# ROMDATA 412 -; CHECK: @G3 -; CHECK: rom_dl 4712 - - diff --git a/test/CodeGen/PIC16/result_direction.ll b/test/CodeGen/PIC16/result_direction.ll deleted file mode 100644 index 8549e21..0000000 --- a/test/CodeGen/PIC16/result_direction.ll +++ /dev/null @@ -1,13 +0,0 @@ -; RUN: llvm-as < %s | llc -march=pic16 | FileCheck %s - -@a = common global i16 0, align 1 ; [#uses=2] - -define void @foo() nounwind { -entry: - %tmp = load i16* @a ; [#uses=1] - %add = add nsw i16 %tmp, 1 ; [#uses=1] - store i16 %add, i16* @a -;CHECK: movlw 1 -;CHECK: addwf @a + 0, F - ret void -} diff --git a/test/CodeGen/PIC16/sext.ll b/test/CodeGen/PIC16/sext.ll deleted file mode 100644 index e51a542..0000000 --- a/test/CodeGen/PIC16/sext.ll +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: llc < %s -march=pic16 -; XFAIL: vg_leak - -@main.auto.c = internal global i8 0 ; [#uses=1] - -define i16 @main() nounwind { -entry: - %tmp = load i8* @main.auto.c ; [#uses=1] - %conv = sext i8 %tmp to i16 ; [#uses=1] - ret i16 %conv -} diff --git a/test/CodeGen/PIC16/test_indf_name.ll b/test/CodeGen/PIC16/test_indf_name.ll deleted file mode 100644 index d52fc11..0000000 --- a/test/CodeGen/PIC16/test_indf_name.ll +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: llvm-as < %s | llc -march=pic16 | FileCheck %s - -@pi = common global i16* null, align 1 ; [#uses=1] - -define void @foo() nounwind { -entry: - %tmp = load i16** @pi ; [#uses=1] - store i16 1, i16* %tmp -; CHECK: movwi {{[0-1]}}[INDF{{[0-1]}}] -; CHECK: movwi {{[0-1]}}[INDF{{[0-1]}}] - ret void -} diff --git a/test/CodeGen/PTX/add.ll b/test/CodeGen/PTX/add.ll new file mode 100644 index 0000000..1259d03 --- /dev/null +++ b/test/CodeGen/PTX/add.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=ptx | FileCheck %s + +define ptx_device i32 @t1(i32 %x, i32 %y) { +; CHECK: add.s32 r0, r1, r2; + %z = add i32 %x, %y +; CHECK: ret; + ret i32 %z +} + +define ptx_device i32 @t2(i32 %x) { +; CHECK: add.s32 r0, r1, 1; + %z = add i32 %x, 1 +; CHECK: ret; + ret i32 %z +} diff --git a/test/CodeGen/PTX/dg.exp b/test/CodeGen/PTX/dg.exp new file mode 100644 index 0000000..2c304b5 --- /dev/null +++ b/test/CodeGen/PTX/dg.exp @@ -0,0 +1,5 @@ +load_lib llvm.exp + +if { [llvm_supports_target PTX] } { + RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]] +} diff --git a/test/CodeGen/PTX/exit.ll b/test/CodeGen/PTX/exit.ll new file mode 100644 index 0000000..4071bab --- /dev/null +++ b/test/CodeGen/PTX/exit.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -march=ptx | FileCheck %s + +define ptx_kernel void @t1() { +; CHECK: exit; +; CHECK-NOT: ret; + ret void +} + +define ptx_kernel void @t2(i32* %p, i32 %x) { + store i32 %x, i32* %p +; CHECK: exit; +; CHECK-NOT: ret; + ret void +} diff --git a/test/CodeGen/PTX/ld.ll b/test/CodeGen/PTX/ld.ll new file mode 100644 index 0000000..836c4d4 --- /dev/null +++ b/test/CodeGen/PTX/ld.ll @@ -0,0 +1,78 @@ +; RUN: llc < %s -march=ptx | FileCheck %s + +;CHECK: .extern .global .s32 array[]; +@array = external global [10 x i32] + +;CHECK: .extern .const .s32 array_constant[]; +@array_constant = external addrspace(1) constant [10 x i32] + +;CHECK: .extern .local .s32 array_local[]; +@array_local = external addrspace(2) global [10 x i32] + +;CHECK: .extern .shared .s32 array_shared[]; +@array_shared = external addrspace(4) global [10 x i32] + +define ptx_device i32 @t1(i32* %p) { +entry: +;CHECK: ld.global.s32 r0, [r1]; + %x = load i32* %p + ret i32 %x +} + +define ptx_device i32 @t2(i32* %p) { +entry: +;CHECK: ld.global.s32 r0, [r1+4]; + %i = getelementptr i32* %p, i32 1 + %x = load i32* %i + ret i32 %x +} + +define ptx_device i32 @t3(i32* %p, i32 %q) { +entry: +;CHECK: shl.b32 r0, r2, 2; +;CHECK: add.s32 r0, r1, r0; +;CHECK: ld.global.s32 r0, [r0]; + %i = getelementptr i32* %p, i32 %q + %x = load i32* %i + ret i32 %x +} + +define ptx_device i32 @t4_global() { +entry: +;CHECK: ld.global.s32 r0, [array]; + %i = getelementptr [10 x i32]* @array, i32 0, i32 0 + %x = load i32* %i + ret i32 %x +} + +define ptx_device i32 @t4_const() { +entry: +;CHECK: ld.const.s32 r0, [array_constant]; + %i = getelementptr [10 x i32] addrspace(1)* @array_constant, i32 0, i32 0 + %x = load i32 addrspace(1)* %i + ret i32 %x +} + +define ptx_device i32 @t4_local() { +entry: +;CHECK: ld.local.s32 r0, [array_local]; + %i = getelementptr [10 x i32] addrspace(2)* @array_local, i32 0, i32 0 + %x = load i32 addrspace(2)* %i + ret i32 %x +} + +define ptx_device i32 @t4_shared() { +entry: +;CHECK: ld.shared.s32 r0, [array_shared]; + %i = getelementptr [10 x i32] addrspace(4)* @array_shared, i32 0, i32 0 + %x = load i32 addrspace(4)* %i + ret i32 %x +} + +define ptx_device i32 @t5() { +entry: +;CHECK: ld.global.s32 r0, [array+4]; + %i = getelementptr [10 x i32]* @array, i32 0, i32 1 + %x = load i32* %i + ret i32 %x +} diff --git a/test/CodeGen/PTX/mov.ll b/test/CodeGen/PTX/mov.ll new file mode 100644 index 0000000..c365e9b --- /dev/null +++ b/test/CodeGen/PTX/mov.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=ptx | FileCheck %s + +define ptx_device i32 @t1() { +; CHECK: mov.s32 r0, 0; +; CHECK: ret; + ret i32 0 +} + +define ptx_device i32 @t2(i32 %x) { +; CHECK: mov.s32 r0, r1; +; CHECK: ret; + ret i32 %x +} diff --git a/test/CodeGen/PTX/options.ll b/test/CodeGen/PTX/options.ll new file mode 100644 index 0000000..a14d5c9 --- /dev/null +++ b/test/CodeGen/PTX/options.ll @@ -0,0 +1,6 @@ +; RUN: llc < %s -march=ptx -ptx-version=2.0 | grep ".version 2.0" +; RUN: llc < %s -march=ptx -ptx-target=sm_20 | grep ".target sm_20" + +define ptx_device void @t1() { + ret void +} diff --git a/test/CodeGen/PTX/ret.ll b/test/CodeGen/PTX/ret.ll new file mode 100644 index 0000000..d5037f2 --- /dev/null +++ b/test/CodeGen/PTX/ret.ll @@ -0,0 +1,7 @@ +; RUN: llc < %s -march=ptx | FileCheck %s + +define ptx_device void @t1() { +; CHECK: ret; +; CHECK-NOT: exit; + ret void +} diff --git a/test/CodeGen/PTX/shl.ll b/test/CodeGen/PTX/shl.ll new file mode 100644 index 0000000..b564b43 --- /dev/null +++ b/test/CodeGen/PTX/shl.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -march=ptx | FileCheck %s + +define ptx_device i32 @t1(i32 %x, i32 %y) { +; CHECK: shl.b32 r0, r1, r2 + %z = shl i32 %x, %y +; CHECK: ret; + ret i32 %z +} + +define ptx_device i32 @t2(i32 %x) { +; CHECK: shl.b32 r0, r1, 3 + %z = shl i32 %x, 3 +; CHECK: ret; + ret i32 %z +} + +define ptx_device i32 @t3(i32 %x) { +; CHECK: shl.b32 r0, 3, r1 + %z = shl i32 3, %x +; CHECK: ret; + ret i32 %z +} diff --git a/test/CodeGen/PTX/shr.ll b/test/CodeGen/PTX/shr.ll new file mode 100644 index 0000000..3f8ade8 --- /dev/null +++ b/test/CodeGen/PTX/shr.ll @@ -0,0 +1,43 @@ +; RUN: llc < %s -march=ptx | FileCheck %s + +define ptx_device i32 @t1(i32 %x, i32 %y) { +; CHECK: shr.u32 r0, r1, r2 + %z = lshr i32 %x, %y +; CHECK: ret; + ret i32 %z +} + +define ptx_device i32 @t2(i32 %x) { +; CHECK: shr.u32 r0, r1, 3 + %z = lshr i32 %x, 3 +; CHECK: ret; + ret i32 %z +} + +define ptx_device i32 @t3(i32 %x) { +; CHECK: shr.u32 r0, 3, r1 + %z = lshr i32 3, %x +; CHECK: ret; + ret i32 %z +} + +define ptx_device i32 @t4(i32 %x, i32 %y) { +; CHECK: shr.s32 r0, r1, r2 + %z = ashr i32 %x, %y +; CHECK: ret; + ret i32 %z +} + +define ptx_device i32 @t5(i32 %x) { +; CHECK: shr.s32 r0, r1, 3 + %z = ashr i32 %x, 3 +; CHECK: ret; + ret i32 %z +} + +define ptx_device i32 @t6(i32 %x) { +; CHECK: shr.s32 r0, -3, r1 + %z = ashr i32 -3, %x +; CHECK: ret; + ret i32 %z +} diff --git a/test/CodeGen/PTX/st.ll b/test/CodeGen/PTX/st.ll new file mode 100644 index 0000000..2cbacb9 --- /dev/null +++ b/test/CodeGen/PTX/st.ll @@ -0,0 +1,71 @@ +; RUN: llc < %s -march=ptx | FileCheck %s + +;CHECK: .extern .global .s32 array[]; +@array = external global [10 x i32] + +;CHECK: .extern .const .s32 array_constant[]; +@array_constant = external addrspace(1) constant [10 x i32] + +;CHECK: .extern .local .s32 array_local[]; +@array_local = external addrspace(2) global [10 x i32] + +;CHECK: .extern .shared .s32 array_shared[]; +@array_shared = external addrspace(4) global [10 x i32] + +define ptx_device void @t1(i32* %p, i32 %x) { +entry: +;CHECK: st.global.s32 [r1], r2; + store i32 %x, i32* %p + ret void +} + +define ptx_device void @t2(i32* %p, i32 %x) { +entry: +;CHECK: st.global.s32 [r1+4], r2; + %i = getelementptr i32* %p, i32 1 + store i32 %x, i32* %i + ret void +} + +define ptx_device void @t3(i32* %p, i32 %q, i32 %x) { +;CHECK: .reg .s32 r0; +entry: +;CHECK: shl.b32 r0, r2, 2; +;CHECK: add.s32 r0, r1, r0; +;CHECK: st.global.s32 [r0], r3; + %i = getelementptr i32* %p, i32 %q + store i32 %x, i32* %i + ret void +} + +define ptx_device void @t4_global(i32 %x) { +entry: +;CHECK: st.global.s32 [array], r1; + %i = getelementptr [10 x i32]* @array, i32 0, i32 0 + store i32 %x, i32* %i + ret void +} + +define ptx_device void @t4_local(i32 %x) { +entry: +;CHECK: st.local.s32 [array_local], r1; + %i = getelementptr [10 x i32] addrspace(2)* @array_local, i32 0, i32 0 + store i32 %x, i32 addrspace(2)* %i + ret void +} + +define ptx_device void @t4_shared(i32 %x) { +entry: +;CHECK: st.shared.s32 [array_shared], r1; + %i = getelementptr [10 x i32] addrspace(4)* @array_shared, i32 0, i32 0 + store i32 %x, i32 addrspace(4)* %i + ret void +} + +define ptx_device void @t5(i32 %x) { +entry: +;CHECK: st.global.s32 [array+4], r1; + %i = getelementptr [10 x i32]* @array, i32 0, i32 1 + store i32 %x, i32* %i + ret void +} diff --git a/test/CodeGen/PTX/sub.ll b/test/CodeGen/PTX/sub.ll new file mode 100644 index 0000000..aab3fda --- /dev/null +++ b/test/CodeGen/PTX/sub.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=ptx | FileCheck %s + +define ptx_device i32 @t1(i32 %x, i32 %y) { +;CHECK: sub.s32 r0, r1, r2; + %z = sub i32 %x, %y +;CHECK: ret; + ret i32 %z +} + +define ptx_device i32 @t2(i32 %x) { +;CHECK: add.s32 r0, r1, -1; + %z = sub i32 %x, 1 +;CHECK: ret; + ret i32 %z +} diff --git a/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll b/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll index e93395a..cca9e65 100644 --- a/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll +++ b/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=ppc64 -mcpu=g5 | grep cntlzd -define i32 @_ZNK4llvm5APInt17countLeadingZerosEv(i64 *%t) { +define i32 @_ZNK4llvm5APInt17countLeadingZerosEv(i64 *%t) nounwind { %tmp19 = load i64* %t %tmp22 = tail call i64 @llvm.ctlz.i64( i64 %tmp19 ) ; [#uses=1] %tmp23 = trunc i64 %tmp22 to i32 diff --git a/test/CodeGen/PowerPC/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/PowerPC/2010-04-07-DbgValueOtherTargets.ll index f48f32f..4a85098 100644 --- a/test/CodeGen/PowerPC/2010-04-07-DbgValueOtherTargets.ll +++ b/test/CodeGen/PowerPC/2010-04-07-DbgValueOtherTargets.ll @@ -1,33 +1,28 @@ ; RUN: llc -O0 -march=ppc32 -asm-verbose < %s | FileCheck %s ; Check that DEBUG_VALUE comments come through on a variety of targets. -%tart.reflect.ComplexType = type { double, double } - -@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } - -define i32 @"main(tart.core.String[])->int32"(i32 %args) { +define i32 @main() nounwind ssp { entry: ; CHECK: DEBUG_VALUE - tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) - tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] - ret i32 3 + call void @llvm.dbg.value(metadata !6, i64 0, metadata !7), !dbg !9 + ret i32 0, !dbg !10 } +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone -declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone -!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] -!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] -!3 = metadata !{metadata !4, metadata !6, metadata !7} -!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] -!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] -!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] -!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] -!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] -!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] -!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] -!12 = metadata !{metadata !13} -!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} +!llvm.dbg.sp = !{!0} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !"clang version 2.9 (trunk 120996)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 589860, metadata !2, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 0} +!7 = metadata !{i32 590080, metadata !8, metadata !"i", metadata !1, i32 3, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!8 = metadata !{i32 589835, metadata !0, i32 2, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!9 = metadata !{i32 3, i32 11, metadata !8, null} +!10 = metadata !{i32 4, i32 2, metadata !8, null} + diff --git a/test/CodeGen/PowerPC/2010-10-11-Fast-Varargs.ll b/test/CodeGen/PowerPC/2010-10-11-Fast-Varargs.ll new file mode 100644 index 0000000..da77b28 --- /dev/null +++ b/test/CodeGen/PowerPC/2010-10-11-Fast-Varargs.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -O0 +; PR8357 +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32" +target triple = "powerpc-unknown-freebsd9.0" + +; RegAllocFast requires that each physreg only be used once. The varargs +; lowering code needs to use virtual registers when storing live-in registers on +; the stack. + +define i32 @testing(i32 %x, float %a, ...) nounwind { + %1 = alloca i32, align 4 + %2 = alloca float, align 4 + store i32 %x, i32* %1, align 4 + store float %a, float* %2, align 4 + ret i32 0 +} diff --git a/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll b/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll new file mode 100644 index 0000000..bf3d577 --- /dev/null +++ b/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll @@ -0,0 +1,22 @@ +; RUN: llc -disable-fp-elim < %s | FileCheck %s +; PR8749 +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32" +target triple = "powerpc-apple-darwin9.8" + +define i32 @main() nounwind { +entry: +; Make sure we're generating references using the red zone +; CHECK: main: +; CHECK: stw r3, -12(r1) + %retval = alloca i32 + %0 = alloca i32 + %"alloca point" = bitcast i32 0 to i32 + store i32 0, i32* %0, align 4 + %1 = load i32* %0, align 4 + store i32 %1, i32* %retval, align 4 + br label %return + +return: ; preds = %entry + %retval1 = load i32* %retval + ret i32 %retval1 +} diff --git a/test/CodeGen/PowerPC/align.ll b/test/CodeGen/PowerPC/align.ll index 109a837..0797ca8 100644 --- a/test/CodeGen/PowerPC/align.ll +++ b/test/CodeGen/PowerPC/align.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -mtriple=powerpc-linux-gnu | FileCheck %s -check-prefix=ELF ; RUN: llc < %s -mtriple=powerpc-apple-darwin9 | FileCheck %s -check-prefix=DARWIN +; RUN: llc < %s -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=DARWIN8 @a = global i1 true ; no alignment @@ -40,3 +41,6 @@ @bar = common global [75 x i8] zeroinitializer, align 128 ;ELF: .comm bar,75,128 ;DARWIN: .comm _bar,75,7 + +;; Darwin8 doesn't support aligned comm. Just miscompile this. +; DARWIN8: .comm _bar,75 ; diff --git a/test/CodeGen/PowerPC/compare-simm.ll b/test/CodeGen/PowerPC/compare-simm.ll index 5ba0500..92d1dbe 100644 --- a/test/CodeGen/PowerPC/compare-simm.ll +++ b/test/CodeGen/PowerPC/compare-simm.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ ; RUN: grep {cmpwi cr0, r3, -1} -define i32 @test(i32 %x) { +define i32 @test(i32 %x) nounwind { %c = icmp eq i32 %x, -1 br i1 %c, label %T, label %F T: diff --git a/test/CodeGen/PowerPC/indirectbr.ll b/test/CodeGen/PowerPC/indirectbr.ll index ab8d9dc..5122ab3 100644 --- a/test/CodeGen/PowerPC/indirectbr.ll +++ b/test/CodeGen/PowerPC/indirectbr.ll @@ -43,8 +43,8 @@ L2: ; preds = %L3, %bb2 L1: ; preds = %L2, %bb2 %res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ] ; [#uses=1] -; PIC: addis r4, r4, ha16(Ltmp0-"L0$pb") -; PIC: li r6, lo16(Ltmp0-"L0$pb") +; PIC: addis r4, r4, ha16(Ltmp0-L0$pb) +; PIC: li r6, lo16(Ltmp0-L0$pb) ; PIC: add r4, r4, r6 ; PIC: stw r4 ; STATIC: li r5, lo16(Ltmp0) diff --git a/test/CodeGen/PowerPC/mult-alt-generic-powerpc.ll b/test/CodeGen/PowerPC/mult-alt-generic-powerpc.ll new file mode 100644 index 0000000..659cdf7 --- /dev/null +++ b/test/CodeGen/PowerPC/mult-alt-generic-powerpc.ll @@ -0,0 +1,321 @@ +; RUN: llc < %s -march=ppc32 +; ModuleID = 'mult-alt-generic.c' +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32" +target triple = "powerpc" + +@mout0 = common global i32 0, align 4 +@min1 = common global i32 0, align 4 +@marray = common global [2 x i32] zeroinitializer, align 4 + +define void @single_m() nounwind { +entry: + call void asm "foo $1,$0", "=*m,*m"(i32* @mout0, i32* @min1) nounwind + ret void +} + +define void @single_o() nounwind { +entry: + %out0 = alloca i32, align 4 + %index = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %index, align 4 + ret void +} + +define void @single_V() nounwind { +entry: + ret void +} + +define void @single_lt() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* %in1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,r>"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + ret void +} + +define void @single_r() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @single_i() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,i"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @single_n() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,n"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @single_E() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r,E"(double 1.000000e+001) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @single_F() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r,F"(double 1.000000e+000) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @single_s() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + ret void +} + +define void @single_g() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r,imr"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + ret void +} + +define void @single_X() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r,X"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + %3 = call i32 asm "foo $1,$0", "=r,X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %3, i32* %out0, align 4 + %4 = call i32 asm "foo $1,$0", "=r,X"(double 1.000000e+001) nounwind + store i32 %4, i32* %out0, align 4 + %5 = call i32 asm "foo $1,$0", "=r,X"(double 1.000000e+000) nounwind + store i32 %5, i32* %out0, align 4 + ret void +} + +define void @single_p() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_m() nounwind { +entry: + %tmp = load i32* @min1, align 4 + call void asm "foo $1,$0", "=*m|r,m|r"(i32* @mout0, i32 %tmp) nounwind + ret void +} + +define void @multi_o() nounwind { +entry: + %out0 = alloca i32, align 4 + %index = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %index, align 4 + ret void +} + +define void @multi_V() nounwind { +entry: + ret void +} + +define void @multi_lt() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* %in1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|r>"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + ret void +} + +define void @multi_r() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|m"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_i() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|i"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_n() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|n"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_E() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r|r,r|E"(double 1.000000e+001) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @multi_F() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r|r,r|F"(double 1.000000e+000) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @multi_s() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + ret void +} + +define void @multi_g() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + ret void +} + +define void @multi_X() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + %3 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %3, i32* %out0, align 4 + %4 = call i32 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+001) nounwind + store i32 %4, i32* %out0, align 4 + %5 = call i32 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+000) nounwind + store i32 %5, i32* %out0, align 4 + ret void +} + +define void @multi_p() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} diff --git a/test/CodeGen/PowerPC/mult-alt-generic-powerpc64.ll b/test/CodeGen/PowerPC/mult-alt-generic-powerpc64.ll new file mode 100644 index 0000000..3da06f6 --- /dev/null +++ b/test/CodeGen/PowerPC/mult-alt-generic-powerpc64.ll @@ -0,0 +1,321 @@ +; RUN: llc < %s -march=ppc64 +; ModuleID = 'mult-alt-generic.c' +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" +target triple = "powerpc64" + +@mout0 = common global i32 0, align 4 +@min1 = common global i32 0, align 4 +@marray = common global [2 x i32] zeroinitializer, align 4 + +define void @single_m() nounwind { +entry: + call void asm "foo $1,$0", "=*m,*m"(i32* @mout0, i32* @min1) nounwind + ret void +} + +define void @single_o() nounwind { +entry: + %out0 = alloca i32, align 4 + %index = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %index, align 4 + ret void +} + +define void @single_V() nounwind { +entry: + ret void +} + +define void @single_lt() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* %in1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,r>"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + ret void +} + +define void @single_r() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @single_i() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,i"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @single_n() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,n"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @single_E() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r,E"(double 1.000000e+001) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @single_F() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r,F"(double 1.000000e+000) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @single_s() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + ret void +} + +define void @single_g() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r,imr"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + ret void +} + +define void @single_X() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r,X"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + %3 = call i32 asm "foo $1,$0", "=r,X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %3, i32* %out0, align 4 + %4 = call i32 asm "foo $1,$0", "=r,X"(double 1.000000e+001) nounwind + store i32 %4, i32* %out0, align 4 + %5 = call i32 asm "foo $1,$0", "=r,X"(double 1.000000e+000) nounwind + store i32 %5, i32* %out0, align 4 + ret void +} + +define void @single_p() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_m() nounwind { +entry: + %tmp = load i32* @min1, align 4 + call void asm "foo $1,$0", "=*m|r,m|r"(i32* @mout0, i32 %tmp) nounwind + ret void +} + +define void @multi_o() nounwind { +entry: + %out0 = alloca i32, align 4 + %index = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %index, align 4 + ret void +} + +define void @multi_V() nounwind { +entry: + ret void +} + +define void @multi_lt() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* %in1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|r>"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + ret void +} + +define void @multi_r() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|m"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_i() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|i"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_n() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|n"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_E() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r|r,r|E"(double 1.000000e+001) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @multi_F() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r|r,r|F"(double 1.000000e+000) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @multi_s() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + ret void +} + +define void @multi_g() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + ret void +} + +define void @multi_X() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + %3 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %3, i32* %out0, align 4 + %4 = call i32 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+001) nounwind + store i32 %4, i32* %out0, align 4 + %5 = call i32 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+000) nounwind + store i32 %5, i32* %out0, align 4 + ret void +} + +define void @multi_p() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} diff --git a/test/CodeGen/PowerPC/rlwimi2.ll b/test/CodeGen/PowerPC/rlwimi2.ll index 59a3655..1bee4e0 100644 --- a/test/CodeGen/PowerPC/rlwimi2.ll +++ b/test/CodeGen/PowerPC/rlwimi2.ll @@ -4,7 +4,7 @@ ; RUN: grep srwi %t | count 1 ; RUN: not grep slwi %t -define i16 @test1(i32 %srcA, i32 %srcB, i32 %alpha) { +define i16 @test1(i32 %srcA, i32 %srcB, i32 %alpha) nounwind { entry: %tmp.1 = shl i32 %srcA, 15 ; [#uses=1] %tmp.4 = and i32 %tmp.1, 32505856 ; [#uses=1] diff --git a/test/CodeGen/PowerPC/stfiwx.ll b/test/CodeGen/PowerPC/stfiwx.ll index d1c3f52..1ad558c 100644 --- a/test/CodeGen/PowerPC/stfiwx.ll +++ b/test/CodeGen/PowerPC/stfiwx.ll @@ -6,13 +6,13 @@ ; RUN: not grep stfiwx %t2 ; RUN: grep r1 %t2 -define void @test(float %a, i32* %b) { +define void @test(float %a, i32* %b) nounwind { %tmp.2 = fptosi float %a to i32 ; [#uses=1] store i32 %tmp.2, i32* %b ret void } -define void @test2(float %a, i32* %b, i32 %i) { +define void @test2(float %a, i32* %b, i32 %i) nounwind { %tmp.2 = getelementptr i32* %b, i32 1 ; [#uses=1] %tmp.5 = getelementptr i32* %b, i32 %i ; [#uses=1] %tmp.7 = fptosi float %a to i32 ; [#uses=3] diff --git a/test/CodeGen/PowerPC/tango.net.ftp.FtpClient.ll b/test/CodeGen/PowerPC/tango.net.ftp.FtpClient.ll deleted file mode 100644 index 6f10346..0000000 --- a/test/CodeGen/PowerPC/tango.net.ftp.FtpClient.ll +++ /dev/null @@ -1,585 +0,0 @@ -; RN: llc < %s -; RUN: false -; XFAIL: * -; PR4534 - -; ModuleID = 'tango.net.ftp.FtpClient.bc' -target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" -target triple = "powerpc-apple-darwin9.6.0" - %"byte[]" = type { i32, i8* } -@.str167 = external constant [11 x i8] ; <[11 x i8]*> [#uses=1] -@.str170 = external constant [11 x i8] ; <[11 x i8]*> [#uses=2] -@.str171 = external constant [5 x i8] ; <[5 x i8]*> [#uses=1] -@llvm.used = appending global [1 x i8*] [i8* bitcast (void (%"byte[]")* @foo to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] - -define fastcc void @foo(%"byte[]" %line_arg) { -entry: - %line_arg830 = extractvalue %"byte[]" %line_arg, 0 ; [#uses=12] - %line_arg831 = extractvalue %"byte[]" %line_arg, 1 ; [#uses=17] - %t5 = load i8* %line_arg831 ; [#uses=1] - br label %forcondi - -forcondi: ; preds = %forbodyi, %entry - %l.0i = phi i32 [ 10, %entry ], [ %t4i, %forbodyi ] ; [#uses=2] - %p.0i = phi i8* [ getelementptr ([11 x i8]* @.str167, i32 0, i32 -1), %entry ], [ %t7i, %forbodyi ] ; [#uses=1] - %t4i = add i32 %l.0i, -1 ; [#uses=1] - %t5i = icmp eq i32 %l.0i, 0 ; [#uses=1] - br i1 %t5i, label %forcond.i, label %forbodyi - -forbodyi: ; preds = %forcondi - %t7i = getelementptr i8* %p.0i, i32 1 ; [#uses=2] - %t8i = load i8* %t7i ; [#uses=1] - %t12i = icmp eq i8 %t8i, %t5 ; [#uses=1] - br i1 %t12i, label %forcond.i, label %forcondi - -forcond.i: ; preds = %forbody.i, %forbodyi, %forcondi - %storemerge.i = phi i32 [ %t106.i, %forbody.i ], [ 1, %forcondi ], [ 1, %forbodyi ] ; [#uses=1] - %t77.i286 = phi i1 [ %phit3, %forbody.i ], [ false, %forcondi ], [ false, %forbodyi ] ; [#uses=1] - br i1 %t77.i286, label %forcond.i295, label %forbody.i - -forbody.i: ; preds = %forcond.i - %t106.i = add i32 %storemerge.i, 1 ; [#uses=2] - %phit3 = icmp ugt i32 %t106.i, 3 ; [#uses=1] - br label %forcond.i - -forcond.i295: ; preds = %forbody.i301, %forcond.i - %storemerge.i292 = phi i32 [ %t106.i325, %forbody.i301 ], [ 4, %forcond.i ] ; [#uses=1] - %t77.i293 = phi i1 [ %phit2, %forbody.i301 ], [ false, %forcond.i ] ; [#uses=1] - br i1 %t77.i293, label %forcond.i332, label %forbody.i301 - -forbody.i301: ; preds = %forcond.i295 - %t106.i325 = add i32 %storemerge.i292, 1 ; [#uses=2] - %phit2 = icmp ugt i32 %t106.i325, 6 ; [#uses=1] - br label %forcond.i295 - -forcond.i332: ; preds = %forbody.i338, %forcond.i295 - %storemerge.i329 = phi i32 [ %t106.i362, %forbody.i338 ], [ 7, %forcond.i295 ] ; [#uses=3] - %t77.i330 = phi i1 [ %phit1, %forbody.i338 ], [ false, %forcond.i295 ] ; [#uses=1] - br i1 %t77.i330, label %wcond.i370, label %forbody.i338 - -forbody.i338: ; preds = %forcond.i332 - %t106.i362 = add i32 %storemerge.i329, 1 ; [#uses=2] - %phit1 = icmp ugt i32 %t106.i362, 9 ; [#uses=1] - br label %forcond.i332 - -wcond.i370: ; preds = %wbody.i372, %forcond.i332 - %.frame.0.11 = phi i32 [ %t18.i371.c, %wbody.i372 ], [ %storemerge.i329, %forcond.i332 ] ; [#uses=2] - %t3.i368 = phi i32 [ %t18.i371.c, %wbody.i372 ], [ %storemerge.i329, %forcond.i332 ] ; [#uses=5] - %t4.i369 = icmp ult i32 %t3.i368, %line_arg830 ; [#uses=1] - br i1 %t4.i369, label %andand.i378, label %wcond22.i383 - -wbody.i372: ; preds = %andand.i378 - %t18.i371.c = add i32 %t3.i368, 1 ; [#uses=2] - br label %wcond.i370 - -andand.i378: ; preds = %wcond.i370 - %t11.i375 = getelementptr i8* %line_arg831, i32 %t3.i368 ; [#uses=1] - %t12.i376 = load i8* %t11.i375 ; [#uses=1] - %t14.i377 = icmp eq i8 %t12.i376, 32 ; [#uses=1] - br i1 %t14.i377, label %wbody.i372, label %wcond22.i383 - -wcond22.i383: ; preds = %wbody23.i385, %andand.i378, %wcond.i370 - %.frame.0.10 = phi i32 [ %t50.i384, %wbody23.i385 ], [ %.frame.0.11, %wcond.i370 ], [ %.frame.0.11, %andand.i378 ] ; [#uses=2] - %t49.i381 = phi i32 [ %t50.i384, %wbody23.i385 ], [ %t3.i368, %wcond.i370 ], [ %t3.i368, %andand.i378 ] ; [#uses=5] - %t32.i382 = icmp ult i32 %t49.i381, %line_arg830 ; [#uses=1] - br i1 %t32.i382, label %andand33.i391, label %wcond54.i396 - -wbody23.i385: ; preds = %andand33.i391 - %t50.i384 = add i32 %t49.i381, 1 ; [#uses=2] - br label %wcond22.i383 - -andand33.i391: ; preds = %wcond22.i383 - %t42.i388 = getelementptr i8* %line_arg831, i32 %t49.i381 ; [#uses=1] - %t43.i389 = load i8* %t42.i388 ; [#uses=1] - %t45.i390 = icmp eq i8 %t43.i389, 32 ; [#uses=1] - br i1 %t45.i390, label %wcond54.i396, label %wbody23.i385 - -wcond54.i396: ; preds = %wbody55.i401, %andand33.i391, %wcond22.i383 - %.frame.0.9 = phi i32 [ %t82.i400, %wbody55.i401 ], [ %.frame.0.10, %wcond22.i383 ], [ %.frame.0.10, %andand33.i391 ] ; [#uses=2] - %t81.i394 = phi i32 [ %t82.i400, %wbody55.i401 ], [ %t49.i381, %wcond22.i383 ], [ %t49.i381, %andand33.i391 ] ; [#uses=3] - %t64.i395 = icmp ult i32 %t81.i394, %line_arg830 ; [#uses=1] - br i1 %t64.i395, label %andand65.i407, label %wcond.i716 - -wbody55.i401: ; preds = %andand65.i407 - %t82.i400 = add i32 %t81.i394, 1 ; [#uses=2] - br label %wcond54.i396 - -andand65.i407: ; preds = %wcond54.i396 - %t74.i404 = getelementptr i8* %line_arg831, i32 %t81.i394 ; [#uses=1] - %t75.i405 = load i8* %t74.i404 ; [#uses=1] - %t77.i406 = icmp eq i8 %t75.i405, 32 ; [#uses=1] - br i1 %t77.i406, label %wbody55.i401, label %wcond.i716 - -wcond.i716: ; preds = %wbody.i717, %andand65.i407, %wcond54.i396 - %.frame.0.0 = phi i32 [ %t18.i.c829, %wbody.i717 ], [ %.frame.0.9, %wcond54.i396 ], [ %.frame.0.9, %andand65.i407 ] ; [#uses=7] - %t4.i715 = icmp ult i32 %.frame.0.0, %line_arg830 ; [#uses=1] - br i1 %t4.i715, label %andand.i721, label %wcond22.i724 - -wbody.i717: ; preds = %andand.i721 - %t18.i.c829 = add i32 %.frame.0.0, 1 ; [#uses=1] - br label %wcond.i716 - -andand.i721: ; preds = %wcond.i716 - %t11.i718 = getelementptr i8* %line_arg831, i32 %.frame.0.0 ; [#uses=1] - %t12.i719 = load i8* %t11.i718 ; [#uses=1] - %t14.i720 = icmp eq i8 %t12.i719, 32 ; [#uses=1] - br i1 %t14.i720, label %wbody.i717, label %wcond22.i724 - -wcond22.i724: ; preds = %wbody23.i726, %andand.i721, %wcond.i716 - %.frame.0.1 = phi i32 [ %t50.i725, %wbody23.i726 ], [ %.frame.0.0, %wcond.i716 ], [ %.frame.0.0, %andand.i721 ] ; [#uses=2] - %t49.i722 = phi i32 [ %t50.i725, %wbody23.i726 ], [ %.frame.0.0, %wcond.i716 ], [ %.frame.0.0, %andand.i721 ] ; [#uses=5] - %t32.i723 = icmp ult i32 %t49.i722, %line_arg830 ; [#uses=1] - br i1 %t32.i723, label %andand33.i731, label %wcond54.i734 - -wbody23.i726: ; preds = %andand33.i731 - %t50.i725 = add i32 %t49.i722, 1 ; [#uses=2] - br label %wcond22.i724 - -andand33.i731: ; preds = %wcond22.i724 - %t42.i728 = getelementptr i8* %line_arg831, i32 %t49.i722 ; [#uses=1] - %t43.i729 = load i8* %t42.i728 ; [#uses=1] - %t45.i730 = icmp eq i8 %t43.i729, 32 ; [#uses=1] - br i1 %t45.i730, label %wcond54.i734, label %wbody23.i726 - -wcond54.i734: ; preds = %wbody55.i736, %andand33.i731, %wcond22.i724 - %.frame.0.2 = phi i32 [ %t82.i735, %wbody55.i736 ], [ %.frame.0.1, %wcond22.i724 ], [ %.frame.0.1, %andand33.i731 ] ; [#uses=2] - %t81.i732 = phi i32 [ %t82.i735, %wbody55.i736 ], [ %t49.i722, %wcond22.i724 ], [ %t49.i722, %andand33.i731 ] ; [#uses=3] - %t64.i733 = icmp ult i32 %t81.i732, %line_arg830 ; [#uses=1] - br i1 %t64.i733, label %andand65.i740, label %wcond.i750 - -wbody55.i736: ; preds = %andand65.i740 - %t82.i735 = add i32 %t81.i732, 1 ; [#uses=2] - br label %wcond54.i734 - -andand65.i740: ; preds = %wcond54.i734 - %t74.i737 = getelementptr i8* %line_arg831, i32 %t81.i732 ; [#uses=1] - %t75.i738 = load i8* %t74.i737 ; [#uses=1] - %t77.i739 = icmp eq i8 %t75.i738, 32 ; [#uses=1] - br i1 %t77.i739, label %wbody55.i736, label %wcond.i750 - -wcond.i750: ; preds = %wbody.i752, %andand65.i740, %wcond54.i734 - %.frame.0.3 = phi i32 [ %t18.i751.c, %wbody.i752 ], [ %.frame.0.2, %wcond54.i734 ], [ %.frame.0.2, %andand65.i740 ] ; [#uses=11] - %t4.i749 = icmp ult i32 %.frame.0.3, %line_arg830 ; [#uses=1] - br i1 %t4.i749, label %andand.i758, label %wcond22.i761 - -wbody.i752: ; preds = %andand.i758 - %t18.i751.c = add i32 %.frame.0.3, 1 ; [#uses=1] - br label %wcond.i750 - -andand.i758: ; preds = %wcond.i750 - %t11.i755 = getelementptr i8* %line_arg831, i32 %.frame.0.3 ; [#uses=1] - %t12.i756 = load i8* %t11.i755 ; [#uses=1] - %t14.i757 = icmp eq i8 %t12.i756, 32 ; [#uses=1] - br i1 %t14.i757, label %wbody.i752, label %wcond22.i761 - -wcond22.i761: ; preds = %wbody23.i763, %andand.i758, %wcond.i750 - %.frame.0.4 = phi i32 [ %t50.i762, %wbody23.i763 ], [ %.frame.0.3, %wcond.i750 ], [ %.frame.0.3, %andand.i758 ] ; [#uses=2] - %t49.i759 = phi i32 [ %t50.i762, %wbody23.i763 ], [ %.frame.0.3, %wcond.i750 ], [ %.frame.0.3, %andand.i758 ] ; [#uses=7] - %t32.i760 = icmp ult i32 %t49.i759, %line_arg830 ; [#uses=1] - br i1 %t32.i760, label %andand33.i769, label %wcond54.i773 - -wbody23.i763: ; preds = %andand33.i769 - %t50.i762 = add i32 %t49.i759, 1 ; [#uses=2] - br label %wcond22.i761 - -andand33.i769: ; preds = %wcond22.i761 - %t42.i766 = getelementptr i8* %line_arg831, i32 %t49.i759 ; [#uses=1] - %t43.i767 = load i8* %t42.i766 ; [#uses=1] - %t45.i768 = icmp eq i8 %t43.i767, 32 ; [#uses=1] - br i1 %t45.i768, label %wcond54.i773, label %wbody23.i763 - -wcond54.i773: ; preds = %wbody55.i775, %andand33.i769, %wcond22.i761 - %.frame.0.5 = phi i32 [ %t82.i774, %wbody55.i775 ], [ %.frame.0.4, %wcond22.i761 ], [ %.frame.0.4, %andand33.i769 ] ; [#uses=1] - %t81.i770 = phi i32 [ %t82.i774, %wbody55.i775 ], [ %t49.i759, %wcond22.i761 ], [ %t49.i759, %andand33.i769 ] ; [#uses=3] - %t64.i771 = icmp ult i32 %t81.i770, %line_arg830 ; [#uses=1] - br i1 %t64.i771, label %andand65.i780, label %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit786 - -wbody55.i775: ; preds = %andand65.i780 - %t82.i774 = add i32 %t81.i770, 1 ; [#uses=2] - br label %wcond54.i773 - -andand65.i780: ; preds = %wcond54.i773 - %t74.i777 = getelementptr i8* %line_arg831, i32 %t81.i770 ; [#uses=1] - %t75.i778 = load i8* %t74.i777 ; [#uses=1] - %t77.i779 = icmp eq i8 %t75.i778, 32 ; [#uses=1] - br i1 %t77.i779, label %wbody55.i775, label %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit786 - -Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit786: ; preds = %andand65.i780, %wcond54.i773 - %t89.i782 = getelementptr i8* %line_arg831, i32 %.frame.0.3 ; [#uses=4] - %t90.i783 = sub i32 %t49.i759, %.frame.0.3 ; [#uses=2] - br label %wcond.i792 - -wcond.i792: ; preds = %wbody.i794, %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit786 - %.frame.0.6 = phi i32 [ %.frame.0.5, %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit786 ], [ %t18.i793.c, %wbody.i794 ] ; [#uses=9] - %t4.i791 = icmp ult i32 %.frame.0.6, %line_arg830 ; [#uses=1] - br i1 %t4.i791, label %andand.i800, label %wcond22.i803 - -wbody.i794: ; preds = %andand.i800 - %t18.i793.c = add i32 %.frame.0.6, 1 ; [#uses=1] - br label %wcond.i792 - -andand.i800: ; preds = %wcond.i792 - %t11.i797 = getelementptr i8* %line_arg831, i32 %.frame.0.6 ; [#uses=1] - %t12.i798 = load i8* %t11.i797 ; [#uses=1] - %t14.i799 = icmp eq i8 %t12.i798, 32 ; [#uses=1] - br i1 %t14.i799, label %wbody.i794, label %wcond22.i803 - -wcond22.i803: ; preds = %wbody23.i805, %andand.i800, %wcond.i792 - %t49.i801 = phi i32 [ %t50.i804, %wbody23.i805 ], [ %.frame.0.6, %wcond.i792 ], [ %.frame.0.6, %andand.i800 ] ; [#uses=7] - %t32.i802 = icmp ult i32 %t49.i801, %line_arg830 ; [#uses=1] - br i1 %t32.i802, label %andand33.i811, label %wcond54.i815 - -wbody23.i805: ; preds = %andand33.i811 - %t50.i804 = add i32 %t49.i801, 1 ; [#uses=1] - br label %wcond22.i803 - -andand33.i811: ; preds = %wcond22.i803 - %t42.i808 = getelementptr i8* %line_arg831, i32 %t49.i801 ; [#uses=1] - %t43.i809 = load i8* %t42.i808 ; [#uses=1] - %t45.i810 = icmp eq i8 %t43.i809, 32 ; [#uses=1] - br i1 %t45.i810, label %wcond54.i815, label %wbody23.i805 - -wcond54.i815: ; preds = %wbody55.i817, %andand33.i811, %wcond22.i803 - %t81.i812 = phi i32 [ %t82.i816, %wbody55.i817 ], [ %t49.i801, %wcond22.i803 ], [ %t49.i801, %andand33.i811 ] ; [#uses=3] - %t64.i813 = icmp ult i32 %t81.i812, %line_arg830 ; [#uses=1] - br i1 %t64.i813, label %andand65.i822, label %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit828 - -wbody55.i817: ; preds = %andand65.i822 - %t82.i816 = add i32 %t81.i812, 1 ; [#uses=1] - br label %wcond54.i815 - -andand65.i822: ; preds = %wcond54.i815 - %t74.i819 = getelementptr i8* %line_arg831, i32 %t81.i812 ; [#uses=1] - %t75.i820 = load i8* %t74.i819 ; [#uses=1] - %t77.i821 = icmp eq i8 %t75.i820, 32 ; [#uses=1] - br i1 %t77.i821, label %wbody55.i817, label %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit828 - -Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit828: ; preds = %andand65.i822, %wcond54.i815 - %t89.i824 = getelementptr i8* %line_arg831, i32 %.frame.0.6 ; [#uses=4] - %t90.i825 = sub i32 %t49.i801, %.frame.0.6 ; [#uses=2] - %t63 = load i8* %t89.i824 ; [#uses=2] - br label %forcondi622 - -forcondi622: ; preds = %forbodyi626, %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit828 - %l.0i618 = phi i32 [ 10, %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit828 ], [ %t4i620, %forbodyi626 ] ; [#uses=2] - %p.0i619 = phi i8* [ getelementptr ([11 x i8]* @.str170, i32 0, i32 -1), %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit828 ], [ %t7i623, %forbodyi626 ] ; [#uses=1] - %t4i620 = add i32 %l.0i618, -1 ; [#uses=1] - %t5i621 = icmp eq i32 %l.0i618, 0 ; [#uses=1] - br i1 %t5i621, label %if65, label %forbodyi626 - -forbodyi626: ; preds = %forcondi622 - %t7i623 = getelementptr i8* %p.0i619, i32 1 ; [#uses=3] - %t8i624 = load i8* %t7i623 ; [#uses=1] - %t12i625 = icmp eq i8 %t8i624, %t63 ; [#uses=1] - br i1 %t12i625, label %ifi630, label %forcondi622 - -ifi630: ; preds = %forbodyi626 - %t15i627 = ptrtoint i8* %t7i623 to i32 ; [#uses=1] - %t17i629 = sub i32 %t15i627, ptrtoint ([11 x i8]* @.str170 to i32) ; [#uses=1] - %phit636 = icmp eq i32 %t17i629, 10 ; [#uses=1] - br i1 %phit636, label %if65, label %e67 - -if65: ; preds = %ifi630, %forcondi622 - %t4i532 = icmp eq i32 %t49.i759, %.frame.0.3 ; [#uses=1] - br i1 %t4i532, label %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i576, label %forcondi539 - -forcondi539: ; preds = %zi546, %if65 - %sign.1.i533 = phi i1 [ %sign.0.i543, %zi546 ], [ false, %if65 ] ; [#uses=2] - %l.0i534 = phi i32 [ %t33i545, %zi546 ], [ %t90.i783, %if65 ] ; [#uses=3] - %p.0i535 = phi i8* [ %t30i544, %zi546 ], [ %t89.i782, %if65 ] ; [#uses=6] - %c.0.ini536 = phi i8* [ %t30i544, %zi546 ], [ %t89.i782, %if65 ] ; [#uses=1] - %c.0i537 = load i8* %c.0.ini536 ; [#uses=2] - %t8i538 = icmp eq i32 %l.0i534, 0 ; [#uses=1] - br i1 %t8i538, label %endfori550, label %forbodyi540 - -forbodyi540: ; preds = %forcondi539 - switch i8 %c.0i537, label %endfori550 [ - i8 32, label %zi546 - i8 9, label %zi546 - i8 45, label %if20i541 - i8 43, label %if26i542 - ] - -if20i541: ; preds = %forbodyi540 - br label %zi546 - -if26i542: ; preds = %forbodyi540 - br label %zi546 - -zi546: ; preds = %if26i542, %if20i541, %forbodyi540, %forbodyi540 - %sign.0.i543 = phi i1 [ false, %if26i542 ], [ true, %if20i541 ], [ %sign.1.i533, %forbodyi540 ], [ %sign.1.i533, %forbodyi540 ] ; [#uses=1] - %t30i544 = getelementptr i8* %p.0i535, i32 1 ; [#uses=2] - %t33i545 = add i32 %l.0i534, -1 ; [#uses=1] - br label %forcondi539 - -endfori550: ; preds = %forbodyi540, %forcondi539 - %t37i547 = icmp eq i8 %c.0i537, 48 ; [#uses=1] - %t39i548 = icmp sgt i32 %l.0i534, 1 ; [#uses=1] - %or.condi549 = and i1 %t37i547, %t39i548 ; [#uses=1] - br i1 %or.condi549, label %if40i554, label %endif41i564 - -if40i554: ; preds = %endfori550 - %t43i551 = getelementptr i8* %p.0i535, i32 1 ; [#uses=2] - %t44i552 = load i8* %t43i551 ; [#uses=1] - %t45i553 = zext i8 %t44i552 to i32 ; [#uses=1] - switch i32 %t45i553, label %endif41i564 [ - i32 120, label %case46i556 - i32 88, label %case46i556 - i32 98, label %case51i558 - i32 66, label %case51i558 - i32 111, label %case56i560 - i32 79, label %case56i560 - ] - -case46i556: ; preds = %if40i554, %if40i554 - %t48i555 = getelementptr i8* %p.0i535, i32 2 ; [#uses=1] - br label %endif41i564 - -case51i558: ; preds = %if40i554, %if40i554 - %t53i557 = getelementptr i8* %p.0i535, i32 2 ; [#uses=1] - br label %endif41i564 - -case56i560: ; preds = %if40i554, %if40i554 - %t58i559 = getelementptr i8* %p.0i535, i32 2 ; [#uses=1] - br label %endif41i564 - -endif41i564: ; preds = %case56i560, %case51i558, %case46i556, %if40i554, %endfori550 - %r.0i561 = phi i32 [ 0, %if40i554 ], [ 8, %case56i560 ], [ 2, %case51i558 ], [ 16, %case46i556 ], [ 0, %endfori550 ] ; [#uses=2] - %p.2i562 = phi i8* [ %t43i551, %if40i554 ], [ %t58i559, %case56i560 ], [ %t53i557, %case51i558 ], [ %t48i555, %case46i556 ], [ %p.0i535, %endfori550 ] ; [#uses=2] - %t63i563 = icmp eq i32 %r.0i561, 0 ; [#uses=1] - br i1 %t63i563, label %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i576, label %if70i568 - -if70i568: ; preds = %endif41i564 - br label %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i576 - -Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i576: ; preds = %if70i568, %endif41i564, %if65 - %radix.0.i570 = phi i32 [ 0, %if65 ], [ %r.0i561, %if70i568 ], [ 10, %endif41i564 ] ; [#uses=2] - %p.1i571 = phi i8* [ %p.2i562, %if70i568 ], [ %t89.i782, %if65 ], [ %p.2i562, %endif41i564 ] ; [#uses=1] - %t84i572 = ptrtoint i8* %p.1i571 to i32 ; [#uses=1] - %t85i573 = ptrtoint i8* %t89.i782 to i32 ; [#uses=1] - %t86i574 = sub i32 %t84i572, %t85i573 ; [#uses=2] - %t6.i575 = sub i32 %t90.i783, %t86i574 ; [#uses=1] - %t59i604 = zext i32 %radix.0.i570 to i64 ; [#uses=1] - br label %fcondi581 - -fcondi581: ; preds = %if55i610, %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i576 - %value.0i577 = phi i64 [ 0, %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i576 ], [ %t65i607, %if55i610 ] ; [#uses=1] - %fkey.0i579 = phi i32 [ 0, %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i576 ], [ %t70i609, %if55i610 ] ; [#uses=3] - %t3i580 = icmp ult i32 %fkey.0i579, %t6.i575 ; [#uses=1] - br i1 %t3i580, label %fbodyi587, label %wcond.i422 - -fbodyi587: ; preds = %fcondi581 - %t5.s.i582 = add i32 %t86i574, %fkey.0i579 ; [#uses=1] - %t89.i782.s = add i32 %.frame.0.3, %t5.s.i582 ; [#uses=1] - %t5i583 = getelementptr i8* %line_arg831, i32 %t89.i782.s ; [#uses=1] - %t6i584 = load i8* %t5i583 ; [#uses=6] - %t6.off84i585 = add i8 %t6i584, -48 ; [#uses=1] - %or.cond.i28.i586 = icmp ugt i8 %t6.off84i585, 9 ; [#uses=1] - br i1 %or.cond.i28.i586, label %ei590, label %endifi603 - -ei590: ; preds = %fbodyi587 - %t6.off83i588 = add i8 %t6i584, -97 ; [#uses=1] - %or.cond81i589 = icmp ugt i8 %t6.off83i588, 25 ; [#uses=1] - br i1 %or.cond81i589, label %e24i595, label %if22i592 - -if22i592: ; preds = %ei590 - %t27i591 = add i8 %t6i584, -39 ; [#uses=1] - br label %endifi603 - -e24i595: ; preds = %ei590 - %t6.offi593 = add i8 %t6i584, -65 ; [#uses=1] - %or.cond82i594 = icmp ugt i8 %t6.offi593, 25 ; [#uses=1] - br i1 %or.cond82i594, label %wcond.i422, label %if39i597 - -if39i597: ; preds = %e24i595 - %t44.i29.i596 = add i8 %t6i584, -7 ; [#uses=1] - br label %endifi603 - -endifi603: ; preds = %if39i597, %if22i592, %fbodyi587 - %c.0.i30.i598 = phi i8 [ %t27i591, %if22i592 ], [ %t44.i29.i596, %if39i597 ], [ %t6i584, %fbodyi587 ] ; [#uses=1] - %t48.i31.i599 = zext i8 %c.0.i30.i598 to i32 ; [#uses=1] - %t49i600 = add i32 %t48.i31.i599, 208 ; [#uses=1] - %t52i601 = and i32 %t49i600, 255 ; [#uses=2] - %t54i602 = icmp ult i32 %t52i601, %radix.0.i570 ; [#uses=1] - br i1 %t54i602, label %if55i610, label %wcond.i422 - -if55i610: ; preds = %endifi603 - %t61i605 = mul i64 %value.0i577, %t59i604 ; [#uses=1] - %t64i606 = zext i32 %t52i601 to i64 ; [#uses=1] - %t65i607 = add i64 %t61i605, %t64i606 ; [#uses=1] - %t70i609 = add i32 %fkey.0i579, 1 ; [#uses=1] - br label %fcondi581 - -e67: ; preds = %ifi630 - %t4i447 = icmp eq i32 %t49.i801, %.frame.0.6 ; [#uses=1] - br i1 %t4i447, label %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i491, label %forcondi454 - -forcondi454: ; preds = %zi461, %e67 - %c.0i452 = phi i8 [ %c.0i452.pre, %zi461 ], [ %t63, %e67 ] ; [#uses=2] - %sign.1.i448 = phi i1 [ %sign.0.i458, %zi461 ], [ false, %e67 ] ; [#uses=2] - %l.0i449 = phi i32 [ %t33i460, %zi461 ], [ %t90.i825, %e67 ] ; [#uses=3] - %p.0i450 = phi i8* [ %t30i459, %zi461 ], [ %t89.i824, %e67 ] ; [#uses=5] - %t8i453 = icmp eq i32 %l.0i449, 0 ; [#uses=1] - br i1 %t8i453, label %endfori465, label %forbodyi455 - -forbodyi455: ; preds = %forcondi454 - switch i8 %c.0i452, label %endfori465 [ - i8 32, label %zi461 - i8 9, label %zi461 - i8 45, label %if20i456 - i8 43, label %if26i457 - ] - -if20i456: ; preds = %forbodyi455 - br label %zi461 - -if26i457: ; preds = %forbodyi455 - br label %zi461 - -zi461: ; preds = %if26i457, %if20i456, %forbodyi455, %forbodyi455 - %sign.0.i458 = phi i1 [ false, %if26i457 ], [ true, %if20i456 ], [ %sign.1.i448, %forbodyi455 ], [ %sign.1.i448, %forbodyi455 ] ; [#uses=1] - %t30i459 = getelementptr i8* %p.0i450, i32 1 ; [#uses=2] - %t33i460 = add i32 %l.0i449, -1 ; [#uses=1] - %c.0i452.pre = load i8* %t30i459 ; [#uses=1] - br label %forcondi454 - -endfori465: ; preds = %forbodyi455, %forcondi454 - %t37i462 = icmp eq i8 %c.0i452, 48 ; [#uses=1] - %t39i463 = icmp sgt i32 %l.0i449, 1 ; [#uses=1] - %or.condi464 = and i1 %t37i462, %t39i463 ; [#uses=1] - br i1 %or.condi464, label %if40i469, label %endif41i479 - -if40i469: ; preds = %endfori465 - %t43i466 = getelementptr i8* %p.0i450, i32 1 ; [#uses=2] - %t44i467 = load i8* %t43i466 ; [#uses=1] - %t45i468 = zext i8 %t44i467 to i32 ; [#uses=1] - switch i32 %t45i468, label %endif41i479 [ - i32 120, label %case46i471 - i32 111, label %case56i475 - ] - -case46i471: ; preds = %if40i469 - %t48i470 = getelementptr i8* %p.0i450, i32 2 ; [#uses=1] - br label %endif41i479 - -case56i475: ; preds = %if40i469 - %t58i474 = getelementptr i8* %p.0i450, i32 2 ; [#uses=1] - br label %endif41i479 - -endif41i479: ; preds = %case56i475, %case46i471, %if40i469, %endfori465 - %r.0i476 = phi i32 [ 0, %if40i469 ], [ 8, %case56i475 ], [ 16, %case46i471 ], [ 0, %endfori465 ] ; [#uses=2] - %p.2i477 = phi i8* [ %t43i466, %if40i469 ], [ %t58i474, %case56i475 ], [ %t48i470, %case46i471 ], [ %p.0i450, %endfori465 ] ; [#uses=2] - %t63i478 = icmp eq i32 %r.0i476, 0 ; [#uses=1] - br i1 %t63i478, label %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i491, label %if70i483 - -if70i483: ; preds = %endif41i479 - br label %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i491 - -Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i491: ; preds = %if70i483, %endif41i479, %e67 - %radix.0.i485 = phi i32 [ 0, %e67 ], [ %r.0i476, %if70i483 ], [ 10, %endif41i479 ] ; [#uses=2] - %p.1i486 = phi i8* [ %p.2i477, %if70i483 ], [ %t89.i824, %e67 ], [ %p.2i477, %endif41i479 ] ; [#uses=1] - %t84i487 = ptrtoint i8* %p.1i486 to i32 ; [#uses=1] - %t85i488 = ptrtoint i8* %t89.i824 to i32 ; [#uses=1] - %t86i489 = sub i32 %t84i487, %t85i488 ; [#uses=2] - %ttt = sub i32 %t90.i825, %t86i489 ; [#uses=1] - %t59i519 = zext i32 %radix.0.i485 to i64 ; [#uses=1] - br label %fcondi496 - -fcondi496: ; preds = %if55i525, %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i491 - %value.0i492 = phi i64 [ 0, %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i491 ], [ %t65i522, %if55i525 ] ; [#uses=1] - %fkey.0i494 = phi i32 [ 0, %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i491 ], [ %t70i524, %if55i525 ] ; [#uses=3] - %t3i495 = icmp ult i32 %fkey.0i494, %ttt ; [#uses=1] - br i1 %t3i495, label %fbodyi502, label %wcond.i422 - -fbodyi502: ; preds = %fcondi496 - %t5.s.i497 = add i32 %t86i489, %fkey.0i494 ; [#uses=1] - %t89.i824.s = add i32 %.frame.0.6, %t5.s.i497 ; [#uses=1] - %t5i498 = getelementptr i8* %line_arg831, i32 %t89.i824.s ; [#uses=1] - %t6i499 = load i8* %t5i498 ; [#uses=6] - %t6.off84i500 = add i8 %t6i499, -48 ; [#uses=1] - %or.cond.i28.i501 = icmp ugt i8 %t6.off84i500, 9 ; [#uses=1] - br i1 %or.cond.i28.i501, label %ei505, label %endifi518 - -ei505: ; preds = %fbodyi502 - %t6.off83i503 = add i8 %t6i499, -97 ; [#uses=1] - %or.cond81i504 = icmp ugt i8 %t6.off83i503, 25 ; [#uses=1] - br i1 %or.cond81i504, label %e24i510, label %if22i507 - -if22i507: ; preds = %ei505 - %t27i506 = add i8 %t6i499, -39 ; [#uses=1] - br label %endifi518 - -e24i510: ; preds = %ei505 - %t6.offi508 = add i8 %t6i499, -65 ; [#uses=1] - %or.cond82i509 = icmp ugt i8 %t6.offi508, 25 ; [#uses=1] - br i1 %or.cond82i509, label %wcond.i422, label %if39i512 - -if39i512: ; preds = %e24i510 - %t44.i29.i511 = add i8 %t6i499, -7 ; [#uses=1] - br label %endifi518 - -endifi518: ; preds = %if39i512, %if22i507, %fbodyi502 - %c.0.i30.i513 = phi i8 [ %t27i506, %if22i507 ], [ %t44.i29.i511, %if39i512 ], [ %t6i499, %fbodyi502 ] ; [#uses=1] - %t48.i31.i514 = zext i8 %c.0.i30.i513 to i32 ; [#uses=1] - %t49i515 = add i32 %t48.i31.i514, 208 ; [#uses=1] - %t52i516 = and i32 %t49i515, 255 ; [#uses=2] - %t54i517 = icmp ult i32 %t52i516, %radix.0.i485 ; [#uses=1] - br i1 %t54i517, label %if55i525, label %wcond.i422 - -if55i525: ; preds = %endifi518 - %t61i520 = mul i64 %value.0i492, %t59i519 ; [#uses=1] - %t64i521 = zext i32 %t52i516 to i64 ; [#uses=1] - %t65i522 = add i64 %t61i520, %t64i521 ; [#uses=1] - %t70i524 = add i32 %fkey.0i494, 1 ; [#uses=1] - br label %fcondi496 - -wcond.i422: ; preds = %e40.i, %endifi518, %e24i510, %fcondi496, %endifi603, %e24i595, %fcondi581 - %sarg60.pn.i = phi i8* [ %p.0.i, %e40.i ], [ undef, %fcondi496 ], [ undef, %e24i510 ], [ undef, %endifi518 ], [ undef, %endifi603 ], [ undef, %e24i595 ], [ undef, %fcondi581 ] ; [#uses=3] - %start_arg.pn.i = phi i32 [ %t49.i443, %e40.i ], [ 0, %fcondi496 ], [ 0, %e24i510 ], [ 0, %endifi518 ], [ 0, %endifi603 ], [ 0, %e24i595 ], [ 0, %fcondi581 ] ; [#uses=3] - %extent.0.i = phi i32 [ %t51.i, %e40.i ], [ undef, %fcondi496 ], [ undef, %e24i510 ], [ undef, %endifi518 ], [ undef, %endifi603 ], [ undef, %e24i595 ], [ undef, %fcondi581 ] ; [#uses=3] - %p.0.i = getelementptr i8* %sarg60.pn.i, i32 %start_arg.pn.i ; [#uses=2] - %p.0.s63.i = add i32 %start_arg.pn.i, -1 ; [#uses=1] - %t2i424 = getelementptr i8* %sarg60.pn.i, i32 %p.0.s63.i ; [#uses=1] - br label %forcondi430 - -forcondi430: ; preds = %forbodyi434, %wcond.i422 - %l.0i426 = phi i32 [ %extent.0.i, %wcond.i422 ], [ %t4i428, %forbodyi434 ] ; [#uses=2] - %p.0i427 = phi i8* [ %t2i424, %wcond.i422 ], [ %t7i431, %forbodyi434 ] ; [#uses=1] - %t4i428 = add i32 %l.0i426, -1 ; [#uses=1] - %t5i429 = icmp eq i32 %l.0i426, 0 ; [#uses=1] - br i1 %t5i429, label %e.i441, label %forbodyi434 - -forbodyi434: ; preds = %forcondi430 - %t7i431 = getelementptr i8* %p.0i427, i32 1 ; [#uses=3] - %t8i432 = load i8* %t7i431 ; [#uses=1] - %t12i433 = icmp eq i8 %t8i432, 32 ; [#uses=1] - br i1 %t12i433, label %ifi438, label %forcondi430 - -ifi438: ; preds = %forbodyi434 - %t15i435 = ptrtoint i8* %t7i431 to i32 ; [#uses=1] - %t16i436 = ptrtoint i8* %p.0.i to i32 ; [#uses=1] - %t17i437 = sub i32 %t15i435, %t16i436 ; [#uses=1] - br label %e.i441 - -e.i441: ; preds = %ifi438, %forcondi430 - %t2561.i = phi i32 [ %t17i437, %ifi438 ], [ %extent.0.i, %forcondi430 ] ; [#uses=2] - %p.0.s.i = add i32 %start_arg.pn.i, %t2561.i ; [#uses=1] - %t32.s.i = add i32 %p.0.s.i, -1 ; [#uses=1] - %t2i.i = getelementptr i8* %sarg60.pn.i, i32 %t32.s.i ; [#uses=1] - br label %forbodyi.i - -forbodyi.i: ; preds = %forbodyi.i, %e.i441 - %p.0i.i = phi i8* [ %t2i.i, %e.i441 ], [ %t7i.i, %forbodyi.i ] ; [#uses=1] - %s2.0i.i = phi i8* [ getelementptr ([5 x i8]* @.str171, i32 0, i32 0), %e.i441 ], [ %t11i.i, %forbodyi.i ] ; [#uses=2] - %t7i.i = getelementptr i8* %p.0i.i, i32 1 ; [#uses=2] - %t8i.i = load i8* %t7i.i ; [#uses=1] - %t11i.i = getelementptr i8* %s2.0i.i, i32 1 ; [#uses=1] - %t12i.i = load i8* %s2.0i.i ; [#uses=1] - %t14i.i = icmp eq i8 %t8i.i, %t12i.i ; [#uses=1] - br i1 %t14i.i, label %forbodyi.i, label %e40.i - -e40.i: ; preds = %forbodyi.i - %t49.i443 = add i32 %t2561.i, 1 ; [#uses=2] - %t51.i = sub i32 %extent.0.i, %t49.i443 ; [#uses=1] - br label %wcond.i422 -} diff --git a/test/CodeGen/PowerPC/unsafe-math.ll b/test/CodeGen/PowerPC/unsafe-math.ll index ef97912..b0bdcc2 100644 --- a/test/CodeGen/PowerPC/unsafe-math.ll +++ b/test/CodeGen/PowerPC/unsafe-math.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -march=ppc32 -enable-unsafe-fp-math | \ ; RUN: grep fmul | count 1 -define double @foo(double %X) { +define double @foo(double %X) nounwind { %tmp1 = fmul double %X, 1.23 %tmp2 = fmul double %tmp1, 4.124 ret double %tmp2 diff --git a/test/CodeGen/PowerPC/varargs.ll b/test/CodeGen/PowerPC/varargs.ll new file mode 100644 index 0000000..1769be9 --- /dev/null +++ b/test/CodeGen/PowerPC/varargs.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -mtriple=powerpc-apple-darwin | FileCheck -check-prefix=P32 %s +; RUN: llc < %s -mtriple=powerpc64-apple-darwin | FileCheck -check-prefix=P64 %s + +; PR8327 +define i8* @test1(i8** %foo) nounwind { + %A = va_arg i8** %foo, i8* + ret i8* %A +} + +; P32: test1: +; P32: lwz r4, 0(r3) +; P32: addi r5, r4, 4 +; P32: stw r5, 0(r3) +; P32: lwz r3, 0(r4) +; P32: blr + +; P64: test1: +; P64: ld r4, 0(r3) +; P64: addi r5, r4, 8 +; P64: std r5, 0(r3) +; P64: ld r3, 0(r4) +; P64: blr diff --git a/test/CodeGen/SPARC/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/SPARC/2010-04-07-DbgValueOtherTargets.ll index f66ee21..3b64498 100644 --- a/test/CodeGen/SPARC/2010-04-07-DbgValueOtherTargets.ll +++ b/test/CodeGen/SPARC/2010-04-07-DbgValueOtherTargets.ll @@ -1,33 +1,28 @@ ; RUN: llc -O0 -march=sparc -asm-verbose < %s | FileCheck %s ; Check that DEBUG_VALUE comments come through on a variety of targets. -%tart.reflect.ComplexType = type { double, double } - -@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } - -define i32 @"main(tart.core.String[])->int32"(i32 %args) { +define i32 @main() nounwind ssp { entry: ; CHECK: DEBUG_VALUE - tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) - tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] - ret i32 3 + call void @llvm.dbg.value(metadata !6, i64 0, metadata !7), !dbg !9 + ret i32 0, !dbg !10 } +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone -declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone -!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] -!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] -!3 = metadata !{metadata !4, metadata !6, metadata !7} -!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] -!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] -!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] -!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] -!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] -!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] -!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] -!12 = metadata !{metadata !13} -!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} +!llvm.dbg.sp = !{!0} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !"clang version 2.9 (trunk 120996)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 589860, metadata !2, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 0} +!7 = metadata !{i32 590080, metadata !8, metadata !"i", metadata !1, i32 3, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!8 = metadata !{i32 589835, metadata !0, i32 2, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!9 = metadata !{i32 3, i32 11, metadata !8, null} +!10 = metadata !{i32 4, i32 2, metadata !8, null} + diff --git a/test/CodeGen/SPARC/2011-01-11-CC.ll b/test/CodeGen/SPARC/2011-01-11-CC.ll new file mode 100755 index 0000000..3ceda95 --- /dev/null +++ b/test/CodeGen/SPARC/2011-01-11-CC.ll @@ -0,0 +1,105 @@ +; RUN: llc -march=sparc <%s | FileCheck %s -check-prefix=V8 +; RUN: llc -march=sparc -mattr=v9 <%s | FileCheck %s -check-prefix=V9 + + +define i32 @test_addx(i64 %a, i64 %b, i64 %c) nounwind readnone noinline { +entry: +; V8: addcc +; V8-NOT: subcc +; V8: addx +; V9: addcc +; V9-NOT: subcc +; V9: addx +; V9: mov{{e|ne}} %icc + %0 = add i64 %a, %b + %1 = icmp ugt i64 %0, %c + %2 = zext i1 %1 to i32 + ret i32 %2 +} + + +define i32 @test_select_int_icc(i32 %a, i32 %b, i32 %c) nounwind readnone noinline { +entry: +; V8: test_select_int_icc +; V8: subcc +; V8: {{be|bne}} +; V9: test_select_int_icc +; V9: subcc +; V9-NOT: {{be|bne}} +; V9: mov{{e|ne}} %icc + %0 = icmp eq i32 %a, 0 + %1 = select i1 %0, i32 %b, i32 %c + ret i32 %1 +} + + +define float @test_select_fp_icc(i32 %a, float %f1, float %f2) nounwind readnone noinline { +entry: +; V8: test_select_fp_icc +; V8: subcc +; V8: {{be|bne}} +; V9: test_select_fp_icc +; V9: subcc +; V9-NOT: {{be|bne}} +; V9: fmovs{{e|ne}} %icc + %0 = icmp eq i32 %a, 0 + %1 = select i1 %0, float %f1, float %f2 + ret float %1 +} + +define double @test_select_dfp_icc(i32 %a, double %f1, double %f2) nounwind readnone noinline { +entry: +; V8: test_select_dfp_icc +; V8: subcc +; V8: {{be|bne}} +; V9: test_select_dfp_icc +; V9: subcc +; V9=NOT: {{be|bne}} +; V9: fmovd{{e|ne}} %icc + %0 = icmp eq i32 %a, 0 + %1 = select i1 %0, double %f1, double %f2 + ret double %1 +} + +define i32 @test_select_int_fcc(float %f, i32 %a, i32 %b) nounwind readnone noinline { +entry: +;V8: test_select_int_fcc +;V8: fcmps +;V8: {{fbe|fbne}} +;V9: test_select_int_fcc +;V9: fcmps +;V9-NOT: {{fbe|fbne}} +;V9: mov{{e|ne}} %fcc0 + %0 = fcmp une float %f, 0.000000e+00 + %a.b = select i1 %0, i32 %a, i32 %b + ret i32 %a.b +} + + +define float @test_select_fp_fcc(float %f, float %f1, float %f2) nounwind readnone noinline { +entry: +;V8: test_select_fp_fcc +;V8: fcmps +;V8: {{fbe|fbne}} +;V9: test_select_fp_fcc +;V9: fcmps +;V9-NOT: {{fbe|fbne}} +;V9: fmovs{{e|ne}} %fcc0 + %0 = fcmp une float %f, 0.000000e+00 + %1 = select i1 %0, float %f1, float %f2 + ret float %1 +} + +define double @test_select_dfp_fcc(double %f, double %f1, double %f2) nounwind readnone noinline { +entry: +;V8: test_select_dfp_fcc +;V8: fcmpd +;V8: {{fbne|fbe}} +;V9: test_select_dfp_fcc +;V9: fcmpd +;V9-NOT: {{fbne|fbe}} +;V9: fmovd{{e|ne}} %fcc0 + %0 = fcmp une double %f, 0.000000e+00 + %1 = select i1 %0, double %f1, double %f2 + ret double %1 +} diff --git a/test/CodeGen/SPARC/2011-01-11-Call.ll b/test/CodeGen/SPARC/2011-01-11-Call.ll new file mode 100644 index 0000000..7350e92 --- /dev/null +++ b/test/CodeGen/SPARC/2011-01-11-Call.ll @@ -0,0 +1,13 @@ +; RUN: llc -march=sparc -O0 <%s + +define void @test() nounwind { +entry: + %0 = tail call i32 (...)* @foo() nounwind + tail call void (...)* @bar() nounwind + ret void +} + +declare i32 @foo(...) + +declare void @bar(...) + diff --git a/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll b/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll new file mode 100644 index 0000000..fbf7242 --- /dev/null +++ b/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll @@ -0,0 +1,64 @@ +;RUN: llc -march=sparc < %s | FileCheck %s -check-prefix=V8 +;RUN: llc -march=sparc -mattr=v9 < %s | FileCheck %s -check-prefix=V9 + +define i8* @frameaddr() nounwind readnone { +entry: +;V8: frameaddr +;V8: or %g0, %fp, {{.+}} + +;V9: frameaddr +;V9: or %g0, %fp, {{.+}} + %0 = tail call i8* @llvm.frameaddress(i32 0) + ret i8* %0 +} + +define i8* @frameaddr2() nounwind readnone { +entry: +;V8: frameaddr2 +;V8: ta 3 +;V8: ld [%fp+56], {{.+}} +;V8: ld [{{.+}}+56], {{.+}} +;V8: ld [{{.+}}+56], {{.+}} + +;V9: frameaddr2 +;V9: flushw +;V9: ld [%fp+56], {{.+}} +;V9: ld [{{.+}}+56], {{.+}} +;V9: ld [{{.+}}+56], {{.+}} + %0 = tail call i8* @llvm.frameaddress(i32 3) + ret i8* %0 +} + +declare i8* @llvm.frameaddress(i32) nounwind readnone + + + +define i8* @retaddr() nounwind readnone { +entry: +;V8: retaddr +;V8: or %g0, %i7, {{.+}} + +;V9: retaddr +;V9: or %g0, %i7, {{.+}} + %0 = tail call i8* @llvm.returnaddress(i32 0) + ret i8* %0 +} + +define i8* @retaddr2() nounwind readnone { +entry: +;V8: retaddr2 +;V8: ta 3 +;V8: ld [%fp+56], {{.+}} +;V8: ld [{{.+}}+56], {{.+}} +;V8: ld [{{.+}}+60], {{.+}} + +;V9: retaddr2 +;V9: flushw +;V9: ld [%fp+56], {{.+}} +;V9: ld [{{.+}}+56], {{.+}} +;V9: ld [{{.+}}+60], {{.+}} + %0 = tail call i8* @llvm.returnaddress(i32 3) + ret i8* %0 +} + +declare i8* @llvm.returnaddress(i32) nounwind readnone diff --git a/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll b/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll new file mode 100644 index 0000000..bc27e98 --- /dev/null +++ b/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll @@ -0,0 +1,90 @@ +;RUN: llc -march=sparc < %s | FileCheck %s +;RUN: llc -march=sparc -O0 < %s | FileCheck %s -check-prefix=UNOPT + + +define i32 @test(i32 %a) nounwind { +entry: +; CHECK: test +; CHECK: call bar +; CHECK-NOT: nop +; CHECK: ret +; CHECK-NEXT: restore + %0 = tail call i32 @bar(i32 %a) nounwind + ret i32 %0 +} + +define i32 @test_jmpl(i32 (i32, i32)* nocapture %f, i32 %a, i32 %b) nounwind { +entry: +; CHECK: test_jmpl +; CHECK: call +; CHECK-NOT: nop +; CHECK: ret +; CHECK-NEXT: restore + %0 = tail call i32 %f(i32 %a, i32 %b) nounwind + ret i32 %0 +} + +define i32 @test_loop(i32 %a, i32 %b) nounwind readnone { +; CHECK: test_loop +entry: + %0 = icmp sgt i32 %b, 0 + br i1 %0, label %bb, label %bb5 + +bb: ; preds = %entry, %bb + %a_addr.18 = phi i32 [ %a_addr.0, %bb ], [ %a, %entry ] + %1 = phi i32 [ %3, %bb ], [ 0, %entry ] + %tmp9 = mul i32 %1, %b + %2 = and i32 %1, 1 + %tmp = xor i32 %2, 1 + %.pn = shl i32 %tmp9, %tmp + %a_addr.0 = add i32 %.pn, %a_addr.18 + %3 = add nsw i32 %1, 1 + %exitcond = icmp eq i32 %3, %b +;CHECK: subcc +;CHECK: bne +;CHECK-NOT: nop + br i1 %exitcond, label %bb5, label %bb + +bb5: ; preds = %bb, %entry + %a_addr.1.lcssa = phi i32 [ %a, %entry ], [ %a_addr.0, %bb ] +;CHECK: ret +;CHECK-NEXT: restore + ret i32 %a_addr.1.lcssa +} + +define i32 @test_inlineasm(i32 %a) nounwind { +entry: +;CHECK: test_inlineasm +;CHECK: sethi +;CHECK: !NO_APP +;CHECK-NEXT: subcc +;CHECK-NEXT: bg +;CHECK-NEXT: nop + tail call void asm sideeffect "sethi 0, %g0", ""() nounwind + %0 = icmp slt i32 %a, 0 + br i1 %0, label %bb, label %bb1 + +bb: ; preds = %entry + %1 = tail call i32 (...)* @foo(i32 %a) nounwind + ret i32 %1 + +bb1: ; preds = %entry + %2 = tail call i32 @bar(i32 %a) nounwind + ret i32 %2 +} + +declare i32 @foo(...) + +declare i32 @bar(i32) + + +define i32 @test_implicit_def() nounwind { +entry: +;UNOPT: test_implicit_def +;UNOPT: call func +;UNOPT-NEXT: nop + %0 = tail call i32 @func(i32* undef) nounwind + ret i32 0 +} + +declare i32 @func(i32*) diff --git a/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll b/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll new file mode 100644 index 0000000..85c16e4 --- /dev/null +++ b/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll @@ -0,0 +1,18 @@ +;RUN: llc -march=sparc < %s | FileCheck %s + +%struct.foo_t = type { i32, i32, i32 } + +@s = internal unnamed_addr global %struct.foo_t { i32 10, i32 20, i32 30 } + +define i32 @test() nounwind { +entry: +;CHECK: test +;CHECK: st +;CHECK: st +;CHECK: st +;CHECK: bar + %0 = tail call i32 @bar(%struct.foo_t* byval @s) nounwind + ret i32 %0 +} + +declare i32 @bar(%struct.foo_t* byval) diff --git a/test/CodeGen/SPARC/2011-01-22-SRet.ll b/test/CodeGen/SPARC/2011-01-22-SRet.ll new file mode 100644 index 0000000..2f684b0 --- /dev/null +++ b/test/CodeGen/SPARC/2011-01-22-SRet.ll @@ -0,0 +1,36 @@ +;RUN: llc -march=sparc < %s | FileCheck %s + +%struct.foo_t = type { i32, i32, i32 } + +define weak void @make_foo(%struct.foo_t* noalias sret %agg.result, i32 %a, i32 %b, i32 %c) nounwind { +entry: +;CHECK: make_foo +;CHECK: ld [%fp+64], {{.+}} +;CHECK: or {{.+}}, {{.+}}, %i0 +;CHECK: ret + %0 = getelementptr inbounds %struct.foo_t* %agg.result, i32 0, i32 0 + store i32 %a, i32* %0, align 4 + %1 = getelementptr inbounds %struct.foo_t* %agg.result, i32 0, i32 1 + store i32 %b, i32* %1, align 4 + %2 = getelementptr inbounds %struct.foo_t* %agg.result, i32 0, i32 2 + store i32 %c, i32* %2, align 4 + ret void +} + +define i32 @test() nounwind { +entry: +;CHECK: test +;CHECK: st {{.+}}, [%sp+64] +;CHECK: make_foo + %f = alloca %struct.foo_t, align 8 + call void @make_foo(%struct.foo_t* noalias sret %f, i32 10, i32 20, i32 30) nounwind + %0 = getelementptr inbounds %struct.foo_t* %f, i32 0, i32 0 + %1 = load i32* %0, align 8 + %2 = getelementptr inbounds %struct.foo_t* %f, i32 0, i32 1 + %3 = load i32* %2, align 4 + %4 = getelementptr inbounds %struct.foo_t* %f, i32 0, i32 2 + %5 = load i32* %4, align 8 + %6 = add nsw i32 %3, %1 + %7 = add nsw i32 %6, %5 + ret i32 %7 +} diff --git a/test/CodeGen/SPARC/basictest.ll b/test/CodeGen/SPARC/basictest.ll index 9c2c16a..4352e62 100644 --- a/test/CodeGen/SPARC/basictest.ll +++ b/test/CodeGen/SPARC/basictest.ll @@ -1,6 +1,26 @@ -; RUN: llc < %s -march=sparc +; RUN: llc < %s -march=sparc | FileCheck %s -define i32 @test(i32 %X) { +define i32 @test0(i32 %X) { %tmp.1 = add i32 %X, 1 ret i32 %tmp.1 +; CHECK: test0: +; CHECK: add %i0, 1, %i0 +} + + +;; xnor tests. +define i32 @test1(i32 %X, i32 %Y) { + %A = xor i32 %X, %Y + %B = xor i32 %A, -1 + ret i32 %B +; CHECK: test1: +; CHECK: xnor %i0, %i1, %i0 +} + +define i32 @test2(i32 %X, i32 %Y) { + %A = xor i32 %X, -1 + %B = xor i32 %A, %Y + ret i32 %B +; CHECK: test2: +; CHECK: xnor %i0, %i1, %i0 } diff --git a/test/CodeGen/SPARC/mult-alt-generic-sparc.ll b/test/CodeGen/SPARC/mult-alt-generic-sparc.ll new file mode 100644 index 0000000..6013b17 --- /dev/null +++ b/test/CodeGen/SPARC/mult-alt-generic-sparc.ll @@ -0,0 +1,323 @@ +; RUN: llc < %s -march=sparc +; ModuleID = 'mult-alt-generic.c' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32" +target triple = "sparc" + +@mout0 = common global i32 0, align 4 +@min1 = common global i32 0, align 4 +@marray = common global [2 x i32] zeroinitializer, align 4 + +define void @single_m() nounwind { +entry: + call void asm "foo $1,$0", "=*m,*m"(i32* @mout0, i32* @min1) nounwind + ret void +} + +define void @single_o() nounwind { +entry: + %out0 = alloca i32, align 4 + %index = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %index, align 4 + ret void +} + +define void @single_V() nounwind { +entry: + ret void +} + +define void @single_lt() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* %in1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,r>"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + ret void +} + +define void @single_r() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @single_i() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,i"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @single_n() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,n"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @single_E() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r,E"(double 1.000000e+001) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @single_F() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r,F"(double 1.000000e+000) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @single_s() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + ret void +} + +define void @single_g() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,imr"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r,imr"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + ret void +} + +define void @single_X() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r,X"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r,X"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + %3 = call i32 asm "foo $1,$0", "=r,X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %3, i32* %out0, align 4 +; No lowering support. +; %4 = call i32 asm "foo $1,$0", "=r,X"(double 1.000000e+001) nounwind +; store i32 %4, i32* %out0, align 4 +; %5 = call i32 asm "foo $1,$0", "=r,X"(double 1.000000e+000) nounwind +; store i32 %5, i32* %out0, align 4 + ret void +} + +define void @single_p() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r,r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_m() nounwind { +entry: + %tmp = load i32* @min1, align 4 + call void asm "foo $1,$0", "=*m|r,m|r"(i32* @mout0, i32 %tmp) nounwind + ret void +} + +define void @multi_o() nounwind { +entry: + %out0 = alloca i32, align 4 + %index = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %index, align 4 + ret void +} + +define void @multi_V() nounwind { +entry: + ret void +} + +define void @multi_lt() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* %in1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|r>"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + ret void +} + +define void @multi_r() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|m"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_i() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|i"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_n() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|n"(i32 1) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} + +define void @multi_E() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r|r,r|E"(double 1.000000e+001) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @multi_F() nounwind { +entry: + %out0 = alloca double, align 8 + store double 0.000000e+000, double* %out0, align 8 +; No lowering support. +; %0 = call double asm "foo $1,$0", "=r|r,r|F"(double 1.000000e+000) nounwind +; store double %0, double* %out0, align 8 + ret void +} + +define void @multi_s() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + ret void +} + +define void @multi_g() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r|r,r|imr"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + ret void +} + +define void @multi_X() nounwind { +entry: + %out0 = alloca i32, align 4 + %in1 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + store i32 1, i32* %in1, align 4 + %tmp = load i32* %in1, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp) nounwind + store i32 %0, i32* %out0, align 4 + %tmp1 = load i32* @min1, align 4 + %1 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 %tmp1) nounwind + store i32 %1, i32* %out0, align 4 + %2 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32 1) nounwind + store i32 %2, i32* %out0, align 4 + %3 = call i32 asm "foo $1,$0", "=r|r,r|X"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %3, i32* %out0, align 4 +; No lowering support. +; %4 = call i32 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+001) nounwind +; store i32 %4, i32* %out0, align 4 +; %5 = call i32 asm "foo $1,$0", "=r|r,r|X"(double 1.000000e+000) nounwind +; store i32 %5, i32* %out0, align 4 + ret void +} + +define void @multi_p() nounwind { +entry: + %out0 = alloca i32, align 4 + store i32 0, i32* %out0, align 4 + %0 = call i32 asm "foo $1,$0", "=r|r,r|r"(i32* getelementptr inbounds ([2 x i32]* @marray, i32 0, i32 0)) nounwind + store i32 %0, i32* %out0, align 4 + ret void +} diff --git a/test/CodeGen/SPARC/xnor.ll b/test/CodeGen/SPARC/xnor.ll deleted file mode 100644 index 6ff66bd..0000000 --- a/test/CodeGen/SPARC/xnor.ll +++ /dev/null @@ -1,15 +0,0 @@ -; RUN: llc < %s -march=sparc | \ -; RUN: grep xnor | count 2 - -define i32 @test1(i32 %X, i32 %Y) { - %A = xor i32 %X, %Y ; [#uses=1] - %B = xor i32 %A, -1 ; [#uses=1] - ret i32 %B -} - -define i32 @test2(i32 %X, i32 %Y) { - %A = xor i32 %X, -1 ; [#uses=1] - %B = xor i32 %A, %Y ; [#uses=1] - ret i32 %B -} - diff --git a/test/CodeGen/SystemZ/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/SystemZ/2010-04-07-DbgValueOtherTargets.ll index 610aa40..c2877ac 100644 --- a/test/CodeGen/SystemZ/2010-04-07-DbgValueOtherTargets.ll +++ b/test/CodeGen/SystemZ/2010-04-07-DbgValueOtherTargets.ll @@ -1,33 +1,28 @@ ; RUN: llc -O0 -march=systemz -asm-verbose < %s | FileCheck %s ; Check that DEBUG_VALUE comments come through on a variety of targets. -%tart.reflect.ComplexType = type { double, double } - -@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } - -define i32 @"main(tart.core.String[])->int32"(i32 %args) { +define i32 @main() nounwind ssp { entry: ; CHECK: DEBUG_VALUE - tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) - tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] - ret i32 3 + call void @llvm.dbg.value(metadata !6, i64 0, metadata !7), !dbg !9 + ret i32 0, !dbg !10 } +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone -declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone -!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] -!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] -!3 = metadata !{metadata !4, metadata !6, metadata !7} -!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] -!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] -!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] -!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] -!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] -!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] -!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] -!12 = metadata !{metadata !13} -!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} +!llvm.dbg.sp = !{!0} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !"clang version 2.9 (trunk 120996)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 589860, metadata !2, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 0} +!7 = metadata !{i32 590080, metadata !8, metadata !"i", metadata !1, i32 3, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!8 = metadata !{i32 589835, metadata !0, i32 2, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!9 = metadata !{i32 3, i32 11, metadata !8, null} +!10 = metadata !{i32 4, i32 2, metadata !8, null} + diff --git a/test/CodeGen/Thumb/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/Thumb/2010-04-07-DbgValueOtherTargets.ll index 6b6c14f..b903977 100644 --- a/test/CodeGen/Thumb/2010-04-07-DbgValueOtherTargets.ll +++ b/test/CodeGen/Thumb/2010-04-07-DbgValueOtherTargets.ll @@ -1,33 +1,28 @@ ; RUN: llc -O0 -march=thumb -asm-verbose < %s | FileCheck %s ; Check that DEBUG_VALUE comments come through on a variety of targets. -%tart.reflect.ComplexType = type { double, double } - -@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } - -define i32 @"main(tart.core.String[])->int32"(i32 %args) { +define i32 @main() nounwind ssp { entry: ; CHECK: DEBUG_VALUE - tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) - tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] - ret i32 3 + call void @llvm.dbg.value(metadata !6, i64 0, metadata !7), !dbg !9 + ret i32 0, !dbg !10 } +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone -declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone -!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] -!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] -!3 = metadata !{metadata !4, metadata !6, metadata !7} -!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] -!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] -!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] -!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] -!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] -!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] -!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] -!12 = metadata !{metadata !13} -!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} +!llvm.dbg.sp = !{!0} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !"clang version 2.9 (trunk 120996)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 589860, metadata !2, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 0} +!7 = metadata !{i32 590080, metadata !8, metadata !"i", metadata !1, i32 3, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!8 = metadata !{i32 589835, metadata !0, i32 2, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!9 = metadata !{i32 3, i32 11, metadata !8, null} +!10 = metadata !{i32 4, i32 2, metadata !8, null} + diff --git a/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll b/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll index 9a6321b..06c0dfe 100644 --- a/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll +++ b/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll @@ -10,7 +10,7 @@ define void @_Z19getClosestDiagonal3ii(%0* noalias sret, i32, i32) nounwind { ; CHECK: blx ___muldf3 ; CHECK: blx ___muldf3 -; CHECK: beq LBB0_8 +; CHECK: beq LBB0_7 ; CHECK: blx ___muldf3 ;