From aa45f148926e3461a1fd8b10c990f0a51a908cc9 Mon Sep 17 00:00:00 2001 From: dim Date: Mon, 10 Jun 2013 20:36:52 +0000 Subject: Vendor import of llvm tags/RELEASE_33/final r183502 (effectively, 3.3 release): http://llvm.org/svn/llvm-project/llvm/tags/RELEASE_33/final@183502 --- test/Analysis/BasicAA/invariant_load.ll | 9 +- test/Analysis/BasicAA/phi-spec-order.ll | 20 +- test/Analysis/CostModel/ARM/cast.ll | 4 +- test/Analysis/CostModel/ARM/divrem.ll | 450 ++++++++ test/Analysis/CostModel/X86/arith.ll | 4 +- test/Analysis/CostModel/X86/loop_v2.ll | 8 +- test/Analysis/CostModel/X86/sitofp.ll | 281 +++++ test/Analysis/CostModel/X86/testshiftashr.ll | 8 +- test/Analysis/CostModel/X86/testshiftlshr.ll | 9 +- test/Analysis/CostModel/X86/testshiftshl.ll | 9 +- test/Analysis/CostModel/X86/uitofp.ll | 368 +++++++ test/Analysis/CostModel/X86/vectorized-loop.ll | 10 +- test/Analysis/GlobalsModRef/volatile-instrs.ll | 8 +- .../MemoryDependenceAnalysis/lit.local.cfg | 1 + .../memdep_requires_dominator_tree.ll | 19 + test/Analysis/Profiling/lit.local.cfg | 5 - test/Analysis/RegionInfo/unreachable_bb.ll | 29 + .../ScalarEvolution/2012-03-26-LoadConstant.ll | 16 +- test/Analysis/TypeBasedAliasAnalysis/tbaa-path.ll | 392 +++++++ test/CodeGen/AArch64/adrp-relocation.ll | 22 +- test/CodeGen/AArch64/atomic-ops-not-barriers.ll | 6 +- test/CodeGen/AArch64/atomic-ops.ll | 381 +++---- test/CodeGen/AArch64/blockaddress.ll | 9 + test/CodeGen/AArch64/code-model-large-abs.ll | 61 ++ test/CodeGen/AArch64/elf-extern.ll | 16 +- test/CodeGen/AArch64/extern-weak.ll | 19 + test/CodeGen/AArch64/jump-table.ll | 28 +- test/CodeGen/AArch64/literal_pools.ll | 40 + test/CodeGen/ARM/2010-08-04-StackVariable.ll | 2 +- test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll | 59 +- test/CodeGen/ARM/2010-11-30-reloc-movt.ll | 39 +- test/CodeGen/ARM/2010-12-08-tpsoft.ll | 24 +- test/CodeGen/ARM/2010-12-15-elf-lcomm.ll | 27 +- test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll | 2 +- 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test/MC/AArch64/elf-objdump.s | 2 +- test/MC/AArch64/elf-reloc-addsubimm.s | 17 +- test/MC/AArch64/elf-reloc-condbr.s | 17 +- test/MC/AArch64/elf-reloc-ldrlit.s | 32 +- test/MC/AArch64/elf-reloc-ldstunsimm.s | 38 +- test/MC/AArch64/elf-reloc-movw.s | 96 +- test/MC/AArch64/elf-reloc-pcreladdressing.s | 32 +- test/MC/AArch64/elf-reloc-tstb.s | 22 +- test/MC/AArch64/elf-reloc-uncondbrimm.s | 22 +- test/MC/AArch64/tls-relocs.s | 531 +++------- test/MC/ARM/arm-thumb-trustzone.s | 25 + test/MC/ARM/arm-trustzone.s | 24 + test/MC/ARM/basic-arm-instructions.s | 13 +- test/MC/ARM/basic-thumb2-instructions.s | 4 - test/MC/ARM/cxx-global-constructor.ll | 5 +- test/MC/ARM/data-in-code.ll | 122 +-- test/MC/ARM/elf-eflags-eabi-cg.ll | 5 +- test/MC/ARM/elf-eflags-eabi.s | 5 +- test/MC/ARM/elf-movt.s | 45 +- test/MC/ARM/elf-reloc-01.ll | 15 +- test/MC/ARM/elf-reloc-02.ll | 14 +- test/MC/ARM/elf-reloc-03.ll | 14 +- test/MC/ARM/elf-reloc-condcall.s | 35 +- test/MC/ARM/elf-thumbfunc-reloc.ll | 28 +- test/MC/ARM/elf-thumbfunc-reloc.s | 11 +- test/MC/ARM/elf-thumbfunc.s | 14 +- test/MC/ARM/invalid-hint-arm.s | 7 + test/MC/ARM/invalid-hint-thumb.s | 9 + test/MC/ARM/neon-cmp-encoding.s | 21 + test/MC/ARM/xscale-attributes.ll | 33 +- test/MC/AsmParser/exprs.s | 1 + test/MC/AsmParser/section.s | 144 +-- test/MC/AsmParser/section_names.s | 62 +- test/MC/COFF/align-nops.s | 64 +- test/MC/COFF/basic-coff-64.s | 137 +++ test/MC/COFF/basic-coff.s | 220 ++-- test/MC/COFF/bss.s | 12 +- test/MC/COFF/diff.s | 34 +- test/MC/COFF/linker-options.ll | 21 + test/MC/COFF/module-asm.ll | 32 +- test/MC/COFF/relocation-imgrel.s | 29 + test/MC/COFF/secrel-variant.s | 19 + test/MC/COFF/secrel32.s | 12 +- test/MC/COFF/seh-section.s | 20 +- test/MC/COFF/seh.s | 119 ++- test/MC/COFF/simple-fixups.s | 11 +- test/MC/COFF/symbol-alias.s | 76 +- test/MC/COFF/symbol-fragment-offset-64.s | 168 +++ test/MC/COFF/symbol-fragment-offset.s | 277 +++-- test/MC/COFF/weak-symbol-section-specification.ll | 30 +- test/MC/COFF/weak.s | 70 +- test/MC/Disassembler/ARM/arm-tests.txt | 42 + test/MC/Disassembler/ARM/arm-thumb-trustzone.txt | 17 + test/MC/Disassembler/ARM/arm-trustzone.txt | 16 + .../MC/Disassembler/ARM/basic-arm-instructions.txt | 18 +- test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt | 1 - test/MC/Disassembler/ARM/invalid-hint-arm.txt | 13 + test/MC/Disassembler/ARM/invalid-hint-thumb.txt | 8 + test/MC/Disassembler/Mips/mips-dsp.txt | 13 + test/MC/Disassembler/Mips/mips32.txt | 1 - test/MC/Disassembler/Mips/mips32_le.txt | 1 - test/MC/Disassembler/Mips/mips32r2.txt | 1 - test/MC/Disassembler/Mips/mips32r2_le.txt | 1 - test/MC/Disassembler/Mips/mips64.txt | 1 - test/MC/Disassembler/Mips/mips64_le.txt | 1 - test/MC/Disassembler/Mips/mips64r2.txt | 1 - test/MC/Disassembler/Mips/mips64r2_le.txt | 1 - test/MC/Disassembler/X86/intel-syntax.txt | 9 + test/MC/Disassembler/X86/x86-64.txt | 15 + test/MC/Disassembler/XCore/xcore.txt | 13 +- test/MC/ELF/abs.s | 19 +- test/MC/ELF/alias-reloc.s | 62 +- test/MC/ELF/alias.s | 144 +-- test/MC/ELF/align-bss.s | 27 +- test/MC/ELF/align-nops.s | 60 +- test/MC/ELF/align-size.s | 19 +- test/MC/ELF/align-text.s | 28 +- test/MC/ELF/align.s | 55 +- test/MC/ELF/basic-elf-32.s | 82 +- test/MC/ELF/basic-elf-64.s | 84 +- test/MC/ELF/call-abs.s | 14 +- test/MC/ELF/cfi-adjust-cfa-offset.s | 75 +- test/MC/ELF/cfi-advance-loc2.s | 71 +- test/MC/ELF/cfi-def-cfa-offset.s | 74 +- test/MC/ELF/cfi-def-cfa-register.s | 70 +- test/MC/ELF/cfi-def-cfa.s | 71 +- test/MC/ELF/cfi-escape.s | 74 +- test/MC/ELF/cfi-offset.s | 71 +- test/MC/ELF/cfi-register.s | 74 +- test/MC/ELF/cfi-rel-offset.s | 75 +- test/MC/ELF/cfi-rel-offset2.s | 74 +- test/MC/ELF/cfi-remember.s | 75 +- test/MC/ELF/cfi-restore.s | 74 +- test/MC/ELF/cfi-same-value.s | 74 +- test/MC/ELF/cfi-sections.s | 65 +- test/MC/ELF/cfi-signal-frame.s | 36 +- test/MC/ELF/cfi-undefined.s | 75 +- test/MC/ELF/cfi-zero-addr-delta.s | 70 +- test/MC/ELF/cfi.s | 679 ++++-------- test/MC/ELF/comdat.s | 134 +-- test/MC/ELF/common.s | 105 +- test/MC/ELF/common2.s | 25 +- test/MC/ELF/debug-line.s | 32 +- test/MC/ELF/debug-loc.s | 28 +- test/MC/ELF/diff.s | 8 +- test/MC/ELF/empty-dwarf-lines.s | 28 +- test/MC/ELF/empty.s | 151 +-- test/MC/ELF/entsize.ll | 56 +- test/MC/ELF/entsize.s | 87 +- test/MC/ELF/file.s | 38 +- test/MC/ELF/gen-dwarf.s | 106 +- test/MC/ELF/global-offset.s | 30 +- test/MC/ELF/got.s | 29 +- test/MC/ELF/ident.s | 31 +- test/MC/ELF/lcomm.s | 36 +- test/MC/ELF/leb128.s | 39 +- test/MC/ELF/local-reloc.s | 30 +- test/MC/ELF/merge.s | 85 +- test/MC/ELF/n_bytes.s | 38 +- test/MC/ELF/noexec.s | 46 +- test/MC/ELF/norelocation.s | 34 +- test/MC/ELF/org.s | 16 +- test/MC/ELF/pic-diff.s | 33 +- test/MC/ELF/plt.s | 15 +- test/MC/ELF/pr9292.s | 37 +- test/MC/ELF/relax-arith.s | 66 +- test/MC/ELF/relax.s | 36 +- test/MC/ELF/relocation-386.s | 219 +--- test/MC/ELF/relocation-pc.s | 53 +- test/MC/ELF/relocation.s | 131 +-- test/MC/ELF/rename.s | 56 +- test/MC/ELF/section.s | 172 ++-- test/MC/ELF/set.s | 36 +- test/MC/ELF/sleb.s | 16 +- test/MC/ELF/subsection.s | 37 + test/MC/ELF/symref.s | 261 +++-- test/MC/ELF/tls-i386.s | 254 ++--- test/MC/ELF/tls.s | 127 +-- test/MC/ELF/type.s | 97 +- test/MC/ELF/uleb.s | 16 +- test/MC/ELF/undef.s | 45 +- test/MC/ELF/undef2.s | 18 +- test/MC/ELF/version.s | 32 +- test/MC/ELF/weak-relocation.s | 13 +- test/MC/ELF/weak.s | 40 +- test/MC/ELF/weakref-plt.s | 14 +- test/MC/ELF/weakref-reloc.s | 79 +- test/MC/ELF/weakref.s | 320 +++--- test/MC/ELF/x86_64-reloc-sizetest.s | 12 +- test/MC/ELF/zero.s | 31 +- test/MC/Mips/elf-N64.ll | 27 +- test/MC/Mips/elf-bigendian.ll | 39 +- test/MC/Mips/elf-gprel-32-64.ll | 15 +- test/MC/Mips/elf-reginfo.ll | 21 +- test/MC/Mips/elf-relsym.ll | 20 +- test/MC/Mips/elf-tls.ll | 12 +- test/MC/Mips/elf_basic.s | 52 +- test/MC/Mips/elf_eflags.ll | 44 +- test/MC/Mips/elf_st_other.ll | 7 +- test/MC/Mips/expr1.s | 26 + test/MC/Mips/higher_highest.ll | 12 +- test/MC/Mips/micromips-alu-instructions.s | 64 ++ test/MC/Mips/micromips-loadstore-instructions.s | 22 + test/MC/Mips/micromips-shift-instructions.s | 22 + test/MC/Mips/mips-alu-instructions.s | 1 - test/MC/Mips/mips-expansions.s | 1 - test/MC/Mips/mips-fpu-instructions.s | 5 +- test/MC/Mips/mips-jump-instructions.s | 122 ++- test/MC/Mips/mips-memory-instructions.s | 1 - test/MC/Mips/mips-relocations.s | 1 - test/MC/Mips/mips64-alu-instructions.s | 3 +- test/MC/Mips/mips_directives.s | 18 + test/MC/Mips/nabi-regs.s | 1 - test/MC/Mips/r-mips-got-disp.ll | 5 +- test/MC/Mips/set-at-directive.s | 1 - test/MC/Mips/sym-offset.ll | 6 +- test/MC/Mips/xgot.ll | 35 +- test/MC/PowerPC/ppc64-encoding-bookII.s | 58 ++ test/MC/PowerPC/ppc64-encoding-ext.s | 331 ++++++ test/MC/PowerPC/ppc64-encoding-fp.s | 263 +++++ test/MC/PowerPC/ppc64-encoding-vmx.s | 384 +++++++ test/MC/PowerPC/ppc64-encoding.s | 480 +++++++++ test/MC/PowerPC/ppc64-errors.s | 80 ++ test/MC/PowerPC/ppc64-fixups.s | 95 ++ test/MC/PowerPC/ppc64-initial-cfa.ll | 134 +-- test/MC/PowerPC/ppc64-operands.s | 87 ++ test/MC/PowerPC/ppc64-relocs-01.ll | 45 +- test/MC/PowerPC/ppc64-tls-relocs-01.ll | 21 +- test/MC/SystemZ/insn-a-01.s | 17 + test/MC/SystemZ/insn-a-02.s | 10 + test/MC/SystemZ/insn-adb-01.s | 17 + test/MC/SystemZ/insn-adb-02.s | 10 + test/MC/SystemZ/insn-adbr-01.s | 11 + test/MC/SystemZ/insn-aeb-01.s | 17 + test/MC/SystemZ/insn-aeb-02.s | 10 + test/MC/SystemZ/insn-aebr-01.s | 11 + test/MC/SystemZ/insn-afi-01.s | 15 + test/MC/SystemZ/insn-afi-02.s | 10 + test/MC/SystemZ/insn-ag-01.s | 23 + test/MC/SystemZ/insn-ag-02.s | 10 + test/MC/SystemZ/insn-agf-01.s | 23 + test/MC/SystemZ/insn-agf-02.s | 10 + test/MC/SystemZ/insn-agfi-01.s | 15 + test/MC/SystemZ/insn-agfi-02.s | 10 + test/MC/SystemZ/insn-agfr-01.s | 11 + test/MC/SystemZ/insn-aghi-01.s | 15 + test/MC/SystemZ/insn-aghi-02.s | 13 + test/MC/SystemZ/insn-agr-01.s | 11 + test/MC/SystemZ/insn-agsi-01.s | 29 + test/MC/SystemZ/insn-agsi-02.s | 19 + test/MC/SystemZ/insn-ah-01.s | 17 + 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a/test/Analysis/BasicAA/invariant_load.ll +++ b/test/Analysis/BasicAA/invariant_load.ll @@ -10,10 +10,10 @@ define i32 @foo(i32* nocapture %p, i8* nocapture %q) { entry: - %0 = load i32* %p, align 4, !tbaa !0, !invariant.load !3 + %0 = load i32* %p, align 4, !invariant.load !3 %conv = trunc i32 %0 to i8 - store i8 %conv, i8* %q, align 1, !tbaa !1 - %1 = load i32* %p, align 4, !tbaa !0, !invariant.load !3 + store i8 %conv, i8* %q, align 1 + %1 = load i32* %p, align 4, !invariant.load !3 %add = add nsw i32 %1, 1 ret i32 %add @@ -23,7 +23,4 @@ entry: ; CHECK: %add = add nsw i32 %0, 1 } -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} !3 = metadata !{} diff --git a/test/Analysis/BasicAA/phi-spec-order.ll b/test/Analysis/BasicAA/phi-spec-order.ll index 27d47bc..4172d09 100644 --- a/test/Analysis/BasicAA/phi-spec-order.ll +++ b/test/Analysis/BasicAA/phi-spec-order.ll @@ -24,23 +24,23 @@ for.body4: ; preds = %for.body4, %for.con %lsr.iv46 = bitcast [16000 x double]* %lsr.iv4 to <4 x double>* %lsr.iv12 = bitcast [16000 x double]* %lsr.iv1 to <4 x double>* %scevgep11 = getelementptr <4 x double>* %lsr.iv46, i64 -2 - %i6 = load <4 x double>* %scevgep11, align 32, !tbaa !0 + %i6 = load <4 x double>* %scevgep11, align 32 %add = fadd <4 x double> %i6, - store <4 x double> %add, <4 x double>* %lsr.iv12, align 32, !tbaa !0 + store <4 x double> %add, <4 x double>* %lsr.iv12, align 32 %scevgep10 = getelementptr <4 x double>* %lsr.iv46, i64 -1 - %i7 = load <4 x double>* %scevgep10, align 32, !tbaa !0 + %i7 = load <4 x double>* %scevgep10, align 32 %add.4 = fadd <4 x double> %i7, %scevgep9 = getelementptr <4 x double>* %lsr.iv12, i64 1 - store <4 x double> %add.4, <4 x double>* %scevgep9, align 32, !tbaa !0 - %i8 = load <4 x double>* %lsr.iv46, align 32, !tbaa !0 + store <4 x double> %add.4, <4 x double>* %scevgep9, align 32 + %i8 = load <4 x double>* %lsr.iv46, align 32 %add.8 = fadd <4 x double> %i8, %scevgep8 = getelementptr <4 x double>* %lsr.iv12, i64 2 - store <4 x double> %add.8, <4 x double>* %scevgep8, align 32, !tbaa !0 + store <4 x double> %add.8, <4 x double>* %scevgep8, align 32 %scevgep7 = getelementptr <4 x double>* %lsr.iv46, i64 1 - %i9 = load <4 x double>* %scevgep7, align 32, !tbaa !0 + %i9 = load <4 x double>* %scevgep7, align 32 %add.12 = fadd <4 x double> %i9, %scevgep3 = getelementptr <4 x double>* %lsr.iv12, i64 3 - store <4 x double> %add.12, <4 x double>* %scevgep3, align 32, !tbaa !0 + store <4 x double> %add.12, <4 x double>* %scevgep3, align 32 ; CHECK: NoAlias:{{[ \t]+}}<4 x double>* %scevgep11, <4 x double>* %scevgep7 ; CHECK: NoAlias:{{[ \t]+}}<4 x double>* %scevgep10, <4 x double>* %scevgep7 @@ -65,7 +65,3 @@ for.end: ; preds = %for.body4 for.end10: ; preds = %for.end ret i32 0 } - -!0 = metadata !{metadata !"double", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/Analysis/CostModel/ARM/cast.ll b/test/Analysis/CostModel/ARM/cast.ll index ba9d84c..0cdd61c 100644 --- a/test/Analysis/CostModel/ARM/cast.ll +++ b/test/Analysis/CostModel/ARM/cast.ll @@ -175,9 +175,9 @@ define i32 @casts() { %rext_5 = zext <4 x i16> undef to <4 x i64> ; Vector cast cost of instructions lowering the cast to the stack. - ; CHECK: cost of 19 {{.*}} trunc + ; CHECK: cost of 3 {{.*}} trunc %r74 = trunc <8 x i32> undef to <8 x i8> - ; CHECK: cost of 38 {{.*}} trunc + ; CHECK: cost of 6 {{.*}} trunc %r75 = trunc <16 x i32> undef to <16 x i8> ; Floating point truncation costs. diff --git a/test/Analysis/CostModel/ARM/divrem.ll b/test/Analysis/CostModel/ARM/divrem.ll new file mode 100644 index 0000000..c4ac59b --- /dev/null +++ b/test/Analysis/CostModel/ARM/divrem.ll @@ -0,0 +1,450 @@ +; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=cortex-a9 | FileCheck %s + +define <2 x i8> @sdiv_v2_i8(<2 x i8> %a, <2 x i8> %b) { + ; CHECK: sdiv_v2_i8 + ; CHECK: cost of 40 {{.*}} sdiv + + %1 = sdiv <2 x i8> %a, %b + ret <2 x i8> %1 +} +define <2 x i16> @sdiv_v2_i16(<2 x i16> %a, <2 x i16> %b) { + ; CHECK: sdiv_v2_i16 + ; CHECK: cost of 40 {{.*}} sdiv + + %1 = sdiv <2 x i16> %a, %b + ret <2 x i16> %1 +} +define <2 x i32> @sdiv_v2_i32(<2 x i32> %a, <2 x i32> %b) { + ; CHECK: sdiv_v2_i32 + ; CHECK: cost of 40 {{.*}} sdiv + + %1 = sdiv <2 x i32> %a, %b + ret <2 x i32> %1 +} +define <2 x i64> @sdiv_v2_i64(<2 x i64> %a, <2 x i64> %b) { + ; CHECK: sdiv_v2_i64 + ; CHECK: cost of 40 {{.*}} sdiv + + %1 = sdiv <2 x i64> %a, %b + ret <2 x i64> %1 +} +define <4 x i8> @sdiv_v4_i8(<4 x i8> %a, <4 x i8> %b) { + ; CHECK: sdiv_v4_i8 + ; CHECK: cost of 10 {{.*}} sdiv + + %1 = sdiv <4 x i8> %a, %b + ret <4 x i8> %1 +} +define <4 x i16> @sdiv_v4_i16(<4 x i16> %a, <4 x i16> %b) { + ; CHECK: sdiv_v4_i16 + ; CHECK: cost of 10 {{.*}} sdiv + + %1 = sdiv <4 x i16> %a, %b + ret <4 x i16> %1 +} +define <4 x i32> @sdiv_v4_i32(<4 x i32> %a, <4 x i32> %b) { + ; CHECK: sdiv_v4_i32 + ; CHECK: cost of 80 {{.*}} sdiv + + %1 = sdiv <4 x i32> %a, %b + ret <4 x i32> %1 +} +define <4 x i64> @sdiv_v4_i64(<4 x i64> %a, <4 x i64> %b) { + ; CHECK: sdiv_v4_i64 + ; CHECK: cost of 80 {{.*}} sdiv + + %1 = sdiv <4 x i64> %a, %b + ret <4 x i64> %1 +} +define <8 x i8> @sdiv_v8_i8(<8 x i8> %a, <8 x i8> %b) { + ; CHECK: sdiv_v8_i8 + ; CHECK: cost of 10 {{.*}} sdiv + + %1 = sdiv <8 x i8> %a, %b + ret <8 x i8> %1 +} +define <8 x i16> @sdiv_v8_i16(<8 x i16> %a, <8 x i16> %b) { + ; CHECK: sdiv_v8_i16 + ; CHECK: cost of 160 {{.*}} sdiv + + %1 = sdiv <8 x i16> %a, %b + ret <8 x i16> %1 +} +define <8 x i32> @sdiv_v8_i32(<8 x i32> %a, <8 x i32> %b) { + ; CHECK: sdiv_v8_i32 + ; CHECK: cost of 160 {{.*}} sdiv + + %1 = sdiv <8 x i32> %a, %b + ret <8 x i32> %1 +} +define <8 x i64> @sdiv_v8_i64(<8 x i64> %a, <8 x i64> %b) { + ; CHECK: sdiv_v8_i64 + ; CHECK: cost of 160 {{.*}} sdiv + + %1 = sdiv <8 x i64> %a, %b + ret <8 x i64> %1 +} +define <16 x i8> @sdiv_v16_i8(<16 x i8> %a, <16 x i8> %b) { + ; CHECK: sdiv_v16_i8 + ; CHECK: cost of 320 {{.*}} sdiv + + %1 = sdiv <16 x i8> %a, %b + ret <16 x i8> %1 +} +define <16 x i16> @sdiv_v16_i16(<16 x i16> %a, <16 x i16> %b) { + ; CHECK: sdiv_v16_i16 + ; CHECK: cost of 320 {{.*}} sdiv + + %1 = sdiv <16 x i16> %a, %b + ret <16 x i16> %1 +} +define <16 x i32> @sdiv_v16_i32(<16 x i32> %a, <16 x i32> %b) { + ; CHECK: sdiv_v16_i32 + ; CHECK: cost of 320 {{.*}} sdiv + + %1 = sdiv <16 x i32> %a, %b + ret <16 x i32> %1 +} +define <16 x i64> @sdiv_v16_i64(<16 x i64> %a, <16 x i64> %b) { + ; CHECK: sdiv_v16_i64 + ; CHECK: cost of 320 {{.*}} sdiv + + %1 = sdiv <16 x i64> %a, %b + ret <16 x i64> %1 +} +define <2 x i8> @udiv_v2_i8(<2 x i8> %a, <2 x i8> %b) { + ; CHECK: udiv_v2_i8 + ; CHECK: cost of 40 {{.*}} udiv + + %1 = udiv <2 x i8> %a, %b + ret <2 x i8> %1 +} +define <2 x i16> @udiv_v2_i16(<2 x i16> %a, <2 x i16> %b) { + ; CHECK: udiv_v2_i16 + ; CHECK: cost of 40 {{.*}} udiv + + %1 = udiv <2 x i16> %a, %b + ret <2 x i16> %1 +} +define <2 x i32> @udiv_v2_i32(<2 x i32> %a, <2 x i32> %b) { + ; CHECK: udiv_v2_i32 + ; CHECK: cost of 40 {{.*}} udiv + + %1 = udiv <2 x i32> %a, %b + ret <2 x i32> %1 +} +define <2 x i64> @udiv_v2_i64(<2 x i64> %a, <2 x i64> %b) { + ; CHECK: udiv_v2_i64 + ; CHECK: cost of 40 {{.*}} udiv + + %1 = udiv <2 x i64> %a, %b + ret <2 x i64> %1 +} +define <4 x i8> @udiv_v4_i8(<4 x i8> %a, <4 x i8> %b) { + ; CHECK: udiv_v4_i8 + ; CHECK: cost of 10 {{.*}} udiv + + %1 = udiv <4 x i8> %a, %b + ret <4 x i8> %1 +} +define <4 x i16> @udiv_v4_i16(<4 x i16> %a, <4 x i16> %b) { + ; CHECK: udiv_v4_i16 + ; CHECK: cost of 10 {{.*}} udiv + + %1 = udiv <4 x i16> %a, %b + ret <4 x i16> %1 +} +define <4 x i32> @udiv_v4_i32(<4 x i32> %a, <4 x i32> %b) { + ; CHECK: udiv_v4_i32 + ; CHECK: cost of 80 {{.*}} udiv + + %1 = udiv <4 x i32> %a, %b + ret <4 x i32> %1 +} +define <4 x i64> @udiv_v4_i64(<4 x i64> %a, <4 x i64> %b) { + ; CHECK: udiv_v4_i64 + ; CHECK: cost of 80 {{.*}} udiv + + %1 = udiv <4 x i64> %a, %b + ret <4 x i64> %1 +} +define <8 x i8> @udiv_v8_i8(<8 x i8> %a, <8 x i8> %b) { + ; CHECK: udiv_v8_i8 + ; CHECK: cost of 10 {{.*}} udiv + + %1 = udiv <8 x i8> %a, %b + ret <8 x i8> %1 +} +define <8 x i16> @udiv_v8_i16(<8 x i16> %a, <8 x i16> %b) { + ; CHECK: udiv_v8_i16 + ; CHECK: cost of 160 {{.*}} udiv + + %1 = udiv <8 x i16> %a, %b + ret <8 x i16> %1 +} +define <8 x i32> @udiv_v8_i32(<8 x i32> %a, <8 x i32> %b) { + ; CHECK: udiv_v8_i32 + ; CHECK: cost of 160 {{.*}} udiv + + %1 = udiv <8 x i32> %a, %b + ret <8 x i32> %1 +} +define <8 x i64> @udiv_v8_i64(<8 x i64> %a, <8 x i64> %b) { + ; CHECK: udiv_v8_i64 + ; CHECK: cost of 160 {{.*}} udiv + + %1 = udiv <8 x i64> %a, %b + ret <8 x i64> %1 +} +define <16 x i8> @udiv_v16_i8(<16 x i8> %a, <16 x i8> %b) { + ; CHECK: udiv_v16_i8 + ; CHECK: cost of 320 {{.*}} udiv + + %1 = udiv <16 x i8> %a, %b + ret <16 x i8> %1 +} +define <16 x i16> @udiv_v16_i16(<16 x i16> %a, <16 x i16> %b) { + ; CHECK: udiv_v16_i16 + ; CHECK: cost of 320 {{.*}} udiv + + %1 = udiv <16 x i16> %a, %b + ret <16 x i16> %1 +} +define <16 x i32> @udiv_v16_i32(<16 x i32> %a, <16 x i32> %b) { + ; CHECK: udiv_v16_i32 + ; CHECK: cost of 320 {{.*}} udiv + + %1 = udiv <16 x i32> %a, %b + ret <16 x i32> %1 +} +define <16 x i64> @udiv_v16_i64(<16 x i64> %a, <16 x i64> %b) { + ; CHECK: udiv_v16_i64 + ; CHECK: cost of 320 {{.*}} udiv + + %1 = udiv <16 x i64> %a, %b + ret <16 x i64> %1 +} +define <2 x i8> @srem_v2_i8(<2 x i8> %a, <2 x i8> %b) { + ; CHECK: srem_v2_i8 + ; CHECK: cost of 40 {{.*}} srem + + %1 = srem <2 x i8> %a, %b + ret <2 x i8> %1 +} +define <2 x i16> @srem_v2_i16(<2 x i16> %a, <2 x i16> %b) { + ; CHECK: srem_v2_i16 + ; CHECK: cost of 40 {{.*}} srem + + %1 = srem <2 x i16> %a, %b + ret <2 x i16> %1 +} +define <2 x i32> @srem_v2_i32(<2 x i32> %a, <2 x i32> %b) { + ; CHECK: srem_v2_i32 + ; CHECK: cost of 40 {{.*}} srem + + %1 = srem <2 x i32> %a, %b + ret <2 x i32> %1 +} +define <2 x i64> @srem_v2_i64(<2 x i64> %a, <2 x i64> %b) { + ; CHECK: srem_v2_i64 + ; CHECK: cost of 40 {{.*}} srem + + %1 = srem <2 x i64> %a, %b + ret <2 x i64> %1 +} +define <4 x i8> @srem_v4_i8(<4 x i8> %a, <4 x i8> %b) { + ; CHECK: srem_v4_i8 + ; CHECK: cost of 80 {{.*}} srem + + %1 = srem <4 x i8> %a, %b + ret <4 x i8> %1 +} +define <4 x i16> @srem_v4_i16(<4 x i16> %a, <4 x i16> %b) { + ; CHECK: srem_v4_i16 + ; CHECK: cost of 80 {{.*}} srem + + %1 = srem <4 x i16> %a, %b + ret <4 x i16> %1 +} +define <4 x i32> @srem_v4_i32(<4 x i32> %a, <4 x i32> %b) { + ; CHECK: srem_v4_i32 + ; CHECK: cost of 80 {{.*}} srem + + %1 = srem <4 x i32> %a, %b + ret <4 x i32> %1 +} +define <4 x i64> @srem_v4_i64(<4 x i64> %a, <4 x i64> %b) { + ; CHECK: srem_v4_i64 + ; CHECK: cost of 80 {{.*}} srem + + %1 = srem <4 x i64> %a, %b + ret <4 x i64> %1 +} +define <8 x i8> @srem_v8_i8(<8 x i8> %a, <8 x i8> %b) { + ; CHECK: srem_v8_i8 + ; CHECK: cost of 160 {{.*}} srem + + %1 = srem <8 x i8> %a, %b + ret <8 x i8> %1 +} +define <8 x i16> @srem_v8_i16(<8 x i16> %a, <8 x i16> %b) { + ; CHECK: srem_v8_i16 + ; CHECK: cost of 160 {{.*}} srem + + %1 = srem <8 x i16> %a, %b + ret <8 x i16> %1 +} +define <8 x i32> @srem_v8_i32(<8 x i32> %a, <8 x i32> %b) { + ; CHECK: srem_v8_i32 + ; CHECK: cost of 160 {{.*}} srem + + %1 = srem <8 x i32> %a, %b + ret <8 x i32> %1 +} +define <8 x i64> @srem_v8_i64(<8 x i64> %a, <8 x i64> %b) { + ; CHECK: srem_v8_i64 + ; CHECK: cost of 160 {{.*}} srem + + %1 = srem <8 x i64> %a, %b + ret <8 x i64> %1 +} +define <16 x i8> @srem_v16_i8(<16 x i8> %a, <16 x i8> %b) { + ; CHECK: srem_v16_i8 + ; CHECK: cost of 320 {{.*}} srem + + %1 = srem <16 x i8> %a, %b + ret <16 x i8> %1 +} +define <16 x i16> @srem_v16_i16(<16 x i16> %a, <16 x i16> %b) { + ; CHECK: srem_v16_i16 + ; CHECK: cost of 320 {{.*}} srem + + %1 = srem <16 x i16> %a, %b + ret <16 x i16> %1 +} +define <16 x i32> @srem_v16_i32(<16 x i32> %a, <16 x i32> %b) { + ; CHECK: srem_v16_i32 + ; CHECK: cost of 320 {{.*}} srem + + %1 = srem <16 x i32> %a, %b + ret <16 x i32> %1 +} +define <16 x i64> @srem_v16_i64(<16 x i64> %a, <16 x i64> %b) { + ; CHECK: srem_v16_i64 + ; CHECK: cost of 320 {{.*}} srem + + %1 = srem <16 x i64> %a, %b + ret <16 x i64> %1 +} +define <2 x i8> @urem_v2_i8(<2 x i8> %a, <2 x i8> %b) { + ; CHECK: urem_v2_i8 + ; CHECK: cost of 40 {{.*}} urem + + %1 = urem <2 x i8> %a, %b + ret <2 x i8> %1 +} +define <2 x i16> @urem_v2_i16(<2 x i16> %a, <2 x i16> %b) { + ; CHECK: urem_v2_i16 + ; CHECK: cost of 40 {{.*}} urem + + %1 = urem <2 x i16> %a, %b + ret <2 x i16> %1 +} +define <2 x i32> @urem_v2_i32(<2 x i32> %a, <2 x i32> %b) { + ; CHECK: urem_v2_i32 + ; CHECK: cost of 40 {{.*}} urem + + %1 = urem <2 x i32> %a, %b + ret <2 x i32> %1 +} +define <2 x i64> @urem_v2_i64(<2 x i64> %a, <2 x i64> %b) { + ; CHECK: urem_v2_i64 + ; CHECK: cost of 40 {{.*}} urem + + %1 = urem <2 x i64> %a, %b + ret <2 x i64> %1 +} +define <4 x i8> @urem_v4_i8(<4 x i8> %a, <4 x i8> %b) { + ; CHECK: urem_v4_i8 + ; CHECK: cost of 80 {{.*}} urem + + %1 = urem <4 x i8> %a, %b + ret <4 x i8> %1 +} +define <4 x i16> @urem_v4_i16(<4 x i16> %a, <4 x i16> %b) { + ; CHECK: urem_v4_i16 + ; CHECK: cost of 80 {{.*}} urem + + %1 = urem <4 x i16> %a, %b + ret <4 x i16> %1 +} +define <4 x i32> @urem_v4_i32(<4 x i32> %a, <4 x i32> %b) { + ; CHECK: urem_v4_i32 + ; CHECK: cost of 80 {{.*}} urem + + %1 = urem <4 x i32> %a, %b + ret <4 x i32> %1 +} +define <4 x i64> @urem_v4_i64(<4 x i64> %a, <4 x i64> %b) { + ; CHECK: urem_v4_i64 + ; CHECK: cost of 80 {{.*}} urem + + %1 = urem <4 x i64> %a, %b + ret <4 x i64> %1 +} +define <8 x i8> @urem_v8_i8(<8 x i8> %a, <8 x i8> %b) { + ; CHECK: urem_v8_i8 + ; CHECK: cost of 160 {{.*}} urem + + %1 = urem <8 x i8> %a, %b + ret <8 x i8> %1 +} +define <8 x i16> @urem_v8_i16(<8 x i16> %a, <8 x i16> %b) { + ; CHECK: urem_v8_i16 + ; CHECK: cost of 160 {{.*}} urem + + %1 = urem <8 x i16> %a, %b + ret <8 x i16> %1 +} +define <8 x i32> @urem_v8_i32(<8 x i32> %a, <8 x i32> %b) { + ; CHECK: urem_v8_i32 + ; CHECK: cost of 160 {{.*}} urem + + %1 = urem <8 x i32> %a, %b + ret <8 x i32> %1 +} +define <8 x i64> @urem_v8_i64(<8 x i64> %a, <8 x i64> %b) { + ; CHECK: urem_v8_i64 + ; CHECK: cost of 160 {{.*}} urem + + %1 = urem <8 x i64> %a, %b + ret <8 x i64> %1 +} +define <16 x i8> @urem_v16_i8(<16 x i8> %a, <16 x i8> %b) { + ; CHECK: urem_v16_i8 + ; CHECK: cost of 320 {{.*}} urem + + %1 = urem <16 x i8> %a, %b + ret <16 x i8> %1 +} +define <16 x i16> @urem_v16_i16(<16 x i16> %a, <16 x i16> %b) { + ; CHECK: urem_v16_i16 + ; CHECK: cost of 320 {{.*}} urem + + %1 = urem <16 x i16> %a, %b + ret <16 x i16> %1 +} +define <16 x i32> @urem_v16_i32(<16 x i32> %a, <16 x i32> %b) { + ; CHECK: urem_v16_i32 + ; CHECK: cost of 320 {{.*}} urem + + %1 = urem <16 x i32> %a, %b + ret <16 x i32> %1 +} +define <16 x i64> @urem_v16_i64(<16 x i64> %a, <16 x i64> %b) { + ; CHECK: urem_v16_i64 + ; CHECK: cost of 320 {{.*}} urem + + %1 = urem <16 x i64> %a, %b + ret <16 x i64> %1 +} diff --git a/test/Analysis/CostModel/X86/arith.ll b/test/Analysis/CostModel/X86/arith.ll index 85b4425..92f5a1e 100644 --- a/test/Analysis/CostModel/X86/arith.ll +++ b/test/Analysis/CostModel/X86/arith.ll @@ -66,9 +66,9 @@ define void @avx2mull() { ; CHECK: fmul define i32 @fmul(i32 %arg) { - ;CHECK: cost of 1 {{.*}} fmul + ;CHECK: cost of 2 {{.*}} fmul %A = fmul <4 x float> undef, undef - ;CHECK: cost of 1 {{.*}} fmul + ;CHECK: cost of 2 {{.*}} fmul %B = fmul <8 x float> undef, undef ret i32 undef } diff --git a/test/Analysis/CostModel/X86/loop_v2.ll b/test/Analysis/CostModel/X86/loop_v2.ll index 260a606..348444e 100644 --- a/test/Analysis/CostModel/X86/loop_v2.ll +++ b/test/Analysis/CostModel/X86/loop_v2.ll @@ -20,10 +20,10 @@ vector.body: ; preds = %vector.body, %vecto ;CHECK: cost of 1 {{.*}} extract %6 = extractelement <2 x i64> %3, i32 1 %7 = getelementptr inbounds i32* %A, i64 %6 - %8 = load i32* %5, align 4, !tbaa !0 + %8 = load i32* %5, align 4 ;CHECK: cost of 1 {{.*}} insert %9 = insertelement <2 x i32> undef, i32 %8, i32 0 - %10 = load i32* %7, align 4, !tbaa !0 + %10 = load i32* %7, align 4 ;CHECK: cost of 1 {{.*}} insert %11 = insertelement <2 x i32> %9, i32 %10, i32 1 %12 = add nsw <2 x i32> %11, %vec.phi @@ -37,7 +37,3 @@ for.end: ; preds = %vector.body %16 = add i32 %14, %15 ret i32 %16 } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/Analysis/CostModel/X86/sitofp.ll b/test/Analysis/CostModel/X86/sitofp.ll new file mode 100644 index 0000000..338d974 --- /dev/null +++ b/test/Analysis/CostModel/X86/sitofp.ll @@ -0,0 +1,281 @@ +; RUN: opt -mtriple=x86_64-apple-darwin -mcpu=core2 -cost-model -analyze < %s | FileCheck --check-prefix=SSE2 %s + +define <2 x double> @sitofpv2i8v2double(<2 x i8> %a) { + ; SSE2: sitofpv2i8v2double + ; SSE2: cost of 20 {{.*}} sitofp + %1 = sitofp <2 x i8> %a to <2 x double> + ret <2 x double> %1 +} + +define <4 x double> @sitofpv4i8v4double(<4 x i8> %a) { + ; SSE2: sitofpv4i8v4double + ; SSE2: cost of 40 {{.*}} sitofp + %1 = sitofp <4 x i8> %a to <4 x double> + ret <4 x double> %1 +} + +define <8 x double> @sitofpv8i8v8double(<8 x i8> %a) { + ; SSE2: sitofpv8i8v8double + ; SSE2: cost of 80 {{.*}} sitofp +%1 = sitofp <8 x i8> %a to <8 x double> + ret <8 x double> %1 +} + +define <16 x double> @sitofpv16i8v16double(<16 x i8> %a) { + ; SSE2: sitofpv16i8v16double + ; SSE2: cost of 160 {{.*}} sitofp + %1 = sitofp <16 x i8> %a to <16 x double> + ret <16 x double> %1 +} + +define <32 x double> @sitofpv32i8v32double(<32 x i8> %a) { + ; SSE2: sitofpv32i8v32double + ; SSE2: cost of 320 {{.*}} sitofp + %1 = sitofp <32 x i8> %a to <32 x double> + ret <32 x double> %1 +} + +define <2 x double> @sitofpv2i16v2double(<2 x i16> %a) { + ; SSE2: sitofpv2i16v2double + ; SSE2: cost of 20 {{.*}} sitofp + %1 = sitofp <2 x i16> %a to <2 x double> + ret <2 x double> %1 +} + +define <4 x double> @sitofpv4i16v4double(<4 x i16> %a) { + ; SSE2: sitofpv4i16v4double + ; SSE2: cost of 40 {{.*}} sitofp + %1 = sitofp <4 x i16> %a to <4 x double> + ret <4 x double> %1 +} + +define <8 x double> @sitofpv8i16v8double(<8 x i16> %a) { + ; SSE2: sitofpv8i16v8double + ; SSE2: cost of 80 {{.*}} sitofp + %1 = sitofp <8 x i16> %a to <8 x double> + ret <8 x double> %1 +} + +define <16 x double> @sitofpv16i16v16double(<16 x i16> %a) { + ; SSE2: sitofpv16i16v16double + ; SSE2: cost of 160 {{.*}} sitofp + %1 = sitofp <16 x i16> %a to <16 x double> + ret <16 x double> %1 +} + +define <32 x double> @sitofpv32i16v32double(<32 x i16> %a) { + ; SSE2: sitofpv32i16v32double + ; SSE2: cost of 320 {{.*}} sitofp + %1 = sitofp <32 x i16> %a to <32 x double> + ret <32 x double> %1 +} + +define <2 x double> @sitofpv2i32v2double(<2 x i32> %a) { + ; SSE2: sitofpv2i32v2double + ; SSE2: cost of 20 {{.*}} sitofp + %1 = sitofp <2 x i32> %a to <2 x double> + ret <2 x double> %1 +} + +define <4 x double> @sitofpv4i32v4double(<4 x i32> %a) { + ; SSE2: sitofpv4i32v4double + ; SSE2: cost of 40 {{.*}} sitofp + %1 = sitofp <4 x i32> %a to <4 x double> + ret <4 x double> %1 +} + +define <8 x double> @sitofpv8i32v8double(<8 x i32> %a) { + ; SSE2: sitofpv8i32v8double + ; SSE2: cost of 80 {{.*}} sitofp + %1 = sitofp <8 x i32> %a to <8 x double> + ret <8 x double> %1 +} + +define <16 x double> @sitofpv16i32v16double(<16 x i32> %a) { + ; SSE2: sitofpv16i32v16double + ; SSE2: cost of 160 {{.*}} sitofp + %1 = sitofp <16 x i32> %a to <16 x double> + ret <16 x double> %1 +} + +define <32 x double> @sitofpv32i32v32double(<32 x i32> %a) { + ; SSE2: sitofpv32i32v32double + ; SSE2: cost of 320 {{.*}} sitofp + %1 = sitofp <32 x i32> %a to <32 x double> + ret <32 x double> %1 +} + +define <2 x double> @sitofpv2i64v2double(<2 x i64> %a) { + ; SSE2: sitofpv2i64v2double + ; SSE2: cost of 20 {{.*}} sitofp + %1 = sitofp <2 x i64> %a to <2 x double> + ret <2 x double> %1 +} + +define <4 x double> @sitofpv4i64v4double(<4 x i64> %a) { + ; SSE2: sitofpv4i64v4double + ; SSE2: cost of 40 {{.*}} sitofp + %1 = sitofp <4 x i64> %a to <4 x double> + ret <4 x double> %1 +} + +define <8 x double> @sitofpv8i64v8double(<8 x i64> %a) { + %1 = sitofp <8 x i64> %a to <8 x double> + ; SSE2: sitofpv8i64v8double + ; SSE2: cost of 80 {{.*}} sitofp + ret <8 x double> %1 +} + +define <16 x double> @sitofpv16i64v16double(<16 x i64> %a) { + ; SSE2: sitofpv16i64v16double + ; SSE2: cost of 160 {{.*}} sitofp + %1 = sitofp <16 x i64> %a to <16 x double> + ret <16 x double> %1 +} + +define <32 x double> @sitofpv32i64v32double(<32 x i64> %a) { + ; SSE2: sitofpv32i64v32double + ; SSE2: cost of 320 {{.*}} sitofp + %1 = sitofp <32 x i64> %a to <32 x double> + ret <32 x double> %1 +} + +define <2 x float> @sitofpv2i8v2float(<2 x i8> %a) { + ; SSE2: sitofpv2i8v2float + ; SSE2: cost of 15 {{.*}} sitofp + %1 = sitofp <2 x i8> %a to <2 x float> + ret <2 x float> %1 +} + +define <4 x float> @sitofpv4i8v4float(<4 x i8> %a) { + ; SSE2: sitofpv4i8v4float + ; SSE2: cost of 15 {{.*}} sitofp + %1 = sitofp <4 x i8> %a to <4 x float> + ret <4 x float> %1 +} + +define <8 x float> @sitofpv8i8v8float(<8 x i8> %a) { + ; SSE2: sitofpv8i8v8float + ; SSE2: cost of 15 {{.*}} sitofp + %1 = sitofp <8 x i8> %a to <8 x float> + ret <8 x float> %1 +} + +define <16 x float> @sitofpv16i8v16float(<16 x i8> %a) { + ; SSE2: sitofpv16i8v16float + ; SSE2: cost of 8 {{.*}} sitofp + %1 = sitofp <16 x i8> %a to <16 x float> + ret <16 x float> %1 +} + +define <32 x float> @sitofpv32i8v32float(<32 x i8> %a) { + ; SSE2: sitofpv32i8v32float + ; SSE2: cost of 16 {{.*}} sitofp + %1 = sitofp <32 x i8> %a to <32 x float> + ret <32 x float> %1 +} + +define <2 x float> @sitofpv2i16v2float(<2 x i16> %a) { + ; SSE2: sitofpv2i16v2float + ; SSE2: cost of 15 {{.*}} sitofp + %1 = sitofp <2 x i16> %a to <2 x float> + ret <2 x float> %1 +} + +define <4 x float> @sitofpv4i16v4float(<4 x i16> %a) { + ; SSE2: sitofpv4i16v4float + ; SSE2: cost of 15 {{.*}} sitofp + %1 = sitofp <4 x i16> %a to <4 x float> + ret <4 x float> %1 +} + +define <8 x float> @sitofpv8i16v8float(<8 x i16> %a) { + ; SSE2: sitofpv8i16v8float + ; SSE2: cost of 15 {{.*}} sitofp + %1 = sitofp <8 x i16> %a to <8 x float> + ret <8 x float> %1 +} + +define <16 x float> @sitofpv16i16v16float(<16 x i16> %a) { + ; SSE2: sitofpv16i16v16float + ; SSE2: cost of 30 {{.*}} sitofp + %1 = sitofp <16 x i16> %a to <16 x float> + ret <16 x float> %1 +} + +define <32 x float> @sitofpv32i16v32float(<32 x i16> %a) { + ; SSE2: sitofpv32i16v32float + ; SSE2: cost of 60 {{.*}} sitofp + %1 = sitofp <32 x i16> %a to <32 x float> + ret <32 x float> %1 +} + +define <2 x float> @sitofpv2i32v2float(<2 x i32> %a) { + ; SSE2: sitofpv2i32v2float + ; SSE2: cost of 15 {{.*}} sitofp + %1 = sitofp <2 x i32> %a to <2 x float> + ret <2 x float> %1 +} + +define <4 x float> @sitofpv4i32v4float(<4 x i32> %a) { + ; SSE2: sitofpv4i32v4float + ; SSE2: cost of 15 {{.*}} sitofp + %1 = sitofp <4 x i32> %a to <4 x float> + ret <4 x float> %1 +} + +define <8 x float> @sitofpv8i32v8float(<8 x i32> %a) { + ; SSE2: sitofpv8i32v8float + ; SSE2: cost of 30 {{.*}} sitofp + %1 = sitofp <8 x i32> %a to <8 x float> + ret <8 x float> %1 +} + +define <16 x float> @sitofpv16i32v16float(<16 x i32> %a) { + ; SSE2: sitofpv16i32v16float + ; SSE2: cost of 60 {{.*}} sitofp + %1 = sitofp <16 x i32> %a to <16 x float> + ret <16 x float> %1 +} + +define <32 x float> @sitofpv32i32v32float(<32 x i32> %a) { + ; SSE2: sitofpv32i32v32float + ; SSE2: cost of 120 {{.*}} sitofp + %1 = sitofp <32 x i32> %a to <32 x float> + ret <32 x float> %1 +} + +define <2 x float> @sitofpv2i64v2float(<2 x i64> %a) { + ; SSE2: sitofpv2i64v2float + ; SSE2: cost of 15 {{.*}} sitofp + %1 = sitofp <2 x i64> %a to <2 x float> + ret <2 x float> %1 +} + +define <4 x float> @sitofpv4i64v4float(<4 x i64> %a) { + ; SSE2: sitofpv4i64v4float + ; SSE2: cost of 30 {{.*}} sitofp + %1 = sitofp <4 x i64> %a to <4 x float> + ret <4 x float> %1 +} + +define <8 x float> @sitofpv8i64v8float(<8 x i64> %a) { + ; SSE2: sitofpv8i64v8float + ; SSE2: cost of 60 {{.*}} sitofp + %1 = sitofp <8 x i64> %a to <8 x float> + ret <8 x float> %1 +} + +define <16 x float> @sitofpv16i64v16float(<16 x i64> %a) { + ; SSE2: sitofpv16i64v16float + ; SSE2: cost of 120 {{.*}} sitofp + %1 = sitofp <16 x i64> %a to <16 x float> + ret <16 x float> %1 +} + +define <32 x float> @sitofpv32i64v32float(<32 x i64> %a) { + ; SSE2: sitofpv32i64v32float + ; SSE2: cost of 240 {{.*}} sitofp + %1 = sitofp <32 x i64> %a to <32 x float> + ret <32 x float> %1 +} diff --git a/test/Analysis/CostModel/X86/testshiftashr.ll b/test/Analysis/CostModel/X86/testshiftashr.ll index f35eea8..d96a92f 100644 --- a/test/Analysis/CostModel/X86/testshiftashr.ll +++ b/test/Analysis/CostModel/X86/testshiftashr.ll @@ -113,7 +113,7 @@ entry: define %shifttype32i32 @shift32i32(%shifttype32i32 %a, %shifttype32i32 %b) { entry: ; SSE2: shift32i32 - ; SSE2: cost of 256 {{.*}} ashr + ; SSE2: cost of 320 {{.*}} ashr ; SSE2-CODEGEN: shift32i32 ; SSE2-CODEGEN: sarl %cl @@ -173,7 +173,7 @@ entry: define %shifttype32i64 @shift32i64(%shifttype32i64 %a, %shifttype32i64 %b) { entry: ; SSE2: shift32i64 - ; SSE2: cost of 256 {{.*}} ashr + ; SSE2: cost of 320 {{.*}} ashr ; SSE2-CODEGEN: shift32i64 ; SSE2-CODEGEN: sarq %cl @@ -373,7 +373,7 @@ define %shifttypec32i32 @shift32i32c(%shifttypec32i32 %a, %shifttypec32i32 %b) { entry: ; SSE2: shift32i32c ; getTypeConversion fails here and promotes this to a i64. - ; SSE2: cost of 256 {{.*}} ashr + ; SSE2: cost of 8 {{.*}} ashr ; SSE2-CODEGEN: shift32i32c ; SSE2-CODEGEN: psrad $3 %0 = ashr %shifttypec32i32 %a , @uitofpv2i8v2double(<2 x i8> %a) { + ; SSE2: uitofpv2i8v2double + ; SSE2: cost of 20 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv2i8v2double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <2 x i8> %a to <2 x double> + ret <2 x double> %1 +} + +define <4 x double> @uitofpv4i8v4double(<4 x i8> %a) { + ; SSE2: uitofpv4i8v4double + ; SSE2: cost of 40 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv4i8v4double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <4 x i8> %a to <4 x double> + ret <4 x double> %1 +} + +define <8 x double> @uitofpv8i8v8double(<8 x i8> %a) { + ; SSE2: uitofpv8i8v8double + ; SSE2: cost of 80 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv8i8v8double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd +%1 = uitofp <8 x i8> %a to <8 x double> + ret <8 x double> %1 +} + +define <16 x double> @uitofpv16i8v16double(<16 x i8> %a) { + ; SSE2: uitofpv16i8v16double + ; SSE2: cost of 160 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv16i8v16double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <16 x i8> %a to <16 x double> + ret <16 x double> %1 +} + +define <32 x double> @uitofpv32i8v32double(<32 x i8> %a) { + ; SSE2: uitofpv32i8v32double + ; SSE2: cost of 320 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv32i8v32double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <32 x i8> %a to <32 x double> + ret <32 x double> %1 +} + +define <2 x double> @uitofpv2i16v2double(<2 x i16> %a) { + ; SSE2: uitofpv2i16v2double + ; SSE2: cost of 20 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv2i16v2double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <2 x i16> %a to <2 x double> + ret <2 x double> %1 +} + +define <4 x double> @uitofpv4i16v4double(<4 x i16> %a) { + ; SSE2: uitofpv4i16v4double + ; SSE2: cost of 40 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv4i16v4double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <4 x i16> %a to <4 x double> + ret <4 x double> %1 +} + +define <8 x double> @uitofpv8i16v8double(<8 x i16> %a) { + ; SSE2: uitofpv8i16v8double + ; SSE2: cost of 80 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv8i16v8double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <8 x i16> %a to <8 x double> + ret <8 x double> %1 +} + +define <16 x double> @uitofpv16i16v16double(<16 x i16> %a) { + ; SSE2: uitofpv16i16v16double + ; SSE2: cost of 160 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv16i16v16double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <16 x i16> %a to <16 x double> + ret <16 x double> %1 +} + +define <32 x double> @uitofpv32i16v32double(<32 x i16> %a) { + ; SSE2: uitofpv32i16v32double + ; SSE2: cost of 320 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv32i16v32double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <32 x i16> %a to <32 x double> + ret <32 x double> %1 +} + +define <2 x double> @uitofpv2i32v2double(<2 x i32> %a) { + ; SSE2: uitofpv2i32v2double + ; SSE2: cost of 20 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv2i32v2double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <2 x i32> %a to <2 x double> + ret <2 x double> %1 +} + +define <4 x double> @uitofpv4i32v4double(<4 x i32> %a) { + ; SSE2: uitofpv4i32v4double + ; SSE2: cost of 40 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv4i32v4double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <4 x i32> %a to <4 x double> + ret <4 x double> %1 +} + +define <8 x double> @uitofpv8i32v8double(<8 x i32> %a) { + ; SSE2: uitofpv8i32v8double + ; SSE2: cost of 80 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv8i32v8double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <8 x i32> %a to <8 x double> + ret <8 x double> %1 +} + +define <16 x double> @uitofpv16i32v16double(<16 x i32> %a) { + ; SSE2: uitofpv16i32v16double + ; SSE2: cost of 160 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv16i32v16double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <16 x i32> %a to <16 x double> + ret <16 x double> %1 +} + +define <32 x double> @uitofpv32i32v32double(<32 x i32> %a) { + ; SSE2: uitofpv32i32v32double + ; SSE2: cost of 320 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv32i32v32double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <32 x i32> %a to <32 x double> + ret <32 x double> %1 +} + +define <2 x double> @uitofpv2i64v2double(<2 x i64> %a) { + ; SSE2: uitofpv2i64v2double + ; SSE2: cost of 20 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv2i64v2double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <2 x i64> %a to <2 x double> + ret <2 x double> %1 +} + +define <4 x double> @uitofpv4i64v4double(<4 x i64> %a) { + ; SSE2: uitofpv4i64v4double + ; SSE2: cost of 40 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv4i64v4double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <4 x i64> %a to <4 x double> + ret <4 x double> %1 +} + +define <8 x double> @uitofpv8i64v8double(<8 x i64> %a) { + %1 = uitofp <8 x i64> %a to <8 x double> + ; SSE2: uitofpv8i64v8double + ; SSE2: cost of 80 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv8i64v8double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + ret <8 x double> %1 +} + +define <16 x double> @uitofpv16i64v16double(<16 x i64> %a) { + ; SSE2: uitofpv16i64v16double + ; SSE2: cost of 160 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv16i64v16double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <16 x i64> %a to <16 x double> + ret <16 x double> %1 +} + +define <32 x double> @uitofpv32i64v32double(<32 x i64> %a) { + ; SSE2: uitofpv32i64v32double + ; SSE2: cost of 320 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv32i64v32double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <32 x i64> %a to <32 x double> + ret <32 x double> %1 +} + +define <2 x float> @uitofpv2i8v2float(<2 x i8> %a) { + ; SSE2: uitofpv2i8v2float + ; SSE2: cost of 15 {{.*}} uitofp + %1 = uitofp <2 x i8> %a to <2 x float> + ret <2 x float> %1 +} + +define <4 x float> @uitofpv4i8v4float(<4 x i8> %a) { + ; SSE2: uitofpv4i8v4float + ; SSE2: cost of 15 {{.*}} uitofp + %1 = uitofp <4 x i8> %a to <4 x float> + ret <4 x float> %1 +} + +define <8 x float> @uitofpv8i8v8float(<8 x i8> %a) { + ; SSE2: uitofpv8i8v8float + ; SSE2: cost of 15 {{.*}} uitofp + %1 = uitofp <8 x i8> %a to <8 x float> + ret <8 x float> %1 +} + +define <16 x float> @uitofpv16i8v16float(<16 x i8> %a) { + ; SSE2: uitofpv16i8v16float + ; SSE2: cost of 8 {{.*}} uitofp + %1 = uitofp <16 x i8> %a to <16 x float> + ret <16 x float> %1 +} + +define <32 x float> @uitofpv32i8v32float(<32 x i8> %a) { + ; SSE2: uitofpv32i8v32float + ; SSE2: cost of 16 {{.*}} uitofp + %1 = uitofp <32 x i8> %a to <32 x float> + ret <32 x float> %1 +} + +define <2 x float> @uitofpv2i16v2float(<2 x i16> %a) { + ; SSE2: uitofpv2i16v2float + ; SSE2: cost of 15 {{.*}} uitofp + %1 = uitofp <2 x i16> %a to <2 x float> + ret <2 x float> %1 +} + +define <4 x float> @uitofpv4i16v4float(<4 x i16> %a) { + ; SSE2: uitofpv4i16v4float + ; SSE2: cost of 15 {{.*}} uitofp + %1 = uitofp <4 x i16> %a to <4 x float> + ret <4 x float> %1 +} + +define <8 x float> @uitofpv8i16v8float(<8 x i16> %a) { + ; SSE2: uitofpv8i16v8float + ; SSE2: cost of 15 {{.*}} uitofp + %1 = uitofp <8 x i16> %a to <8 x float> + ret <8 x float> %1 +} + +define <16 x float> @uitofpv16i16v16float(<16 x i16> %a) { + ; SSE2: uitofpv16i16v16float + ; SSE2: cost of 30 {{.*}} uitofp + %1 = uitofp <16 x i16> %a to <16 x float> + ret <16 x float> %1 +} + +define <32 x float> @uitofpv32i16v32float(<32 x i16> %a) { + ; SSE2: uitofpv32i16v32float + ; SSE2: cost of 60 {{.*}} uitofp + %1 = uitofp <32 x i16> %a to <32 x float> + ret <32 x float> %1 +} + +define <2 x float> @uitofpv2i32v2float(<2 x i32> %a) { + ; SSE2: uitofpv2i32v2float + ; SSE2: cost of 15 {{.*}} uitofp + %1 = uitofp <2 x i32> %a to <2 x float> + ret <2 x float> %1 +} + +define <4 x float> @uitofpv4i32v4float(<4 x i32> %a) { + ; SSE2: uitofpv4i32v4float + ; SSE2: cost of 15 {{.*}} uitofp + %1 = uitofp <4 x i32> %a to <4 x float> + ret <4 x float> %1 +} + +define <8 x float> @uitofpv8i32v8float(<8 x i32> %a) { + ; SSE2: uitofpv8i32v8float + ; SSE2: cost of 30 {{.*}} uitofp + %1 = uitofp <8 x i32> %a to <8 x float> + ret <8 x float> %1 +} + +define <16 x float> @uitofpv16i32v16float(<16 x i32> %a) { + ; SSE2: uitofpv16i32v16float + ; SSE2: cost of 60 {{.*}} uitofp + %1 = uitofp <16 x i32> %a to <16 x float> + ret <16 x float> %1 +} + +define <32 x float> @uitofpv32i32v32float(<32 x i32> %a) { + ; SSE2: uitofpv32i32v32float + ; SSE2: cost of 120 {{.*}} uitofp + %1 = uitofp <32 x i32> %a to <32 x float> + ret <32 x float> %1 +} + +define <2 x float> @uitofpv2i64v2float(<2 x i64> %a) { + ; SSE2: uitofpv2i64v2float + ; SSE2: cost of 15 {{.*}} uitofp + %1 = uitofp <2 x i64> %a to <2 x float> + ret <2 x float> %1 +} + +define <4 x float> @uitofpv4i64v4float(<4 x i64> %a) { + ; SSE2: uitofpv4i64v4float + ; SSE2: cost of 30 {{.*}} uitofp + %1 = uitofp <4 x i64> %a to <4 x float> + ret <4 x float> %1 +} + +define <8 x float> @uitofpv8i64v8float(<8 x i64> %a) { + ; SSE2: uitofpv8i64v8float + ; SSE2: cost of 60 {{.*}} uitofp + %1 = uitofp <8 x i64> %a to <8 x float> + ret <8 x float> %1 +} + +define <16 x float> @uitofpv16i64v16float(<16 x i64> %a) { + ; SSE2: uitofpv16i64v16float + ; SSE2: cost of 120 {{.*}} uitofp + %1 = uitofp <16 x i64> %a to <16 x float> + ret <16 x float> %1 +} + +define <32 x float> @uitofpv32i64v32float(<32 x i64> %a) { + ; SSE2: uitofpv32i64v32float + ; SSE2: cost of 240 {{.*}} uitofp + %1 = uitofp <32 x i64> %a to <32 x float> + ret <32 x float> %1 +} + diff --git a/test/Analysis/CostModel/X86/vectorized-loop.ll b/test/Analysis/CostModel/X86/vectorized-loop.ll index 25b1114..af7d1df 100644 --- a/test/Analysis/CostModel/X86/vectorized-loop.ll +++ b/test/Analysis/CostModel/X86/vectorized-loop.ll @@ -54,14 +54,14 @@ for.body: ; preds = %middle.block, %for. %13 = add nsw i64 %indvars.iv, 2 %arrayidx = getelementptr inbounds i32* %B, i64 %13 ;CHECK: cost of 1 {{.*}} load - %14 = load i32* %arrayidx, align 4, !tbaa !0 + %14 = load i32* %arrayidx, align 4 ;CHECK: cost of 1 {{.*}} mul %mul = mul nsw i32 %14, 5 %arrayidx2 = getelementptr inbounds i32* %A, i64 %indvars.iv ;CHECK: cost of 1 {{.*}} load - %15 = load i32* %arrayidx2, align 4, !tbaa !0 + %15 = load i32* %arrayidx2, align 4 %add3 = add nsw i32 %15, %mul - store i32 %add3, i32* %arrayidx2, align 4, !tbaa !0 + store i32 %add3, i32* %arrayidx2, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 ;CHECK: cost of 0 {{.*}} trunc %16 = trunc i64 %indvars.iv.next to i32 @@ -73,7 +73,3 @@ for.end: ; preds = %middle.block, %for. ;CHECK: cost of 0 {{.*}} ret ret i32 undef } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/Analysis/GlobalsModRef/volatile-instrs.ll b/test/Analysis/GlobalsModRef/volatile-instrs.ll index 49bce67..46d3d76 100644 --- a/test/Analysis/GlobalsModRef/volatile-instrs.ll +++ b/test/Analysis/GlobalsModRef/volatile-instrs.ll @@ -22,13 +22,9 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, define i32 @main() nounwind uwtable ssp { main_entry: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* bitcast (%struct.anon* @b to i8*), i8* bitcast (%struct.anon* @a to i8*), i64 12, i32 4, i1 false) - %0 = load volatile i32* getelementptr inbounds (%struct.anon* @b, i64 0, i32 0), align 4, !tbaa !0 - store i32 %0, i32* @c, align 4, !tbaa !0 + %0 = load volatile i32* getelementptr inbounds (%struct.anon* @b, i64 0, i32 0), align 4 + store i32 %0, i32* @c, align 4 tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* bitcast (%struct.anon* @b to i8*), i8* bitcast (%struct.anon* @a to i8*), i64 12, i32 4, i1 false) nounwind %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32 %0) nounwind ret i32 0 } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/Analysis/MemoryDependenceAnalysis/lit.local.cfg b/test/Analysis/MemoryDependenceAnalysis/lit.local.cfg new file mode 100644 index 0000000..c6106e4 --- /dev/null +++ b/test/Analysis/MemoryDependenceAnalysis/lit.local.cfg @@ -0,0 +1 @@ +config.suffixes = ['.ll'] diff --git a/test/Analysis/MemoryDependenceAnalysis/memdep_requires_dominator_tree.ll b/test/Analysis/MemoryDependenceAnalysis/memdep_requires_dominator_tree.ll new file mode 100644 index 0000000..3c95770 --- /dev/null +++ b/test/Analysis/MemoryDependenceAnalysis/memdep_requires_dominator_tree.ll @@ -0,0 +1,19 @@ +; RUN: opt -memdep -gvn < %s + +define void @__memdep_requires_dominator_tree(i32* nocapture %bufUInt, i32* nocapture %pattern) nounwind { +entry: + br label %for.body + +for.exit: ; preds = %for.body + ret void + +for.body: ; preds = %for.body, %entry + %i.01 = phi i32 [ 0, %entry ], [ %tmp8.7, %for.body ] + %arrayidx = getelementptr i32* %bufUInt, i32 %i.01 + %arrayidx5 = getelementptr i32* %pattern, i32 %i.01 + %tmp6 = load i32* %arrayidx5, align 4 + store i32 %tmp6, i32* %arrayidx, align 4 + %tmp8.7 = add i32 %i.01, 8 + %cmp.7 = icmp ult i32 %tmp8.7, 1024 + br i1 %cmp.7, label %for.body, label %for.exit +} diff --git a/test/Analysis/Profiling/lit.local.cfg b/test/Analysis/Profiling/lit.local.cfg index 444b7dc..d40fa4f 100644 --- a/test/Analysis/Profiling/lit.local.cfg +++ b/test/Analysis/Profiling/lit.local.cfg @@ -7,10 +7,5 @@ def getRoot(config): root = getRoot(config) -# Most profiling tests rely on a JIT being present to gather their data; AArch64 -# doesn't have any JIT at present so they will fail when run there. -if root.host_arch in ['AArch64']: - config.unsupported = True - if 'hexagon' in root.target_triple: config.unsupported = True diff --git a/test/Analysis/RegionInfo/unreachable_bb.ll b/test/Analysis/RegionInfo/unreachable_bb.ll new file mode 100644 index 0000000..626ccbe --- /dev/null +++ b/test/Analysis/RegionInfo/unreachable_bb.ll @@ -0,0 +1,29 @@ +; RUN: opt -regions -analyze < %s | FileCheck %s + +; We should not crash if there are some bbs that are not reachable. +define void @f() { +entry: + br label %for.pre + +notintree: ; No predecessors! + br label %ret + +for.pre: ; preds = %entry + br label %for + +for: ; preds = %for.inc, %for.pre + %indvar = phi i64 [ 0, %for.pre ], [ %indvar.next, %for.inc ] + %exitcond = icmp ne i64 %indvar, 200 + br i1 %exitcond, label %for.inc, label %ret + +for.inc: ; preds = %for + %indvar.next = add i64 %indvar, 1 + br label %for + +ret: ; preds = %for, %notintree + ret void +} + +; CHECK: [0] entry => +; CHECK: [1] for => ret + diff --git a/test/Analysis/ScalarEvolution/2012-03-26-LoadConstant.ll b/test/Analysis/ScalarEvolution/2012-03-26-LoadConstant.ll index 138c015..b88e33f 100644 --- a/test/Analysis/ScalarEvolution/2012-03-26-LoadConstant.ll +++ b/test/Analysis/ScalarEvolution/2012-03-26-LoadConstant.ll @@ -15,24 +15,24 @@ entry: lbl_818: ; preds = %for.end, %entry call void (...)* @func_27() - store i32 0, i32* @g_814, align 4, !tbaa !0 + store i32 0, i32* @g_814, align 4 br label %for.cond for.cond: ; preds = %for.body, %lbl_818 - %0 = load i32* @g_814, align 4, !tbaa !0 + %0 = load i32* @g_814, align 4 %cmp = icmp sle i32 %0, 0 br i1 %cmp, label %for.body, label %for.end for.body: ; preds = %for.cond %idxprom = sext i32 %0 to i64 %arrayidx = getelementptr inbounds [0 x i32]* getelementptr inbounds ([1 x [0 x i32]]* @g_244, i32 0, i64 0), i32 0, i64 %idxprom - %1 = load i32* %arrayidx, align 1, !tbaa !0 - store i32 %1, i32* @func_21_l_773, align 4, !tbaa !0 - store i32 1, i32* @g_814, align 4, !tbaa !0 + %1 = load i32* %arrayidx, align 1 + store i32 %1, i32* @func_21_l_773, align 4 + store i32 1, i32* @g_814, align 4 br label %for.cond for.end: ; preds = %for.cond - %2 = load i32* @func_21_l_773, align 4, !tbaa !0 + %2 = load i32* @func_21_l_773, align 4 %tobool = icmp ne i32 %2, 0 br i1 %tobool, label %lbl_818, label %if.end @@ -41,7 +41,3 @@ if.end: ; preds = %for.end } declare void @func_27(...) - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/Analysis/TypeBasedAliasAnalysis/tbaa-path.ll b/test/Analysis/TypeBasedAliasAnalysis/tbaa-path.ll new file mode 100644 index 0000000..ee52763 --- /dev/null +++ b/test/Analysis/TypeBasedAliasAnalysis/tbaa-path.ll @@ -0,0 +1,392 @@ +; RUN: opt < %s -tbaa -basicaa -struct-path-tbaa -aa-eval -evaluate-tbaa -print-no-aliases -print-may-aliases -disable-output 2>&1 | FileCheck %s +; RUN: opt < %s -tbaa -basicaa -struct-path-tbaa -gvn -S | FileCheck %s --check-prefix=OPT +; Generated from clang/test/CodeGen/tbaa.cpp with "-O1 -struct-path-tbaa -disable-llvm-optzns". + +%struct.StructA = type { i16, i32, i16, i32 } +%struct.StructB = type { i16, %struct.StructA, i32 } +%struct.StructS = type { i16, i32 } +%struct.StructS2 = type { i16, i32 } +%struct.StructC = type { i16, %struct.StructB, i32 } +%struct.StructD = type { i16, %struct.StructB, i32, i8 } + +define i32 @_Z1gPjP7StructAy(i32* %s, %struct.StructA* %A, i64 %count) #0 { +entry: +; Access to i32* and &(A->f32). +; CHECK: Function +; CHECK: MayAlias: store i32 4, i32* %f32, align 4, !tbaa !8 <-> store i32 1, i32* %0, align 4, !tbaa !6 +; OPT: define +; OPT: store i32 1 +; OPT: store i32 4 +; OPT: %[[RET:.*]] = load i32* +; OPT: ret i32 %[[RET]] + %s.addr = alloca i32*, align 8 + %A.addr = alloca %struct.StructA*, align 8 + %count.addr = alloca i64, align 8 + store i32* %s, i32** %s.addr, align 8, !tbaa !0 + store %struct.StructA* %A, %struct.StructA** %A.addr, align 8, !tbaa !0 + store i64 %count, i64* %count.addr, align 8, !tbaa !4 + %0 = load i32** %s.addr, align 8, !tbaa !0 + store i32 1, i32* %0, align 4, !tbaa !6 + %1 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f32 = getelementptr inbounds %struct.StructA* %1, i32 0, i32 1 + store i32 4, i32* %f32, align 4, !tbaa !8 + %2 = load i32** %s.addr, align 8, !tbaa !0 + %3 = load i32* %2, align 4, !tbaa !6 + ret i32 %3 +} + +define i32 @_Z2g2PjP7StructAy(i32* %s, %struct.StructA* %A, i64 %count) #0 { +entry: +; Access to i32* and &(A->f16). +; CHECK: Function +; CHECK: NoAlias: store i16 4, i16* %f16, align 2, !tbaa !8 <-> store i32 1, i32* %0, align 4, !tbaa !6 +; OPT: define +; OPT: store i32 1 +; OPT: store i16 4 +; Remove a load and propogate the value from store. +; OPT: ret i32 1 + %s.addr = alloca i32*, align 8 + %A.addr = alloca %struct.StructA*, align 8 + %count.addr = alloca i64, align 8 + store i32* %s, i32** %s.addr, align 8, !tbaa !0 + store %struct.StructA* %A, %struct.StructA** %A.addr, align 8, !tbaa !0 + store i64 %count, i64* %count.addr, align 8, !tbaa !4 + %0 = load i32** %s.addr, align 8, !tbaa !0 + store i32 1, i32* %0, align 4, !tbaa !6 + %1 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f16 = getelementptr inbounds %struct.StructA* %1, i32 0, i32 0 + store i16 4, i16* %f16, align 2, !tbaa !11 + %2 = load i32** %s.addr, align 8, !tbaa !0 + %3 = load i32* %2, align 4, !tbaa !6 + ret i32 %3 +} + +define i32 @_Z2g3P7StructAP7StructBy(%struct.StructA* %A, %struct.StructB* %B, i64 %count) #0 { +entry: +; Access to &(A->f32) and &(B->a.f32). +; CHECK: Function +; CHECK: MayAlias: store i32 4, i32* %f321, align 4, !tbaa !10 <-> store i32 1, i32* %f32, align 4, !tbaa !6 +; OPT: define +; OPT: store i32 1 +; OPT: store i32 4 +; OPT: %[[RET:.*]] = load i32* +; OPT: ret i32 %[[RET]] + %A.addr = alloca %struct.StructA*, align 8 + %B.addr = alloca %struct.StructB*, align 8 + %count.addr = alloca i64, align 8 + store %struct.StructA* %A, %struct.StructA** %A.addr, align 8, !tbaa !0 + store %struct.StructB* %B, %struct.StructB** %B.addr, align 8, !tbaa !0 + store i64 %count, i64* %count.addr, align 8, !tbaa !4 + %0 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f32 = getelementptr inbounds %struct.StructA* %0, i32 0, i32 1 + store i32 1, i32* %f32, align 4, !tbaa !8 + %1 = load %struct.StructB** %B.addr, align 8, !tbaa !0 + %a = getelementptr inbounds %struct.StructB* %1, i32 0, i32 1 + %f321 = getelementptr inbounds %struct.StructA* %a, i32 0, i32 1 + store i32 4, i32* %f321, align 4, !tbaa !12 + %2 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f322 = getelementptr inbounds %struct.StructA* %2, i32 0, i32 1 + %3 = load i32* %f322, align 4, !tbaa !8 + ret i32 %3 +} + +define i32 @_Z2g4P7StructAP7StructBy(%struct.StructA* %A, %struct.StructB* %B, i64 %count) #0 { +entry: +; Access to &(A->f32) and &(B->a.f16). +; CHECK: Function +; CHECK: NoAlias: store i16 4, i16* %f16, align 2, !tbaa !10 <-> store i32 1, i32* %f32, align 4, !tbaa !6 +; OPT: define +; OPT: store i32 1 +; OPT: store i16 4 +; Remove a load and propogate the value from store. +; OPT: ret i32 1 + %A.addr = alloca %struct.StructA*, align 8 + %B.addr = alloca %struct.StructB*, align 8 + %count.addr = alloca i64, align 8 + store %struct.StructA* %A, %struct.StructA** %A.addr, align 8, !tbaa !0 + store %struct.StructB* %B, %struct.StructB** %B.addr, align 8, !tbaa !0 + store i64 %count, i64* %count.addr, align 8, !tbaa !4 + %0 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f32 = getelementptr inbounds %struct.StructA* %0, i32 0, i32 1 + store i32 1, i32* %f32, align 4, !tbaa !8 + %1 = load %struct.StructB** %B.addr, align 8, !tbaa !0 + %a = getelementptr inbounds %struct.StructB* %1, i32 0, i32 1 + %f16 = getelementptr inbounds %struct.StructA* %a, i32 0, i32 0 + store i16 4, i16* %f16, align 2, !tbaa !14 + %2 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f321 = getelementptr inbounds %struct.StructA* %2, i32 0, i32 1 + %3 = load i32* %f321, align 4, !tbaa !8 + ret i32 %3 +} + +define i32 @_Z2g5P7StructAP7StructBy(%struct.StructA* %A, %struct.StructB* %B, i64 %count) #0 { +entry: +; Access to &(A->f32) and &(B->f32). +; CHECK: Function +; CHECK: NoAlias: store i32 4, i32* %f321, align 4, !tbaa !10 <-> store i32 1, i32* %f32, align 4, !tbaa !6 +; OPT: define +; OPT: store i32 1 +; OPT: store i32 4 +; Remove a load and propogate the value from store. +; OPT: ret i32 1 + %A.addr = alloca %struct.StructA*, align 8 + %B.addr = alloca %struct.StructB*, align 8 + %count.addr = alloca i64, align 8 + store %struct.StructA* %A, %struct.StructA** %A.addr, align 8, !tbaa !0 + store %struct.StructB* %B, %struct.StructB** %B.addr, align 8, !tbaa !0 + store i64 %count, i64* %count.addr, align 8, !tbaa !4 + %0 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f32 = getelementptr inbounds %struct.StructA* %0, i32 0, i32 1 + store i32 1, i32* %f32, align 4, !tbaa !8 + %1 = load %struct.StructB** %B.addr, align 8, !tbaa !0 + %f321 = getelementptr inbounds %struct.StructB* %1, i32 0, i32 2 + store i32 4, i32* %f321, align 4, !tbaa !15 + %2 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f322 = getelementptr inbounds %struct.StructA* %2, i32 0, i32 1 + %3 = load i32* %f322, align 4, !tbaa !8 + ret i32 %3 +} + +define i32 @_Z2g6P7StructAP7StructBy(%struct.StructA* %A, %struct.StructB* %B, i64 %count) #0 { +entry: +; Access to &(A->f32) and &(B->a.f32_2). +; CHECK: Function +; CHECK: NoAlias: store i32 4, i32* %f32_2, align 4, !tbaa !10 <-> store i32 1, i32* %f32, align 4, !tbaa !6 +; OPT: define +; OPT: store i32 1 +; OPT: store i32 4 +; Remove a load and propogate the value from store. +; OPT: ret i32 1 + %A.addr = alloca %struct.StructA*, align 8 + %B.addr = alloca %struct.StructB*, align 8 + %count.addr = alloca i64, align 8 + store %struct.StructA* %A, %struct.StructA** %A.addr, align 8, !tbaa !0 + store %struct.StructB* %B, %struct.StructB** %B.addr, align 8, !tbaa !0 + store i64 %count, i64* %count.addr, align 8, !tbaa !4 + %0 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f32 = getelementptr inbounds %struct.StructA* %0, i32 0, i32 1 + store i32 1, i32* %f32, align 4, !tbaa !8 + %1 = load %struct.StructB** %B.addr, align 8, !tbaa !0 + %a = getelementptr inbounds %struct.StructB* %1, i32 0, i32 1 + %f32_2 = getelementptr inbounds %struct.StructA* %a, i32 0, i32 3 + store i32 4, i32* %f32_2, align 4, !tbaa !16 + %2 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f321 = getelementptr inbounds %struct.StructA* %2, i32 0, i32 1 + %3 = load i32* %f321, align 4, !tbaa !8 + ret i32 %3 +} + +define i32 @_Z2g7P7StructAP7StructSy(%struct.StructA* %A, %struct.StructS* %S, i64 %count) #0 { +entry: +; Access to &(A->f32) and &(S->f32). +; CHECK: Function +; CHECK: NoAlias: store i32 4, i32* %f321, align 4, !tbaa !10 <-> store i32 1, i32* %f32, align 4, !tbaa !6 +; OPT: define +; OPT: store i32 1 +; OPT: store i32 4 +; Remove a load and propogate the value from store. +; OPT: ret i32 1 + %A.addr = alloca %struct.StructA*, align 8 + %S.addr = alloca %struct.StructS*, align 8 + %count.addr = alloca i64, align 8 + store %struct.StructA* %A, %struct.StructA** %A.addr, align 8, !tbaa !0 + store %struct.StructS* %S, %struct.StructS** %S.addr, align 8, !tbaa !0 + store i64 %count, i64* %count.addr, align 8, !tbaa !4 + %0 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f32 = getelementptr inbounds %struct.StructA* %0, i32 0, i32 1 + store i32 1, i32* %f32, align 4, !tbaa !8 + %1 = load %struct.StructS** %S.addr, align 8, !tbaa !0 + %f321 = getelementptr inbounds %struct.StructS* %1, i32 0, i32 1 + store i32 4, i32* %f321, align 4, !tbaa !17 + %2 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f322 = getelementptr inbounds %struct.StructA* %2, i32 0, i32 1 + %3 = load i32* %f322, align 4, !tbaa !8 + ret i32 %3 +} + +define i32 @_Z2g8P7StructAP7StructSy(%struct.StructA* %A, %struct.StructS* %S, i64 %count) #0 { +entry: +; Access to &(A->f32) and &(S->f16). +; CHECK: Function +; CHECK: NoAlias: store i16 4, i16* %f16, align 2, !tbaa !10 <-> store i32 1, i32* %f32, align 4, !tbaa !6 +; OPT: define +; OPT: store i32 1 +; OPT: store i16 4 +; Remove a load and propogate the value from store. +; OPT: ret i32 1 + %A.addr = alloca %struct.StructA*, align 8 + %S.addr = alloca %struct.StructS*, align 8 + %count.addr = alloca i64, align 8 + store %struct.StructA* %A, %struct.StructA** %A.addr, align 8, !tbaa !0 + store %struct.StructS* %S, %struct.StructS** %S.addr, align 8, !tbaa !0 + store i64 %count, i64* %count.addr, align 8, !tbaa !4 + %0 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f32 = getelementptr inbounds %struct.StructA* %0, i32 0, i32 1 + store i32 1, i32* %f32, align 4, !tbaa !8 + %1 = load %struct.StructS** %S.addr, align 8, !tbaa !0 + %f16 = getelementptr inbounds %struct.StructS* %1, i32 0, i32 0 + store i16 4, i16* %f16, align 2, !tbaa !19 + %2 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f321 = getelementptr inbounds %struct.StructA* %2, i32 0, i32 1 + %3 = load i32* %f321, align 4, !tbaa !8 + ret i32 %3 +} + +define i32 @_Z2g9P7StructSP8StructS2y(%struct.StructS* %S, %struct.StructS2* %S2, i64 %count) #0 { +entry: +; Access to &(S->f32) and &(S2->f32). +; CHECK: Function +; CHECK: NoAlias: store i32 4, i32* %f321, align 4, !tbaa !10 <-> store i32 1, i32* %f32, align 4, !tbaa !6 +; OPT: define +; OPT: store i32 1 +; OPT: store i32 4 +; Remove a load and propogate the value from store. +; OPT: ret i32 1 + %S.addr = alloca %struct.StructS*, align 8 + %S2.addr = alloca %struct.StructS2*, align 8 + %count.addr = alloca i64, align 8 + store %struct.StructS* %S, %struct.StructS** %S.addr, align 8, !tbaa !0 + store %struct.StructS2* %S2, %struct.StructS2** %S2.addr, align 8, !tbaa !0 + store i64 %count, i64* %count.addr, align 8, !tbaa !4 + %0 = load %struct.StructS** %S.addr, align 8, !tbaa !0 + %f32 = getelementptr inbounds %struct.StructS* %0, i32 0, i32 1 + store i32 1, i32* %f32, align 4, !tbaa !17 + %1 = load %struct.StructS2** %S2.addr, align 8, !tbaa !0 + %f321 = getelementptr inbounds %struct.StructS2* %1, i32 0, i32 1 + store i32 4, i32* %f321, align 4, !tbaa !20 + %2 = load %struct.StructS** %S.addr, align 8, !tbaa !0 + %f322 = getelementptr inbounds %struct.StructS* %2, i32 0, i32 1 + %3 = load i32* %f322, align 4, !tbaa !17 + ret i32 %3 +} + +define i32 @_Z3g10P7StructSP8StructS2y(%struct.StructS* %S, %struct.StructS2* %S2, i64 %count) #0 { +entry: +; Access to &(S->f32) and &(S2->f16). +; CHECK: Function +; CHECK: NoAlias: store i16 4, i16* %f16, align 2, !tbaa !10 <-> store i32 1, i32* %f32, align 4, !tbaa !6 +; OPT: define +; OPT: store i32 1 +; OPT: store i16 4 +; Remove a load and propogate the value from store. +; OPT: ret i32 1 + %S.addr = alloca %struct.StructS*, align 8 + %S2.addr = alloca %struct.StructS2*, align 8 + %count.addr = alloca i64, align 8 + store %struct.StructS* %S, %struct.StructS** %S.addr, align 8, !tbaa !0 + store %struct.StructS2* %S2, %struct.StructS2** %S2.addr, align 8, !tbaa !0 + store i64 %count, i64* %count.addr, align 8, !tbaa !4 + %0 = load %struct.StructS** %S.addr, align 8, !tbaa !0 + %f32 = getelementptr inbounds %struct.StructS* %0, i32 0, i32 1 + store i32 1, i32* %f32, align 4, !tbaa !17 + %1 = load %struct.StructS2** %S2.addr, align 8, !tbaa !0 + %f16 = getelementptr inbounds %struct.StructS2* %1, i32 0, i32 0 + store i16 4, i16* %f16, align 2, !tbaa !22 + %2 = load %struct.StructS** %S.addr, align 8, !tbaa !0 + %f321 = getelementptr inbounds %struct.StructS* %2, i32 0, i32 1 + %3 = load i32* %f321, align 4, !tbaa !17 + ret i32 %3 +} + +define i32 @_Z3g11P7StructCP7StructDy(%struct.StructC* %C, %struct.StructD* %D, i64 %count) #0 { +entry: +; Access to &(C->b.a.f32) and &(D->b.a.f32). +; CHECK: Function +; CHECK: NoAlias: store i32 4, i32* %f323, align 4, !tbaa !12 <-> store i32 1, i32* %f32, align 4, !tbaa !6 +; OPT: define +; OPT: store i32 1 +; OPT: store i32 4 +; Remove a load and propogate the value from store. +; OPT: ret i32 1 + %C.addr = alloca %struct.StructC*, align 8 + %D.addr = alloca %struct.StructD*, align 8 + %count.addr = alloca i64, align 8 + store %struct.StructC* %C, %struct.StructC** %C.addr, align 8, !tbaa !0 + store %struct.StructD* %D, %struct.StructD** %D.addr, align 8, !tbaa !0 + store i64 %count, i64* %count.addr, align 8, !tbaa !4 + %0 = load %struct.StructC** %C.addr, align 8, !tbaa !0 + %b = getelementptr inbounds %struct.StructC* %0, i32 0, i32 1 + %a = getelementptr inbounds %struct.StructB* %b, i32 0, i32 1 + %f32 = getelementptr inbounds %struct.StructA* %a, i32 0, i32 1 + store i32 1, i32* %f32, align 4, !tbaa !23 + %1 = load %struct.StructD** %D.addr, align 8, !tbaa !0 + %b1 = getelementptr inbounds %struct.StructD* %1, i32 0, i32 1 + %a2 = getelementptr inbounds %struct.StructB* %b1, i32 0, i32 1 + %f323 = getelementptr inbounds %struct.StructA* %a2, i32 0, i32 1 + store i32 4, i32* %f323, align 4, !tbaa !25 + %2 = load %struct.StructC** %C.addr, align 8, !tbaa !0 + %b4 = getelementptr inbounds %struct.StructC* %2, i32 0, i32 1 + %a5 = getelementptr inbounds %struct.StructB* %b4, i32 0, i32 1 + %f326 = getelementptr inbounds %struct.StructA* %a5, i32 0, i32 1 + %3 = load i32* %f326, align 4, !tbaa !23 + ret i32 %3 +} + +define i32 @_Z3g12P7StructCP7StructDy(%struct.StructC* %C, %struct.StructD* %D, i64 %count) #0 { +entry: +; Access to &(b1->a.f32) and &(b2->a.f32). +; CHECK: Function +; CHECK: MayAlias: store i32 4, i32* %f325, align 4, !tbaa !6 <-> store i32 1, i32* %f32, align 4, !tbaa !6 +; OPT: define +; OPT: store i32 1 +; OPT: store i32 4 +; OPT: %[[RET:.*]] = load i32* +; OPT: ret i32 %[[RET]] + %C.addr = alloca %struct.StructC*, align 8 + %D.addr = alloca %struct.StructD*, align 8 + %count.addr = alloca i64, align 8 + %b1 = alloca %struct.StructB*, align 8 + %b2 = alloca %struct.StructB*, align 8 + store %struct.StructC* %C, %struct.StructC** %C.addr, align 8, !tbaa !0 + store %struct.StructD* %D, %struct.StructD** %D.addr, align 8, !tbaa !0 + store i64 %count, i64* %count.addr, align 8, !tbaa !4 + %0 = load %struct.StructC** %C.addr, align 8, !tbaa !0 + %b = getelementptr inbounds %struct.StructC* %0, i32 0, i32 1 + store %struct.StructB* %b, %struct.StructB** %b1, align 8, !tbaa !0 + %1 = load %struct.StructD** %D.addr, align 8, !tbaa !0 + %b3 = getelementptr inbounds %struct.StructD* %1, i32 0, i32 1 + store %struct.StructB* %b3, %struct.StructB** %b2, align 8, !tbaa !0 + %2 = load %struct.StructB** %b1, align 8, !tbaa !0 + %a = getelementptr inbounds %struct.StructB* %2, i32 0, i32 1 + %f32 = getelementptr inbounds %struct.StructA* %a, i32 0, i32 1 + store i32 1, i32* %f32, align 4, !tbaa !12 + %3 = load %struct.StructB** %b2, align 8, !tbaa !0 + %a4 = getelementptr inbounds %struct.StructB* %3, i32 0, i32 1 + %f325 = getelementptr inbounds %struct.StructA* %a4, i32 0, i32 1 + store i32 4, i32* %f325, align 4, !tbaa !12 + %4 = load %struct.StructB** %b1, align 8, !tbaa !0 + %a6 = getelementptr inbounds %struct.StructB* %4, i32 0, i32 1 + %f327 = getelementptr inbounds %struct.StructA* %a6, i32 0, i32 1 + %5 = load i32* %f327, align 4, !tbaa !12 + ret i32 %5 +} + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } + +!0 = metadata !{metadata !1, metadata !1, i64 0} +!1 = metadata !{metadata !"any pointer", metadata !2} +!2 = metadata !{metadata !"omnipotent char", metadata !3} +!3 = metadata !{metadata !"Simple C/C++ TBAA"} +!4 = metadata !{metadata !5, metadata !5, i64 0} +!5 = metadata !{metadata !"long long", metadata !2} +!6 = metadata !{metadata !7, metadata !7, i64 0} +!7 = metadata !{metadata !"int", metadata !2} +!8 = metadata !{metadata !9, metadata !7, i64 4} +!9 = metadata !{metadata !"_ZTS7StructA", metadata !10, i64 0, metadata !7, i64 4, metadata !10, i64 8, metadata !7, i64 12} +!10 = metadata !{metadata !"short", metadata !2} +!11 = metadata !{metadata !9, metadata !10, i64 0} +!12 = metadata !{metadata !13, metadata !7, i64 8} +!13 = metadata !{metadata !"_ZTS7StructB", metadata !10, i64 0, metadata !9, i64 4, metadata !7, i64 20} +!14 = metadata !{metadata !13, metadata !10, i64 4} +!15 = metadata !{metadata !13, metadata !7, i64 20} +!16 = metadata !{metadata !13, metadata !7, i64 16} +!17 = metadata !{metadata !18, metadata !7, i64 4} +!18 = metadata !{metadata !"_ZTS7StructS", metadata !10, i64 0, metadata !7, i64 4} +!19 = metadata !{metadata !18, metadata !10, i64 0} +!20 = metadata !{metadata !21, metadata !7, i64 4} +!21 = metadata !{metadata !"_ZTS8StructS2", metadata !10, i64 0, metadata !7, i64 4} +!22 = metadata !{metadata !21, metadata !10, i64 0} +!23 = metadata !{metadata !24, metadata !7, i64 12} +!24 = metadata !{metadata !"_ZTS7StructC", metadata !10, i64 0, metadata !13, i64 4, metadata !7, i64 28} +!25 = metadata !{metadata !26, metadata !7, i64 12} +!26 = metadata !{metadata !"_ZTS7StructD", metadata !10, i64 0, metadata !13, i64 4, metadata !7, i64 28, metadata !2, i64 32} diff --git a/test/CodeGen/AArch64/adrp-relocation.ll b/test/CodeGen/AArch64/adrp-relocation.ll index c33b442..cf41116 100644 --- a/test/CodeGen/AArch64/adrp-relocation.ll +++ b/test/CodeGen/AArch64/adrp-relocation.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -filetype=obj < %s | elf-dump | FileCheck %s +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -filetype=obj < %s | llvm-readobj -s -r | FileCheck %s define i64 @testfn() nounwind { entry: @@ -19,17 +19,9 @@ entry: ; relative offsets of testfn and foo) because its value depends on where this ; object file's .text section gets relocated in memory. -; CHECK: .rela.text - -; CHECK: # Relocation 0 -; CHECK-NEXT: (('r_offset', 0x0000000000000010) -; CHECK-NEXT: ('r_sym', 0x00000007) -; CHECK-NEXT: ('r_type', 0x00000113) -; CHECK-NEXT: ('r_addend', 0x0000000000000000) -; CHECK-NEXT: ), -; CHECK-NEXT: Relocation 1 -; CHECK-NEXT: (('r_offset', 0x0000000000000014) -; CHECK-NEXT: ('r_sym', 0x00000007) -; CHECK-NEXT: ('r_type', 0x00000115) -; CHECK-NEXT: ('r_addend', 0x0000000000000000) -; CHECK-NEXT: ), +; CHECK: Relocations [ +; CHECK-NEXT: Section (1) .text { +; CHECK-NEXT: 0x10 R_AARCH64_ADR_PREL_PG_HI21 testfn 0x0 +; CHECK-NEXT: 0x14 R_AARCH64_ADD_ABS_LO12_NC testfn 0x0 +; CHECK-NEXT: } +; CHECK-NEXT: ] diff --git a/test/CodeGen/AArch64/atomic-ops-not-barriers.ll b/test/CodeGen/AArch64/atomic-ops-not-barriers.ll index 3c03e47..9888a74 100644 --- a/test/CodeGen/AArch64/atomic-ops-not-barriers.ll +++ b/test/CodeGen/AArch64/atomic-ops-not-barriers.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s define i32 @foo(i32* %var, i1 %cond) { ; CHECK: foo: @@ -9,7 +9,9 @@ simple_ver: store i32 %newval, i32* %var br label %somewhere atomic_ver: - %val = atomicrmw add i32* %var, i32 -1 seq_cst + fence seq_cst + %val = atomicrmw add i32* %var, i32 -1 monotonic + fence seq_cst br label %somewhere ; CHECK: dmb ; CHECK: ldxr diff --git a/test/CodeGen/AArch64/atomic-ops.ll b/test/CodeGen/AArch64/atomic-ops.ll index f3c1617..5e87f21 100644 --- a/test/CodeGen/AArch64/atomic-ops.ll +++ b/test/CodeGen/AArch64/atomic-ops.ll @@ -8,18 +8,18 @@ define i8 @test_atomic_load_add_i8(i8 %offset) nounwind { ; CHECK: test_atomic_load_add_i8: %old = atomicrmw add i8* @var8, i8 %offset seq_cst -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i8 %old @@ -27,19 +27,19 @@ define i8 @test_atomic_load_add_i8(i8 %offset) nounwind { define i16 @test_atomic_load_add_i16(i16 %offset) nounwind { ; CHECK: test_atomic_load_add_i16: - %old = atomicrmw add i16* @var16, i16 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw add i16* @var16, i16 %offset acquire +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0 ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i16 %old @@ -47,8 +47,8 @@ define i16 @test_atomic_load_add_i16(i16 %offset) nounwind { define i32 @test_atomic_load_add_i32(i32 %offset) nounwind { ; CHECK: test_atomic_load_add_i32: - %old = atomicrmw add i32* @var32, i32 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw add i32* @var32, i32 %offset release +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 @@ -57,9 +57,9 @@ define i32 @test_atomic_load_add_i32(i32 %offset) nounwind { ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i32 %old @@ -67,8 +67,8 @@ define i32 @test_atomic_load_add_i32(i32 %offset) nounwind { define i64 @test_atomic_load_add_i64(i64 %offset) nounwind { ; CHECK: test_atomic_load_add_i64: - %old = atomicrmw add i64* @var64, i64 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw add i64* @var64, i64 %offset monotonic +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 @@ -79,7 +79,7 @@ define i64 @test_atomic_load_add_i64(i64 %offset) nounwind { ; CHECK-NEXT: add [[NEW:x[0-9]+]], x[[OLD]], x0 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i64 %old @@ -87,8 +87,8 @@ define i64 @test_atomic_load_add_i64(i64 %offset) nounwind { define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind { ; CHECK: test_atomic_load_sub_i8: - %old = atomicrmw sub i8* @var8, i8 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw sub i8* @var8, i8 %offset monotonic +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 @@ -99,7 +99,7 @@ define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind { ; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0 ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i8 %old @@ -107,8 +107,8 @@ define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind { define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind { ; CHECK: test_atomic_load_sub_i16: - %old = atomicrmw sub i16* @var16, i16 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw sub i16* @var16, i16 %offset release +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 @@ -117,9 +117,9 @@ define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind { ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i16 %old @@ -127,19 +127,19 @@ define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind { define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind { ; CHECK: test_atomic_load_sub_i32: - %old = atomicrmw sub i32* @var32, i32 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw sub i32* @var32, i32 %offset acquire +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i32 %old @@ -148,18 +148,18 @@ define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind { define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind { ; CHECK: test_atomic_load_sub_i64: %old = atomicrmw sub i64* @var64, i64 %offset seq_cst -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]] ; x0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: sub [[NEW:x[0-9]+]], x[[OLD]], x0 -; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i64 %old @@ -167,8 +167,8 @@ define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind { define i8 @test_atomic_load_and_i8(i8 %offset) nounwind { ; CHECK: test_atomic_load_and_i8: - %old = atomicrmw and i8* @var8, i8 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw and i8* @var8, i8 %offset release +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 @@ -177,9 +177,9 @@ define i8 @test_atomic_load_and_i8(i8 %offset) nounwind { ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i8 %old @@ -187,8 +187,8 @@ define i8 @test_atomic_load_and_i8(i8 %offset) nounwind { define i16 @test_atomic_load_and_i16(i16 %offset) nounwind { ; CHECK: test_atomic_load_and_i16: - %old = atomicrmw and i16* @var16, i16 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw and i16* @var16, i16 %offset monotonic +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 @@ -199,7 +199,7 @@ define i16 @test_atomic_load_and_i16(i16 %offset) nounwind { ; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0 ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i16 %old @@ -208,18 +208,18 @@ define i16 @test_atomic_load_and_i16(i16 %offset) nounwind { define i32 @test_atomic_load_and_i32(i32 %offset) nounwind { ; CHECK: test_atomic_load_and_i32: %old = atomicrmw and i32* @var32, i32 %offset seq_cst -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i32 %old @@ -227,19 +227,19 @@ define i32 @test_atomic_load_and_i32(i32 %offset) nounwind { define i64 @test_atomic_load_and_i64(i64 %offset) nounwind { ; CHECK: test_atomic_load_and_i64: - %old = atomicrmw and i64* @var64, i64 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw and i64* @var64, i64 %offset acquire +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]] ; x0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: and [[NEW:x[0-9]+]], x[[OLD]], x0 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i64 %old @@ -248,18 +248,18 @@ define i64 @test_atomic_load_and_i64(i64 %offset) nounwind { define i8 @test_atomic_load_or_i8(i8 %offset) nounwind { ; CHECK: test_atomic_load_or_i8: %old = atomicrmw or i8* @var8, i8 %offset seq_cst -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i8 %old @@ -267,8 +267,8 @@ define i8 @test_atomic_load_or_i8(i8 %offset) nounwind { define i16 @test_atomic_load_or_i16(i16 %offset) nounwind { ; CHECK: test_atomic_load_or_i16: - %old = atomicrmw or i16* @var16, i16 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw or i16* @var16, i16 %offset monotonic +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 @@ -279,7 +279,7 @@ define i16 @test_atomic_load_or_i16(i16 %offset) nounwind { ; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0 ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i16 %old @@ -287,19 +287,19 @@ define i16 @test_atomic_load_or_i16(i16 %offset) nounwind { define i32 @test_atomic_load_or_i32(i32 %offset) nounwind { ; CHECK: test_atomic_load_or_i32: - %old = atomicrmw or i32* @var32, i32 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw or i32* @var32, i32 %offset acquire +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i32 %old @@ -307,8 +307,8 @@ define i32 @test_atomic_load_or_i32(i32 %offset) nounwind { define i64 @test_atomic_load_or_i64(i64 %offset) nounwind { ; CHECK: test_atomic_load_or_i64: - %old = atomicrmw or i64* @var64, i64 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw or i64* @var64, i64 %offset release +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 @@ -317,9 +317,9 @@ define i64 @test_atomic_load_or_i64(i64 %offset) nounwind { ; x0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: orr [[NEW:x[0-9]+]], x[[OLD]], x0 -; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i64 %old @@ -327,19 +327,19 @@ define i64 @test_atomic_load_or_i64(i64 %offset) nounwind { define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind { ; CHECK: test_atomic_load_xor_i8: - %old = atomicrmw xor i8* @var8, i8 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw xor i8* @var8, i8 %offset acquire +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0 ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i8 %old @@ -347,8 +347,8 @@ define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind { define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind { ; CHECK: test_atomic_load_xor_i16: - %old = atomicrmw xor i16* @var16, i16 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw xor i16* @var16, i16 %offset release +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 @@ -357,9 +357,9 @@ define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind { ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i16 %old @@ -368,18 +368,18 @@ define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind { define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind { ; CHECK: test_atomic_load_xor_i32: %old = atomicrmw xor i32* @var32, i32 %offset seq_cst -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i32 %old @@ -387,8 +387,8 @@ define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind { define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind { ; CHECK: test_atomic_load_xor_i64: - %old = atomicrmw xor i64* @var64, i64 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw xor i64* @var64, i64 %offset monotonic +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 @@ -399,7 +399,7 @@ define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind { ; CHECK-NEXT: eor [[NEW:x[0-9]+]], x[[OLD]], x0 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i64 %old @@ -407,8 +407,8 @@ define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind { define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind { ; CHECK: test_atomic_load_xchg_i8: - %old = atomicrmw xchg i8* @var8, i8 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw xchg i8* @var8, i8 %offset monotonic +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 @@ -418,7 +418,7 @@ define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind { ; function there. ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], w0, [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i8 %old @@ -427,17 +427,17 @@ define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind { define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind { ; CHECK: test_atomic_load_xchg_i16: %old = atomicrmw xchg i16* @var16, i16 %offset seq_cst -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], w0, [x[[ADDR]]] +; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], w0, [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i16 %old @@ -445,8 +445,8 @@ define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind { define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind { ; CHECK: test_atomic_load_xchg_i32: - %old = atomicrmw xchg i32* @var32, i32 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw xchg i32* @var32, i32 %offset release +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 @@ -454,9 +454,9 @@ define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind { ; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], w0, [x[[ADDR]]] +; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], w0, [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i32 %old @@ -464,18 +464,18 @@ define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind { define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind { ; CHECK: test_atomic_load_xchg_i64: - %old = atomicrmw xchg i64* @var64, i64 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw xchg i64* @var64, i64 %offset acquire +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]] ; x0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], x0, [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i64 %old @@ -484,20 +484,20 @@ define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind { define i8 @test_atomic_load_min_i8(i8 %offset) nounwind { ; CHECK: test_atomic_load_min_i8: - %old = atomicrmw min i8* @var8, i8 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw min i8* @var8, i8 %offset acquire +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp w0, w[[OLD]], sxtb ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i8 %old @@ -505,8 +505,8 @@ define i8 @test_atomic_load_min_i8(i8 %offset) nounwind { define i16 @test_atomic_load_min_i16(i16 %offset) nounwind { ; CHECK: test_atomic_load_min_i16: - %old = atomicrmw min i16* @var16, i16 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw min i16* @var16, i16 %offset release +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 @@ -516,9 +516,9 @@ define i16 @test_atomic_load_min_i16(i16 %offset) nounwind { ; function there. ; CHECK-NEXT: cmp w0, w[[OLD]], sxth ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt -; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i16 %old @@ -526,8 +526,8 @@ define i16 @test_atomic_load_min_i16(i16 %offset) nounwind { define i32 @test_atomic_load_min_i32(i32 %offset) nounwind { ; CHECK: test_atomic_load_min_i32: - %old = atomicrmw min i32* @var32, i32 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw min i32* @var32, i32 %offset monotonic +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 @@ -539,7 +539,7 @@ define i32 @test_atomic_load_min_i32(i32 %offset) nounwind { ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i32 %old @@ -548,19 +548,19 @@ define i32 @test_atomic_load_min_i32(i32 %offset) nounwind { define i64 @test_atomic_load_min_i64(i64 %offset) nounwind { ; CHECK: test_atomic_load_min_i64: %old = atomicrmw min i64* @var64, i64 %offset seq_cst -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]] ; x0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp x0, x[[OLD]] ; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, gt -; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i64 %old @@ -569,19 +569,19 @@ define i64 @test_atomic_load_min_i64(i64 %offset) nounwind { define i8 @test_atomic_load_max_i8(i8 %offset) nounwind { ; CHECK: test_atomic_load_max_i8: %old = atomicrmw max i8* @var8, i8 %offset seq_cst -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp w0, w[[OLD]], sxtb ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lt -; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i8 %old @@ -589,20 +589,20 @@ define i8 @test_atomic_load_max_i8(i8 %offset) nounwind { define i16 @test_atomic_load_max_i16(i16 %offset) nounwind { ; CHECK: test_atomic_load_max_i16: - %old = atomicrmw max i16* @var16, i16 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw max i16* @var16, i16 %offset acquire +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp w0, w[[OLD]], sxth ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lt ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i16 %old @@ -610,8 +610,8 @@ define i16 @test_atomic_load_max_i16(i16 %offset) nounwind { define i32 @test_atomic_load_max_i32(i32 %offset) nounwind { ; CHECK: test_atomic_load_max_i32: - %old = atomicrmw max i32* @var32, i32 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw max i32* @var32, i32 %offset release +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 @@ -621,9 +621,9 @@ define i32 @test_atomic_load_max_i32(i32 %offset) nounwind { ; function there. ; CHECK-NEXT: cmp w0, w[[OLD]] ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lt -; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i32 %old @@ -631,8 +631,8 @@ define i32 @test_atomic_load_max_i32(i32 %offset) nounwind { define i64 @test_atomic_load_max_i64(i64 %offset) nounwind { ; CHECK: test_atomic_load_max_i64: - %old = atomicrmw max i64* @var64, i64 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw max i64* @var64, i64 %offset monotonic +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 @@ -644,7 +644,7 @@ define i64 @test_atomic_load_max_i64(i64 %offset) nounwind { ; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, lt ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i64 %old @@ -652,8 +652,8 @@ define i64 @test_atomic_load_max_i64(i64 %offset) nounwind { define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind { ; CHECK: test_atomic_load_umin_i8: - %old = atomicrmw umin i8* @var8, i8 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw umin i8* @var8, i8 %offset monotonic +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 @@ -665,7 +665,7 @@ define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind { ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i8 %old @@ -673,20 +673,20 @@ define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind { define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind { ; CHECK: test_atomic_load_umin_i16: - %old = atomicrmw umin i16* @var16, i16 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw umin i16* @var16, i16 %offset acquire +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp w0, w[[OLD]], uxth ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i16 %old @@ -695,19 +695,19 @@ define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind { define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind { ; CHECK: test_atomic_load_umin_i32: %old = atomicrmw umin i32* @var32, i32 %offset seq_cst -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp w0, w[[OLD]] ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi -; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i32 %old @@ -715,20 +715,20 @@ define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind { define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind { ; CHECK: test_atomic_load_umin_i64: - %old = atomicrmw umin i64* @var64, i64 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw umin i64* @var64, i64 %offset acq_rel +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]] ; x0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp x0, x[[OLD]] ; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, hi -; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i64 %old @@ -736,20 +736,20 @@ define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind { define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind { ; CHECK: test_atomic_load_umax_i8: - %old = atomicrmw umax i8* @var8, i8 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw umax i8* @var8, i8 %offset acq_rel +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp w0, w[[OLD]], uxtb ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lo -; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i8 %old @@ -757,8 +757,8 @@ define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind { define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind { ; CHECK: test_atomic_load_umax_i16: - %old = atomicrmw umax i16* @var16, i16 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw umax i16* @var16, i16 %offset monotonic +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 @@ -770,7 +770,7 @@ define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind { ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lo ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i16 %old @@ -779,19 +779,19 @@ define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind { define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind { ; CHECK: test_atomic_load_umax_i32: %old = atomicrmw umax i32* @var32, i32 %offset seq_cst -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp w0, w[[OLD]] ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lo -; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i32 %old @@ -799,8 +799,8 @@ define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind { define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind { ; CHECK: test_atomic_load_umax_i64: - %old = atomicrmw umax i64* @var64, i64 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw umax i64* @var64, i64 %offset release +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 @@ -810,9 +810,9 @@ define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind { ; function there. ; CHECK-NEXT: cmp x0, x[[OLD]] ; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, lo -; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i64 %old @@ -820,13 +820,13 @@ define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind { define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind { ; CHECK: test_atomic_cmpxchg_i8: - %old = cmpxchg i8* @var8, i8 %wanted, i8 %new seq_cst -; CHECK: dmb ish + %old = cmpxchg i8* @var8, i8 %wanted, i8 %new acquire +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 ; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]: -; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp w[[OLD]], w0 @@ -834,7 +834,7 @@ define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind { ; As above, w1 is a reasonable guess. ; CHECK: stxrb [[STATUS:w[0-9]+]], w1, [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]] -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i8 %old @@ -843,20 +843,20 @@ define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind { define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind { ; CHECK: test_atomic_cmpxchg_i16: %old = cmpxchg i16* @var16, i16 %wanted, i16 %new seq_cst -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 ; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]: -; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp w[[OLD]], w0 ; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]] ; As above, w1 is a reasonable guess. -; CHECK: stxrh [[STATUS:w[0-9]+]], w1, [x[[ADDR]]] +; CHECK: stlxrh [[STATUS:w[0-9]+]], w1, [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]] -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i16 %old @@ -864,8 +864,8 @@ define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind { define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind { ; CHECK: test_atomic_cmpxchg_i32: - %old = cmpxchg i32* @var32, i32 %wanted, i32 %new seq_cst -; CHECK: dmb ish + %old = cmpxchg i32* @var32, i32 %wanted, i32 %new release +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 @@ -876,9 +876,9 @@ define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind { ; CHECK-NEXT: cmp w[[OLD]], w0 ; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]] ; As above, w1 is a reasonable guess. -; CHECK: stxr [[STATUS:w[0-9]+]], w1, [x[[ADDR]]] +; CHECK: stlxr [[STATUS:w[0-9]+]], w1, [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]] -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i32 %old @@ -886,8 +886,8 @@ define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind { define i64 @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind { ; CHECK: test_atomic_cmpxchg_i64: - %old = cmpxchg i64* @var64, i64 %wanted, i64 %new seq_cst -; CHECK: dmb ish + %old = cmpxchg i64* @var64, i64 %wanted, i64 %new monotonic +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 @@ -900,7 +900,7 @@ define i64 @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind { ; As above, w1 is a reasonable guess. ; CHECK: stxr [[STATUS:w[0-9]+]], x1, [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]] -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i64 %old @@ -933,19 +933,26 @@ define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind { define i8 @test_atomic_load_acquire_i8() nounwind { ; CHECK: test_atomic_load_acquire_i8: %val = load atomic i8* @var8 acquire, align 1 +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 +; CHECK-NOT: dmb ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 - +; CHECK-NOT: dmb ; CHECK: ldarb w0, [x[[ADDR]]] +; CHECK-NOT: dmb ret i8 %val } define i8 @test_atomic_load_seq_cst_i8() nounwind { ; CHECK: test_atomic_load_seq_cst_i8: %val = load atomic i8* @var8 seq_cst, align 1 -; CHECK: adrp x[[HIADDR:[0-9]+]], var8 -; CHECK: ldrb w0, [x[[HIADDR]], #:lo12:var8] -; CHECK: dmb ish +; CHECK-NOT: dmb +; CHECK: adrp [[HIADDR:x[0-9]+]], var8 +; CHECK-NOT: dmb +; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], #:lo12:var8 +; CHECK-NOT: dmb +; CHECK: ldarb w0, [x[[ADDR]]] +; CHECK-NOT: dmb ret i8 %val } @@ -954,6 +961,7 @@ define i16 @test_atomic_load_monotonic_i16() nounwind { %val = load atomic i16* @var16 monotonic, align 2 ; CHECK-NOT: dmb ; CHECK: adrp x[[HIADDR:[0-9]+]], var16 +; CHECK-NOT: dmb ; CHECK: ldrh w0, [x[[HIADDR]], #:lo12:var16] ; CHECK-NOT: dmb @@ -976,9 +984,13 @@ define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind define i64 @test_atomic_load_seq_cst_i64() nounwind { ; CHECK: test_atomic_load_seq_cst_i64: %val = load atomic i64* @var64 seq_cst, align 8 -; CHECK: adrp x[[HIADDR:[0-9]+]], var64 -; CHECK: ldr x0, [x[[HIADDR]], #:lo12:var64] -; CHECK: dmb ish +; CHECK-NOT: dmb +; CHECK: adrp [[HIADDR:x[0-9]+]], var64 +; CHECK-NOT: dmb +; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], #:lo12:var64 +; CHECK-NOT: dmb +; CHECK: ldar x0, [x[[ADDR]]] +; CHECK-NOT: dmb ret i64 %val } @@ -1005,20 +1017,26 @@ define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val) define void @test_atomic_store_release_i8(i8 %val) nounwind { ; CHECK: test_atomic_store_release_i8: store atomic i8 %val, i8* @var8 release, align 1 +; CHECK-NOT: dmb ; CHECK: adrp [[HIADDR:x[0-9]+]], var8 +; CHECK-NOT: dmb ; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], #:lo12:var8 +; CHECK-NOT: dmb ; CHECK: stlrb w0, [x[[ADDR]]] - +; CHECK-NOT: dmb ret void } define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind { ; CHECK: test_atomic_store_seq_cst_i8: store atomic i8 %val, i8* @var8 seq_cst, align 1 +; CHECK-NOT: dmb ; CHECK: adrp [[HIADDR:x[0-9]+]], var8 +; CHECK-NOT: dmb ; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], #:lo12:var8 +; CHECK-NOT: dmb ; CHECK: stlrb w0, [x[[ADDR]]] -; CHECK: dmb ish +; CHECK-NOT: dmb ret void } @@ -1026,9 +1044,11 @@ define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind { define void @test_atomic_store_monotonic_i16(i16 %val) nounwind { ; CHECK: test_atomic_store_monotonic_i16: store atomic i16 %val, i16* @var16 monotonic, align 2 +; CHECK-NOT: dmb ; CHECK: adrp x[[HIADDR:[0-9]+]], var16 +; CHECK-NOT: dmb ; CHECK: strh w0, [x[[HIADDR]], #:lo12:var16] - +; CHECK-NOT: dmb ret void } @@ -1039,7 +1059,9 @@ define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %va %addr = inttoptr i64 %addr_int to i32* store atomic i32 %val, i32* %addr monotonic, align 4 +; CHECK-NOT: dmb ; CHECK: str w2, [x0, x1] +; CHECK-NOT: dmb ret void } @@ -1047,9 +1069,12 @@ define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %va define void @test_atomic_store_release_i64(i64 %val) nounwind { ; CHECK: test_atomic_store_release_i64: store atomic i64 %val, i64* @var64 release, align 8 +; CHECK-NOT: dmb ; CHECK: adrp [[HIADDR:x[0-9]+]], var64 +; CHECK-NOT: dmb ; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], #:lo12:var64 +; CHECK-NOT: dmb ; CHECK: stlr x0, [x[[ADDR]]] - +; CHECK-NOT: dmb ret void } diff --git a/test/CodeGen/AArch64/blockaddress.ll b/test/CodeGen/AArch64/blockaddress.ll index 3d0a5cf..5e85057 100644 --- a/test/CodeGen/AArch64/blockaddress.ll +++ b/test/CodeGen/AArch64/blockaddress.ll @@ -1,4 +1,5 @@ ; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -code-model=large -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-LARGE %s @addr = global i8* null @@ -13,6 +14,14 @@ define void @test_blockaddress() { ; CHECK: ldr [[NEWDEST:x[0-9]+]] ; CHECK: br [[NEWDEST]] +; CHECK-LARGE: movz [[ADDR_REG:x[0-9]+]], #:abs_g3:[[DEST_LBL:.Ltmp[0-9]+]] +; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g2_nc:[[DEST_LBL]] +; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g1_nc:[[DEST_LBL]] +; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g0_nc:[[DEST_LBL]] +; CHECK-LARGE: str [[ADDR_REG]], +; CHECK-LARGE: ldr [[NEWDEST:x[0-9]+]] +; CHECK-LARGE: br [[NEWDEST]] + block: ret void } diff --git a/test/CodeGen/AArch64/code-model-large-abs.ll b/test/CodeGen/AArch64/code-model-large-abs.ll new file mode 100644 index 0000000..a365568 --- /dev/null +++ b/test/CodeGen/AArch64/code-model-large-abs.ll @@ -0,0 +1,61 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -code-model=large < %s | FileCheck %s + +@var8 = global i8 0 +@var16 = global i16 0 +@var32 = global i32 0 +@var64 = global i64 0 + +define i8* @global_addr() { +; CHECK: global_addr: + ret i8* @var8 + ; The movz/movk calculation should end up returned directly in x0. +; CHECK: movz x0, #:abs_g3:var8 +; CHECK: movk x0, #:abs_g2_nc:var8 +; CHECK: movk x0, #:abs_g1_nc:var8 +; CHECK: movk x0, #:abs_g0_nc:var8 +; CHECK-NEXT: ret +} + +define i8 @global_i8() { +; CHECK: global_i8: + %val = load i8* @var8 + ret i8 %val +; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var8 +; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8 +; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8 +; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var8 +; CHECK: ldrb w0, [x[[ADDR_REG]]] +} + +define i16 @global_i16() { +; CHECK: global_i16: + %val = load i16* @var16 + ret i16 %val +; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16 +; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var16 +; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var16 +; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var16 +; CHECK: ldrh w0, [x[[ADDR_REG]]] +} + +define i32 @global_i32() { +; CHECK: global_i32: + %val = load i32* @var32 + ret i32 %val +; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var32 +; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var32 +; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var32 +; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var32 +; CHECK: ldr w0, [x[[ADDR_REG]]] +} + +define i64 @global_i64() { +; CHECK: global_i64: + %val = load i64* @var64 + ret i64 %val +; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var64 +; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var64 +; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var64 +; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var64 +; CHECK: ldr x0, [x[[ADDR_REG]]] +} diff --git a/test/CodeGen/AArch64/elf-extern.ll b/test/CodeGen/AArch64/elf-extern.ll index ee89d8d..8bf1b2f 100644 --- a/test/CodeGen/AArch64/elf-extern.ll +++ b/test/CodeGen/AArch64/elf-extern.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -filetype=obj | elf-dump | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -filetype=obj | llvm-readobj -r | FileCheck %s ; External symbols are a different concept to global variables but should still ; get relocations and so on when used. @@ -10,12 +10,8 @@ define i32 @check_extern() { ret i32 0 } -; CHECK: .rela.text -; CHECK: ('r_sym', 0x00000009) -; CHECK-NEXT: ('r_type', 0x0000011b) - -; CHECK: .symtab -; CHECK: Symbol 9 -; CHECK-NEXT: memcpy - - +; CHECK: Relocations [ +; CHECK: Section (1) .text { +; CHECK: 0x{{[0-9,A-F]+}} R_AARCH64_CALL26 memcpy +; CHECK: } +; CHECK: ] diff --git a/test/CodeGen/AArch64/extern-weak.ll b/test/CodeGen/AArch64/extern-weak.ll index 3d3d867..bc0acc2 100644 --- a/test/CodeGen/AArch64/extern-weak.ll +++ b/test/CodeGen/AArch64/extern-weak.ll @@ -1,4 +1,5 @@ ; RUN: llc -mtriple=aarch64-none-linux-gnu -o - < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-none-linux-gnu -code-model=large -o - < %s | FileCheck --check-prefix=CHECK-LARGE %s declare extern_weak i32 @var() @@ -11,6 +12,12 @@ define i32()* @foo() { ; CHECK: ldr x0, [{{x[0-9]+}}, #:lo12:.LCPI0_0] + ; In the large model, the usual relocations are absolute and can + ; materialise 0. +; CHECK-LARGE: movz x0, #:abs_g3:var +; CHECK-LARGE: movk x0, #:abs_g2_nc:var +; CHECK-LARGE: movk x0, #:abs_g1_nc:var +; CHECK-LARGE: movk x0, #:abs_g0_nc:var } @@ -24,6 +31,13 @@ define i32* @bar() { ; CHECK: ldr [[BASE:x[0-9]+]], [{{x[0-9]+}}, #:lo12:.LCPI1_0] ; CHECK: add x0, [[BASE]], #20 ret i32* %addr + + ; In the large model, the usual relocations are absolute and can + ; materialise 0. +; CHECK-LARGE: movz x0, #:abs_g3:arr_var +; CHECK-LARGE: movk x0, #:abs_g2_nc:arr_var +; CHECK-LARGE: movk x0, #:abs_g1_nc:arr_var +; CHECK-LARGE: movk x0, #:abs_g0_nc:arr_var } @defined_weak_var = internal unnamed_addr global i32 0 @@ -32,4 +46,9 @@ define i32* @wibble() { ret i32* @defined_weak_var ; CHECK: adrp [[BASE:x[0-9]+]], defined_weak_var ; CHECK: add x0, [[BASE]], #:lo12:defined_weak_var + +; CHECK-LARGE: movz x0, #:abs_g3:defined_weak_var +; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var +; CHECK-LARGE: movk x0, #:abs_g1_nc:defined_weak_var +; CHECK-LARGE: movk x0, #:abs_g0_nc:defined_weak_var } \ No newline at end of file diff --git a/test/CodeGen/AArch64/jump-table.ll b/test/CodeGen/AArch64/jump-table.ll index dcf9f4e..3c7f5f9 100644 --- a/test/CodeGen/AArch64/jump-table.ll +++ b/test/CodeGen/AArch64/jump-table.ll @@ -1,5 +1,6 @@ ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -filetype=obj | elf-dump | FileCheck %s -check-prefix=CHECK-ELF +; RUN: llc -code-model=large -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck --check-prefix=CHECK-LARGE %s +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -filetype=obj | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF define i32 @test_jumptable(i32 %in) { ; CHECK: test_jumptable @@ -15,6 +16,13 @@ define i32 @test_jumptable(i32 %in) { ; CHECK: ldr [[DEST:x[0-9]+]], [x[[JT]], {{x[0-9]+}}, lsl #3] ; CHECK: br [[DEST]] +; CHECK-LARGE: movz x[[JTADDR:[0-9]+]], #:abs_g3:.LJTI0_0 +; CHECK-LARGE: movk x[[JTADDR]], #:abs_g2_nc:.LJTI0_0 +; CHECK-LARGE: movk x[[JTADDR]], #:abs_g1_nc:.LJTI0_0 +; CHECK-LARGE: movk x[[JTADDR]], #:abs_g0_nc:.LJTI0_0 +; CHECK-LARGE: ldr [[DEST:x[0-9]+]], [x[[JTADDR]], {{x[0-9]+}}, lsl #3] +; CHECK-LARGE: br [[DEST]] + def: ret i32 0 @@ -44,13 +52,15 @@ lbl4: ; ELF tests: ; First make sure we get a page/lo12 pair in .text to pick up the jump-table -; CHECK-ELF: .rela.text -; CHECK-ELF: ('r_sym', 0x00000008) -; CHECK-ELF-NEXT: ('r_type', 0x00000113) -; CHECK-ELF: ('r_sym', 0x00000008) -; CHECK-ELF-NEXT: ('r_type', 0x00000115) + +; CHECK-ELF: Relocations [ +; CHECK-ELF: Section ({{[0-9]+}}) .text { +; CHECK-ELF-NEXT: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 .rodata +; CHECK-ELF-NEXT: 0x{{[0-9,A-F]+}} R_AARCH64_ADD_ABS_LO12_NC .rodata +; CHECK-ELF: } ; Also check the targets in .rodata are relocated -; CHECK-ELF: .rela.rodata -; CHECK-ELF: ('r_sym', 0x00000005) -; CHECK-ELF-NEXT: ('r_type', 0x00000101) \ No newline at end of file +; CHECK-ELF: Section ({{[0-9]+}}) .rodata { +; CHECK-ELF-NEXT: 0x{{[0-9,A-F]+}} R_AARCH64_ABS64 .text +; CHECK-ELF: } +; CHECK-ELF: ] diff --git a/test/CodeGen/AArch64/literal_pools.ll b/test/CodeGen/AArch64/literal_pools.ll index e090841..9cfa8c5 100644 --- a/test/CodeGen/AArch64/literal_pools.ll +++ b/test/CodeGen/AArch64/literal_pools.ll @@ -1,4 +1,5 @@ ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -code-model=large | FileCheck --check-prefix=CHECK-LARGE %s @var32 = global i32 0 @var64 = global i64 0 @@ -13,21 +14,45 @@ define void @foo() { ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI0_[0-9]+]] ; CHECK: ldr {{w[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]] +; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI0_[0-9]+]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g0_nc:[[CURLIT]] +; CHECK-LARGE: ldr {{w[0-9]+}}, [x[[LITADDR]]] + %val64_lit32 = and i64 %val64, 305402420 store volatile i64 %val64_lit32, i64* @var64 ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI0_[0-9]+]] ; CHECK: ldr {{w[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]] +; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI0_[0-9]+]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g0_nc:[[CURLIT]] +; CHECK-LARGE: ldr {{w[0-9]+}}, [x[[LITADDR]]] + %val64_lit32signed = and i64 %val64, -12345678 store volatile i64 %val64_lit32signed, i64* @var64 ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI0_[0-9]+]] ; CHECK: ldrsw {{x[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]] +; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI0_[0-9]+]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g0_nc:[[CURLIT]] +; CHECK-LARGE: ldrsw {{x[0-9]+}}, [x[[LITADDR]]] + %val64_lit64 = and i64 %val64, 1234567898765432 store volatile i64 %val64_lit64, i64* @var64 ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI0_[0-9]+]] ; CHECK: ldr {{x[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]] +; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI0_[0-9]+]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g0_nc:[[CURLIT]] +; CHECK-LARGE: ldr {{x[0-9]+}}, [x[[LITADDR]]] + ret void } @@ -42,6 +67,14 @@ define void @floating_lits() { ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI1_[0-9]+]] ; CHECK: ldr {{s[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]] ; CHECK: fadd + +; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI1_[0-9]+]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g0_nc:[[CURLIT]] +; CHECK-LARGE: ldr {{s[0-9]+}}, [x[[LITADDR]]] +; CHECK-LARGE: fadd + store float %newfloat, float* @varfloat %doubleval = load double* @vardouble @@ -49,6 +82,13 @@ define void @floating_lits() { ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI1_[0-9]+]] ; CHECK: ldr {{d[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]] ; CHECK: fadd + +; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI1_[0-9]+]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g0_nc:[[CURLIT]] +; CHECK-LARGE: ldr {{d[0-9]+}}, [x[[LITADDR]]] + store double %newdouble, double* @vardouble ret void diff --git a/test/CodeGen/ARM/2010-08-04-StackVariable.ll b/test/CodeGen/ARM/2010-08-04-StackVariable.ll index 91a9903..112512f 100644 --- a/test/CodeGen/ARM/2010-08-04-StackVariable.ll +++ b/test/CodeGen/ARM/2010-08-04-StackVariable.ll @@ -79,7 +79,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !0 = metadata !{i32 786478, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"", metadata !2, i32 11, metadata !14, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786451, metadata !2, metadata !"SVal", metadata !2, i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_structure_type ] !2 = metadata !{i32 786473, metadata !48} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 786449, i32 4, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, metadata !47, metadata !47, metadata !46, metadata !47, metadata !""} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786449, i32 4, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, metadata !47, metadata !47, metadata !46, metadata !47, metadata !47, metadata !""} ; [ DW_TAG_compile_unit ] !4 = metadata !{metadata !5, metadata !7, metadata !0, metadata !9} !5 = metadata !{i32 786445, metadata !1, metadata !"Data", metadata !2, i32 7, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] !6 = metadata !{i32 786447, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] diff --git a/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll b/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll index 36d1575..b253fef 100644 --- a/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll +++ b/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll @@ -1,36 +1,47 @@ ; RUN: llc %s -mtriple=arm-linux-gnueabi -filetype=obj -o - | \ -; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=BASIC %s +; RUN: llvm-readobj -s -sd | FileCheck -check-prefix=BASIC %s ; RUN: llc %s -mtriple=armv7-linux-gnueabi -march=arm -mcpu=cortex-a8 \ ; RUN: -mattr=-neon,-vfp3,+vfp2 \ ; RUN: -arm-reserve-r9 -filetype=obj -o - | \ -; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=CORTEXA8 %s +; RUN: llvm-readobj -s -sd | FileCheck -check-prefix=CORTEXA8 %s ; This tests that the extpected ARM attributes are emitted. ; -; BASIC: .ARM.attributes -; BASIC-NEXT: 0x70000003 -; BASIC-NEXT: 0x00000000 -; BASIC-NEXT: 0x00000000 -; BASIC-NEXT: 0x0000003c -; BASIC-NEXT: 0x00000022 -; BASIC-NEXT: 0x00000000 -; BASIC-NEXT: 0x00000000 -; BASIC-NEXT: 0x00000001 -; BASIC-NEXT: 0x00000000 -; BASIC-NEXT: '41210000 00616561 62690001 17000000 060a0741 08010902 14011501 17031801 1901' +; BASIC: Section { +; BASIC: Name: .ARM.attributes +; BASIC-NEXT: Type: SHT_ARM_ATTRIBUTES +; BASIC-NEXT: Flags [ (0x0) +; BASIC-NEXT: ] +; BASIC-NEXT: Address: 0x0 +; BASIC-NEXT: Offset: 0x3C +; BASIC-NEXT: Size: 34 +; BASIC-NEXT: Link: 0 +; BASIC-NEXT: Info: 0 +; BASIC-NEXT: AddressAlignment: 1 +; BASIC-NEXT: EntrySize: 0 +; BASIC-NEXT: SectionData ( +; BASIC-NEXT: 0000: 41210000 00616561 62690001 17000000 +; BASIC-NEXT: 0010: 060A0741 08010902 14011501 17031801 +; BASIC-NEXT: 0020: 1901 +; BASIC-NEXT: ) -; CORTEXA8: .ARM.attributes -; CORTEXA8-NEXT: 0x70000003 -; CORTEXA8-NEXT: 0x00000000 -; CORTEXA8-NEXT: 0x00000000 -; CORTEXA8-NEXT: 0x0000003c -; CORTEXA8-NEXT: 0x0000002f -; CORTEXA8-NEXT: 0x00000000 -; CORTEXA8-NEXT: 0x00000000 -; CORTEXA8-NEXT: 0x00000001 -; CORTEXA8-NEXT: 0x00000000 -; CORTEXA8-NEXT: '412e0000 00616561 62690001 24000000 05434f52 5445582d 41380006 0a074108 0109020a 02140115 01170318 011901' +; CORTEXA8: Name: .ARM.attributes +; CORTEXA8-NEXT: Type: SHT_ARM_ATTRIBUTES +; CORTEXA8-NEXT: Flags [ (0x0) +; CORTEXA8-NEXT: ] +; CORTEXA8-NEXT: Address: 0x0 +; CORTEXA8-NEXT: Offset: 0x3C +; CORTEXA8-NEXT: Size: 47 +; CORTEXA8-NEXT: Link: 0 +; CORTEXA8-NEXT: Info: 0 +; CORTEXA8-NEXT: AddressAlignment: 1 +; CORTEXA8-NEXT: EntrySize: 0 +; CORTEXA8-NEXT: SectionData ( +; CORTEXA8-NEXT: 0000: 412E0000 00616561 62690001 24000000 +; CORTEXA8-NEXT: 0010: 05434F52 5445582D 41380006 0A074108 +; CORTEXA8-NEXT: 0020: 0109020A 02140115 01170318 011901 +; CORTEXA8-NEXT: ) define i32 @f(i64 %z) { ret i32 0 diff --git a/test/CodeGen/ARM/2010-11-30-reloc-movt.ll b/test/CodeGen/ARM/2010-11-30-reloc-movt.ll index 94a0541..9eecd04 100644 --- a/test/CodeGen/ARM/2010-11-30-reloc-movt.ll +++ b/test/CodeGen/ARM/2010-11-30-reloc-movt.ll @@ -1,5 +1,5 @@ ; RUN: llc %s -mtriple=armv7-linux-gnueabi -filetype=obj -o - | \ -; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s +; RUN: llvm-readobj -s -sr -sd | FileCheck -check-prefix=OBJ %s target triple = "armv7-none-linux-gnueabi" @@ -9,32 +9,17 @@ define arm_aapcs_vfpcc i32 @barf() nounwind { entry: %0 = tail call arm_aapcs_vfpcc i32 @foo(i8* @a) nounwind ret i32 %0 -; OBJ: '.text' -; OBJ-NEXT: 'sh_type' -; OBJ-NEXT: 'sh_flags' -; OBJ-NEXT: 'sh_addr' -; OBJ-NEXT: 'sh_offset' -; OBJ-NEXT: 'sh_size' -; OBJ-NEXT: 'sh_link' -; OBJ-NEXT: 'sh_info' -; OBJ-NEXT: 'sh_addralign' -; OBJ-NEXT: 'sh_entsize' -; OBJ-NEXT: '_section_data', '00482de9 000000e3 000040e3 feffffeb 0088bde8' - -; OBJ: Relocation 0 -; OBJ-NEXT: 'r_offset', 0x00000004 -; OBJ-NEXT: 'r_sym', 0x000009 -; OBJ-NEXT: 'r_type', 0x2b - -; OBJ: Relocation 1 -; OBJ-NEXT: 'r_offset', 0x00000008 -; OBJ-NEXT: 'r_sym' -; OBJ-NEXT: 'r_type', 0x2c - -; OBJ: # Relocation 2 -; OBJ-NEXT: 'r_offset', 0x0000000c -; OBJ-NEXT: 'r_sym', 0x00000a -; OBJ-NEXT: 'r_type', 0x1c +; OBJ: Section { +; OBJ: Name: .text +; OBJ: Relocations [ +; OBJ-NEXT: 0x4 R_ARM_MOVW_ABS_NC a +; OBJ-NEXT: 0x8 R_ARM_MOVT_ABS +; OBJ-NEXT: 0xC R_ARM_CALL foo +; OBJ-NEXT: ] +; OBJ-NEXT: SectionData ( +; OBJ-NEXT: 0000: 00482DE9 000000E3 000040E3 FEFFFFEB +; OBJ-NEXT: 0010: 0088BDE8 +; OBJ-NEXT: ) } diff --git a/test/CodeGen/ARM/2010-12-08-tpsoft.ll b/test/CodeGen/ARM/2010-12-08-tpsoft.ll index b8ed819..1351a26 100644 --- a/test/CodeGen/ARM/2010-12-08-tpsoft.ll +++ b/test/CodeGen/ARM/2010-12-08-tpsoft.ll @@ -1,9 +1,9 @@ ; RUN: llc %s -mtriple=armv7-linux-gnueabi -o - | \ ; RUN: FileCheck -check-prefix=ELFASM %s ; RUN: llc %s -mtriple=armv7-linux-gnueabi -filetype=obj -o - | \ -; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=ELFOBJ %s +; RUN: llvm-readobj -s -sd | FileCheck -check-prefix=ELFOBJ %s -;; Make sure that bl __aeabi_read_tp is materiazlied and fixed up correctly +;; Make sure that bl __aeabi_read_tp is materialized and fixed up correctly ;; in the obj case. @i = external thread_local global i32 @@ -24,19 +24,13 @@ bb: ; preds = %entry ; ELFASM: bl __aeabi_read_tp -; ELFOBJ: '.text' -; ELFOBJ-NEXT: 'sh_type' -; ELFOBJ-NEXT: 'sh_flags' -; ELFOBJ-NEXT: 'sh_addr' -; ELFOBJ-NEXT: 'sh_offset' -; ELFOBJ-NEXT: 'sh_size' -; ELFOBJ-NEXT: 'sh_link' -; ELFOBJ-NEXT: 'sh_info' -; ELFOBJ-NEXT: 'sh_addralign' -; ELFOBJ-NEXT: 'sh_entsize' -;;; BL __aeabi_read_tp is ---+ -;;; V -; ELFOBJ-NEXT: 00482de9 3c009fe5 00109fe7 feffffeb +; ELFOBJ: Sections [ +; ELFOBJ: Section { +; ELFOBJ: Name: .text +; ELFOBJ: SectionData ( +;;; BL __aeabi_read_tp is ---------+ +;;; V +; ELFOBJ-NEXT: 0000: 00482DE9 3C009FE5 00109FE7 FEFFFFEB bb1: ; preds = %entry diff --git a/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll b/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll index 1272a25..f13bc12 100644 --- a/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll +++ b/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll @@ -1,5 +1,5 @@ ; RUN: llc %s -mtriple=armv7-linux-gnueabi -filetype=obj -o - | \ -; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s +; RUN: llvm-readobj -s -t | FileCheck -check-prefix=OBJ %s ; RUN: llc %s -mtriple=armv7-linux-gnueabi -o - | \ ; RUN: FileCheck -check-prefix=ASM %s @@ -15,17 +15,20 @@ ; ASM-NEXT: .type _MergedGlobals,%object @ @_MergedGlobals - -; OBJ: Section 4 -; OBJ-NEXT: '.bss' - -; OBJ: 'array00' -; OBJ-NEXT: 'st_value', 0x00000000 -; OBJ-NEXT: 'st_size', 0x00000050 -; OBJ-NEXT: 'st_bind', 0x0 -; OBJ-NEXT: 'st_type', 0x1 -; OBJ-NEXT: 'st_other', 0x00 -; OBJ-NEXT: 'st_shndx', 0x0004 +; OBJ: Sections [ +; OBJ: Section { +; OBJ: Index: 4 +; OBJ-NEXT: Name: .bss + +; OBJ: Symbols [ +; OBJ: Symbol { +; OBJ: Name: array00 +; OBJ-NEXT: Value: 0x0 +; OBJ-NEXT: Size: 80 +; OBJ-NEXT: Binding: Local +; OBJ-NEXT: Type: Object +; OBJ-NEXT: Other: 0 +; OBJ-NEXT: Section: .bss define i32 @main(i32 %argc) nounwind { %1 = load i32* @sum, align 4 diff --git a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll index 1d1b89a..98c0af3 100644 --- a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll +++ b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll @@ -79,7 +79,7 @@ entry: !0 = metadata !{i32 786478, metadata !1, metadata !"get1", metadata !"get1", metadata !"get1", metadata !1, i32 4, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get1, null, null, metadata !42, i32 4} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786473, metadata !47} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, metadata !47, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 2369.8)", i1 true, metadata !"", i32 0, null, null, metadata !40, metadata !41, metadata !""} ; [ DW_TAG_compile_unit ] +!2 = metadata !{i32 786449, metadata !47, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 2369.8)", i1 true, metadata !"", i32 0, null, null, metadata !40, metadata !41, metadata !41, metadata !""} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !1, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5, metadata !5} !5 = metadata !{i32 786468, metadata !1, metadata !1, metadata !"_Bool", i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ] diff --git a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll index 266609b8..7a7ca8e 100644 --- a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll +++ b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll @@ -74,7 +74,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !47, i32 12, metadata !"clang", i1 true, metadata !"", i32 0, null, null, metadata !40, metadata !41, null} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, metadata !47, i32 12, metadata !"clang", i1 true, metadata !"", i32 0, null, null, metadata !40, metadata !41, metadata !41, null} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 786478, metadata !2, metadata !"get1", metadata !"get1", metadata !"", metadata !2, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get1, null, null, metadata !42, i32 5} ; [ DW_TAG_subprogram ] !2 = metadata !{i32 786473, metadata !47} ; [ DW_TAG_file_type ] !3 = metadata !{i32 786453, metadata !2, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] diff --git a/test/CodeGen/ARM/2011-12-14-machine-sink.ll b/test/CodeGen/ARM/2011-12-14-machine-sink.ll index 1b21f75..9334bf3 100644 --- a/test/CodeGen/ARM/2011-12-14-machine-sink.ll +++ b/test/CodeGen/ARM/2011-12-14-machine-sink.ll @@ -15,13 +15,13 @@ for.cond: ; preds = %for.body, %entry for.body: ; preds = %for.cond %v.5 = select i1 undef, i32 undef, i32 0 - %0 = load i8* undef, align 1, !tbaa !0 + %0 = load i8* undef, align 1 %conv88 = zext i8 %0 to i32 %sub89 = sub nsw i32 0, %conv88 %v.8 = select i1 undef, i32 undef, i32 %sub89 - %1 = load i8* null, align 1, !tbaa !0 + %1 = load i8* null, align 1 %conv108 = zext i8 %1 to i32 - %2 = load i8* undef, align 1, !tbaa !0 + %2 = load i8* undef, align 1 %conv110 = zext i8 %2 to i32 %sub111 = sub nsw i32 %conv108, %conv110 %cmp112 = icmp slt i32 %sub111, 0 @@ -44,6 +44,3 @@ if.end299: ; preds = %for.body, %for.cond %s.10 = phi i32 [ %add172, %for.body ], [ 0, %for.cond ] ret i32 %s.10 } - -!0 = metadata !{metadata !"omnipotent char", metadata !1} -!1 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll b/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll index 926daaf..0f1c452 100644 --- a/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll +++ b/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll @@ -18,7 +18,7 @@ bb3: ; preds = %bb4, %bb2 br i1 %tmp, label %bb4, label %bb67 bb4: ; preds = %bb3 - %tmp5 = load <4 x i32>* undef, align 16, !tbaa !0 + %tmp5 = load <4 x i32>* undef, align 16 %tmp6 = and <4 x i32> %tmp5, %tmp7 = or <4 x i32> %tmp6, %tmp8 = bitcast <4 x i32> %tmp7 to <4 x float> @@ -41,9 +41,9 @@ bb4: ; preds = %bb3 %tmp24 = trunc i128 %tmp23 to i64 %tmp25 = insertvalue [2 x i64] undef, i64 %tmp24, 0 %tmp26 = insertvalue [2 x i64] %tmp25, i64 0, 1 - %tmp27 = load float* undef, align 4, !tbaa !2 + %tmp27 = load float* undef, align 4 %tmp28 = insertelement <4 x float> undef, float %tmp27, i32 3 - %tmp29 = load <4 x i32>* undef, align 16, !tbaa !0 + %tmp29 = load <4 x i32>* undef, align 16 %tmp30 = and <4 x i32> %tmp29, %tmp31 = or <4 x i32> %tmp30, %tmp32 = bitcast <4 x i32> %tmp31 to <4 x float> @@ -52,10 +52,10 @@ bb4: ; preds = %bb3 %tmp35 = fmul <4 x float> %tmp34, undef %tmp36 = fmul <4 x float> %tmp35, undef %tmp37 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind - %tmp38 = load float* undef, align 4, !tbaa !2 + %tmp38 = load float* undef, align 4 %tmp39 = insertelement <2 x float> undef, float %tmp38, i32 0 %tmp40 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind - %tmp41 = load float* undef, align 4, !tbaa !2 + %tmp41 = load float* undef, align 4 %tmp42 = insertelement <4 x float> undef, float %tmp41, i32 3 %tmp43 = shufflevector <2 x float> %tmp39, <2 x float> undef, <4 x i32> zeroinitializer %tmp44 = fmul <4 x float> %tmp33, %tmp43 @@ -64,10 +64,10 @@ bb4: ; preds = %bb3 %tmp47 = fmul <4 x float> %tmp46, %tmp36 %tmp48 = fadd <4 x float> undef, %tmp47 %tmp49 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind - %tmp50 = load float* undef, align 4, !tbaa !2 + %tmp50 = load float* undef, align 4 %tmp51 = insertelement <4 x float> undef, float %tmp50, i32 3 %tmp52 = call arm_aapcs_vfpcc float* null(i8* undef) nounwind - %tmp54 = load float* %tmp52, align 4, !tbaa !2 + %tmp54 = load float* %tmp52, align 4 %tmp55 = insertelement <4 x float> undef, float %tmp54, i32 3 %tmp56 = fsub <4 x float> , %tmp22 %tmp57 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp56, <4 x float> %tmp55) nounwind @@ -99,7 +99,3 @@ declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwin declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone - -!0 = metadata !{metadata !"omnipotent char", metadata !1} -!1 = metadata !{metadata !"Simple C/C++ TBAA", null} -!2 = metadata !{metadata !"float", metadata !0} diff --git a/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll b/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll index f1c85f1..61623ec 100644 --- a/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll +++ b/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll @@ -7,7 +7,7 @@ target triple = "armv7-none-linux-eabi" ; This test case is exercising REG_SEQUENCE, and chains of REG_SEQUENCE. define arm_aapcs_vfpcc void @foo(i8* nocapture %arg, i8* %arg1) nounwind align 2 { bb: - %tmp = load <2 x float>* undef, align 8, !tbaa !0 + %tmp = load <2 x float>* undef, align 8 %tmp2 = extractelement <2 x float> %tmp, i32 0 %tmp3 = insertelement <4 x float> undef, float %tmp2, i32 0 %tmp4 = insertelement <4 x float> %tmp3, float 0.000000e+00, i32 1 @@ -70,6 +70,3 @@ entry: declare arm_aapcs_vfpcc void @bar(i8*, float, float, float) declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind declare void @llvm.arm.neon.vst2.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind - -!0 = metadata !{metadata !"omnipotent char", metadata !1} -!1 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll b/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll index 5f24e42..a9e2ebb 100644 --- a/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll +++ b/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll @@ -56,9 +56,9 @@ bb3: ; preds = %bb2 %tmp39 = shufflevector <2 x i64> %tmp38, <2 x i64> undef, <1 x i32> zeroinitializer %tmp40 = bitcast <1 x i64> %tmp39 to <2 x float> %tmp41 = shufflevector <2 x float> %tmp40, <2 x float> undef, <4 x i32> - %tmp42 = load <4 x float>* null, align 16, !tbaa !0 + %tmp42 = load <4 x float>* null, align 16 %tmp43 = fmul <4 x float> %tmp42, %tmp41 - %tmp44 = load <4 x float>* undef, align 16, !tbaa !0 + %tmp44 = load <4 x float>* undef, align 16 %tmp45 = fadd <4 x float> undef, %tmp43 %tmp46 = fadd <4 x float> undef, %tmp45 %tmp47 = bitcast <4 x float> %tmp36 to <2 x i64> @@ -108,7 +108,7 @@ bb3: ; preds = %bb2 %tmp89 = fmul <4 x float> undef, %tmp88 %tmp90 = fadd <4 x float> %tmp89, undef %tmp91 = fadd <4 x float> undef, %tmp90 - store <4 x float> %tmp91, <4 x float>* undef, align 16, !tbaa !0 + store <4 x float> %tmp91, <4 x float>* undef, align 16 unreachable bb92: ; preds = %bb2 @@ -116,6 +116,3 @@ bb92: ; preds = %bb2 } declare arm_aapcs_vfpcc void @bar(i8* noalias nocapture sret, [8 x i64]) nounwind uwtable inlinehint - -!0 = metadata !{metadata !"omnipotent char", metadata !1} -!1 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/ARM/2012-04-02-TwoAddrInstrCrash.ll b/test/CodeGen/ARM/2012-04-02-TwoAddrInstrCrash.ll index 33ad187..0843fdc 100644 --- a/test/CodeGen/ARM/2012-04-02-TwoAddrInstrCrash.ll +++ b/test/CodeGen/ARM/2012-04-02-TwoAddrInstrCrash.ll @@ -9,16 +9,13 @@ define arm_aapcs_vfpcc void @foo() nounwind align 2 { ;