From 1fc08f5e9ef733ef1ce6f363fecedc2260e78974 Mon Sep 17 00:00:00 2001 From: dim Date: Sat, 14 Apr 2012 13:54:10 +0000 Subject: Vendor import of llvm trunk r154661: http://llvm.org/svn/llvm-project/llvm/trunk@r154661 --- test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll | 2 +- test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll | 2 +- test/CodeGen/ARM/2009-08-31-LSDA-Name.ll | 11 +- test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll | 2 +- test/CodeGen/ARM/2009-09-24-spill-align.ll | 2 +- test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll | 2 +- test/CodeGen/ARM/2010-05-18-PostIndexBug.ll | 2 +- test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll | 2 +- test/CodeGen/ARM/2010-05-21-BuildVector.ll | 8 +- .../ARM/2010-06-29-PartialRedefFastAlloc.ll | 2 +- test/CodeGen/ARM/2010-07-26-GlobalMerge.ll | 11 +- test/CodeGen/ARM/2010-08-04-EHCrash.ll | 12 +- test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll | 2 +- test/CodeGen/ARM/2010-11-29-PrologueBug.ll | 4 +- test/CodeGen/ARM/2010-12-07-PEIBug.ll | 30 +- test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll | 13 +- test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll | 2 +- .../ARM/2011-05-04-MultipleLandingPadSuccs.ll | 25 +- test/CodeGen/ARM/2011-06-16-TailCallByVal.ll | 2 +- test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll | 4 +- test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll | 3 +- test/CodeGen/ARM/2011-08-25-ldmia_ret.ll | 2 +- .../ARM/2011-10-26-ExpandUnalignedLoadCrash.ll | 22 + test/CodeGen/ARM/2011-10-26-memset-inline.ll | 21 + test/CodeGen/ARM/2011-10-26-memset-with-neon.ll | 20 + .../ARM/2011-11-07-PromoteVectorLoadStore.ll | 24 + test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll | 15 + .../ARM/2011-11-09-IllegalVectorFPIntConvert.ll | 37 + test/CodeGen/ARM/2011-11-14-EarlyClobber.ll | 62 + test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll | 38 + test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll | 302 +++++ test/CodeGen/ARM/2011-11-30-MergeAlignment.ll | 24 + test/CodeGen/ARM/2011-12-14-machine-sink.ll | 48 + test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll | 55 + test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll | 105 ++ .../CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll | 67 + test/CodeGen/ARM/2012-01-26-CoalescerBug.ll | 21 + test/CodeGen/ARM/2012-01-26-CopyPropKills.ll | 121 ++ test/CodeGen/ARM/2012-02-01-CoalescerBug.ll | 26 + test/CodeGen/ARM/2012-03-05-FPSCR-bug.ll | 36 + test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll | 15 + test/CodeGen/ARM/2012-03-26-FoldImmBug.ll | 33 + test/CodeGen/ARM/2012-04-02-TwoAddrInstrCrash.ll | 24 + test/CodeGen/ARM/2012-04-10-DAGCombine.ll | 31 + test/CodeGen/ARM/arm-returnaddr.ll | 8 +- test/CodeGen/ARM/atomic-op.ll | 88 +- test/CodeGen/ARM/avoid-cpsr-rmw.ll | 44 +- test/CodeGen/ARM/call-tc.ll | 71 +- test/CodeGen/ARM/call.ll | 2 +- test/CodeGen/ARM/clz.ll | 4 +- test/CodeGen/ARM/code-placement.ll | 6 +- test/CodeGen/ARM/commute-movcc.ll | 67 + test/CodeGen/ARM/cse-call.ll | 31 + test/CodeGen/ARM/cse-libcalls.ll | 4 +- test/CodeGen/ARM/ctor_order.ll | 30 + test/CodeGen/ARM/ctz.ll | 4 +- test/CodeGen/ARM/dagcombine-anyexttozeroext.ll | 30 + test/CodeGen/ARM/debug-info-arg.ll | 2 +- test/CodeGen/ARM/debug-info-blocks.ll | 4 +- test/CodeGen/ARM/debug-info-d16-reg.ll | 2 +- test/CodeGen/ARM/debug-info-qreg.ll | 6 +- test/CodeGen/ARM/debug-info-s16-reg.ll | 3 +- test/CodeGen/ARM/debug-info-sreg2.ll | 8 +- test/CodeGen/ARM/dg.exp | 5 - test/CodeGen/ARM/eh-resume-darwin.ll | 13 +- test/CodeGen/ARM/ehabi-unwind.ll | 16 + test/CodeGen/ARM/fast-isel-GEP-coalesce.ll | 65 + test/CodeGen/ARM/fast-isel-binary.ll | 116 ++ test/CodeGen/ARM/fast-isel-br-const.ll | 48 + test/CodeGen/ARM/fast-isel-br-phi.ll | 44 + test/CodeGen/ARM/fast-isel-call.ll | 128 ++ test/CodeGen/ARM/fast-isel-cmp-imm.ll | 250 ++++ test/CodeGen/ARM/fast-isel-conversion.ll | 242 ++++ test/CodeGen/ARM/fast-isel-deadcode.ll | 22 + test/CodeGen/ARM/fast-isel-fold.ll | 80 ++ test/CodeGen/ARM/fast-isel-icmp.ll | 47 + test/CodeGen/ARM/fast-isel-indirectbr.ll | 17 + test/CodeGen/ARM/fast-isel-intrinsic.ll | 110 ++ test/CodeGen/ARM/fast-isel-ldr-str-arm.ll | 55 + .../ARM/fast-isel-ldr-str-thumb-neg-index.ll | 168 +++ test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll | 149 +++ test/CodeGen/ARM/fast-isel-mvn.ll | 107 ++ test/CodeGen/ARM/fast-isel-redefinition.ll | 2 +- test/CodeGen/ARM/fast-isel-ret.ll | 57 + test/CodeGen/ARM/fast-isel-select.ll | 99 ++ test/CodeGen/ARM/fast-isel.ll | 96 +- test/CodeGen/ARM/fcopysign.ll | 26 +- test/CodeGen/ARM/fold-const.ll | 4 +- test/CodeGen/ARM/fp.ll | 2 +- test/CodeGen/ARM/fpcmp-opt.ll | 63 +- test/CodeGen/ARM/fpcmp_ueq.ll | 2 +- test/CodeGen/ARM/fpmem.ll | 8 +- test/CodeGen/ARM/fusedMAC.ll | 185 +++ test/CodeGen/ARM/global-merge.ll | 2 +- test/CodeGen/ARM/globals.ll | 1 - test/CodeGen/ARM/hello.ll | 2 +- test/CodeGen/ARM/ifcvt1.ll | 6 +- test/CodeGen/ARM/ifcvt10.ll | 2 +- test/CodeGen/ARM/ifcvt11.ll | 4 +- test/CodeGen/ARM/ifcvt3.ll | 7 +- test/CodeGen/ARM/ifcvt5.ll | 2 +- test/CodeGen/ARM/ifcvt6.ll | 2 +- test/CodeGen/ARM/inlineasm3.ll | 10 + test/CodeGen/ARM/insn-sched1.ll | 2 +- test/CodeGen/ARM/ldrd-memoper.ll | 15 + test/CodeGen/ARM/ldrd.ll | 68 +- test/CodeGen/ARM/lit.local.cfg | 6 + test/CodeGen/ARM/load_i1_select.ll | 19 + test/CodeGen/ARM/log2_not_readnone.ll | 15 + test/CodeGen/ARM/long_shift.ll | 4 +- test/CodeGen/ARM/lsr-icmp-imm.ll | 33 + test/CodeGen/ARM/lsr-on-unrolled-loops.ll | 640 --------- test/CodeGen/ARM/lsr-unfolded-offset.ll | 2 +- test/CodeGen/ARM/machine-cse-cmp.ll | 33 +- test/CodeGen/ARM/memcpy-inline.ll | 3 +- test/CodeGen/ARM/memfunc.ll | 3 + test/CodeGen/ARM/mul_const.ll | 42 + test/CodeGen/ARM/neon_ld1.ll | 14 +- test/CodeGen/ARM/neon_ld2.ll | 15 +- test/CodeGen/ARM/neon_spill.ll | 54 + test/CodeGen/ARM/odr_comdat.ll | 16 + test/CodeGen/ARM/opt-shuff-tstore.ll | 19 + test/CodeGen/ARM/peephole-bitcast.ll | 4 +- test/CodeGen/ARM/reg_asc_order.ll | 16 + test/CodeGen/ARM/reg_sequence.ll | 8 +- test/CodeGen/ARM/rev.ll | 4 +- test/CodeGen/ARM/select-imm.ll | 4 +- test/CodeGen/ARM/select.ll | 10 +- test/CodeGen/ARM/select_xform.ll | 46 + test/CodeGen/ARM/shifter_operand.ll | 4 + test/CodeGen/ARM/spill-q.ll | 2 +- test/CodeGen/ARM/str_pre-2.ll | 1 - test/CodeGen/ARM/subreg-remat.ll | 16 +- test/CodeGen/ARM/tail-dup.ll | 44 + test/CodeGen/ARM/test-sharedidx.ll | 96 ++ test/CodeGen/ARM/vbsl-constant.ll | 18 +- test/CodeGen/ARM/vdiv_combine.ll | 12 +- test/CodeGen/ARM/vdup.ll | 2 +- test/CodeGen/ARM/vector-DAGCombine.ll | 16 +- test/CodeGen/ARM/vector-extend-narrow.ll | 46 + test/CodeGen/ARM/vext.ll | 2 +- test/CodeGen/ARM/vlddup.ll | 4 +- test/CodeGen/ARM/vldlane.ll | 14 +- test/CodeGen/ARM/vmov.ll | 63 +- test/CodeGen/ARM/vmul.ll | 11 + test/CodeGen/ARM/vrev.ll | 6 +- test/CodeGen/ARM/vst2.ll | 18 + test/CodeGen/ARM/vstlane.ll | 9 +- test/CodeGen/ARM/widen-vmovs.ll | 8 +- test/CodeGen/Alpha/2005-12-12-MissingFCMov.ll | 40 - test/CodeGen/Alpha/2006-01-18-MissedGlobal.ll | 27 - test/CodeGen/Alpha/2006-01-26-VaargBreak.ll | 14 - test/CodeGen/Alpha/2006-04-04-zextload.ll | 30 - test/CodeGen/Alpha/2006-07-03-ASMFormalLowering.ll | 18 - test/CodeGen/Alpha/2006-11-01-vastart.ll | 15 - test/CodeGen/Alpha/2007-11-27-mulneg3.ll | 13 - test/CodeGen/Alpha/2008-11-10-smul_lohi.ll | 22 - test/CodeGen/Alpha/2008-11-12-Add128.ll | 14 - .../Alpha/2009-07-16-PromoteFloatCompare.ll | 6 - .../Alpha/2010-04-07-DbgValueOtherTargets.ll | 28 - test/CodeGen/Alpha/2010-08-01-mulreduce64.ll | 11 - test/CodeGen/Alpha/add.ll | 178 --- test/CodeGen/Alpha/add128.ll | 9 - test/CodeGen/Alpha/bic.ll | 9 - test/CodeGen/Alpha/bsr.ll | 12 - test/CodeGen/Alpha/call_adj.ll | 13 - test/CodeGen/Alpha/cmov.ll | 23 - test/CodeGen/Alpha/cmpbge.ll | 16 - test/CodeGen/Alpha/ctlz.ll | 14 - test/CodeGen/Alpha/ctlz_e.ll | 11 - test/CodeGen/Alpha/ctpop.ll | 17 - test/CodeGen/Alpha/dg.exp | 5 - test/CodeGen/Alpha/eqv.ll | 10 - test/CodeGen/Alpha/i32_sub_1.ll | 9 - test/CodeGen/Alpha/illegal-element-type.ll | 23 - test/CodeGen/Alpha/jmp_table.ll | 99 -- test/CodeGen/Alpha/mb.ll | 6 - test/CodeGen/Alpha/mul128.ll | 7 - test/CodeGen/Alpha/mul5.ll | 33 - test/CodeGen/Alpha/neg1.ll | 7 - test/CodeGen/Alpha/not.ll | 8 - test/CodeGen/Alpha/ornot.ll | 10 - test/CodeGen/Alpha/private.ll | 19 - test/CodeGen/Alpha/rpcc.ll | 9 - test/CodeGen/Alpha/srl_and.ll | 10 - test/CodeGen/Alpha/sub128.ll | 9 - test/CodeGen/Alpha/weak.ll | 16 - test/CodeGen/Alpha/zapnot.ll | 9 - test/CodeGen/Alpha/zapnot2.ll | 9 - test/CodeGen/Alpha/zapnot3.ll | 15 - test/CodeGen/Alpha/zapnot4.ll | 7 - .../Blackfin/2009-08-04-LowerExtract-Live.ll | 16 - .../Blackfin/2009-08-11-RegScavenger-CSR.ll | 17 - test/CodeGen/Blackfin/2009-08-15-LiveIn-SubReg.ll | 19 - test/CodeGen/Blackfin/2009-08-15-MissingDead.ll | 25 - test/CodeGen/Blackfin/2009-08-15-SetCC-Undef.ll | 16 - test/CodeGen/Blackfin/add-overflow.ll | 18 - test/CodeGen/Blackfin/add.ll | 5 - test/CodeGen/Blackfin/addsub-i128.ll | 42 - test/CodeGen/Blackfin/basic-i1.ll | 51 - test/CodeGen/Blackfin/basic-i16.ll | 36 - test/CodeGen/Blackfin/basic-i32.ll | 51 - test/CodeGen/Blackfin/basic-i64.ll | 51 - test/CodeGen/Blackfin/basic-i8.ll | 51 - test/CodeGen/Blackfin/basictest.ll | 19 - test/CodeGen/Blackfin/cmp-small-imm.ll | 6 - test/CodeGen/Blackfin/cmp64.ll | 17 - test/CodeGen/Blackfin/ct32.ll | 20 - test/CodeGen/Blackfin/ct64.ll | 20 - test/CodeGen/Blackfin/ctlz16.ll | 18 - test/CodeGen/Blackfin/ctlz64.ll | 15 - test/CodeGen/Blackfin/ctpop16.ll | 18 - test/CodeGen/Blackfin/cttz16.ll | 18 - test/CodeGen/Blackfin/cycles.ll | 17 - test/CodeGen/Blackfin/dg.exp | 5 - test/CodeGen/Blackfin/double-cast.ll | 8 - test/CodeGen/Blackfin/frameindex.ll | 10 - test/CodeGen/Blackfin/i17mem.ll | 9 - test/CodeGen/Blackfin/i1mem.ll | 9 - test/CodeGen/Blackfin/i1ops.ll | 10 - test/CodeGen/Blackfin/i216mem.ll | 9 - test/CodeGen/Blackfin/i248mem.ll | 9 - test/CodeGen/Blackfin/i256mem.ll | 9 - test/CodeGen/Blackfin/i256param.ll | 7 - test/CodeGen/Blackfin/i56param.ll | 8 - test/CodeGen/Blackfin/i8mem.ll | 10 - test/CodeGen/Blackfin/inline-asm.ll | 38 - test/CodeGen/Blackfin/int-setcc.ll | 80 -- test/CodeGen/Blackfin/invalid-apint.ll | 15 - test/CodeGen/Blackfin/jumptable.ll | 53 - test/CodeGen/Blackfin/large-switch.ll | 187 --- test/CodeGen/Blackfin/load-i16.ll | 13 - test/CodeGen/Blackfin/logic-i16.ll | 16 - test/CodeGen/Blackfin/many-args.ll | 23 - test/CodeGen/Blackfin/mulhu.ll | 106 -- test/CodeGen/Blackfin/printf.ll | 10 - test/CodeGen/Blackfin/printf2.ll | 8 - test/CodeGen/Blackfin/promote-logic.ll | 42 - test/CodeGen/Blackfin/promote-setcc.ll | 37 - test/CodeGen/Blackfin/sdiv.ll | 5 - test/CodeGen/Blackfin/simple-select.ll | 11 - test/CodeGen/Blackfin/switch.ll | 18 - test/CodeGen/Blackfin/switch2.ll | 16 - test/CodeGen/Blackfin/sync-intr.ll | 16 - test/CodeGen/CBackend/2002-05-16-NameCollide.ll | 8 - test/CodeGen/CBackend/2002-05-21-MissingReturn.ll | 20 - .../CodeGen/CBackend/2002-08-19-ConstPointerRef.ll | 7 - test/CodeGen/CBackend/2002-08-19-ConstantExpr.ll | 8 - test/CodeGen/CBackend/2002-08-19-DataPointer.ll | 4 - .../CodeGen/CBackend/2002-08-19-FunctionPointer.ll | 5 - .../CBackend/2002-08-19-HardConstantExpr.ll | 5 - .../CodeGen/CBackend/2002-08-20-UnnamedArgument.ll | 10 - .../CBackend/2002-08-26-IndirectCallTest.ll | 17 - .../CBackend/2002-08-30-StructureOrderingTest.ll | 8 - .../CBackend/2002-09-20-ArrayTypeFailure.ll | 7 - .../CBackend/2002-09-20-VarArgPrototypes.ll | 6 - test/CodeGen/CBackend/2002-10-16-External.ll | 4 - test/CodeGen/CBackend/2002-11-06-PrintEscaped.ll | 11 - .../CBackend/2003-05-12-IntegerSizeWarning.ll | 8 - test/CodeGen/CBackend/2003-05-13-VarArgFunction.ll | 11 - .../CBackend/2003-05-31-MissingStructName.ll | 5 - .../CodeGen/CBackend/2003-06-01-NullPointerType.ll | 9 - test/CodeGen/CBackend/2003-06-11-HexConstant.ll | 4 - .../CBackend/2003-06-11-LiteralStringProblem.ll | 3 - test/CodeGen/CBackend/2003-06-28-InvokeSupport.ll | 17 - .../CBackend/2003-06-28-LinkOnceGlobalVars.ll | 3 - test/CodeGen/CBackend/2003-10-12-NANGlobalInits.ll | 5 - test/CodeGen/CBackend/2003-10-23-UnusedType.ll | 8 - .../CBackend/2003-10-28-CastToPtrToStruct.ll | 12 - .../CBackend/2003-11-21-ConstantShiftExpr.ll | 13 - .../CBackend/2004-02-13-FrameReturnAddress.ll | 16 - .../CBackend/2004-02-15-PreexistingExternals.ll | 18 - .../CBackend/2004-02-26-FPNotPrintableConstants.ll | 11 - .../CBackend/2004-02-26-LinkOnceFunctions.ll | 6 - test/CodeGen/CBackend/2004-08-09-va-end-null.ll | 10 - .../CBackend/2004-11-13-FunctionPointerCast.ll | 12 - test/CodeGen/CBackend/2004-12-03-ExternStatics.ll | 10 - .../CBackend/2004-12-28-LogicalConstantExprs.ll | 5 - .../CBackend/2005-02-14-VolatileOperations.ll | 8 - .../CBackend/2005-07-14-NegationToMinusMinus.ll | 18 - test/CodeGen/CBackend/2005-08-23-Fmod.ll | 7 - .../CodeGen/CBackend/2005-09-27-VolatileFuncPtr.ll | 10 - test/CodeGen/CBackend/2006-12-11-Float-Bitcast.ll | 49 - test/CodeGen/CBackend/2007-01-08-ParamAttr-ICmp.ll | 26 - .../CBackend/2007-01-17-StackSaveNRestore.ll | 12 - test/CodeGen/CBackend/2007-02-05-memset.ll | 13 - test/CodeGen/CBackend/2007-02-23-NameConflicts.ll | 14 - test/CodeGen/CBackend/2007-07-11-PackedStruct.ll | 9 - .../CBackend/2008-02-01-UnalignedLoadStore.ll | 15 - test/CodeGen/CBackend/2008-05-31-BoolOverflow.ll | 14 - .../CBackend/2008-10-21-PPCLongDoubleConstant.ll | 29 - .../CodeGen/CBackend/2011-06-08-addWithOverflow.ll | 35 - .../CodeGen/CBackend/X86/2008-06-04-IndirectMem.ll | 12 - test/CodeGen/CBackend/X86/dg.exp | 5 - test/CodeGen/CBackend/dg.exp | 5 - test/CodeGen/CBackend/fneg.ll | 7 - test/CodeGen/CBackend/pr2408.ll | 12 - test/CodeGen/CBackend/vectors.ll | 37 - test/CodeGen/CPP/2012-02-05-UnitVarCrash.ll | 6 + test/CodeGen/CPP/dg.exp | 5 - test/CodeGen/CPP/lit.local.cfg | 6 + test/CodeGen/CellSPU/and_ops.ll | 3 + test/CodeGen/CellSPU/call.ll | 4 - test/CodeGen/CellSPU/call_indirect.ll | 49 - test/CodeGen/CellSPU/dg.exp | 5 - test/CodeGen/CellSPU/lit.local.cfg | 6 + test/CodeGen/CellSPU/nand.ll | 4 + test/CodeGen/CellSPU/or_ops.ll | 3 + test/CodeGen/CellSPU/rotate_ops.ll | 2 +- test/CodeGen/CellSPU/select_bits.ll | 3 + test/CodeGen/CellSPU/shift_ops.ll | 12 +- test/CodeGen/CellSPU/shuffles.ll | 12 +- test/CodeGen/CellSPU/struct_1.ll | 3 + test/CodeGen/CellSPU/v2i32.ll | 20 +- test/CodeGen/Generic/2007-12-31-UnusedSelector.ll | 2 - test/CodeGen/Generic/2008-02-04-Ctlz.ll | 8 +- test/CodeGen/Generic/2009-11-16-BadKillsCrash.ll | 2 - test/CodeGen/Generic/bool-vector.ll | 11 - test/CodeGen/Generic/dbg-declare.ll | 59 + test/CodeGen/Generic/dg.exp | 3 - test/CodeGen/Generic/lit.local.cfg | 1 + test/CodeGen/Generic/llvm-ct-intrinsics.ll | 32 +- test/CodeGen/Generic/pr12507.ll | 18 + test/CodeGen/Generic/select.ll | 8 + test/CodeGen/Hexagon/args.ll | 19 + test/CodeGen/Hexagon/combine.ll | 18 + test/CodeGen/Hexagon/double.ll | 23 + test/CodeGen/Hexagon/float.ll | 23 + test/CodeGen/Hexagon/frame.ll | 24 + test/CodeGen/Hexagon/lit.local.cfg | 6 + test/CodeGen/Hexagon/mpy.ll | 20 + test/CodeGen/Hexagon/static.ll | 21 + test/CodeGen/Hexagon/struct_args.ll | 16 + test/CodeGen/Hexagon/struct_args_large.ll | 17 + test/CodeGen/Hexagon/vaddh.ll | 17 + test/CodeGen/MBlaze/cc.ll | 12 +- test/CodeGen/MBlaze/dg.exp | 5 - test/CodeGen/MBlaze/div.ll | 18 +- test/CodeGen/MBlaze/lit.local.cfg | 6 + test/CodeGen/MSP430/2009-05-10-CyclicDAG.ll | 4 +- .../CodeGen/MSP430/2009-08-25-DynamicStackAlloc.ll | 8 +- test/CodeGen/MSP430/2009-09-18-AbsoluteAddr.ll | 4 +- test/CodeGen/MSP430/2009-10-10-OrImpDef.ll | 4 +- test/CodeGen/MSP430/AddrMode-bis-rx.ll | 2 +- test/CodeGen/MSP430/AddrMode-bis-xr.ll | 4 +- test/CodeGen/MSP430/AddrMode-mov-rx.ll | 2 +- test/CodeGen/MSP430/AddrMode-mov-xr.ll | 2 +- test/CodeGen/MSP430/Inst16mm.ll | 2 +- test/CodeGen/MSP430/dg.exp | 5 - test/CodeGen/MSP430/indirectbr2.ll | 2 +- test/CodeGen/MSP430/lit.local.cfg | 6 + test/CodeGen/Mips/2008-06-05-Carry.ll | 19 +- test/CodeGen/Mips/2008-07-03-SRet.ll | 23 +- test/CodeGen/Mips/2008-07-07-Float2Int.ll | 17 +- test/CodeGen/Mips/2008-07-16-SignExtInReg.ll | 12 +- test/CodeGen/Mips/2008-07-22-Cstpool.ll | 17 +- test/CodeGen/Mips/2008-08-01-AsmInline.ll | 58 +- test/CodeGen/Mips/2008-08-04-Bitconvert.ll | 17 +- test/CodeGen/Mips/2008-08-06-Alloca.ll | 20 +- test/CodeGen/Mips/2008-08-08-ctlz.ll | 10 +- test/CodeGen/Mips/2008-11-10-xint_to_fp.ll | 3 +- test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll | 23 +- test/CodeGen/Mips/2010-07-20-Switch.ll | 46 +- test/CodeGen/Mips/2010-11-09-CountLeading.ll | 10 +- test/CodeGen/Mips/blockaddr.ll | 40 +- test/CodeGen/Mips/br-jmp.ll | 13 + test/CodeGen/Mips/bswap.ll | 25 + test/CodeGen/Mips/cmov.ll | 23 +- test/CodeGen/Mips/cprestore.ll | 8 +- test/CodeGen/Mips/dg.exp | 5 - test/CodeGen/Mips/eh.ll | 10 - test/CodeGen/Mips/extins.ll | 2 +- test/CodeGen/Mips/fabs.ll | 52 + test/CodeGen/Mips/fcopysign-f32-f64.ll | 50 + test/CodeGen/Mips/fcopysign.ll | 80 +- test/CodeGen/Mips/fmadd1.ll | 88 ++ test/CodeGen/Mips/fneg.ll | 17 + test/CodeGen/Mips/fp-indexed-ls.ll | 98 ++ test/CodeGen/Mips/fpcmp.ll | 18 - test/CodeGen/Mips/frem.ll | 13 + test/CodeGen/Mips/global-address.ll | 46 + test/CodeGen/Mips/global-pointer-reg.ll | 22 + test/CodeGen/Mips/i64arg.ll | 8 +- test/CodeGen/Mips/imm.ll | 38 + test/CodeGen/Mips/indirectcall.ll | 8 + test/CodeGen/Mips/inlineasm64.ll | 17 + test/CodeGen/Mips/inlineasmmemop.ll | 2 +- test/CodeGen/Mips/largeimmprinting.ll | 10 +- test/CodeGen/Mips/lit.local.cfg | 6 + test/CodeGen/Mips/mips64-fp-indexed-ls.ll | 110 ++ test/CodeGen/Mips/mips64countleading.ll | 19 + test/CodeGen/Mips/mips64directive.ll | 11 + test/CodeGen/Mips/mips64ext.ll | 26 + test/CodeGen/Mips/mips64extins.ll | 55 + test/CodeGen/Mips/mips64fpimm0.ll | 7 + test/CodeGen/Mips/mips64fpldst.ll | 12 +- test/CodeGen/Mips/mips64imm.ll | 52 + test/CodeGen/Mips/mips64instrs.ll | 8 +- test/CodeGen/Mips/mips64intldst.ll | 26 +- test/CodeGen/Mips/mips64lea.ll | 12 + test/CodeGen/Mips/mips64muldiv.ll | 49 + test/CodeGen/Mips/mips64shift.ll | 8 +- test/CodeGen/Mips/mipslopat.ll | 2 +- test/CodeGen/Mips/o32_cc_byval.ll | 54 +- test/CodeGen/Mips/private.ll | 19 +- test/CodeGen/Mips/rotate.ll | 2 +- test/CodeGen/Mips/swzero.ll | 19 + test/CodeGen/Mips/tls.ll | 27 +- test/CodeGen/Mips/unalignedload.ll | 14 +- test/CodeGen/Mips/zeroreg.ll | 27 + test/CodeGen/PTX/cvt.ll | 12 +- test/CodeGen/PTX/dg.exp | 5 - test/CodeGen/PTX/ld.ll | 30 +- test/CodeGen/PTX/lit.local.cfg | 6 + test/CodeGen/PTX/mad-disabling.ll | 12 +- test/CodeGen/PTX/mov.ll | 10 +- test/CodeGen/PTX/parameter-order.ll | 2 +- test/CodeGen/PTX/printf.ll | 25 + test/CodeGen/PTX/st.ll | 30 +- .../PowerPC/2006-10-11-combiner-aa-regression.ll | 23 - test/CodeGen/PowerPC/2007-03-24-cntlzd.ll | 4 +- .../PowerPC/2008-03-05-RegScavengerAssert.ll | 2 +- .../PowerPC/2008-03-17-RegScavengerCrash.ll | 2 +- .../PowerPC/2008-03-18-RegScavengerAssert.ll | 2 +- test/CodeGen/PowerPC/2008-04-23-CoalescerCrash.ll | 6 +- test/CodeGen/PowerPC/2010-02-12-saveCR.ll | 22 +- test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll | 191 +++ .../PowerPC/2011-12-06-SpillAndRestoreCR.ll | 225 ++++ .../PowerPC/2011-12-08-DemandedBitsMiscompile.ll | 16 + test/CodeGen/PowerPC/Frames-alloca.ll | 6 +- test/CodeGen/PowerPC/Frames-large.ll | 11 +- test/CodeGen/PowerPC/LargeAbsoluteAddr.ll | 6 +- test/CodeGen/PowerPC/a2-fp-basic.ll | 33 + test/CodeGen/PowerPC/big-endian-formal-args.ll | 2 +- test/CodeGen/PowerPC/bl8_elf_nop.ll | 16 + test/CodeGen/PowerPC/can-lower-ret.ll | 19 + test/CodeGen/PowerPC/cttz.ll | 4 +- test/CodeGen/PowerPC/dbg.ll | 40 + test/CodeGen/PowerPC/dg.exp | 5 - test/CodeGen/PowerPC/indirectbr.ll | 14 +- test/CodeGen/PowerPC/lit.local.cfg | 6 + test/CodeGen/PowerPC/ppc32-vaarg.ll | 167 --- test/CodeGen/PowerPC/ppc440-fp-basic.ll | 33 + test/CodeGen/PowerPC/ppc440-msync.ll | 27 + test/CodeGen/PowerPC/ppc64-ind-call.ll | 16 + test/CodeGen/PowerPC/ppc64-linux-func-size.ll | 21 + test/CodeGen/PowerPC/ppc64-prefetch.ll | 15 + test/CodeGen/PowerPC/ppc64-vaarg-int.ll | 20 + test/CodeGen/SPARC/2011-12-03-TailDuplication.ll | 25 + test/CodeGen/SPARC/dg.exp | 5 - test/CodeGen/SPARC/lit.local.cfg | 6 + test/CodeGen/SystemZ/00-RetVoid.ll | 6 - test/CodeGen/SystemZ/01-RetArg.ll | 6 - test/CodeGen/SystemZ/01-RetImm.ll | 49 - test/CodeGen/SystemZ/02-MemArith.ll | 133 -- test/CodeGen/SystemZ/02-RetAdd.ll | 6 - test/CodeGen/SystemZ/02-RetAddImm.ll | 6 - test/CodeGen/SystemZ/02-RetAnd.ll | 7 - test/CodeGen/SystemZ/02-RetAndImm.ll | 28 - test/CodeGen/SystemZ/02-RetNeg.ll | 7 - test/CodeGen/SystemZ/02-RetOr.ll | 6 - test/CodeGen/SystemZ/02-RetOrImm.ll | 28 - test/CodeGen/SystemZ/02-RetSub.ll | 7 - test/CodeGen/SystemZ/02-RetSubImm.ll | 7 - test/CodeGen/SystemZ/02-RetXor.ll | 6 - test/CodeGen/SystemZ/02-RetXorImm.ll | 6 - test/CodeGen/SystemZ/03-RetAddImmSubreg.ll | 42 - test/CodeGen/SystemZ/03-RetAddSubreg.ll | 22 - test/CodeGen/SystemZ/03-RetAndImmSubreg.ll | 38 - test/CodeGen/SystemZ/03-RetAndSubreg.ll | 21 - test/CodeGen/SystemZ/03-RetArgSubreg.ll | 19 - test/CodeGen/SystemZ/03-RetImmSubreg.ll | 42 - test/CodeGen/SystemZ/03-RetNegImmSubreg.ll | 8 - test/CodeGen/SystemZ/03-RetOrImmSubreg.ll | 60 - test/CodeGen/SystemZ/03-RetOrSubreg.ll | 23 - test/CodeGen/SystemZ/03-RetSubImmSubreg.ll | 42 - test/CodeGen/SystemZ/03-RetSubSubreg.ll | 22 - test/CodeGen/SystemZ/03-RetXorImmSubreg.ll | 58 - test/CodeGen/SystemZ/03-RetXorSubreg.ll | 23 - test/CodeGen/SystemZ/04-RetShifts.ll | 121 -- test/CodeGen/SystemZ/05-LoadAddr.ll | 11 - test/CodeGen/SystemZ/05-MemImmStores.ll | 50 - test/CodeGen/SystemZ/05-MemLoadsStores.ll | 44 - test/CodeGen/SystemZ/05-MemLoadsStores16.ll | 85 -- test/CodeGen/SystemZ/05-MemRegLoads.ll | 75 -- test/CodeGen/SystemZ/05-MemRegStores.ll | 79 -- test/CodeGen/SystemZ/06-CallViaStack.ll | 17 - test/CodeGen/SystemZ/06-FrameIdxLoad.ll | 16 - test/CodeGen/SystemZ/06-LocalFrame.ll | 13 - test/CodeGen/SystemZ/06-SimpleCall.ll | 12 - test/CodeGen/SystemZ/07-BrCond.ll | 141 -- test/CodeGen/SystemZ/07-BrCond32.ll | 142 -- test/CodeGen/SystemZ/07-BrUnCond.ll | 18 - test/CodeGen/SystemZ/07-CmpImm.ll | 137 -- test/CodeGen/SystemZ/07-CmpImm32.ll | 139 -- test/CodeGen/SystemZ/07-SelectCC.ll | 11 - test/CodeGen/SystemZ/08-DivRem.ll | 55 - test/CodeGen/SystemZ/08-DivRemMemOp.ll | 64 - test/CodeGen/SystemZ/08-SimpleMuls.ll | 29 - test/CodeGen/SystemZ/09-DynamicAlloca.ll | 14 - test/CodeGen/SystemZ/09-Globals.ll | 23 - test/CodeGen/SystemZ/09-Switches.ll | 39 - test/CodeGen/SystemZ/10-FuncsPic.ll | 27 - test/CodeGen/SystemZ/10-GlobalsPic.ll | 29 - test/CodeGen/SystemZ/11-BSwap.ll | 74 -- .../CodeGen/SystemZ/2009-05-29-InvalidRetResult.ll | 12 - test/CodeGen/SystemZ/2009-06-02-And32Imm.ll | 14 - test/CodeGen/SystemZ/2009-06-02-Rotate.ll | 13 - test/CodeGen/SystemZ/2009-06-05-InvalidArgLoad.ll | 19 - test/CodeGen/SystemZ/2009-07-04-Shl32.ll | 27 - test/CodeGen/SystemZ/2009-07-05-Shifts.ll | 25 - .../SystemZ/2009-07-10-BadIncomingArgOffset.ll | 25 - test/CodeGen/SystemZ/2009-07-11-FloatBitConvert.ll | 16 - test/CodeGen/SystemZ/2009-07-11-InvalidRIISel.ll | 32 - .../SystemZ/2009-08-21-InlineAsmRConstraint.ll | 21 - test/CodeGen/SystemZ/2009-08-22-FCopySign.ll | 22 - test/CodeGen/SystemZ/2010-01-04-DivMem.ll | 50 - .../SystemZ/2010-04-07-DbgValueOtherTargets.ll | 28 - test/CodeGen/SystemZ/dg.exp | 5 - test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll | 6 +- test/CodeGen/Thumb/dg.exp | 5 - test/CodeGen/Thumb/large-stack.ll | 2 +- test/CodeGen/Thumb/lit.local.cfg | 6 + test/CodeGen/Thumb/vargs.ll | 4 +- test/CodeGen/Thumb2/2009-07-21-ISelBug.ll | 2 +- test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll | 2 +- test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll | 4 +- test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll | 2 +- test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll | 2 +- .../Thumb2/2011-12-16-T2SizeReduceAssert.ll | 28 + test/CodeGen/Thumb2/2012-01-13-CBNZBug.ll | 103 ++ test/CodeGen/Thumb2/aligned-constants.ll | 26 + test/CodeGen/Thumb2/aligned-spill.ll | 95 ++ test/CodeGen/Thumb2/constant-islands.ll | 1400 ++++++++++++++++++++ test/CodeGen/Thumb2/crash.ll | 31 +- test/CodeGen/Thumb2/dg.exp | 5 - test/CodeGen/Thumb2/large-call.ll | 29 + test/CodeGen/Thumb2/ldr-str-imm12.ll | 10 +- test/CodeGen/Thumb2/lit.local.cfg | 6 + test/CodeGen/Thumb2/lsr-deficiency.ll | 11 +- test/CodeGen/Thumb2/machine-licm.ll | 7 +- test/CodeGen/Thumb2/thumb2-cbnz.ll | 5 +- test/CodeGen/Thumb2/thumb2-clz.ll | 4 +- test/CodeGen/Thumb2/thumb2-ifcvt2.ll | 2 +- test/CodeGen/Thumb2/thumb2-ldm.ll | 2 +- test/CodeGen/Thumb2/thumb2-ldrd.ll | 5 +- test/CodeGen/Thumb2/thumb2-mls.ll | 2 +- test/CodeGen/Thumb2/thumb2-mul.ll | 2 +- test/CodeGen/Thumb2/thumb2-select_xform.ll | 2 +- test/CodeGen/X86/2004-04-09-SameValueCoalescing.ll | 13 - test/CodeGen/X86/2006-05-11-InstrSched.ll | 6 +- test/CodeGen/X86/2007-01-08-InstrSched.ll | 2 +- test/CodeGen/X86/2007-05-05-Personality.ll | 14 +- test/CodeGen/X86/2007-11-06-InstrSched.ll | 2 +- test/CodeGen/X86/2007-12-18-LoadCSEBug.ll | 2 +- test/CodeGen/X86/2008-01-16-Trampoline.ll | 14 - test/CodeGen/X86/2008-02-22-ReMatBug.ll | 49 - test/CodeGen/X86/2008-03-18-CoalescerBug.ll | 51 - test/CodeGen/X86/2008-05-21-CoalescerBug.ll | 2 +- test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll | 2 - .../CodeGen/X86/2008-06-13-NotVolatileLoadStore.ll | 2 +- test/CodeGen/X86/2008-06-13-VolatileLoadStore.ll | 10 +- test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll | 4 +- test/CodeGen/X86/2008-09-05-sinttofp-2xi32.ll | 4 +- test/CodeGen/X86/2008-09-18-inline-asm-2.ll | 1 - test/CodeGen/X86/2008-09-29-VolatileBug.ll | 2 +- test/CodeGen/X86/2008-12-16-BadShift.ll | 19 - test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll | 2 +- test/CodeGen/X86/2009-01-31-BigShift2.ll | 2 +- test/CodeGen/X86/2009-02-05-CoalescerBug.ll | 14 - test/CodeGen/X86/2009-03-16-SpillerBug.ll | 167 --- test/CodeGen/X86/2009-03-23-MultiUseSched.ll | 50 +- test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll | 3 +- test/CodeGen/X86/2009-05-11-tailmerge-crash.ll | 2 +- test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll | 2 +- test/CodeGen/X86/2009-06-05-VZextByteShort.ll | 2 +- test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll | 2 +- test/CodeGen/X86/2009-07-17-StackColoringBug.ll | 55 - test/CodeGen/X86/2009-08-23-SubRegReuseUndo.ll | 6 +- test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll | 2 +- test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll | 12 +- .../X86/2010-04-30-LocalAlloc-LandingPad.ll | 21 +- .../X86/2010-05-03-CoalescerSubRegClobber.ll | 2 +- test/CodeGen/X86/2010-06-28-DbgEntryPC.ll | 108 -- test/CodeGen/X86/2010-08-04-MingWCrash.ll | 13 +- test/CodeGen/X86/2010-08-10-DbgConstant.ll | 4 +- test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll | 3 +- test/CodeGen/X86/2011-08-29-InitOrder.ll | 30 +- .../X86/2011-10-18-FastISel-VectorParams.ll | 29 + test/CodeGen/X86/2011-10-19-LegelizeLoad.ll | 28 + test/CodeGen/X86/2011-10-19-widen_vselect.ll | 68 + test/CodeGen/X86/2011-10-21-widen-cmp.ll | 45 + test/CodeGen/X86/2011-10-27-tstore.ll | 16 + test/CodeGen/X86/2011-10-30-padd.ll | 20 + test/CodeGen/X86/2011-11-07-LegalizeBuildVector.ll | 14 + test/CodeGen/X86/2011-11-22-AVX2-Domains.ll | 99 ++ test/CodeGen/X86/2011-11-30-or.ll | 25 + .../X86/2011-12-06-AVXVectorExtractCombine.ll | 18 + test/CodeGen/X86/2011-12-06-BitcastVectorGlobal.ll | 5 + test/CodeGen/X86/2011-12-08-AVXISelBugs.ll | 80 ++ test/CodeGen/X86/2011-12-15-vec_shift.ll | 19 + .../2011-12-26-extractelement-duplicate-load.ll | 16 + test/CodeGen/X86/2011-12-28-vselecti8.ll | 20 + test/CodeGen/X86/2011-12-8-bitcastintprom.ll | 15 + test/CodeGen/X86/2011-20-21-zext-ui2fp.ll | 19 + test/CodeGen/X86/2012-01-10-UndefExceptionEdge.ll | 155 +++ test/CodeGen/X86/2012-01-11-split-cv.ll | 12 + test/CodeGen/X86/2012-01-12-extract-sv.ll | 12 + test/CodeGen/X86/2012-01-16-mfence-nosse-flags.ll | 34 + test/CodeGen/X86/2012-01-18-vbitcast.ll | 14 + test/CodeGen/X86/2012-02-12-dagco.ll | 16 + test/CodeGen/X86/2012-02-14-scalar.ll | 13 + test/CodeGen/X86/2012-02-20-MachineCPBug.ll | 78 ++ test/CodeGen/X86/2012-02-23-mmx-inlineasm.ll | 12 + test/CodeGen/X86/2012-02-29-CoalescerBug.ll | 58 + test/CodeGen/X86/2012-03-15-build_vector_wl.ll | 10 + test/CodeGen/X86/2012-03-20-LargeConstantExpr.ll | 17 + test/CodeGen/X86/2012-03-26-PostRALICMBug.ll | 59 + test/CodeGen/X86/2012-04-09-TwoAddrPassBug.ll | 34 + test/CodeGen/X86/2012-1-10-buildvector.ll | 26 + test/CodeGen/X86/GC/dg.exp | 5 - test/CodeGen/X86/GC/lit.local.cfg | 6 + test/CodeGen/X86/SwizzleShuff.ll | 68 + test/CodeGen/X86/abi-isel.ll | 20 +- test/CodeGen/X86/add.ll | 6 +- test/CodeGen/X86/apm.ll | 4 +- test/CodeGen/X86/atom-lea-sp.ll | 48 + test/CodeGen/X86/atom-sched.ll | 28 + test/CodeGen/X86/avx-arith.ll | 11 + test/CodeGen/X86/avx-basic.ll | 18 +- test/CodeGen/X86/avx-cast.ll | 2 +- test/CodeGen/X86/avx-cvt.ll | 2 +- test/CodeGen/X86/avx-fp2int.ll | 19 + test/CodeGen/X86/avx-intrinsics-x86.ll | 389 +++--- test/CodeGen/X86/avx-load-store.ll | 12 +- test/CodeGen/X86/avx-logic.ll | 40 +- test/CodeGen/X86/avx-minmax.ll | 8 +- test/CodeGen/X86/avx-sext.ll | 17 + test/CodeGen/X86/avx-shift.ll | 63 + test/CodeGen/X86/avx-shuffle-x86_32.ll | 8 + test/CodeGen/X86/avx-shuffle.ll | 196 ++- test/CodeGen/X86/avx-splat.ll | 4 +- test/CodeGen/X86/avx-trunc.ll | 15 + test/CodeGen/X86/avx-unpack.ll | 72 + test/CodeGen/X86/avx-varargs-x86_64.ll | 15 + test/CodeGen/X86/avx-vbroadcast.ll | 32 +- test/CodeGen/X86/avx-vextractf128.ll | 88 ++ test/CodeGen/X86/avx-vinsertf128.ll | 73 + test/CodeGen/X86/avx-vperm2f128.ll | 9 +- test/CodeGen/X86/avx-vpermil.ll | 11 +- test/CodeGen/X86/avx-vshufp.ll | 128 ++ test/CodeGen/X86/avx-vzeroupper.ll | 83 +- test/CodeGen/X86/avx-win64-args.ll | 18 + test/CodeGen/X86/avx-win64.ll | 47 + test/CodeGen/X86/avx-zext.ll | 30 + test/CodeGen/X86/avx2-arith.ll | 76 ++ test/CodeGen/X86/avx2-cmp.ll | 58 + test/CodeGen/X86/avx2-intrinsics-x86.ll | 994 ++++++++++++++ test/CodeGen/X86/avx2-logic.ll | 96 ++ test/CodeGen/X86/avx2-nontemporal.ll | 22 + test/CodeGen/X86/avx2-palignr.ll | 57 + test/CodeGen/X86/avx2-phaddsub.ll | 73 + test/CodeGen/X86/avx2-shift.ll | 268 ++++ test/CodeGen/X86/avx2-unpack.ll | 86 ++ test/CodeGen/X86/avx2-vbroadcast.ll | 187 +++ test/CodeGen/X86/avx2-vperm2i128.ll | 47 + test/CodeGen/X86/bc-extract.ll | 2 +- test/CodeGen/X86/blend-msb.ll | 37 + test/CodeGen/X86/block-placement.ll | 930 +++++++++++++ test/CodeGen/X86/bmi.ll | 184 ++- test/CodeGen/X86/brcond.ll | 4 +- test/CodeGen/X86/btq.ll | 35 + test/CodeGen/X86/byval6.ll | 2 +- test/CodeGen/X86/cfstring.ll | 36 + test/CodeGen/X86/change-compare-stride-0.ll | 83 -- test/CodeGen/X86/change-compare-stride-1.ll | 4 + test/CodeGen/X86/clz.ll | 145 +- test/CodeGen/X86/cmov.ll | 4 +- test/CodeGen/X86/cmpxchg16b.ll | 2 +- test/CodeGen/X86/coalescer-commute1.ll | 2 +- test/CodeGen/X86/crash.ll | 6 +- test/CodeGen/X86/dbg-file-name.ll | 4 +- test/CodeGen/X86/dbg-inline.ll | 140 -- test/CodeGen/X86/dbg-merge-loc-entry.ll | 2 +- test/CodeGen/X86/dbg-subrange.ll | 37 + test/CodeGen/X86/dbg-value-inlined-parameter.ll | 2 +- test/CodeGen/X86/dbg-value-location.ll | 3 +- test/CodeGen/X86/dg.exp | 5 - test/CodeGen/X86/divide-by-constant.ll | 2 +- test/CodeGen/X86/dwarf-comp-dir.ll | 16 + test/CodeGen/X86/empty-functions.ll | 4 - test/CodeGen/X86/epilogue.ll | 4 +- test/CodeGen/X86/f16c-intrinsics.ll | 32 + test/CodeGen/X86/fast-cc-merge-stack-adj.ll | 2 +- test/CodeGen/X86/fast-isel-bc.ll | 2 +- test/CodeGen/X86/fast-isel-gep.ll | 5 +- test/CodeGen/X86/fast-isel-x86-64.ll | 16 +- test/CodeGen/X86/fast-isel-x86.ll | 2 +- test/CodeGen/X86/fast-isel.ll | 11 +- test/CodeGen/X86/fdiv.ll | 41 + test/CodeGen/X86/fltused.ll | 2 + test/CodeGen/X86/fltused_function_pointer.ll | 19 + test/CodeGen/X86/fma4-intrinsics-x86_64.ll | 295 +++++ test/CodeGen/X86/fold-and-shift.ll | 82 +- test/CodeGen/X86/fold-load.ll | 2 +- test/CodeGen/X86/fold-pcmpeqd-0.ll | 4 +- test/CodeGen/X86/fold-pcmpeqd-2.ll | 11 +- test/CodeGen/X86/fp-stack-O0.ll | 2 +- test/CodeGen/X86/fp-stack-ret-conv.ll | 2 +- test/CodeGen/X86/fsgsbase.ll | 57 + test/CodeGen/X86/gcc_except_table.ll | 27 + test/CodeGen/X86/haddsub.ll | 91 ++ test/CodeGen/X86/hoist-invariant-load.ll | 29 + test/CodeGen/X86/i128-sdiv.ll | 24 + test/CodeGen/X86/inline-asm-fpstack.ll | 2 +- test/CodeGen/X86/inline-asm-q-regs.ll | 17 +- test/CodeGen/X86/inline-asm-tied.ll | 4 +- test/CodeGen/X86/iv-users-in-other-loops.ll | 300 ----- test/CodeGen/X86/jump_sign.ll | 16 +- test/CodeGen/X86/legalize-libcalls.ll | 35 + test/CodeGen/X86/legalize-shift-64.ll | 56 + test/CodeGen/X86/lit.local.cfg | 6 + test/CodeGen/X86/log2_not_readnone.ll | 15 + test/CodeGen/X86/loop-strength-reduce3.ll | 37 - test/CodeGen/X86/loop-strength-reduce5.ll | 4 +- test/CodeGen/X86/lsr-loop-exit-cond.ll | 45 +- test/CodeGen/X86/lsr-nonaffine.ll | 2 +- test/CodeGen/X86/lsr-reuse.ll | 1 + test/CodeGen/X86/lsr-sort.ll | 2 +- test/CodeGen/X86/lzcnt.ll | 56 +- test/CodeGen/X86/machine-cp.ll | 36 + test/CodeGen/X86/machine-cse.ll | 24 +- test/CodeGen/X86/masked-iv-safe.ll | 6 +- test/CodeGen/X86/mcinst-avx-lowering.ll | 19 + test/CodeGen/X86/memcpy.ll | 13 + test/CodeGen/X86/misched-new.ll | 27 + test/CodeGen/X86/mmx-builtins.ll | 1 + test/CodeGen/X86/mmx-pinsrw.ll | 2 +- test/CodeGen/X86/mmx-vzmovl-2.ll | 29 - test/CodeGen/X86/mmx-vzmovl.ll | 15 - test/CodeGen/X86/movmsk.ll | 16 + test/CodeGen/X86/multiple-loop-post-inc.ll | 4 + test/CodeGen/X86/nancvt.ll | 12 +- test/CodeGen/X86/narrow-shl-load.ll | 2 +- test/CodeGen/X86/negate-add-zero.ll | 4 - test/CodeGen/X86/no-cfi.ll | 8 +- test/CodeGen/X86/nontemporal.ll | 9 +- test/CodeGen/X86/null-streamer.ll | 11 + test/CodeGen/X86/objc-gc-module-flags.ll | 13 + test/CodeGen/X86/object-size.ll | 6 +- test/CodeGen/X86/odr_comdat.ll | 16 + test/CodeGen/X86/optimize-max-3.ll | 4 +- test/CodeGen/X86/overlap-shift.ll | 2 +- test/CodeGen/X86/peep-test-3.ll | 2 +- test/CodeGen/X86/peep-vector-extract-insert.ll | 2 +- test/CodeGen/X86/personality_size.ll | 28 + test/CodeGen/X86/phaddsub.ll | 170 +++ test/CodeGen/X86/pic.ll | 2 +- test/CodeGen/X86/pointer-vector.ll | 138 ++ test/CodeGen/X86/pr11202.ll | 19 + test/CodeGen/X86/pr11415.ll | 23 + test/CodeGen/X86/pr12360.ll | 46 + test/CodeGen/X86/pr1505b.ll | 4 +- test/CodeGen/X86/pr2182.ll | 16 +- test/CodeGen/X86/pr3495-2.ll | 54 - test/CodeGen/X86/pr3495.ll | 81 -- test/CodeGen/X86/prefetch.ll | 3 + test/CodeGen/X86/promote.ll | 42 + test/CodeGen/X86/rd-mod-wr-eflags.ll | 179 +++ test/CodeGen/X86/red-zone.ll | 2 +- test/CodeGen/X86/red-zone2.ll | 2 +- test/CodeGen/X86/reghinting.ll | 2 +- test/CodeGen/X86/remat-scalar-zero.ll | 1 + test/CodeGen/X86/rounding-ops.ll | 132 ++ test/CodeGen/X86/scalar_widen_div.ll | 38 +- test/CodeGen/X86/segmented-stacks-dynamic.ll | 64 + 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100644 test/CodeGen/XCore/global_negative_offset.ll create mode 100644 test/CodeGen/XCore/lit.local.cfg delete mode 100644 test/CodeGen/XCore/log.ll delete mode 100644 test/CodeGen/XCore/log10.ll delete mode 100644 test/CodeGen/XCore/log2.ll delete mode 100644 test/CodeGen/XCore/pow.ll delete mode 100644 test/CodeGen/XCore/powi.ll delete mode 100644 test/CodeGen/XCore/sin.ll delete mode 100644 test/CodeGen/XCore/sqrt.ll (limited to 'test/CodeGen') diff --git a/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll b/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll index 3694aaa..0bfe331 100644 --- a/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll +++ b/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2 | FileCheck %s +; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+v6,+vfp2 | FileCheck %s @quant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1] @dequant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1] diff --git a/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll b/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll index 78c6222..94c562b 100644 --- a/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll +++ b/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll @@ -11,7 +11,7 @@ bb74.i: ; preds = %bb88.i, %bb74.i, %entry bb88.i: ; preds = %bb74.i br i1 false, label %mandel.exit, label %bb74.i mandel.exit: ; preds = %bb88.i - %tmp2 = volatile load double* getelementptr ({ double, double }* @accum, i32 0, i32 0), align 8 ; [#uses=1] + %tmp2 = load volatile double* getelementptr ({ double, double }* @accum, i32 0, i32 0), align 8 ; [#uses=1] %tmp23 = fptosi double %tmp2 to i32 ; [#uses=1] %tmp5 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i32 %tmp23 ) ; [#uses=0] ret i32 0 diff --git a/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll b/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll index 8bde748..a016809 100644 --- a/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll +++ b/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll @@ -37,10 +37,11 @@ return: ; preds = %invcont ret void lpad: ; preds = %entry - %eh_ptr = call i8* @llvm.eh.exception() + %exn = landingpad {i8*, i32} personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) + cleanup + %eh_ptr = extractvalue {i8*, i32} %exn, 0 store i8* %eh_ptr, i8** %eh_exception - %eh_ptr1 = load i8** %eh_exception - %eh_select2 = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %eh_ptr1, i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*), i32 0) + %eh_select2 = extractvalue {i8*, i32} %exn, 1 store i32 %eh_select2, i32* %eh_selector br label %ppad @@ -94,10 +95,6 @@ declare void @_ZdlPv(i8*) nounwind declare void @_Z3barv() -declare i8* @llvm.eh.exception() nounwind readonly - -declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind - declare i32 @llvm.eh.typeid.for(i8*) nounwind declare i32 @__gxx_personality_sj0(...) diff --git a/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll b/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll index 0a157c9..426bd17 100644 --- a/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll +++ b/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll @@ -9,7 +9,7 @@ define void @test(double* %x, double* %y) nounwind { br i1 %4, label %bb1, label %bb2 bb1: -;CHECK: vstrhi.64 +;CHECK: vstrhi store double %1, double* %y br label %bb2 diff --git a/test/CodeGen/ARM/2009-09-24-spill-align.ll b/test/CodeGen/ARM/2009-09-24-spill-align.ll index 8bfd026..eb9c2d0 100644 --- a/test/CodeGen/ARM/2009-09-24-spill-align.ll +++ b/test/CodeGen/ARM/2009-09-24-spill-align.ll @@ -6,7 +6,7 @@ entry: %arg0_poly16x4_t = alloca <4 x i16> ; <<4 x i16>*> [#uses=1] %out_poly16_t = alloca i16 ; [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] -; CHECK: vldr.64 +; CHECK: vldr %0 = load <4 x i16>* %arg0_poly16x4_t, align 8 ; <<4 x i16>> [#uses=1] %1 = extractelement <4 x i16> %0, i32 1 ; [#uses=1] store i16 %1, i16* %out_poly16_t, align 2 diff --git a/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll b/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll index 7aae3ac..a8afc20 100644 --- a/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll +++ b/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=cortex-a8 < %s | FileCheck %s +; RUN: llc -mcpu=cortex-a8 -mattr=-neonfp < %s | FileCheck %s ; PR5423 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" diff --git a/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll b/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll index df9dbca..0ae7f84 100644 --- a/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll +++ b/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll @@ -11,7 +11,7 @@ entry: ; THUMB: t: ; THUMB-NOT: str r0, [r1], r0 -; THUMB: str r2, [r1] +; THUMB: str r1, [r0] %0 = getelementptr inbounds %struct.foo* %this, i32 0, i32 1 ; [#uses=1] store i32 0, i32* inttoptr (i32 8 to i32*), align 8 br i1 undef, label %bb.nph96, label %bb3 diff --git a/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll b/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll index e47c038..e0f50c9 100644 --- a/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll +++ b/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon -O0 -regalloc=linearscan +; RUN: llc < %s -march=arm -mattr=+neon -O0 -optimize-regalloc -regalloc=basic ; This test would crash the rewriter when trying to handle a spill after one of ; the @llvm.arm.neon.vld3.v8i8 defined three parts of a register. diff --git a/test/CodeGen/ARM/2010-05-21-BuildVector.ll b/test/CodeGen/ARM/2010-05-21-BuildVector.ll index cd1c9c8..a400b7b 100644 --- a/test/CodeGen/ARM/2010-05-21-BuildVector.ll +++ b/test/CodeGen/ARM/2010-05-21-BuildVector.ll @@ -10,28 +10,28 @@ entry: %4 = ashr i32 %3, 30 %.sum = add i32 %4, 4 %5 = getelementptr inbounds float* %table, i32 %.sum -;CHECK: vldr.32 s +;CHECK: vldr s %6 = load float* %5, align 4 %tmp11 = insertelement <4 x float> undef, float %6, i32 0 %7 = shl i32 %packedValue, 18 %8 = ashr i32 %7, 30 %.sum12 = add i32 %8, 4 %9 = getelementptr inbounds float* %table, i32 %.sum12 -;CHECK: vldr.32 s +;CHECK: vldr s %10 = load float* %9, align 4 %tmp9 = insertelement <4 x float> %tmp11, float %10, i32 1 %11 = shl i32 %packedValue, 20 %12 = ashr i32 %11, 30 %.sum13 = add i32 %12, 4 %13 = getelementptr inbounds float* %table, i32 %.sum13 -;CHECK: vldr.32 s +;CHECK: vldr s %14 = load float* %13, align 4 %tmp7 = insertelement <4 x float> %tmp9, float %14, i32 2 %15 = shl i32 %packedValue, 22 %16 = ashr i32 %15, 30 %.sum14 = add i32 %16, 4 %17 = getelementptr inbounds float* %table, i32 %.sum14 -;CHECK: vldr.32 s +;CHECK: vldr s %18 = load float* %17, align 4 %tmp5 = insertelement <4 x float> %tmp7, float %18, i32 3 %19 = fmul <4 x float> %tmp5, %2 diff --git a/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll b/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll index b9d5600..1aee508 100644 --- a/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll +++ b/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll @@ -12,7 +12,7 @@ target triple = "thumbv7-apple-darwin10" ; CHECK: vld1.64 {d16, d17}, [r{{.}}] ; CHECK-NOT: vld1.64 {d16, d17} -; CHECK: vmov.f64 d19, d16 +; CHECK: vmov.f64 define i32 @test(i8* %arg) nounwind { entry: diff --git a/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll b/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll index c03c815..2842437 100644 --- a/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll +++ b/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll @@ -21,12 +21,8 @@ declare i32 @printf(i8* nocapture, ...) nounwind declare i8* @__cxa_allocate_exception(i32) -declare i8* @llvm.eh.exception() nounwind readonly - declare i32 @__gxx_personality_sj0(...) -declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind - declare i32 @llvm.eh.typeid.for(i8*) nounwind declare void @_Unwind_SjLj_Resume(i8*) @@ -75,8 +71,11 @@ try.cont: ; preds = %lpad ret i32 %conv lpad: ; preds = %entry - %exn = tail call i8* @llvm.eh.exception() nounwind ; [#uses=4] - %eh.selector = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn, i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*), i8* bitcast (%0* @_ZTI1A to i8*), i8* null) nounwind ; [#uses=1] + %exn.ptr = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) + catch i8* bitcast (%0* @_ZTI1A to i8*) + catch i8* null + %exn = extractvalue { i8*, i32 } %exn.ptr, 0 + %eh.selector = extractvalue { i8*, i32 } %exn.ptr, 1 %2 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (%0* @_ZTI1A to i8*)) nounwind ; [#uses=1] %3 = icmp eq i32 %eh.selector, %2 ; [#uses=1] br i1 %3, label %try.cont, label %eh.resume diff --git a/test/CodeGen/ARM/2010-08-04-EHCrash.ll b/test/CodeGen/ARM/2010-08-04-EHCrash.ll index f57b7e6..4b47085 100644 --- a/test/CodeGen/ARM/2010-08-04-EHCrash.ll +++ b/test/CodeGen/ARM/2010-08-04-EHCrash.ll @@ -34,10 +34,12 @@ return: ; preds = %entry ret void lpad: ; preds = %bb - %eh_ptr = call i8* @llvm.eh.exception() ; [#uses=1] - store i8* %eh_ptr, i8** %eh_exception + %eh_ptr = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) + cleanup + %exn = extractvalue { i8*, i32 } %eh_ptr, 0 + store i8* %exn, i8** %eh_exception %eh_ptr13 = load i8** %eh_exception ; [#uses=1] - %eh_select14 = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %eh_ptr13, i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*), i32 1) + %eh_select14 = extractvalue { i8*, i32 } %eh_ptr, 1 store i32 %eh_select14, i32* %eh_selector br label %ppad @@ -54,10 +56,6 @@ declare arm_apcscc void @func2() declare arm_apcscc void @_ZSt9terminatev() noreturn nounwind -declare i8* @llvm.eh.exception() nounwind readonly - -declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind - declare arm_apcscc void @_Unwind_SjLj_Resume(i8*) declare arm_apcscc void @func3() diff --git a/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll b/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll index 0422094..ec74880 100644 --- a/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll +++ b/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -verify-machineinstrs -spiller=standard +; RUN: llc < %s -verify-machineinstrs -spiller=trivial ; RUN: llc < %s -verify-machineinstrs -spiller=inline ; PR8612 ; diff --git a/test/CodeGen/ARM/2010-11-29-PrologueBug.ll b/test/CodeGen/ARM/2010-11-29-PrologueBug.ll index e3c18ce..da4d157 100644 --- a/test/CodeGen/ARM/2010-11-29-PrologueBug.ll +++ b/test/CodeGen/ARM/2010-11-29-PrologueBug.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB2 +; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB2 ; rdar://8690640 define i32* @t(i32* %x) nounwind { diff --git a/test/CodeGen/ARM/2010-12-07-PEIBug.ll b/test/CodeGen/ARM/2010-12-07-PEIBug.ll index c65952b..770ad44 100644 --- a/test/CodeGen/ARM/2010-12-07-PEIBug.ll +++ b/test/CodeGen/ARM/2010-12-07-PEIBug.ll @@ -1,39 +1,15 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-a8 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 | FileCheck %s ; rdar://8728956 define hidden void @foo() nounwind ssp { entry: ; CHECK: foo: -; CHECK: push {r7, lr} -; CHECK-NEXT: mov r7, sp +; CHECK: mov r7, sp ; CHECK-NEXT: vpush {d8} ; CHECK-NEXT: vpush {d10, d11} - %tmp40 = load <4 x i8>* undef - %tmp41 = extractelement <4 x i8> %tmp40, i32 2 - %conv42 = zext i8 %tmp41 to i32 - %conv43 = sitofp i32 %conv42 to float - %div44 = fdiv float %conv43, 2.560000e+02 - %vecinit45 = insertelement <4 x float> undef, float %div44, i32 2 - %vecinit46 = insertelement <4 x float> %vecinit45, float 1.000000e+00, i32 3 - store <4 x float> %vecinit46, <4 x float>* undef - br i1 undef, label %if.then105, label %if.else109 - -if.then105: ; preds = %entry - br label %if.end114 - -if.else109: ; preds = %entry - br label %if.end114 - -if.end114: ; preds = %if.else109, %if.then105 - %call185 = call float @bar() - %vecinit186 = insertelement <4 x float> undef, float %call185, i32 1 - %call189 = call float @bar() - %vecinit190 = insertelement <4 x float> %vecinit186, float %call189, i32 2 - %vecinit191 = insertelement <4 x float> %vecinit190, float 1.000000e+00, i32 3 - store <4 x float> %vecinit191, <4 x float>* undef + tail call void asm sideeffect "","~{d8},~{d10},~{d11}"() nounwind ; CHECK: vpop {d10, d11} ; CHECK-NEXT: vpop {d8} -; CHECK-NEXT: pop {r7, pc} ret void } diff --git a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll index 9484212..ca88eed 100644 --- a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll +++ b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll @@ -3,11 +3,11 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32" target triple = "thumbv7-apple-darwin10" -@x1 = internal global i8 1 -@x2 = internal global i8 1 -@x3 = internal global i8 1 -@x4 = internal global i8 1 -@x5 = global i8 1 +@x1 = internal global i8 1, align 1 +@x2 = internal global i8 1, align 1 +@x3 = internal global i8 1, align 1 +@x4 = internal global i8 1, align 1 +@x5 = global i8 1, align 1 ; Check debug info output for merged global. ; DW_AT_location @@ -17,8 +17,7 @@ target triple = "thumbv7-apple-darwin10" ; DW_OP_constu ; offset -;CHECK: .ascii "x2" @ DW_AT_name -;CHECK-NEXT: .byte 0 +;CHECK: .long Lset6 ;CHECK-NEXT: @ DW_AT_type ;CHECK-NEXT: @ DW_AT_decl_file ;CHECK-NEXT: @ DW_AT_decl_line diff --git a/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll b/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll index ccda281e9..2faa04a 100644 --- a/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll +++ b/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -relocation-model=pic -disable-fp-elim -disable-cgp-delete-dead-blocks -mcpu=cortex-a8 | FileCheck %s ; Do not form Thumb2 ldrd / strd if the offset is not multiple of 4. ; rdar://9133587 diff --git a/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll b/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll index 0b5f962..d3394b5 100644 --- a/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll +++ b/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll @@ -35,14 +35,14 @@ for.cond.backedge: br label %for.cond lpad: - %exn = tail call i8* @llvm.eh.exception() nounwind - %eh.selector = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn, i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*), i8* null) nounwind + %exn = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) + catch i8* null invoke void @foo() to label %eh.resume unwind label %terminate.lpad lpad26: - %exn27 = tail call i8* @llvm.eh.exception() nounwind - %eh.selector28 = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn27, i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*), i8* null) nounwind + %exn27 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) + catch i8* null invoke void @foo() to label %eh.resume unwind label %terminate.lpad @@ -57,31 +57,26 @@ call8.i.i.i.noexc: ret void lpad44: - %exn45 = tail call i8* @llvm.eh.exception() nounwind - %eh.selector46 = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn45, i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*), i8* null) nounwind + %exn45 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) + catch i8* null invoke void @foo() to label %eh.resume unwind label %terminate.lpad eh.resume: - %exn.slot.0 = phi i8* [ %exn27, %lpad26 ], [ %exn, %lpad ], [ %exn45, %lpad44 ] - tail call void @_Unwind_SjLj_Resume_or_Rethrow(i8* %exn.slot.0) noreturn - unreachable + %exn.slot.0 = phi { i8*, i32 } [ %exn27, %lpad26 ], [ %exn, %lpad ], [ %exn45, %lpad44 ] + resume { i8*, i32 } %exn.slot.0 terminate.lpad: - %exn51 = tail call i8* @llvm.eh.exception() nounwind - %eh.selector52 = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn51, i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*), i8* null) nounwind + %exn51 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) + catch i8* null tail call void @_ZSt9terminatev() noreturn nounwind unreachable } declare void @foo() -declare i8* @llvm.eh.exception() nounwind readonly - declare i32 @__gxx_personality_sj0(...) -declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind - declare void @_Unwind_SjLj_Resume_or_Rethrow(i8*) declare void @_ZSt9terminatev() diff --git a/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll b/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll index 7baacfe..3e78c46 100644 --- a/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll +++ b/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -arm-tail-calls=1 | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" -target triple = "thumbv7-apple-darwin10" +target triple = "thumbv7-apple-ios" %struct.A = type <{ i16, i16, i32, i16, i16, i32, i16, [8 x %struct.B], [418 x i8], %struct.C }> %struct.B = type <{ i32, i16, i16 }> diff --git a/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll b/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll index 1b5b8a9..091d037 100644 --- a/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll +++ b/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll @@ -1,12 +1,10 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 | FileCheck %s ; CHECK: .zerofill __DATA,__bss,__MergedGlobals,16,2 -%struct.config = type { i16, i16, i16, i16 } - @prev = external global [0 x i16] @max_lazy_match = internal unnamed_addr global i32 0, align 4 @read_buf = external global i32 (i8*, i32)* @window = external global [0 x i8] @lookahead = internal unnamed_addr global i32 0, align 4 -@eofile.b = internal unnamed_addr global i1 false +@eofile.b = internal unnamed_addr global i32 0 @ins_h = internal unnamed_addr global i32 0, align 4 diff --git a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll index f681c34..f2b0c5d 100644 --- a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll +++ b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll @@ -8,8 +8,7 @@ ; DW_OP_constu ; offset -;CHECK: .ascii "x2" @ DW_AT_name -;CHECK-NEXT: .byte 0 +;CHECK: .long Lset33 ;CHECK-NEXT: @ DW_AT_type ;CHECK-NEXT: @ DW_AT_decl_file ;CHECK-NEXT: @ DW_AT_decl_line diff --git a/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll b/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll index 17264ee..216057a 100644 --- a/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll +++ b/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a9 | FileCheck %s ; Test that ldmia_ret preserves implicit operands for return values. ; ; This CFG is reduced from a benchmark miscompile. With current diff --git a/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll b/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll new file mode 100644 index 0000000..09db740 --- /dev/null +++ b/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -march=arm -mcpu=cortex-a9 -mattr=+neon,+neonfp -relocation-model=pic + +target triple = "armv6-none-linux-gnueabi" + +define void @sample_test(i8* %.T0348, i16* nocapture %sourceA, i16* nocapture %destValues) { +L.entry: + %0 = call i32 (...)* @get_index(i8* %.T0348, i32 0) + %1 = bitcast i16* %destValues to i8* + %2 = mul i32 %0, 6 + %3 = getelementptr i8* %1, i32 %2 + %4 = bitcast i8* %3 to <3 x i16>* + %5 = load <3 x i16>* %4, align 1 + %6 = bitcast i16* %sourceA to i8* + %7 = getelementptr i8* %6, i32 %2 + %8 = bitcast i8* %7 to <3 x i16>* + %9 = load <3 x i16>* %8, align 1 + %10 = or <3 x i16> %9, %5 + store <3 x i16> %10, <3 x i16>* %4, align 1 + ret void +} + +declare i32 @get_index(...) diff --git a/test/CodeGen/ARM/2011-10-26-memset-inline.ll b/test/CodeGen/ARM/2011-10-26-memset-inline.ll new file mode 100644 index 0000000..ff049c8 --- /dev/null +++ b/test/CodeGen/ARM/2011-10-26-memset-inline.ll @@ -0,0 +1,21 @@ +; Make sure short memsets on ARM lower to stores, even when optimizing for size. +; RUN: llc -march=arm < %s | FileCheck %s -check-prefix=CHECK-GENERIC +; RUN: llc -march=arm -mcpu=cortex-a8 < %s | FileCheck %s -check-prefix=CHECK-UNALIGNED + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" +target triple = "thumbv7-apple-ios5.0.0" + +; CHECK-GENERIC: strb +; CHECK-GENERIT-NEXT: strb +; CHECK-GENERIT-NEXT: strb +; CHECK-GENERIT-NEXT: strb +; CHECK-GENERIT-NEXT: strb +; CHECK-UNALIGNED: strb +; CHECK-UNALIGNED-NEXT: str +define void @foo(i8* nocapture %c) nounwind optsize { +entry: + call void @llvm.memset.p0i8.i64(i8* %c, i8 -1, i64 5, i32 1, i1 false) + ret void +} + +declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind diff --git a/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll b/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll new file mode 100644 index 0000000..42b1491 --- /dev/null +++ b/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll @@ -0,0 +1,20 @@ +; RUN: llc -march=arm -mcpu=cortex-a8 < %s | FileCheck %s + +; Should trigger a NEON store. +; CHECK: vstr +define void @f_0_12(i8* nocapture %c) nounwind optsize { +entry: + call void @llvm.memset.p0i8.i64(i8* %c, i8 0, i64 12, i32 8, i1 false) + ret void +} + +; Trigger multiple NEON stores. +; CHECK: vstmia +; CHECK-NEXT: vstmia +define void @f_0_40(i8* nocapture %c) nounwind optsize { +entry: + call void @llvm.memset.p0i8.i64(i8* %c, i8 0, i64 40, i32 16, i1 false) + ret void +} + +declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind diff --git a/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll b/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll new file mode 100644 index 0000000..113cbfe --- /dev/null +++ b/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; PR11319 + +@i8_res = global <2 x i8> +@i8_src1 = global <2 x i8> +@i8_src2 = global <2 x i8> + +define void @test_neon_vector_add_2xi8() nounwind { +; CHECK: test_neon_vector_add_2xi8: + %1 = load <2 x i8>* @i8_src1 + %2 = load <2 x i8>* @i8_src2 + %3 = add <2 x i8> %1, %2 + store <2 x i8> %3, <2 x i8>* @i8_res + ret void +} + +define void @test_neon_ld_st_volatile_with_ashr_2xi8() { +; CHECK: test_neon_ld_st_volatile_with_ashr_2xi8: + %1 = load volatile <2 x i8>* @i8_src1 + %2 = load volatile <2 x i8>* @i8_src2 + %3 = ashr <2 x i8> %1, %2 + store volatile <2 x i8> %3, <2 x i8>* @i8_res + ret void +} diff --git a/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll b/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll new file mode 100644 index 0000000..2ab6a4f --- /dev/null +++ b/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; PR11319 + +@src1_v2i16 = global <2 x i16> +@res_v2i16 = global <2 x i16> + +declare <2 x i16> @foo_v2i16(<2 x i16>) nounwind + +define void @test_neon_call_return_v2i16() { +; CHECK: test_neon_call_return_v2i16: + %1 = load <2 x i16>* @src1_v2i16 + %2 = call <2 x i16> @foo_v2i16(<2 x i16> %1) nounwind + store <2 x i16> %2, <2 x i16>* @res_v2i16 + ret void +} diff --git a/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll b/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll new file mode 100644 index 0000000..719571b --- /dev/null +++ b/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll @@ -0,0 +1,37 @@ +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s + +define <2 x i32> @test1(<2 x double>* %A) { +; CHECK: test1 +; CHECK: vcvt.s32.f64 +; CHECK: vcvt.s32.f64 + %tmp1 = load <2 x double>* %A + %tmp2 = fptosi <2 x double> %tmp1 to <2 x i32> + ret <2 x i32> %tmp2 +} + +define <2 x i32> @test2(<2 x double>* %A) { +; CHECK: test2 +; CHECK: vcvt.u32.f64 +; CHECK: vcvt.u32.f64 + %tmp1 = load <2 x double>* %A + %tmp2 = fptoui <2 x double> %tmp1 to <2 x i32> + ret <2 x i32> %tmp2 +} + +define <2 x double> @test3(<2 x i32>* %A) { +; CHECK: test3 +; CHECK: vcvt.f64.s32 +; CHECK: vcvt.f64.s32 + %tmp1 = load <2 x i32>* %A + %tmp2 = sitofp <2 x i32> %tmp1 to <2 x double> + ret <2 x double> %tmp2 +} + +define <2 x double> @test4(<2 x i32>* %A) { +; CHECK: test4 +; CHECK: vcvt.f64.u32 +; CHECK: vcvt.f64.u32 + %tmp1 = load <2 x i32>* %A + %tmp2 = uitofp <2 x i32> %tmp1 to <2 x double> + ret <2 x double> %tmp2 +} diff --git a/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll b/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll new file mode 100644 index 0000000..52aa0bf --- /dev/null +++ b/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll @@ -0,0 +1,62 @@ +; RUN: llc < %s -mcpu=cortex-a8 -verify-regalloc +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" +target triple = "thumbv7-apple-ios" + +; This test calls shrinkToUses with an early-clobber redefined live range during +; spilling. +; +; Shrink: %vreg47,1.158257e-02 = [384r,400e:0)[400e,420r:1) 0@384r 1@400e +; +; The early-clobber instruction is an str: +; +; %vreg12 = t2STR_PRE %vreg6, %vreg12, 32, pred:14, pred:%noreg +; +; This tests that shrinkToUses handles the EC redef correctly. + +%struct.Transform_Struct.0.11.12.17.43.46.56.58.60 = type { [4 x [4 x double]] } + +define void @Compute_Axis_Rotation_Transform(%struct.Transform_Struct.0.11.12.17.43.46.56.58.60* nocapture %transform, double* nocapture %V1, double %angle) nounwind { +entry: + store double 1.000000e+00, double* null, align 4 + %arrayidx5.1.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 0, i32 1 + store double 0.000000e+00, double* %arrayidx5.1.i, align 4 + %arrayidx5.2.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 0, i32 2 + store double 0.000000e+00, double* %arrayidx5.2.i, align 4 + %arrayidx5.114.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 1, i32 0 + store double 0.000000e+00, double* %arrayidx5.114.i, align 4 + %arrayidx5.1.1.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 1, i32 1 + store double 1.000000e+00, double* %arrayidx5.1.1.i, align 4 + store double 0.000000e+00, double* null, align 4 + store double 1.000000e+00, double* null, align 4 + store double 0.000000e+00, double* null, align 4 + %call = tail call double @cos(double %angle) nounwind readnone + %call1 = tail call double @sin(double %angle) nounwind readnone + %0 = load double* %V1, align 4 + %arrayidx2 = getelementptr inbounds double* %V1, i32 1 + %1 = load double* %arrayidx2, align 4 + %mul = fmul double %0, %1 + %sub = fsub double 1.000000e+00, %call + %mul3 = fmul double %mul, %sub + %2 = load double* undef, align 4 + %mul5 = fmul double %2, %call1 + %add = fadd double %mul3, %mul5 + store double %add, double* %arrayidx5.1.i, align 4 + %3 = load double* %V1, align 4 + %mul11 = fmul double %3, undef + %mul13 = fmul double %mul11, %sub + %4 = load double* %arrayidx2, align 4 + %mul15 = fmul double %4, %call1 + %sub16 = fsub double %mul13, %mul15 + store double %sub16, double* %arrayidx5.2.i, align 4 + %5 = load double* %V1, align 4 + %6 = load double* %arrayidx2, align 4 + %mul22 = fmul double %5, %6 + %mul24 = fmul double %mul22, %sub + %sub27 = fsub double %mul24, undef + store double %sub27, double* %arrayidx5.114.i, align 4 + ret void +} + +declare double @cos(double) nounwind readnone + +declare double @sin(double) nounwind readnone diff --git a/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll b/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll new file mode 100644 index 0000000..5409f8c --- /dev/null +++ b/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll @@ -0,0 +1,38 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-ios5.0.0 | FileCheck %s +; rdar://10464621 + +; DAG combine increases loads from packed types. ARM load / store optimizer then +; combined them into a ldm which causes runtime exception. + +%struct.InformationBlock = type <{ i32, %struct.FlagBits, %struct.FlagBits }> +%struct.FlagBits = type <{ [4 x i32] }> + +@infoBlock = external global %struct.InformationBlock + +define hidden void @foo() { +; CHECK: foo: +; CHECK: ldr.w +; CHECK: ldr.w +; CHECK-NOT: ldm +entry: + %tmp13 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 0), align 1 + %tmp15 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 1), align 1 + %tmp17 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 2), align 1 + %tmp19 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 3), align 1 + %tmp = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 0), align 1 + %tmp3 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 1), align 1 + %tmp4 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 2), align 1 + %tmp5 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 3), align 1 + %insert21 = insertvalue [4 x i32] undef, i32 %tmp13, 0 + %insert23 = insertvalue [4 x i32] %insert21, i32 %tmp15, 1 + %insert25 = insertvalue [4 x i32] %insert23, i32 %tmp17, 2 + %insert27 = insertvalue [4 x i32] %insert25, i32 %tmp19, 3 + %insert = insertvalue [4 x i32] undef, i32 %tmp, 0 + %insert7 = insertvalue [4 x i32] %insert, i32 %tmp3, 1 + %insert9 = insertvalue [4 x i32] %insert7, i32 %tmp4, 2 + %insert11 = insertvalue [4 x i32] %insert9, i32 %tmp5, 3 + tail call void @bar([4 x i32] %insert27, [4 x i32] %insert11) + ret void +} + +declare void @bar([4 x i32], [4 x i32]) diff --git a/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll b/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll new file mode 100644 index 0000000..6fbae19 --- /dev/null +++ b/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll @@ -0,0 +1,302 @@ +; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s + +@A = global <4 x float> + +define void @test_sqrt(<4 x float>* %X) nounwind { + +; CHECK: test_sqrt: + +; CHECK: movw r1, :lower16:{{.*}} +; CHECK: movt r1, :upper16:{{.*}} +; CHECK: vldmia r1 +; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}} +; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}} +; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}} +; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}} +; CHECK: vstmia {{.*}} + +L.entry: + %0 = load <4 x float>* @A, align 16 + %1 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %0) + store <4 x float> %1, <4 x float>* %X, align 16 + ret void +} + +declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) nounwind readonly + + +define void @test_cos(<4 x float>* %X) nounwind { + +; CHECK: test_cos: + +; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} +; CHECK: movt [[reg0]], :upper16:{{.*}} +; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}} + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}cosf + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}cosf + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}cosf + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}cosf + +; CHECK: vstmia {{.*}} + +L.entry: + %0 = load <4 x float>* @A, align 16 + %1 = call <4 x float> @llvm.cos.v4f32(<4 x float> %0) + store <4 x float> %1, <4 x float>* %X, align 16 + ret void +} + +declare <4 x float> @llvm.cos.v4f32(<4 x float>) nounwind readonly + +define void @test_exp(<4 x float>* %X) nounwind { + +; CHECK: test_exp: + +; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} +; CHECK: movt [[reg0]], :upper16:{{.*}} +; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}} + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}expf + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}expf + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}expf + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}expf + +; CHECK: vstmia {{.*}} + +L.entry: + %0 = load <4 x float>* @A, align 16 + %1 = call <4 x float> @llvm.exp.v4f32(<4 x float> %0) + store <4 x float> %1, <4 x float>* %X, align 16 + ret void +} + +declare <4 x float> @llvm.exp.v4f32(<4 x float>) nounwind readonly + +define void @test_exp2(<4 x float>* %X) nounwind { + +; CHECK: test_exp2: + +; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} +; CHECK: movt [[reg0]], :upper16:{{.*}} +; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}} + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}exp2f + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}exp2f + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}exp2f + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}exp2f + +; CHECK: vstmia {{.*}} + +L.entry: + %0 = load <4 x float>* @A, align 16 + %1 = call <4 x float> @llvm.exp2.v4f32(<4 x float> %0) + store <4 x float> %1, <4 x float>* %X, align 16 + ret void +} + +declare <4 x float> @llvm.exp2.v4f32(<4 x float>) nounwind readonly + +define void @test_log10(<4 x float>* %X) nounwind { + +; CHECK: test_log10: + +; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} +; CHECK: movt [[reg0]], :upper16:{{.*}} +; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}} + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}log10f + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}log10f + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}log10f + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}log10f + +; CHECK: vstmia {{.*}} + +L.entry: + %0 = load <4 x float>* @A, align 16 + %1 = call <4 x float> @llvm.log10.v4f32(<4 x float> %0) + store <4 x float> %1, <4 x float>* %X, align 16 + ret void +} + +declare <4 x float> @llvm.log10.v4f32(<4 x float>) nounwind readonly + +define void @test_log(<4 x float>* %X) nounwind { + +; CHECK: test_log: + +; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} +; CHECK: movt [[reg0]], :upper16:{{.*}} +; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}} + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}logf + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}logf + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}logf + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}logf + +; CHECK: vstmia {{.*}} + +L.entry: + %0 = load <4 x float>* @A, align 16 + %1 = call <4 x float> @llvm.log.v4f32(<4 x float> %0) + store <4 x float> %1, <4 x float>* %X, align 16 + ret void +} + +declare <4 x float> @llvm.log.v4f32(<4 x float>) nounwind readonly + +define void @test_log2(<4 x float>* %X) nounwind { + +; CHECK: test_log2: + +; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} +; CHECK: movt [[reg0]], :upper16:{{.*}} +; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}} + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}log2f + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}log2f + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}log2f + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}log2f + +; CHECK: vstmia {{.*}} + +L.entry: + %0 = load <4 x float>* @A, align 16 + %1 = call <4 x float> @llvm.log2.v4f32(<4 x float> %0) + store <4 x float> %1, <4 x float>* %X, align 16 + ret void +} + +declare <4 x float> @llvm.log2.v4f32(<4 x float>) nounwind readonly + + +define void @test_pow(<4 x float>* %X) nounwind { + +; CHECK: test_pow: + +; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} +; CHECK: movt [[reg0]], :upper16:{{.*}} +; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}} + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}powf + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}powf + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}powf + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}powf + +; CHECK: vstmia {{.*}} + +L.entry: + + %0 = load <4 x float>* @A, align 16 + %1 = call <4 x float> @llvm.pow.v4f32(<4 x float> %0, <4 x float> ) + + store <4 x float> %1, <4 x float>* %X, align 16 + + ret void +} + +declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>) nounwind readonly + +define void @test_powi(<4 x float>* %X) nounwind { + +; CHECK: test_powi: + +; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} +; CHECK: movt [[reg0]], :upper16:{{.*}} +; CHECK: vldmia [[reg0]], {{.*}} +; CHECK: vmul.f32 {{.*}} + +; CHECK: vstmia {{.*}} + +L.entry: + + %0 = load <4 x float>* @A, align 16 + %1 = call <4 x float> @llvm.powi.v4f32(<4 x float> %0, i32 2) + + store <4 x float> %1, <4 x float>* %X, align 16 + + ret void +} + +declare <4 x float> @llvm.powi.v4f32(<4 x float>, i32) nounwind readonly + +define void @test_sin(<4 x float>* %X) nounwind { + +; CHECK: test_sin: + +; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} +; CHECK: movt [[reg0]], :upper16:{{.*}} +; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}} + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}sinf + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}sinf + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}sinf + +; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}} +; CHECK: bl {{.*}}sinf + +; CHECK: vstmia {{.*}} + +L.entry: + %0 = load <4 x float>* @A, align 16 + %1 = call <4 x float> @llvm.sin.v4f32(<4 x float> %0) + store <4 x float> %1, <4 x float>* %X, align 16 + ret void +} + +declare <4 x float> @llvm.sin.v4f32(<4 x float>) nounwind readonly + diff --git a/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll b/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll new file mode 100644 index 0000000..0c90f4c --- /dev/null +++ b/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s | FileCheck %s +; + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10" + +@x1 = internal global i32 1 +@x2 = internal global i64 12 + +define i64 @f() { + %ax = load i32* @x1 + %a = zext i32 %ax to i64 + %b = load i64* @x2 + %c = add i64 %a, %b + ret i64 %c +} + +; We can global-merge the i64 in theory, but the current code doesn't handle +; the alignment correctly; for the moment, just check that we don't do it. +; See also + +; CHECK-NOT: MergedGlobals +; CHECK: _x2 +; CHECK-NOT: MergedGlobals diff --git a/test/CodeGen/ARM/2011-12-14-machine-sink.ll b/test/CodeGen/ARM/2011-12-14-machine-sink.ll new file mode 100644 index 0000000..5ce600d --- /dev/null +++ b/test/CodeGen/ARM/2011-12-14-machine-sink.ll @@ -0,0 +1,48 @@ +; RUN: llc < %s -o /dev/null -stats |& FileCheck %s -check-prefix=STATS +; Radar 10266272 +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" +target triple = "thumbv7-apple-ios4.0.0" +; STATS-NOT: machine-sink + +define i32 @foo(i32 %h) nounwind readonly ssp { +entry: + br label %for.cond + +for.cond: ; preds = %for.body, %entry + %cmp = icmp slt i32 0, %h + br i1 %cmp, label %for.body, label %if.end299 + +for.body: ; preds = %for.cond + %v.5 = select i1 undef, i32 undef, i32 0 + %0 = load i8* undef, align 1, !tbaa !0 + %conv88 = zext i8 %0 to i32 + %sub89 = sub nsw i32 0, %conv88 + %v.8 = select i1 undef, i32 undef, i32 %sub89 + %1 = load i8* null, align 1, !tbaa !0 + %conv108 = zext i8 %1 to i32 + %2 = load i8* undef, align 1, !tbaa !0 + %conv110 = zext i8 %2 to i32 + %sub111 = sub nsw i32 %conv108, %conv110 + %cmp112 = icmp slt i32 %sub111, 0 + %sub115 = sub nsw i32 0, %sub111 + %v.10 = select i1 %cmp112, i32 %sub115, i32 %sub111 + %add62 = add i32 0, %v.5 + %add73 = add i32 %add62, 0 + %add84 = add i32 %add73, 0 + %add95 = add i32 %add84, %v.8 + %add106 = add i32 %add95, 0 + %add117 = add i32 %add106, %v.10 + %add128 = add i32 %add117, 0 + %add139 = add i32 %add128, 0 + %add150 = add i32 %add139, 0 + %add161 = add i32 %add150, 0 + %add172 = add i32 %add161, 0 + br i1 undef, label %for.cond, label %if.end299 + +if.end299: ; preds = %for.body, %for.cond + %s.10 = phi i32 [ %add172, %for.body ], [ 0, %for.cond ] + ret i32 %s.10 +} + +!0 = metadata !{metadata !"omnipotent char", metadata !1} +!1 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll b/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll new file mode 100644 index 0000000..ddb7632 --- /dev/null +++ b/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll @@ -0,0 +1,55 @@ +; RUN: llc < %s -O0 -mtriple=thumbv7-apple-ios | FileCheck %s + +; Radar 10567930: Make sure that all the caller-saved registers are saved and +; restored in a function with setjmp/longjmp EH. In particular, r6 was not +; being saved here. +; CHECK: push {r4, r5, r6, r7, lr} + +%0 = type opaque +%struct.NSConstantString = type { i32*, i32, i8*, i32 } + +define i32 @asdf(i32 %a, i32 %b, i8** %c, i8* %d) { +bb: + %tmp = alloca i32, align 4 + %tmp1 = alloca i32, align 4 + %tmp2 = alloca i8*, align 4 + %tmp3 = alloca i1 + %myException = alloca %0*, align 4 + %tmp4 = alloca i8* + %tmp5 = alloca i32 + %exception = alloca %0*, align 4 + store i32 %a, i32* %tmp, align 4 + store i32 %b, i32* %tmp1, align 4 + store i8* %d, i8** %tmp2, align 4 + store i1 false, i1* %tmp3 + %tmp7 = load i8** %c + %tmp10 = invoke %0* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %0* (i8*, i8*, %0*)*)(i8* %tmp7, i8* %d, %0* null) + to label %bb11 unwind label %bb15 + +bb11: ; preds = %bb + store %0* %tmp10, %0** %myException, align 4 + %tmp12 = load %0** %myException, align 4 + %tmp13 = bitcast %0* %tmp12 to i8* + invoke void @objc_exception_throw(i8* %tmp13) noreturn + to label %bb14 unwind label %bb15 + +bb14: ; preds = %bb11 + unreachable + +bb15: ; preds = %bb11, %bb + %tmp16 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__objc_personality_v0 to i8*) + catch i8* null + %tmp17 = extractvalue { i8*, i32 } %tmp16, 0 + store i8* %tmp17, i8** %tmp4 + %tmp18 = extractvalue { i8*, i32 } %tmp16, 1 + store i32 %tmp18, i32* %tmp5 + store i1 true, i1* %tmp3 + br label %bb56 + +bb56: + unreachable +} + +declare i8* @objc_msgSend(i8*, i8*, ...) nonlazybind +declare i32 @__objc_personality_v0(...) +declare void @objc_exception_throw(i8*) diff --git a/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll b/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll new file mode 100644 index 0000000..926daaf --- /dev/null +++ b/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll @@ -0,0 +1,105 @@ +; RUN: llc < %s -mcpu=cortex-a8 -verify-machineinstrs +; PR11829 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64" +target triple = "armv7-none-linux-gnueabi" + +define arm_aapcs_vfpcc void @foo(i8* nocapture %arg) nounwind uwtable align 2 { +bb: + br i1 undef, label %bb1, label %bb2 + +bb1: ; preds = %bb + unreachable + +bb2: ; preds = %bb + br label %bb3 + +bb3: ; preds = %bb4, %bb2 + %tmp = icmp slt i32 undef, undef + br i1 %tmp, label %bb4, label %bb67 + +bb4: ; preds = %bb3 + %tmp5 = load <4 x i32>* undef, align 16, !tbaa !0 + %tmp6 = and <4 x i32> %tmp5, + %tmp7 = or <4 x i32> %tmp6, + %tmp8 = bitcast <4 x i32> %tmp7 to <4 x float> + %tmp9 = fsub <4 x float> %tmp8, bitcast (i128 or (i128 shl (i128 zext (i64 trunc (i128 lshr (i128 bitcast (<4 x float> to i128), i128 64) to i64) to i128), i128 64), i128 zext (i64 trunc (i128 bitcast (<4 x float> to i128) to i64) to i128)) to <4 x float>) + %tmp10 = fmul <4 x float> undef, %tmp9 + %tmp11 = fadd <4 x float> undef, %tmp10 + %tmp12 = bitcast <4 x float> zeroinitializer to i128 + %tmp13 = lshr i128 %tmp12, 64 + %tmp14 = trunc i128 %tmp13 to i64 + %tmp15 = insertvalue [2 x i64] undef, i64 %tmp14, 1 + %tmp16 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp11) nounwind + %tmp17 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp16, <4 x float> %tmp11) nounwind + %tmp18 = fmul <4 x float> %tmp17, %tmp16 + %tmp19 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp18, <4 x float> %tmp11) nounwind + %tmp20 = fmul <4 x float> %tmp19, %tmp18 + %tmp21 = fmul <4 x float> %tmp20, zeroinitializer + %tmp22 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp21, <4 x float> undef) nounwind + call arm_aapcs_vfpcc void @bar(i8* null, i8* undef, <4 x i32>* undef, [2 x i64] zeroinitializer) nounwind + %tmp23 = bitcast <4 x float> %tmp22 to i128 + %tmp24 = trunc i128 %tmp23 to i64 + %tmp25 = insertvalue [2 x i64] undef, i64 %tmp24, 0 + %tmp26 = insertvalue [2 x i64] %tmp25, i64 0, 1 + %tmp27 = load float* undef, align 4, !tbaa !2 + %tmp28 = insertelement <4 x float> undef, float %tmp27, i32 3 + %tmp29 = load <4 x i32>* undef, align 16, !tbaa !0 + %tmp30 = and <4 x i32> %tmp29, + %tmp31 = or <4 x i32> %tmp30, + %tmp32 = bitcast <4 x i32> %tmp31 to <4 x float> + %tmp33 = fsub <4 x float> %tmp32, bitcast (i128 or (i128 shl (i128 zext (i64 trunc (i128 lshr (i128 bitcast (<4 x float> to i128), i128 64) to i64) to i128), i128 64), i128 zext (i64 trunc (i128 bitcast (<4 x float> to i128) to i64) to i128)) to <4 x float>) + %tmp34 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> undef, <4 x float> %tmp28) nounwind + %tmp35 = fmul <4 x float> %tmp34, undef + %tmp36 = fmul <4 x float> %tmp35, undef + %tmp37 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind + %tmp38 = load float* undef, align 4, !tbaa !2 + %tmp39 = insertelement <2 x float> undef, float %tmp38, i32 0 + %tmp40 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind + %tmp41 = load float* undef, align 4, !tbaa !2 + %tmp42 = insertelement <4 x float> undef, float %tmp41, i32 3 + %tmp43 = shufflevector <2 x float> %tmp39, <2 x float> undef, <4 x i32> zeroinitializer + %tmp44 = fmul <4 x float> %tmp33, %tmp43 + %tmp45 = fadd <4 x float> %tmp42, %tmp44 + %tmp46 = fsub <4 x float> %tmp45, undef + %tmp47 = fmul <4 x float> %tmp46, %tmp36 + %tmp48 = fadd <4 x float> undef, %tmp47 + %tmp49 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind + %tmp50 = load float* undef, align 4, !tbaa !2 + %tmp51 = insertelement <4 x float> undef, float %tmp50, i32 3 + %tmp52 = call arm_aapcs_vfpcc float* null(i8* undef) nounwind + %tmp54 = load float* %tmp52, align 4, !tbaa !2 + %tmp55 = insertelement <4 x float> undef, float %tmp54, i32 3 + %tmp56 = fsub <4 x float> , %tmp22 + %tmp57 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp56, <4 x float> %tmp55) nounwind + %tmp58 = fmul <4 x float> undef, %tmp57 + %tmp59 = fsub <4 x float> %tmp51, %tmp48 + %tmp60 = fsub <4 x float> , %tmp58 + %tmp61 = fmul <4 x float> %tmp59, %tmp60 + %tmp62 = fadd <4 x float> %tmp48, %tmp61 + call arm_aapcs_vfpcc void @baz(i8* undef, i8* undef, [2 x i64] %tmp26, <4 x i32>* undef) + %tmp63 = bitcast <4 x float> %tmp62 to i128 + %tmp64 = lshr i128 %tmp63, 64 + %tmp65 = trunc i128 %tmp64 to i64 + %tmp66 = insertvalue [2 x i64] zeroinitializer, i64 %tmp65, 1 + call arm_aapcs_vfpcc void @quux(i8* undef, i8* undef, [2 x i64] undef, i8* undef, [2 x i64] %tmp66, i8* undef, i8* undef, [2 x i64] %tmp26, [2 x i64] %tmp15, <4 x i32>* undef) + br label %bb3 + +bb67: ; preds = %bb3 + ret void +} + +declare arm_aapcs_vfpcc void @bar(i8*, i8*, <4 x i32>*, [2 x i64]) + +declare arm_aapcs_vfpcc void @baz(i8*, i8* nocapture, [2 x i64], <4 x i32>* nocapture) nounwind uwtable inlinehint align 2 + +declare arm_aapcs_vfpcc void @quux(i8*, i8*, [2 x i64], i8* nocapture, [2 x i64], i8* nocapture, i8* nocapture, [2 x i64], [2 x i64], <4 x i32>* nocapture) nounwind uwtable inlinehint align 2 + +declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnone + +declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone + +declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone + +!0 = metadata !{metadata !"omnipotent char", metadata !1} +!1 = metadata !{metadata !"Simple C/C++ TBAA", null} +!2 = metadata !{metadata !"float", metadata !0} diff --git a/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll b/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll new file mode 100644 index 0000000..872eca3 --- /dev/null +++ b/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll @@ -0,0 +1,67 @@ +; RUN: llc < %s -mcpu=cortex-a8 -verify-machineinstrs -verify-coalescing +; PR11841 +; PR11829 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64" +target triple = "armv7-none-linux-eabi" + +; This test case is exercising REG_SEQUENCE, and chains of REG_SEQUENCE. +define arm_aapcs_vfpcc void @foo(i8* nocapture %arg, i8* %arg1) nounwind align 2 { +bb: + %tmp = load <2 x float>* undef, align 8, !tbaa !0 + %tmp2 = extractelement <2 x float> %tmp, i32 0 + %tmp3 = insertelement <4 x float> undef, float %tmp2, i32 0 + %tmp4 = insertelement <4 x float> %tmp3, float 0.000000e+00, i32 1 + %tmp5 = insertelement <4 x float> %tmp4, float 0.000000e+00, i32 2 + %tmp6 = insertelement <4 x float> %tmp5, float 0.000000e+00, i32 3 + %tmp7 = extractelement <2 x float> %tmp, i32 1 + %tmp8 = insertelement <4 x float> %tmp3, float %tmp7, i32 1 + %tmp9 = insertelement <4 x float> %tmp8, float 0.000000e+00, i32 2 + %tmp10 = insertelement <4 x float> %tmp9, float 0.000000e+00, i32 3 + %tmp11 = bitcast <4 x float> %tmp6 to <2 x i64> + %tmp12 = shufflevector <2 x i64> %tmp11, <2 x i64> undef, <1 x i32> zeroinitializer + %tmp13 = bitcast <1 x i64> %tmp12 to <2 x float> + %tmp14 = shufflevector <2 x float> %tmp13, <2 x float> undef, <4 x i32> zeroinitializer + %tmp15 = bitcast <4 x float> %tmp14 to <2 x i64> + %tmp16 = shufflevector <2 x i64> %tmp15, <2 x i64> undef, <1 x i32> zeroinitializer + %tmp17 = bitcast <1 x i64> %tmp16 to <2 x float> + %tmp18 = extractelement <2 x float> %tmp17, i32 0 + tail call arm_aapcs_vfpcc void @bar(i8* undef, float %tmp18, float undef, float 0.000000e+00) nounwind + %tmp19 = bitcast <4 x float> %tmp10 to <2 x i64> + %tmp20 = shufflevector <2 x i64> %tmp19, <2 x i64> undef, <1 x i32> zeroinitializer + %tmp21 = bitcast <1 x i64> %tmp20 to <2 x float> + %tmp22 = shufflevector <2 x float> %tmp21, <2 x float> undef, <4 x i32> + %tmp23 = bitcast <4 x float> %tmp22 to <2 x i64> + %tmp24 = shufflevector <2 x i64> %tmp23, <2 x i64> undef, <1 x i32> zeroinitializer + %tmp25 = bitcast <1 x i64> %tmp24 to <2 x float> + %tmp26 = extractelement <2 x float> %tmp25, i32 0 + tail call arm_aapcs_vfpcc void @bar(i8* undef, float undef, float %tmp26, float 0.000000e+00) nounwind + ret void +} + +define arm_aapcs_vfpcc void @foo2() nounwind uwtable { +entry: + br i1 undef, label %for.end, label %cond.end295 + +cond.end295: ; preds = %entry + %shuffle.i39.i.i1035 = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer + %shuffle.i38.i.i1036 = shufflevector <2 x i64> zeroinitializer, <2 x i64> undef, <1 x i32> zeroinitializer + %shuffle.i37.i.i1037 = shufflevector <1 x i64> %shuffle.i39.i.i1035, <1 x i64> %shuffle.i38.i.i1036, <2 x i32> + %0 = bitcast <2 x i64> %shuffle.i37.i.i1037 to <4 x float> + %1 = bitcast <4 x float> undef to <2 x i64> + %shuffle.i36.i.i = shufflevector <2 x i64> %1, <2 x i64> undef, <1 x i32> zeroinitializer + %shuffle.i35.i.i = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer + %shuffle.i34.i.i = shufflevector <1 x i64> %shuffle.i36.i.i, <1 x i64> %shuffle.i35.i.i, <2 x i32> + %2 = bitcast <2 x i64> %shuffle.i34.i.i to <4 x float> + tail call void @llvm.arm.neon.vst1.v4f32(i8* undef, <4 x float> %0, i32 4) nounwind + tail call void @llvm.arm.neon.vst1.v4f32(i8* undef, <4 x float> %2, i32 4) nounwind + unreachable + +for.end: ; preds = %entry + ret void +} + +declare arm_aapcs_vfpcc void @bar(i8*, float, float, float) +declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind + +!0 = metadata !{metadata !"omnipotent char", metadata !1} +!1 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/ARM/2012-01-26-CoalescerBug.ll b/test/CodeGen/ARM/2012-01-26-CoalescerBug.ll new file mode 100644 index 0000000..ec5b2e9 --- /dev/null +++ b/test/CodeGen/ARM/2012-01-26-CoalescerBug.ll @@ -0,0 +1,21 @@ +; RUN: llc < %s -verify-coalescing +; PR11861 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64" +target triple = "armv7-none-linux-eabi" + +define arm_aapcs_vfpcc void @foo() nounwind uwtable align 2 { + br label %1 + +;