From dab875b1fd1f9e4fc9f6c7d4d66be9b337d07232 Mon Sep 17 00:00:00 2001 From: nwhitehorn Date: Mon, 15 Mar 2010 00:27:40 +0000 Subject: Fix two small bugs. The PowerPC 970 does not support non-coherent memory access, and reflects this by autonomously writing LPTE_M into PTE entries. As such, we should not panic if LPTE_M changes by itself. While here, fix a harmless typo in moea64_sync_icache(). --- sys/powerpc/aim/mmu_oea64.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'sys') diff --git a/sys/powerpc/aim/mmu_oea64.c b/sys/powerpc/aim/mmu_oea64.c index cf64af1..bc7e5cf 100644 --- a/sys/powerpc/aim/mmu_oea64.c +++ b/sys/powerpc/aim/mmu_oea64.c @@ -2268,7 +2268,7 @@ moea64_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) } if (((pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo) & - ~(LPTE_CHG|LPTE_REF)) != 0) { + ~(LPTE_M|LPTE_CHG|LPTE_REF)) != 0) { panic("moea64_pvo_to_pte: pvo %p pte does not match " "pte %p in moea64_pteg_table difference is %#x", pvo, pt, @@ -2511,7 +2511,7 @@ moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) len = MIN(lim - va, sz); pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL); if (pvo != NULL) { - pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | + pa = (pvo->pvo_pte.pte.pte_lo & LPTE_RPGN) | (va & ADDR_POFF); moea64_syncicache(pm, va, pa, len); } -- cgit v1.1