From 16fc3a3c4b824ddbea8ec98084b5c4c061c0faba Mon Sep 17 00:00:00 2001 From: gibbs Date: Mon, 17 Jun 2013 01:43:07 +0000 Subject: Adjust i386 Xen PV support for updated Xen interface files. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit sys/i386/include/xen/xenvar.h: sys/i386/xen/xen_machdep.c: sys/xen/interface/foreign/structs.py: sys/xen/evtchn/evtchn.c: MAX_VIRT_CPUS => XEN_LEGACY_MAX_VCPUS Submitted by: Roger Pau Monné Reviewed by: gibbs --- sys/xen/evtchn/evtchn.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'sys/xen/evtchn') diff --git a/sys/xen/evtchn/evtchn.c b/sys/xen/evtchn/evtchn.c index eb18b57..baff9aa 100644 --- a/sys/xen/evtchn/evtchn.c +++ b/sys/xen/evtchn/evtchn.c @@ -146,7 +146,7 @@ static int irq_bindcount[NR_IRQS]; #ifdef SMP static uint8_t cpu_evtchn[NR_EVENT_CHANNELS]; -static unsigned long cpu_evtchn_mask[MAX_VIRT_CPUS][NR_EVENT_CHANNELS/LONG_BIT]; +static unsigned long cpu_evtchn_mask[XEN_LEGACY_MAX_VCPUS][NR_EVENT_CHANNELS/LONG_BIT]; #define active_evtchns(cpu,sh,idx) \ ((sh)->evtchn_pending[idx] & \ @@ -998,7 +998,7 @@ void irq_resume(void) } /* Secondary CPUs must have no VIRQ or IPI bindings. */ - for (cpu = 1; cpu < MAX_VIRT_CPUS; cpu++) { + for (cpu = 1; cpu < XEN_LEGACY_MAX_VCPUS; cpu++) { for (virq = 0; virq < NR_VIRQS; virq++) { KASSERT(pcpu_find(cpu)->pc_virq_to_irq[virq] == -1, ("virq_to_irq inconsistent")); -- cgit v1.1