From e3faa1c7bc06aa0955397278ab8aa726f3cb9fa0 Mon Sep 17 00:00:00 2001
From: raj <raj@FreeBSD.org>
Date: Sat, 26 Apr 2008 18:03:00 +0000
Subject: Use RSTCR for resetting the MPC8572 (the old way does not apply).

Obtained from:	Freescale, Semihalf
---
 sys/powerpc/mpc85xx/mpc85xx.c | 27 ++++++++++++++++++++-------
 1 file changed, 20 insertions(+), 7 deletions(-)

(limited to 'sys/powerpc/mpc85xx/mpc85xx.c')

diff --git a/sys/powerpc/mpc85xx/mpc85xx.c b/sys/powerpc/mpc85xx/mpc85xx.c
index d5831ee..144867e 100644
--- a/sys/powerpc/mpc85xx/mpc85xx.c
+++ b/sys/powerpc/mpc85xx/mpc85xx.c
@@ -33,10 +33,16 @@ __FBSDID("$FreeBSD$");
 #include <sys/param.h>
 #include <sys/systm.h>
 
+#include <vm/vm.h>
+#include <vm/vm_param.h>
+
 #include <machine/cpu.h>
 #include <machine/cpufunc.h>
+#include <machine/pio.h>
 #include <machine/spr.h>
 
+#include <powerpc/mpc85xx/ocpbus.h>
+
 /*
  * MPC85xx system specific routines
  */
@@ -44,16 +50,23 @@ __FBSDID("$FreeBSD$");
 void
 cpu_reset()
 {
+	uint32_t svr = mfsvr();
+
+	if (svr == SVR_MPC8572E || svr == SVR_MPC8572)
+		/* Systems with dedicated reset register */
+		out32(OCP85XX_RSTCR, 2);
+	else {
+		/* Clear DBCR0, disables debug interrupts and events. */
+		mtspr(SPR_DBCR0, 0);
+		__asm volatile("isync");
 
-	/* Clear DBCR0, disables debug interrupts and events. */
-	mtspr(SPR_DBCR0, 0);
-	__asm volatile("isync");
+		/* Enable Debug Interrupts in MSR. */
+		mtmsr(mfmsr() | PSL_DE);
 
-	/* Enable Debug Interrupts in MSR. */
-	mtmsr(mfmsr() | PSL_DE);
+		/* Enable debug interrupts and issue reset. */
+		mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM);
+	}
 
-	/* Enable debug interrupts and issue reset. */
-	mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM);
 	printf("Reset failed...\n");
 	while (1);
 }
-- 
cgit v1.1