From 0757a4afb5d18c5b874cc918eb56d7264456bd20 Mon Sep 17 00:00:00 2001 From: raj Date: Mon, 3 Mar 2008 17:17:00 +0000 Subject: Initial support for Freescale PowerQUICC III MPC85xx system-on-chip family. The PQ3 is a high performance integrated communications processing system based on the e500 core, which is an embedded RISC processor that implements the 32-bit Book E definition of the PowerPC architecture. For details refer to: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8555E This port was tested and successfully run on the following members of the PQ3 family: MPC8533, MPC8541, MPC8548, MPC8555. The following major integrated peripherals are supported: * On-chip peripherals bus * OpenPIC interrupt controller * UART * Ethernet (TSEC) * Host/PCI bridge * QUICC engine (SCC functionality) This commit brings the main functionality and will be followed by individual drivers that are logically separate from this base. Approved by: cognet (mentor) Obtained from: Juniper, Semihalf MFp4: e500 --- sys/powerpc/include/ocpbus.h | 45 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 sys/powerpc/include/ocpbus.h (limited to 'sys/powerpc/include/ocpbus.h') diff --git a/sys/powerpc/include/ocpbus.h b/sys/powerpc/include/ocpbus.h new file mode 100644 index 0000000..6cd7f9e --- /dev/null +++ b/sys/powerpc/include/ocpbus.h @@ -0,0 +1,45 @@ +/*- + * Copyright (c) 2006 Juniper Networks + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_OCPBUS_H_ +#define _MACHINE_OCPBUS_H_ + +#define OCPBUS_IVAR_DEVTYPE 1 +#define OCPBUS_IVAR_CLOCK 2 +#define OCPBUS_IVAR_HWUNIT 3 + +/* Device types. */ +#define OCPBUS_DEVTYPE_PIC 1 +#define OCPBUS_DEVTYPE_TSEC 2 +#define OCPBUS_DEVTYPE_UART 3 +#define OCPBUS_DEVTYPE_QUICC 4 +#define OCPBUS_DEVTYPE_PCIB 5 +#define OCPBUS_DEVTYPE_LBC 6 +#define OCPBUS_DEVTYPE_I2C 7 + +#endif /* _MACHINE_OCPBUS_H_ */ -- cgit v1.1