From 6fa14f9355adf884566931a644103b09971c3558 Mon Sep 17 00:00:00 2001 From: yongari Date: Mon, 18 Dec 2006 01:38:10 +0000 Subject: Don't assume IF_LLADDR returns aligned memory address. Because accessing ID registers in rtl81x9 needs 32bit register access and RL_IDR4/RL_IDR5 registers are reservered registers bzero() is needed before copying ethernet address. This fixes unaligned memory accesses panic in sparc64. PR: kern/106801 MFC after: 3 days --- sys/pci/if_rl.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'sys/pci/if_rl.c') diff --git a/sys/pci/if_rl.c b/sys/pci/if_rl.c index 7c9dd3f..29c1152 100644 --- a/sys/pci/if_rl.c +++ b/sys/pci/if_rl.c @@ -1495,6 +1495,7 @@ rl_init_locked(struct rl_softc *sc) struct ifnet *ifp = sc->rl_ifp; struct mii_data *mii; uint32_t rxcfg = 0; + uint32_t eaddr[2]; RL_LOCK_ASSERT(sc); @@ -1511,10 +1512,10 @@ rl_init_locked(struct rl_softc *sc) * register write enable" mode to modify the ID registers. */ CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); - CSR_WRITE_STREAM_4(sc, RL_IDR0, - *(uint32_t *)(&IF_LLADDR(sc->rl_ifp)[0])); - CSR_WRITE_STREAM_4(sc, RL_IDR4, - *(uint32_t *)(&IF_LLADDR(sc->rl_ifp)[4])); + bzero(eaddr, sizeof(eaddr)); + bcopy(IF_LLADDR(sc->rl_ifp), eaddr, ETHER_ADDR_LEN); + CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]); + CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]); CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); /* Init the RX buffer pointer register. */ -- cgit v1.1