From ab69bb0ca5ba497377d209f7d6c92fbd4e4972fb Mon Sep 17 00:00:00 2001 From: fabient Date: Fri, 16 Apr 2010 15:43:24 +0000 Subject: MFC r206089, r206684: - Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ --- sys/modules/hwpmc/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'sys/modules') diff --git a/sys/modules/hwpmc/Makefile b/sys/modules/hwpmc/Makefile index 0a696a1..1febf54 100644 --- a/sys/modules/hwpmc/Makefile +++ b/sys/modules/hwpmc/Makefile @@ -10,7 +10,7 @@ SRCS= hwpmc_mod.c hwpmc_logging.c vnode_if.h .if ${MACHINE_ARCH} == "amd64" SRCS+= hwpmc_amd.c hwpmc_core.c hwpmc_intel.c hwpmc_piv.c hwpmc_tsc.c -SRCS+= hwpmc_x86.c +SRCS+= hwpmc_x86.c hwpmc_uncore.c SRCS+= device_if.h bus_if.h .endif @@ -20,7 +20,7 @@ SRCS+= hwpmc_arm.c .if ${MACHINE_ARCH} == "i386" SRCS+= hwpmc_amd.c hwpmc_core.c hwpmc_intel.c hwpmc_piv.c hwpmc_ppro.c -SRCS+= hwpmc_pentium.c hwpmc_tsc.c hwpmc_x86.c +SRCS+= hwpmc_pentium.c hwpmc_tsc.c hwpmc_x86.c hwpmc_uncore.c SRCS+= device_if.h bus_if.h .endif -- cgit v1.1