From 8a0279994de9e2e860de4a740b1a7b6dfec51e3e Mon Sep 17 00:00:00 2001
From: kib <kib@FreeBSD.org>
Date: Mon, 1 Jul 2013 02:48:27 +0000
Subject: Fix issues with zeroing and fetching the counters, on x86 and ppc64.
 Issues were noted by Bruce Evans and are present on all architectures.

On i386, a counter fetch should use atomic read of 64bit value,
otherwise carry from the increment on other CPU could be lost for the
given fetch, making error of 2^32.  If 64bit read (cmpxchg8b) is not
available on the machine, it cannot be SMP and it is enough to disable
preemption around read to avoid the split read.

On x86 the counter increment is not atomic on purpose, which makes it
possible for the store of the incremented result to override just
zeroed per-cpu slot.  The effect would be a counter going off by
arbitrary value after zeroing.  Perform the counter zeroing on the
same processor which does the increments, making the operations
mutually exclusive.  On i386, same as for the fetching, if the
cmpxchg8b is not available, machine is not SMP and we disable
preemption for zeroing.

PowerPC64 is treated the same as amd64.

For other architectures, the changes made to allow the compilation to
succeed, without fixing the issues with zeroing or fetching.  It
should be possible to handle them by using the 64bit loads and stores
atomic WRT preemption (assuming the architectures also converted from
using critical sections to proper asm).  If architecture does not
provide the facility, using global (spin) mutex would be non-optimal
but working solution.

Noted by:  bde
Sponsored by:	The FreeBSD Foundation
---
 sys/mips/include/counter.h | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

(limited to 'sys/mips')

diff --git a/sys/mips/include/counter.h b/sys/mips/include/counter.h
index 68f89e2..193c98e 100644
--- a/sys/mips/include/counter.h
+++ b/sys/mips/include/counter.h
@@ -37,6 +37,46 @@
 #define	counter_enter()	critical_enter()
 #define	counter_exit()	critical_exit()
 
+#ifdef IN_SUBR_COUNTER_C
+/* XXXKIB non-atomic 64bit read on 32bit */
+static inline uint64_t
+counter_u64_read_one(uint64_t *p, int cpu)
+{
+
+	return (*(uint64_t *)((char *)p + sizeof(struct pcpu) * cpu));
+}
+
+static inline uint64_t
+counter_u64_fetch_inline(uint64_t *p)
+{
+	uint64_t r;
+	int i;
+
+	r = 0;
+	for (i = 0; i < mp_ncpus; i++)
+		r += counter_u64_read_one((uint64_t *)p, i);
+
+	return (r);
+}
+
+/* XXXKIB non-atomic 64bit store on 32bit, might interrupt increment */
+static void
+counter_u64_zero_one_cpu(void *arg)
+{
+
+	*((uint64_t *)((char *)arg + sizeof(struct pcpu) *
+	    PCPU_GET(cpuid))) = 0;
+}
+
+static inline void
+counter_u64_zero_inline(counter_u64_t c)
+{
+
+	smp_rendezvous(smp_no_rendevous_barrier, counter_u64_zero_one_cpu,
+	    smp_no_rendevous_barrier, c);
+}
+#endif
+
 #define	counter_u64_add_protected(c, inc)	do {	\
 	CRITICAL_ASSERT(curthread);			\
 	*(uint64_t *)zpcpu_get(c) += (inc);		\
-- 
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