From 66d589b127f7dad9c8668d9aa90fa686c0360301 Mon Sep 17 00:00:00 2001 From: adrian Date: Sun, 15 Apr 2012 22:34:22 +0000 Subject: The AR913x MII speed configuration matches the AR71xx MII configuration. So share the code. Don't do it for the AR724x - that has a completely different set of PLL and MII configuration parameters. --- sys/mips/atheros/ar71xx_chip.h | 1 + 1 file changed, 1 insertion(+) (limited to 'sys/mips/atheros/ar71xx_chip.h') diff --git a/sys/mips/atheros/ar71xx_chip.h b/sys/mips/atheros/ar71xx_chip.h index ccecc23..4869f31 100644 --- a/sys/mips/atheros/ar71xx_chip.h +++ b/sys/mips/atheros/ar71xx_chip.h @@ -30,5 +30,6 @@ #define __AR71XX_CHIP_H__ extern struct ar71xx_cpu_def ar71xx_chip_def; +extern void ar71xx_chip_set_mii_speed(uint32_t unit, uint32_t speed); #endif -- cgit v1.1