From 7cd751dbd6cdde4a9ed12d2ef1578f4ecc3cd934 Mon Sep 17 00:00:00 2001 From: marcel Date: Fri, 23 May 2003 23:16:43 +0000 Subject: In swapctx(), put the RSE in enforced lazy mode before we flush the register stack. There's nothing really wrong with flushing before putting the RSE in enforced lazy mode, provided you don't depend on ar.bspstore being equal to ar.bsp when the RSE has been put in enforced lazy more. The small window between the flush and setting the RSE may be sufficient to have the RSE eagerly increase the dirty region (and hence cause ar.bspstore != ar.bsp) or have an interrupt that may even get the laziest RSE to do something. Anyway: we don't depend on ar.bspstore being equal to ar.bsp, so nothing was and is broken. But the code was non-intuitive and easily confuses. This is a source of future bugs. Note: the advantage of not depending on ar.bspstore is that there's some recilience against an interrupted flushrs. Clobbering is limited to stacked register contents only, not to RSE address clobbering. Approved: re@ (blanket) --- sys/ia64/ia64/context.S | 4 ++-- sys/ia64/ia64/context.s | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'sys/ia64') diff --git a/sys/ia64/ia64/context.S b/sys/ia64/ia64/context.S index 67f2fe6..c2f9ef8 100644 --- a/sys/ia64/ia64/context.S +++ b/sys/ia64/ia64/context.S @@ -168,14 +168,14 @@ END(restorectx) ENTRY(swapctx, 2) { .mmi - flushrs + mov ar.rsc=0 mov r16=ar.unat add r31=8,r32 ;; } { .mmi + flushrs st8 [r32]=sp,16 // sp - mov ar.rsc=0 mov r17=rp ;; } diff --git a/sys/ia64/ia64/context.s b/sys/ia64/ia64/context.s index 67f2fe6..c2f9ef8 100644 --- a/sys/ia64/ia64/context.s +++ b/sys/ia64/ia64/context.s @@ -168,14 +168,14 @@ END(restorectx) ENTRY(swapctx, 2) { .mmi - flushrs + mov ar.rsc=0 mov r16=ar.unat add r31=8,r32 ;; } { .mmi + flushrs st8 [r32]=sp,16 // sp - mov ar.rsc=0 mov r17=rp ;; } -- cgit v1.1