From ab88cc6719e2d569d7f78bc2fdf7925513a538c8 Mon Sep 17 00:00:00 2001 From: ps Date: Fri, 22 Sep 2000 23:40:10 +0000 Subject: Remove the NCPU, NAPIC, NBUS, NINTR config options. Make NAPIC, NBUS, NINTR dynamic and set NCPU to a maximum of 16 under SMP. Reviewed by: peter --- sys/i386/isa/apic_ipl.s | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'sys/i386/isa') diff --git a/sys/i386/isa/apic_ipl.s b/sys/i386/isa/apic_ipl.s index 0def1de..596adf6 100644 --- a/sys/i386/isa/apic_ipl.s +++ b/sys/i386/isa/apic_ipl.s @@ -235,7 +235,8 @@ write_ioapic_mask: jz all_done /* no change, return */ movl _APIC, %esi /* APIC # */ - movl _ioapic(,%esi,4), %esi /* %esi holds APIC base address */ + movl _ioapic, %ecx + movl (%ecx,%esi,4), %esi /* %esi holds APIC base address */ next_loop: /* %ebx = diffs, %esi = APIC base */ bsfl %ebx, %ecx /* %ecx = index if 1st/next set bit */ @@ -355,7 +356,8 @@ clr_ioapic_maskbit: */ ENTRY(io_apic_read) movl 4(%esp), %ecx /* APIC # */ - movl _ioapic(,%ecx,4), %edx /* APIC base register address */ + movl _ioapic, %eax + movl (%eax,%ecx,4), %edx /* APIC base register address */ movl 8(%esp), %eax /* target register index */ movl %eax, (%edx) /* write the target register index */ movl 16(%edx), %eax /* read the APIC register data */ @@ -366,7 +368,8 @@ ENTRY(io_apic_read) */ ENTRY(io_apic_write) movl 4(%esp), %ecx /* APIC # */ - movl _ioapic(,%ecx,4), %edx /* APIC base register address */ + movl _ioapic, %eax + movl (%eax,%ecx,4), %edx /* APIC base register address */ movl 8(%esp), %eax /* target register index */ movl %eax, (%edx) /* write the target register index */ movl 12(%esp), %eax /* target register value */ -- cgit v1.1