From 99451e9e7417c523343c14e3808924954ae700da Mon Sep 17 00:00:00 2001
From: jimharris <jimharris@FreeBSD.org>
Date: Tue, 18 Dec 2012 23:27:18 +0000
Subject: Map BAR 4/5, because NVMe spec says devices may place the MSI-X table
 behind BAR 4/5, rather than in BAR 0/1 with the control/doorbell registers.

Sponsored by:	Intel
---
 sys/dev/nvme/nvme.c         |  5 +++++
 sys/dev/nvme/nvme_ctrlr.c   | 11 +++++++++++
 sys/dev/nvme/nvme_private.h |  8 ++++++++
 3 files changed, 24 insertions(+)

(limited to 'sys/dev')

diff --git a/sys/dev/nvme/nvme.c b/sys/dev/nvme/nvme.c
index dcb0c81..ed5dbdb 100644
--- a/sys/dev/nvme/nvme.c
+++ b/sys/dev/nvme/nvme.c
@@ -313,6 +313,11 @@ nvme_detach (device_t dev)
 		    ctrlr->resource_id, ctrlr->resource);
 	}
 
+	if (ctrlr->bar4_resource != NULL) {
+		bus_release_resource(dev, SYS_RES_MEMORY,
+		    ctrlr->bar4_resource_id, ctrlr->bar4_resource);
+	}
+
 #ifdef CHATHAM2
 	if (ctrlr->chatham_resource != NULL) {
 		bus_release_resource(dev, SYS_RES_MEMORY,
diff --git a/sys/dev/nvme/nvme_ctrlr.c b/sys/dev/nvme/nvme_ctrlr.c
index f3514a4..1ddf9cc 100644
--- a/sys/dev/nvme/nvme_ctrlr.c
+++ b/sys/dev/nvme/nvme_ctrlr.c
@@ -78,6 +78,17 @@ nvme_ctrlr_allocate_bar(struct nvme_controller *ctrlr)
 	ctrlr->bus_handle = rman_get_bushandle(ctrlr->resource);
 	ctrlr->regs = (struct nvme_registers *)ctrlr->bus_handle;
 
+	/*
+	 * The NVMe spec allows for the MSI-X table to be placed behind
+	 *  BAR 4/5, separate from the control/doorbell registers.  Always
+	 *  try to map this bar, because it must be mapped prior to calling
+	 *  pci_alloc_msix().  If the table isn't behind BAR 4/5,
+	 *  bus_alloc_resource() will just return NULL which is OK.
+	 */
+	ctrlr->bar4_resource_id = PCIR_BAR(4);
+	ctrlr->bar4_resource = bus_alloc_resource(ctrlr->dev, SYS_RES_MEMORY,
+	    &ctrlr->bar4_resource_id, 0, ~0, 1, RF_ACTIVE);
+
 	return (0);
 }
 
diff --git a/sys/dev/nvme/nvme_private.h b/sys/dev/nvme/nvme_private.h
index e811901..a74b876 100644
--- a/sys/dev/nvme/nvme_private.h
+++ b/sys/dev/nvme/nvme_private.h
@@ -199,6 +199,14 @@ struct nvme_controller {
 	int			resource_id;
 	struct resource		*resource;
 
+	/*
+	 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5,
+	 *  separate from the control registers which are in BAR 0/1.  These
+	 *  members track the mapping of BAR 4/5 for that reason.
+	 */
+	int			bar4_resource_id;
+	struct resource		*bar4_resource;
+
 #ifdef CHATHAM2
 	bus_space_tag_t		chatham_bus_tag;
 	bus_space_handle_t	chatham_bus_handle;
-- 
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