From 31fd8f4296cf6fa92a20171e42e9891d2df49b5c Mon Sep 17 00:00:00 2001 From: yongari Date: Fri, 29 Feb 2008 03:38:12 +0000 Subject: Workaround GMAC hardware hang of Yukon II on the receipt of pause frames. This bug seems to happen on certain hardware model/revision (e.g. 88E8053) but it's not identified which hardwares are affected. Revision 1.4 of if_mskreg.h was not enough to workaround the bug. To workaround it, inrease GMAC FIFO threshold by one FIFO word to flush received pause frames. Reported by: das, Kirill Nuzhdin < kirill.nuzhdin AT rad dot chem dot msu dot ru > Tested by: das, Kirill Nuzhdin --- sys/dev/msk/if_msk.c | 7 +++++-- sys/dev/msk/if_mskreg.h | 1 + 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'sys/dev') diff --git a/sys/dev/msk/if_msk.c b/sys/dev/msk/if_msk.c index 2613b81..bb4ba13 100644 --- a/sys/dev/msk/if_msk.c +++ b/sys/dev/msk/if_msk.c @@ -3658,9 +3658,12 @@ msk_init_locked(struct msk_if_softc *sc_if) CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); - /* Set Rx FIFO flush threshold to 64 bytes. */ + /* + * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word + * due to hardware hang on receipt of pause frames. + */ CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), - RX_GMF_FL_THR_DEF); + RX_GMF_FL_THR_DEF + 1); /* Configure Tx MAC FIFO. */ CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); diff --git a/sys/dev/msk/if_mskreg.h b/sys/dev/msk/if_mskreg.h index 1f8ff7d..ba0d730 100644 --- a/sys/dev/msk/if_mskreg.h +++ b/sys/dev/msk/if_mskreg.h @@ -1818,6 +1818,7 @@ GMR_FS_LONG_ERR | \ GMR_FS_MII_ERR | \ GMR_FS_BAD_FC | \ + GMR_FS_GOOD_FC | \ GMR_FS_UN_SIZE | \ GMR_FS_JABBER) -- cgit v1.1