From 74b8e10dc8320877d77c972a0f9a432c58388311 Mon Sep 17 00:00:00 2001 From: ray Date: Mon, 7 Jul 2014 14:16:05 +0000 Subject: =?UTF-8?q?267622=20Log:=20=20=20Rename=20vt(4)=20vga=20module=20t?= =?UTF-8?q?o=20dismiss=20interference=20with=20syscons(4)=20vga=20module.?= =?UTF-8?q?=20267623=20Log:=20=20=20Remove=20stale=20link=20to=20deleted?= =?UTF-8?q?=20vt(4)=20xboxfb=20driver.=20267624=20Log:=20=20=20syscons(4)?= =?UTF-8?q?=20and=20vt(4)=20can=20be=20built=20together=20now.=20267625=20?= =?UTF-8?q?Log:=20=20=20Allow=20to=20disable=20syscons(4)=20if=20"hw.sysco?= =?UTF-8?q?ns.disable"=20kenv=20is=20set.=20267626=20Log:=20=20=20Suspend?= =?UTF-8?q?=20vt(4)=20initialization=20if=20"kern.vt.disable"=20kenv=20is?= =?UTF-8?q?=20set.=20267965=20by=20emaste@=20Log:=20=20=20Use=20a=20common?= =?UTF-8?q?=20tunable=20to=20choose=20between=20vt(4)/sc(4)=20=20=20With?= =?UTF-8?q?=20this=20change=20and=20previous=20work=20from=20ray@=20it=20w?= =?UTF-8?q?ill=20be=20possible=20to=20put=20=20=20both=20in=20GENERIC,=20a?= =?UTF-8?q?nd=20have=20one=20enabled=20by=20default,=20but=20allow=20the?= =?UTF-8?q?=20other=20to=20=20=20be=20selected=20via=20the=20loader.=20=20?= =?UTF-8?q?=20(The=20previous=20implementation=20had=20separate=20kern.vt.?= =?UTF-8?q?disable=20and=20=20=20hw.syscons.disable=20tunables,=20and=20wo?= =?UTF-8?q?uld=20panic=20if=20both=20drivers=20were=20=20=20compiled=20in?= =?UTF-8?q?=20and=20neither=20was=20explicitly=20disabled.)=20268175=20by?= =?UTF-8?q?=20emaste@=20Log:=20=20=20Fix=20vt(4)=20detection=20in=20kbdcon?= =?UTF-8?q?trol=20and=20vidcontrol=20=20=20As=20sc(4)=20and=20vt(4)=20coex?= =?UTF-8?q?ist=20and=20are=20both=20enabled=20in=20GENERIC,=20the=20existe?= =?UTF-8?q?nce=20=20=20of=20a=20vt(4)=20sysctl=20is=20not=20sufficient=20t?= =?UTF-8?q?o=20determine=20that=20vt(4)=20is=20in=20use.=20=20=20Reported?= =?UTF-8?q?=20by:=20=20Trond=20Endrest=C3=B8l=20268045=20by=20emaste@=20Lo?= =?UTF-8?q?g:=20=20=20Add=20vt(4)=20to=20GENERIC=20and=20retire=20the=20se?= =?UTF-8?q?parate=20VT=20config=20=20=20vt(4)=20and=20sc(4)=20can=20now=20?= =?UTF-8?q?coexist=20in=20the=20same=20kernel.=20=20To=20choose=20the=20vt?= =?UTF-8?q?=20=20=20driver,=20set=20the=20loader=20tunable=20kern.vty=3Dvt?= =?UTF-8?q?=20.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sponsored by: The FreeBSD Foundation --- sys/dev/vt/hw/vga/vga.c | 690 ----------------------------------------- sys/dev/vt/hw/vga/vga_reg.h | 220 ------------- sys/dev/vt/hw/vga/vt_vga.c | 690 +++++++++++++++++++++++++++++++++++++++++ sys/dev/vt/hw/vga/vt_vga_reg.h | 220 +++++++++++++ sys/dev/vt/vt.h | 5 - sys/dev/vt/vt_consolectl.c | 2 + sys/dev/vt/vt_core.c | 11 + sys/dev/vt/vt_sysmouse.c | 2 + 8 files changed, 925 insertions(+), 915 deletions(-) delete mode 100644 sys/dev/vt/hw/vga/vga.c delete mode 100644 sys/dev/vt/hw/vga/vga_reg.h create mode 100644 sys/dev/vt/hw/vga/vt_vga.c create mode 100644 sys/dev/vt/hw/vga/vt_vga_reg.h (limited to 'sys/dev/vt') diff --git a/sys/dev/vt/hw/vga/vga.c b/sys/dev/vt/hw/vga/vga.c deleted file mode 100644 index a13e094..0000000 --- a/sys/dev/vt/hw/vga/vga.c +++ /dev/null @@ -1,690 +0,0 @@ -/*- - * Copyright (c) 2005 Marcel Moolenaar - * All rights reserved. - * - * Copyright (c) 2009 The FreeBSD Foundation - * All rights reserved. - * - * Portions of this software were developed by Ed Schouten - * under sponsorship from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include - -#include -#include - -#include - -#if defined(__amd64__) || defined(__i386__) -#include -#include -#include -#include -#endif /* __amd64__ || __i386__ */ - -struct vga_softc { - bus_space_tag_t vga_fb_tag; - bus_space_handle_t vga_fb_handle; - bus_space_tag_t vga_reg_tag; - bus_space_handle_t vga_reg_handle; - int vga_curcolor; -}; - -/* Convenience macros. */ -#define MEM_READ1(sc, ofs) \ - bus_space_read_1(sc->vga_fb_tag, sc->vga_fb_handle, ofs) -#define MEM_WRITE1(sc, ofs, val) \ - bus_space_write_1(sc->vga_fb_tag, sc->vga_fb_handle, ofs, val) -#define REG_READ1(sc, reg) \ - bus_space_read_1(sc->vga_reg_tag, sc->vga_reg_handle, reg) -#define REG_WRITE1(sc, reg, val) \ - bus_space_write_1(sc->vga_reg_tag, sc->vga_reg_handle, reg, val) - -#define VT_VGA_WIDTH 640 -#define VT_VGA_HEIGHT 480 -#define VT_VGA_MEMSIZE (VT_VGA_WIDTH * VT_VGA_HEIGHT / 8) - -static vd_probe_t vga_probe; -static vd_init_t vga_init; -static vd_blank_t vga_blank; -static vd_bitbltchr_t vga_bitbltchr; -static vd_maskbitbltchr_t vga_maskbitbltchr; -static vd_drawrect_t vga_drawrect; -static vd_setpixel_t vga_setpixel; -static vd_putchar_t vga_putchar; -static vd_postswitch_t vga_postswitch; - -static const struct vt_driver vt_vga_driver = { - .vd_name = "vga", - .vd_probe = vga_probe, - .vd_init = vga_init, - .vd_blank = vga_blank, - .vd_bitbltchr = vga_bitbltchr, - .vd_maskbitbltchr = vga_maskbitbltchr, - .vd_drawrect = vga_drawrect, - .vd_setpixel = vga_setpixel, - .vd_putchar = vga_putchar, - .vd_postswitch = vga_postswitch, - .vd_priority = VD_PRIORITY_GENERIC, -}; - -/* - * Driver supports both text mode and graphics mode. Make sure the - * buffer is always big enough to support both. - */ -static struct vga_softc vga_conssoftc; -VT_DRIVER_DECLARE(vt_vga, vt_vga_driver); - -static inline void -vga_setcolor(struct vt_device *vd, term_color_t color) -{ - struct vga_softc *sc = vd->vd_softc; - - if (sc->vga_curcolor != color) { - REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_SET_RESET); - REG_WRITE1(sc, VGA_GC_DATA, color); - sc->vga_curcolor = color; - } -} - -static void -vga_blank(struct vt_device *vd, term_color_t color) -{ - struct vga_softc *sc = vd->vd_softc; - u_int ofs; - - vga_setcolor(vd, color); - for (ofs = 0; ofs < VT_VGA_MEMSIZE; ofs++) - MEM_WRITE1(sc, ofs, 0xff); -} - -static inline void -vga_bitblt_put(struct vt_device *vd, u_long dst, term_color_t color, - uint8_t v) -{ - struct vga_softc *sc = vd->vd_softc; - - /* Skip empty writes, in order to avoid palette changes. */ - if (v != 0x00) { - vga_setcolor(vd, color); - /* - * When this MEM_READ1() gets disabled, all sorts of - * artifacts occur. This is because this read loads the - * set of 8 pixels that are about to be changed. There - * is one scenario where we can avoid the read, namely - * if all pixels are about to be overwritten anyway. - */ - if (v != 0xff) - MEM_READ1(sc, dst); - MEM_WRITE1(sc, dst, v); - } -} - -static void -vga_setpixel(struct vt_device *vd, int x, int y, term_color_t color) -{ - - vga_bitblt_put(vd, (y * VT_VGA_WIDTH / 8) + (x / 8), color, - 0x80 >> (x % 8)); -} - -static void -vga_drawrect(struct vt_device *vd, int x1, int y1, int x2, int y2, int fill, - term_color_t color) -{ - int x, y; - - for (y = y1; y <= y2; y++) { - if (fill || (y == y1) || (y == y2)) { - for (x = x1; x <= x2; x++) - vga_setpixel(vd, x, y, color); - } else { - vga_setpixel(vd, x1, y, color); - vga_setpixel(vd, x2, y, color); - } - } -} - -static inline void -vga_bitblt_draw(struct vt_device *vd, const uint8_t *src, - u_long ldst, uint8_t shift, unsigned int width, unsigned int height, - term_color_t color, int negate) -{ - u_long dst; - int w; - uint8_t b, r, out; - - for (; height > 0; height--) { - dst = ldst; - ldst += VT_VGA_WIDTH / 8; - r = 0; - for (w = width; w > 0; w -= 8) { - b = *src++; - if (negate) { - b = ~b; - /* Don't go too far. */ - if (w < 8) - b &= 0xff << (8 - w); - } - /* Reintroduce bits from previous column. */ - out = (b >> shift) | r; - r = b << (8 - shift); - vga_bitblt_put(vd, dst++, color, out); - } - /* Print the remainder. */ - vga_bitblt_put(vd, dst, color, r); - } -} - -static void -vga_bitbltchr(struct vt_device *vd, const uint8_t *src, const uint8_t *mask, - int bpl, vt_axis_t top, vt_axis_t left, unsigned int width, - unsigned int height, term_color_t fg, term_color_t bg) -{ - u_long dst, ldst; - int w; - - /* Don't try to put off screen pixels */ - if (((left + width) > VT_VGA_WIDTH) || ((top + height) > - VT_VGA_HEIGHT)) - return; - - dst = (VT_VGA_WIDTH * top + left) / 8; - - for (; height > 0; height--) { - ldst = dst; - for (w = width; w > 0; w -= 8) { - vga_bitblt_put(vd, ldst, fg, *src); - vga_bitblt_put(vd, ldst, bg, ~*src); - ldst++; - src++; - } - dst += VT_VGA_WIDTH / 8; - } -} - -/* Bitblt with mask support. Slow. */ -static void -vga_maskbitbltchr(struct vt_device *vd, const uint8_t *src, const uint8_t *mask, - int bpl, vt_axis_t top, vt_axis_t left, unsigned int width, - unsigned int height, term_color_t fg, term_color_t bg) -{ - struct vga_softc *sc = vd->vd_softc; - u_long dst; - uint8_t shift; - - dst = (VT_VGA_WIDTH * top + left) / 8; - shift = left % 8; - - /* Don't try to put off screen pixels */ - if (((left + width) > VT_VGA_WIDTH) || ((top + height) > - VT_VGA_HEIGHT)) - return; - - if (sc->vga_curcolor == fg) { - vga_bitblt_draw(vd, src, dst, shift, width, height, fg, 0); - vga_bitblt_draw(vd, src, dst, shift, width, height, bg, 1); - } else { - vga_bitblt_draw(vd, src, dst, shift, width, height, bg, 1); - vga_bitblt_draw(vd, src, dst, shift, width, height, fg, 0); - } -} - -/* - * Binary searchable table for Unicode to CP437 conversion. - */ - -struct unicp437 { - uint16_t unicode_base; - uint8_t cp437_base; - uint8_t length; -}; - -static const struct unicp437 cp437table[] = { - { 0x0020, 0x20, 0x5e }, { 0x00a0, 0x20, 0x00 }, - { 0x00a1, 0xad, 0x00 }, { 0x00a2, 0x9b, 0x00 }, - { 0x00a3, 0x9c, 0x00 }, { 0x00a5, 0x9d, 0x00 }, - { 0x00a7, 0x15, 0x00 }, { 0x00aa, 0xa6, 0x00 }, - { 0x00ab, 0xae, 0x00 }, { 0x00ac, 0xaa, 0x00 }, - { 0x00b0, 0xf8, 0x00 }, { 0x00b1, 0xf1, 0x00 }, - { 0x00b2, 0xfd, 0x00 }, { 0x00b5, 0xe6, 0x00 }, - { 0x00b6, 0x14, 0x00 }, { 0x00b7, 0xfa, 0x00 }, - { 0x00ba, 0xa7, 0x00 }, { 0x00bb, 0xaf, 0x00 }, - { 0x00bc, 0xac, 0x00 }, { 0x00bd, 0xab, 0x00 }, - { 0x00bf, 0xa8, 0x00 }, { 0x00c4, 0x8e, 0x01 }, - { 0x00c6, 0x92, 0x00 }, { 0x00c7, 0x80, 0x00 }, - { 0x00c9, 0x90, 0x00 }, { 0x00d1, 0xa5, 0x00 }, - { 0x00d6, 0x99, 0x00 }, { 0x00dc, 0x9a, 0x00 }, - { 0x00df, 0xe1, 0x00 }, { 0x00e0, 0x85, 0x00 }, - { 0x00e1, 0xa0, 0x00 }, { 0x00e2, 0x83, 0x00 }, - { 0x00e4, 0x84, 0x00 }, { 0x00e5, 0x86, 0x00 }, - { 0x00e6, 0x91, 0x00 }, { 0x00e7, 0x87, 0x00 }, - { 0x00e8, 0x8a, 0x00 }, { 0x00e9, 0x82, 0x00 }, - { 0x00ea, 0x88, 0x01 }, { 0x00ec, 0x8d, 0x00 }, - { 0x00ed, 0xa1, 0x00 }, { 0x00ee, 0x8c, 0x00 }, - { 0x00ef, 0x8b, 0x00 }, { 0x00f0, 0xeb, 0x00 }, - { 0x00f1, 0xa4, 0x00 }, { 0x00f2, 0x95, 0x00 }, - { 0x00f3, 0xa2, 0x00 }, { 0x00f4, 0x93, 0x00 }, - { 0x00f6, 0x94, 0x00 }, { 0x00f7, 0xf6, 0x00 }, - { 0x00f8, 0xed, 0x00 }, { 0x00f9, 0x97, 0x00 }, - { 0x00fa, 0xa3, 0x00 }, { 0x00fb, 0x96, 0x00 }, - { 0x00fc, 0x81, 0x00 }, { 0x00ff, 0x98, 0x00 }, - { 0x0192, 0x9f, 0x00 }, { 0x0393, 0xe2, 0x00 }, - { 0x0398, 0xe9, 0x00 }, { 0x03a3, 0xe4, 0x00 }, - { 0x03a6, 0xe8, 0x00 }, { 0x03a9, 0xea, 0x00 }, - { 0x03b1, 0xe0, 0x01 }, { 0x03b4, 0xeb, 0x00 }, - { 0x03b5, 0xee, 0x00 }, { 0x03bc, 0xe6, 0x00 }, - { 0x03c0, 0xe3, 0x00 }, { 0x03c3, 0xe5, 0x00 }, - { 0x03c4, 0xe7, 0x00 }, { 0x03c6, 0xed, 0x00 }, - { 0x03d5, 0xed, 0x00 }, { 0x2010, 0x2d, 0x00 }, - { 0x2014, 0x2d, 0x00 }, { 0x2018, 0x60, 0x00 }, - { 0x2019, 0x27, 0x00 }, { 0x201c, 0x22, 0x00 }, - { 0x201d, 0x22, 0x00 }, { 0x2022, 0x07, 0x00 }, - { 0x203c, 0x13, 0x00 }, { 0x207f, 0xfc, 0x00 }, - { 0x20a7, 0x9e, 0x00 }, { 0x20ac, 0xee, 0x00 }, - { 0x2126, 0xea, 0x00 }, { 0x2190, 0x1b, 0x00 }, - { 0x2191, 0x18, 0x00 }, { 0x2192, 0x1a, 0x00 }, - { 0x2193, 0x19, 0x00 }, { 0x2194, 0x1d, 0x00 }, - { 0x2195, 0x12, 0x00 }, { 0x21a8, 0x17, 0x00 }, - { 0x2202, 0xeb, 0x00 }, { 0x2208, 0xee, 0x00 }, - { 0x2211, 0xe4, 0x00 }, { 0x2212, 0x2d, 0x00 }, - { 0x2219, 0xf9, 0x00 }, { 0x221a, 0xfb, 0x00 }, - { 0x221e, 0xec, 0x00 }, { 0x221f, 0x1c, 0x00 }, - { 0x2229, 0xef, 0x00 }, { 0x2248, 0xf7, 0x00 }, - { 0x2261, 0xf0, 0x00 }, { 0x2264, 0xf3, 0x00 }, - { 0x2265, 0xf2, 0x00 }, { 0x2302, 0x7f, 0x00 }, - { 0x2310, 0xa9, 0x00 }, { 0x2320, 0xf4, 0x00 }, - { 0x2321, 0xf5, 0x00 }, { 0x2500, 0xc4, 0x00 }, - { 0x2502, 0xb3, 0x00 }, { 0x250c, 0xda, 0x00 }, - { 0x2510, 0xbf, 0x00 }, { 0x2514, 0xc0, 0x00 }, - { 0x2518, 0xd9, 0x00 }, { 0x251c, 0xc3, 0x00 }, - { 0x2524, 0xb4, 0x00 }, { 0x252c, 0xc2, 0x00 }, - { 0x2534, 0xc1, 0x00 }, { 0x253c, 0xc5, 0x00 }, - { 0x2550, 0xcd, 0x00 }, { 0x2551, 0xba, 0x00 }, - { 0x2552, 0xd5, 0x00 }, { 0x2553, 0xd6, 0x00 }, - { 0x2554, 0xc9, 0x00 }, { 0x2555, 0xb8, 0x00 }, - { 0x2556, 0xb7, 0x00 }, { 0x2557, 0xbb, 0x00 }, - { 0x2558, 0xd4, 0x00 }, { 0x2559, 0xd3, 0x00 }, - { 0x255a, 0xc8, 0x00 }, { 0x255b, 0xbe, 0x00 }, - { 0x255c, 0xbd, 0x00 }, { 0x255d, 0xbc, 0x00 }, - { 0x255e, 0xc6, 0x01 }, { 0x2560, 0xcc, 0x00 }, - { 0x2561, 0xb5, 0x00 }, { 0x2562, 0xb6, 0x00 }, - { 0x2563, 0xb9, 0x00 }, { 0x2564, 0xd1, 0x01 }, - { 0x2566, 0xcb, 0x00 }, { 0x2567, 0xcf, 0x00 }, - { 0x2568, 0xd0, 0x00 }, { 0x2569, 0xca, 0x00 }, - { 0x256a, 0xd8, 0x00 }, { 0x256b, 0xd7, 0x00 }, - { 0x256c, 0xce, 0x00 }, { 0x2580, 0xdf, 0x00 }, - { 0x2584, 0xdc, 0x00 }, { 0x2588, 0xdb, 0x00 }, - { 0x258c, 0xdd, 0x00 }, { 0x2590, 0xde, 0x00 }, - { 0x2591, 0xb0, 0x02 }, { 0x25a0, 0xfe, 0x00 }, - { 0x25ac, 0x16, 0x00 }, { 0x25b2, 0x1e, 0x00 }, - { 0x25ba, 0x10, 0x00 }, { 0x25bc, 0x1f, 0x00 }, - { 0x25c4, 0x11, 0x00 }, { 0x25cb, 0x09, 0x00 }, - { 0x25d8, 0x08, 0x00 }, { 0x25d9, 0x0a, 0x00 }, - { 0x263a, 0x01, 0x01 }, { 0x263c, 0x0f, 0x00 }, - { 0x2640, 0x0c, 0x00 }, { 0x2642, 0x0b, 0x00 }, - { 0x2660, 0x06, 0x00 }, { 0x2663, 0x05, 0x00 }, - { 0x2665, 0x03, 0x01 }, { 0x266a, 0x0d, 0x00 }, - { 0x266c, 0x0e, 0x00 }, -}; - -static uint8_t -vga_get_cp437(term_char_t c) -{ - int min, mid, max; - - min = 0; - max = (sizeof(cp437table) / sizeof(struct unicp437)) - 1; - - if (c < cp437table[0].unicode_base || - c > cp437table[max].unicode_base + cp437table[max].length) - return '?'; - - while (max >= min) { - mid = (min + max) / 2; - if (c < cp437table[mid].unicode_base) - max = mid - 1; - else if (c > cp437table[mid].unicode_base + - cp437table[mid].length) - min = mid + 1; - else - return (c - cp437table[mid].unicode_base + - cp437table[mid].cp437_base); - } - - return '?'; -} - -static void -vga_putchar(struct vt_device *vd, term_char_t c, - vt_axis_t top, vt_axis_t left, term_color_t fg, term_color_t bg) -{ - struct vga_softc *sc = vd->vd_softc; - uint8_t ch, attr; - - /* - * Convert character to CP437, which is the character set used - * by the VGA hardware by default. - */ - ch = vga_get_cp437(c); - - /* - * Convert colors to VGA attributes. - */ - attr = bg << 4 | fg; - - MEM_WRITE1(sc, 0x18000 + (top * 80 + left) * 2 + 0, ch); - MEM_WRITE1(sc, 0x18000 + (top * 80 + left) * 2 + 1, attr); -} - -static void -vga_initialize_graphics(struct vt_device *vd) -{ - struct vga_softc *sc = vd->vd_softc; - - /* Clock select. */ - REG_WRITE1(sc, VGA_GEN_MISC_OUTPUT_W, VGA_GEN_MO_VSP | VGA_GEN_MO_HSP | - VGA_GEN_MO_PB | VGA_GEN_MO_ER | VGA_GEN_MO_IOA); - /* Set sequencer clocking and memory mode. */ - REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_CLOCKING_MODE); - REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_CM_89); - REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MEMORY_MODE); - REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_MM_OE | VGA_SEQ_MM_EM); - - /* Set the graphics controller in graphics mode. */ - REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_MISCELLANEOUS); - REG_WRITE1(sc, VGA_GC_DATA, 0x04 + VGA_GC_MISC_GA); - /* Program the CRT controller. */ - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_HORIZ_TOTAL); - REG_WRITE1(sc, VGA_CRTC_DATA, 0x5f); /* 760 */ - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_HORIZ_DISP_END); - REG_WRITE1(sc, VGA_CRTC_DATA, 0x4f); /* 640 - 8 */ - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_HORIZ_BLANK); - REG_WRITE1(sc, VGA_CRTC_DATA, 0x50); /* 640 */ - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_HORIZ_BLANK); - REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_EHB_CR + 2); - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_HORIZ_RETRACE); - REG_WRITE1(sc, VGA_CRTC_DATA, 0x54); /* 672 */ - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_HORIZ_RETRACE); - REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_EHR_EHB + 0); - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_TOTAL); - REG_WRITE1(sc, VGA_CRTC_DATA, 0x0b); /* 523 */ - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_OVERFLOW); - REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_OF_VT9 | VGA_CRTC_OF_LC8 | - VGA_CRTC_OF_VBS8 | VGA_CRTC_OF_VRS8 | VGA_CRTC_OF_VDE8); - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MAX_SCAN_LINE); - REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_MSL_LC9); - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_START); - REG_WRITE1(sc, VGA_CRTC_DATA, 0xea); /* 480 + 10 */ - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_END); - REG_WRITE1(sc, VGA_CRTC_DATA, 0x0c); - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_DISPLAY_END); - REG_WRITE1(sc, VGA_CRTC_DATA, 0xdf); /* 480 - 1*/ - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_OFFSET); - REG_WRITE1(sc, VGA_CRTC_DATA, 0x28); - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_VERT_BLANK); - REG_WRITE1(sc, VGA_CRTC_DATA, 0xe7); /* 480 + 7 */ - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_VERT_BLANK); - REG_WRITE1(sc, VGA_CRTC_DATA, 0x04); - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL); - REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_MC_WB | VGA_CRTC_MC_AW | - VGA_CRTC_MC_SRS | VGA_CRTC_MC_CMS); - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_LINE_COMPARE); - REG_WRITE1(sc, VGA_CRTC_DATA, 0xff); /* 480 + 31 */ - - REG_WRITE1(sc, VGA_GEN_FEATURE_CTRL_W, 0); - - REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MAP_MASK); - REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_MM_EM3 | VGA_SEQ_MM_EM2 | - VGA_SEQ_MM_EM1 | VGA_SEQ_MM_EM0); - REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_CHAR_MAP_SELECT); - REG_WRITE1(sc, VGA_SEQ_DATA, 0); - - REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_SET_RESET); - REG_WRITE1(sc, VGA_GC_DATA, 0); - REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_ENABLE_SET_RESET); - REG_WRITE1(sc, VGA_GC_DATA, 0x0f); - REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_COLOR_COMPARE); - REG_WRITE1(sc, VGA_GC_DATA, 0); - REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_DATA_ROTATE); - REG_WRITE1(sc, VGA_GC_DATA, 0); - REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_READ_MAP_SELECT); - REG_WRITE1(sc, VGA_GC_DATA, 0); - REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_MODE); - REG_WRITE1(sc, VGA_GC_DATA, 0); - REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_COLOR_DONT_CARE); - REG_WRITE1(sc, VGA_GC_DATA, 0x0f); - REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_BIT_MASK); - REG_WRITE1(sc, VGA_GC_DATA, 0xff); -} - -static void -vga_initialize(struct vt_device *vd, int textmode) -{ - struct vga_softc *sc = vd->vd_softc; - uint8_t x; - - /* Make sure the VGA adapter is not in monochrome emulation mode. */ - x = REG_READ1(sc, VGA_GEN_MISC_OUTPUT_R); - REG_WRITE1(sc, VGA_GEN_MISC_OUTPUT_W, x | VGA_GEN_MO_IOA); - - /* Unprotect CRTC registers 0-7. */ - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_END); - x = REG_READ1(sc, VGA_CRTC_DATA); - REG_WRITE1(sc, VGA_CRTC_DATA, x & ~VGA_CRTC_VRE_PR); - - /* - * Wait for the vertical retrace. - * NOTE: this code reads the VGA_GEN_INPUT_STAT_1 register, which has - * the side-effect of clearing the internal flip-flip of the attribute - * controller's write register. This means that because this code is - * here, we know for sure that the first write to the attribute - * controller will be a write to the address register. Removing this - * code therefore also removes that guarantee and appropriate measures - * need to be taken. - */ - do { - x = REG_READ1(sc, VGA_GEN_INPUT_STAT_1); - x &= VGA_GEN_IS1_VR | VGA_GEN_IS1_DE; - } while (x != (VGA_GEN_IS1_VR | VGA_GEN_IS1_DE)); - - /* Now, disable the sync. signals. */ - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL); - x = REG_READ1(sc, VGA_CRTC_DATA); - REG_WRITE1(sc, VGA_CRTC_DATA, x & ~VGA_CRTC_MC_HR); - - /* Asynchronous sequencer reset. */ - REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_RESET); - REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_RST_SR); - - if (!textmode) - vga_initialize_graphics(vd); - - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_PRESET_ROW_SCAN); - REG_WRITE1(sc, VGA_CRTC_DATA, 0); - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_START); - REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_CS_COO); - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_END); - REG_WRITE1(sc, VGA_CRTC_DATA, 0); - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_ADDR_HIGH); - REG_WRITE1(sc, VGA_CRTC_DATA, 0); - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_ADDR_LOW); - REG_WRITE1(sc, VGA_CRTC_DATA, 0); - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_LOC_HIGH); - REG_WRITE1(sc, VGA_CRTC_DATA, 0); - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_LOC_LOW); - REG_WRITE1(sc, VGA_CRTC_DATA, 0x59); - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_UNDERLINE_LOC); - REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_UL_UL); - - if (textmode) { - /* Set the attribute controller to blink disable. */ - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_MODE_CONTROL); - REG_WRITE1(sc, VGA_AC_WRITE, 0); - } else { - /* Set the attribute controller in graphics mode. */ - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_MODE_CONTROL); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_MC_GA); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_HORIZ_PIXEL_PANNING); - REG_WRITE1(sc, VGA_AC_WRITE, 0); - } - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(0)); - REG_WRITE1(sc, VGA_AC_WRITE, 0); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(1)); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_R); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(2)); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_G); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(3)); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SG | VGA_AC_PAL_R); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(4)); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_B); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(5)); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_R | VGA_AC_PAL_B); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(6)); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_G | VGA_AC_PAL_B); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(7)); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_R | VGA_AC_PAL_G | VGA_AC_PAL_B); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(8)); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | - VGA_AC_PAL_SB); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(9)); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | - VGA_AC_PAL_SB | VGA_AC_PAL_R); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(10)); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | - VGA_AC_PAL_SB | VGA_AC_PAL_G); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(11)); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | - VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_G); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(12)); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | - VGA_AC_PAL_SB | VGA_AC_PAL_B); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(13)); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | - VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_B); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(14)); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | - VGA_AC_PAL_SB | VGA_AC_PAL_G | VGA_AC_PAL_B); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(15)); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | - VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_G | VGA_AC_PAL_B); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_OVERSCAN_COLOR); - REG_WRITE1(sc, VGA_AC_WRITE, 0); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_COLOR_PLANE_ENABLE); - REG_WRITE1(sc, VGA_AC_WRITE, 0x0f); - REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_COLOR_SELECT); - REG_WRITE1(sc, VGA_AC_WRITE, 0); - - if (!textmode) { - u_int ofs; - - /* - * Done. Clear the frame buffer. All bit planes are - * enabled, so a single-paged loop should clear all - * planes. - */ - for (ofs = 0; ofs < VT_VGA_MEMSIZE; ofs++) { - MEM_READ1(sc, ofs); - MEM_WRITE1(sc, ofs, 0); - } - } - - /* Re-enable the sequencer. */ - REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_RESET); - REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_RST_SR | VGA_SEQ_RST_NAR); - /* Re-enable the sync signals. */ - REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL); - x = REG_READ1(sc, VGA_CRTC_DATA); - REG_WRITE1(sc, VGA_CRTC_DATA, x | VGA_CRTC_MC_HR); - - if (!textmode) { - /* Switch to write mode 3, because we'll mainly do bitblt. */ - REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_MODE); - REG_WRITE1(sc, VGA_GC_DATA, 3); - REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_ENABLE_SET_RESET); - REG_WRITE1(sc, VGA_GC_DATA, 0x0f); - } -} - -static int -vga_probe(struct vt_device *vd) -{ - - return (CN_INTERNAL); -} - -static int -vga_init(struct vt_device *vd) -{ - struct vga_softc *sc; - int textmode; - - if (vd->vd_softc == NULL) - vd->vd_softc = (void *)&vga_conssoftc; - sc = vd->vd_softc; - textmode = 0; - -#if defined(__amd64__) || defined(__i386__) - sc->vga_fb_tag = X86_BUS_SPACE_MEM; - sc->vga_fb_handle = KERNBASE + VGA_MEM_BASE; - sc->vga_reg_tag = X86_BUS_SPACE_IO; - sc->vga_reg_handle = VGA_REG_BASE; -#elif defined(__ia64__) - sc->vga_fb_tag = IA64_BUS_SPACE_MEM; - sc->vga_fb_handle = IA64_PHYS_TO_RR6(VGA_MEM_BASE); - sc->vga_reg_tag = IA64_BUS_SPACE_IO; - sc->vga_reg_handle = VGA_REG_BASE; -#else -# error "Architecture not yet supported!" -#endif - - TUNABLE_INT_FETCH("hw.vga.textmode", &textmode); - if (textmode) { - vd->vd_flags |= VDF_TEXTMODE; - vd->vd_width = 80; - vd->vd_height = 25; - } else { - vd->vd_width = VT_VGA_WIDTH; - vd->vd_height = VT_VGA_HEIGHT; - } - vga_initialize(vd, textmode); - - return (CN_INTERNAL); -} - -static void -vga_postswitch(struct vt_device *vd) -{ - - /* Reinit VGA mode, to restore view after app which change mode. */ - vga_initialize(vd, (vd->vd_flags & VDF_TEXTMODE)); - /* Ask vt(9) to update chars on visible area. */ - vd->vd_flags |= VDF_INVALID; -} diff --git a/sys/dev/vt/hw/vga/vga_reg.h b/sys/dev/vt/hw/vga/vga_reg.h deleted file mode 100644 index 5bfb8ce..0000000 --- a/sys/dev/vt/hw/vga/vga_reg.h +++ /dev/null @@ -1,220 +0,0 @@ -/*- - * Copyright (c) 2005 Marcel Moolenaar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#ifndef _DEV_VT_HW_VGA_VGA_REG_H_ -#define _DEV_VT_HW_VGA_VGA_REG_H_ - -/* - * The VGA adapter uses two I/O port blocks. One of these blocks, the CRT - * controller registers, can be located either at 0x3B0 or at 0x3D0 in I/O - * port space. This allows compatibility with the monochrome adapter, which - * has the CRT controller registers at 0x3B0. - * - * It is assumed that compatibility with the monochrome adapter is not of - * interest anymore. As such, the CRT controller can be located at 0x3D0 in - * I/O port space unconditionally. This means that the 2 I/O blocks are - * always adjacent and can therefore be treated as a single logical I/O port - * range. In practical terms: there only has to be a single tag and handle - * to access all registers. - * - * The following definitions are taken from or inspired by: - * Programmer's Guide to the EGA, VGA, and Super VGA Cards -- 3rd ed., - * Richard F. Ferraro, Addison-Wesley, ISBN 0-201-62490-7 - */ - -#define VGA_MEM_BASE 0xA0000 -#define VGA_MEM_SIZE 0x10000 -#define VGA_REG_BASE 0x3c0 -#define VGA_REG_SIZE 0x10+0x0c - -/* Attribute controller registers. */ -#define VGA_AC_WRITE 0x00 -#define VGA_AC_READ 0x01 -#define VGA_AC_PALETTE(x) (x) /* 0 <= x <= 15 */ -#define VGA_AC_PAL_SR 0x20 /* Secondary red */ -#define VGA_AC_PAL_SG 0x10 /* Secondary green */ -#define VGA_AC_PAL_SB 0x08 /* Secondary blue */ -#define VGA_AC_PAL_R 0x04 /* Red */ -#define VGA_AC_PAL_G 0x02 /* Green */ -#define VGA_AC_PAL_B 0x01 /* Blue */ -#define VGA_AC_MODE_CONTROL (32+16) -#define VGA_AC_MC_IPS 0x80 /* Internal palette size */ -#define VGA_AC_MC_PCS 0x40 /* Pixel clock select */ -#define VGA_AC_MC_PPC 0x20 /* Pixel panning compat. */ -#define VGA_AC_MC_BI 0x08 /* Blink/intensity */ -#define VGA_AC_MC_ELG 0x04 /* Enable line graphics cc. */ -#define VGA_AC_MC_DT 0x02 /* Display type */ -#define VGA_AC_MC_GA 0x01 /* Graphics/alphanumeric */ -#define VGA_AC_OVERSCAN_COLOR (32+17) -#define VGA_AC_COLOR_PLANE_ENABLE (32+18) -#define VGA_AC_HORIZ_PIXEL_PANNING (32+19) -#define VGA_AC_COLOR_SELECT (32+20) -#define VGA_AC_CS_C67 0x0C /* Color reg. addr. bits 6+7 */ -#define VGA_AC_CS_C45 0x03 /* Color reg. addr. bits 4+5 */ - -/* General registers. */ -#define VGA_GEN_MISC_OUTPUT_W 0x02 /* Write only. */ -#define VGA_GEN_MISC_OUTPUT_R 0x0c /* Read only. */ -#define VGA_GEN_MO_VSP 0x80 /* Vertical sync. polarity */ -#define VGA_GEN_MO_HSP 0x40 /* Horiz. sync. polarity */ -#define VGA_GEN_MO_PB 0x20 /* Page bit for odd/even */ -#define VGA_GEN_MO_CS 0x0C /* Clock select */ -#define VGA_GEN_MO_ER 0x02 /* Enable RAM */ -#define VGA_GEN_MO_IOA 0x01 /* Input/output address */ -#define VGA_GEN_INPUT_STAT_0 0x02 /* Read only. */ -#define VGA_GEN_FEATURE_CTRL_W 0x1a /* Write only. */ -#define VGA_GEN_FEATURE_CTRL_R 0x0a /* Read only. */ -#define VGA_GEN_INPUT_STAT_1 0x1a /* Read only. */ -#define VGA_GEN_IS1_VR 0x08 /* Vertical retrace */ -#define VGA_GEN_IS1_DE 0x01 /* Display enable not */ - -/* Sequencer registers. */ -#define VGA_SEQ_ADDRESS 0x04 -#define VGA_SEQ_RESET 0 -#define VGA_SEQ_RST_SR 0x02 /* Synchronous reset */ -#define VGA_SEQ_RST_NAR 0x01 /* No async. reset */ -#define VGA_SEQ_CLOCKING_MODE 1 -#define VGA_SEQ_CM_SO 0x20 /* Screen off */ -#define VGA_SEQ_CM_S4 0x10 /* Shift four */ -#define VGA_SEQ_CM_DC 0x08 /* Dot clock */ -#define VGA_SEQ_CM_SL 0x04 /* Shift load */ -#define VGA_SEQ_CM_89 0x01 /* 8/9 Dot clocks */ -#define VGA_SEQ_MAP_MASK 2 -#define VGA_SEQ_MM_EM3 0x08 /* Enable memory plane 3 */ -#define VGA_SEQ_MM_EM2 0x04 /* Enable memory plane 2 */ -#define VGA_SEQ_MM_EM1 0x02 /* Enable memory plane 1 */ -#define VGA_SEQ_MM_EM0 0x01 /* Enable memory plane 0 */ -#define VGA_SEQ_CHAR_MAP_SELECT 3 -#define VGA_SEQ_CMS_SAH 0x20 /* Char. A (bit 2) */ -#define VGA_SEQ_CMS_SBH 0x10 /* Char. B (bit 2) */ -#define VGA_SEQ_CMS_SA 0x0C /* Char. A (bit 0+1) */ -#define VGA_SEQ_CMS_SB 0x03 /* Char. B (bit 0+1) */ -#define VGA_SEQ_MEMORY_MODE 4 -#define VGA_SEQ_MM_C4 0x08 /* Chain four */ -#define VGA_SEQ_MM_OE 0x04 /* Odd/even */ -#define VGA_SEQ_MM_EM 0x02 /* Extended memory */ -#define VGA_SEQ_DATA 0x05 - -/* Color registers. */ -#define VGA_PEL_MASK 0x06 -#define VGA_PEL_ADDR_RD_MODE 0x07 /* Write only. */ -#define VGA_DAC_STATE 0x07 /* Read only. */ -#define VGA_PEL_ADDR_WR_MODE 0x08 -#define VGA_PEL_DATA 0x09 - -/* Graphics controller registers. */ -#define VGA_GC_ADDRESS 0x0e -#define VGA_GC_SET_RESET 0 -#define VGA_GC_ENABLE_SET_RESET 1 -#define VGA_GC_COLOR_COMPARE 2 -#define VGA_GC_DATA_ROTATE 3 -#define VGA_GC_DR_FS_XOR 0x18 /* Function select - XOR */ -#define VGA_GC_DR_FS_OR 0x10 /* Function select - OR */ -#define VGA_GC_DR_FS_AND 0x08 /* Function select - AND */ -#define VGA_GC_DR_RC 0x07 /* Rotate count */ -#define VGA_GC_READ_MAP_SELECT 4 -#define VGA_GC_MODE 5 -#define VGA_GC_MODE_SR 0x60 /* Shift register */ -#define VGA_GC_MODE_OE 0x10 /* Odd/even */ -#define VGA_GC_MODE_RM 0x08 /* Read mode */ -#define VGA_GC_MODE_WM 0x03 /* Write mode */ -#define VGA_GC_MISCELLANEOUS 6 -#define VGA_GC_MISC_MM 0x0C /* memory map */ -#define VGA_GC_MISC_COE 0x02 /* Chain odd/even */ -#define VGA_GC_MISC_GA 0x01 /* Graphics/text mode */ -#define VGA_GC_COLOR_DONT_CARE 7 -#define VGA_GC_BIT_MASK 8 -#define VGA_GC_DATA 0x0f - -/* CRT controller registers. */ -#define VGA_CRTC_ADDRESS 0x14 -#define VGA_CRTC_HORIZ_TOTAL 0 -#define VGA_CRTC_HORIZ_DISP_END 1 -#define VGA_CRTC_START_HORIZ_BLANK 2 -#define VGA_CRTC_END_HORIZ_BLANK 3 -#define VGA_CRTC_EHB_CR 0x80 /* Compatible read */ -#define VGA_CRTC_EHB_DES 0x60 /* Display enable skew */ -#define VGA_CRTC_EHB_EHB 0x1F /* End horizontal blank */ -#define VGA_CRTC_START_HORIZ_RETRACE 4 -#define VGA_CRTC_END_HORIZ_RETRACE 5 -#define VGA_CRTC_EHR_EHB 0x80 /* End horizontal blanking */ -#define VGA_CRTC_EHR_HRD 0x60 /* Horizontal retrace delay */ -#define VGA_CRTC_EHR_EHR 0x1F /* End horizontal retrace */ -#define VGA_CRTC_VERT_TOTAL 6 -#define VGA_CRTC_OVERFLOW 7 -#define VGA_CRTC_OF_VRS9 0x80 /* Vertical retrace start */ -#define VGA_CRTC_OF_VDE9 0x40 /* Vertical disp. enable end */ -#define VGA_CRTC_OF_VT9 0x20 /* Vertical total (bit 9) */ -#define VGA_CRTC_OF_LC8 0x10 /* Line compare */ -#define VGA_CRTC_OF_VBS8 0x08 /* Start vertical blanking */ -#define VGA_CRTC_OF_VRS8 0x04 /* Vertical retrace start */ -#define VGA_CRTC_OF_VDE8 0x02 /* Vertical disp. enable end */ -#define VGA_CRTC_OF_VT8 0x01 /* Vertical total (bit 8) */ -#define VGA_CRTC_PRESET_ROW_SCAN 8 -#define VGA_CRTC_PRS_BP 0x60 /* Byte panning */ -#define VGA_CRTC_PRS_PRS 0x1F /* Preset row scan */ -#define VGA_CRTC_MAX_SCAN_LINE 9 -#define VGA_CRTC_MSL_2T4 0x80 /* 200-to-400 line conversion */ -#define VGA_CRTC_MSL_LC9 0x40 /* Line compare (bit 9) */ -#define VGA_CRTC_MSL_VBS9 0x20 /* Start vertical blanking */ -#define VGA_CRTC_MSL_MSL 0x1F /* Maximum scan line */ -#define VGA_CRTC_CURSOR_START 10 -#define VGA_CRTC_CS_COO 0x20 /* Cursor on/off */ -#define VGA_CRTC_CS_CS 0x1F /* Cursor start */ -#define VGA_CRTC_CURSOR_END 11 -#define VGA_CRTC_CE_CSK 0x60 /* Cursor skew */ -#define VGA_CRTC_CE_CE 0x1F /* Cursor end */ -#define VGA_CRTC_START_ADDR_HIGH 12 -#define VGA_CRTC_START_ADDR_LOW 13 -#define VGA_CRTC_CURSOR_LOC_HIGH 14 -#define VGA_CRTC_CURSOR_LOC_LOW 15 -#define VGA_CRTC_VERT_RETRACE_START 16 -#define VGA_CRTC_VERT_RETRACE_END 17 -#define VGA_CRTC_VRE_PR 0x80 /* Protect register 0-7 */ -#define VGA_CRTC_VRE_BW 0x40 /* Bandwidth */ -#define VGA_CRTC_VRE_VRE 0x1F /* Vertical retrace end */ -#define VGA_CRTC_VERT_DISPLAY_END 18 -#define VGA_CRTC_OFFSET 19 -#define VGA_CRTC_UNDERLINE_LOC 20 -#define VGA_CRTC_UL_DW 0x40 /* Double word mode */ -#define VGA_CRTC_UL_CB4 0x20 /* Count by four */ -#define VGA_CRTC_UL_UL 0x1F /* Underline location */ -#define VGA_CRTC_START_VERT_BLANK 21 -#define VGA_CRTC_END_VERT_BLANK 22 -#define VGA_CRTC_MODE_CONTROL 23 -#define VGA_CRTC_MC_HR 0x80 /* hardware reset */ -#define VGA_CRTC_MC_WB 0x40 /* Word/byte mode */ -#define VGA_CRTC_MC_AW 0x20 /* Address wrap */ -#define VGA_CRTC_MC_CBT 0x08 /* Count by two */ -#define VGA_CRTC_MC_HRS 0x04 /* Horizontal retrace select */ -#define VGA_CRTC_MC_SRS 0x02 /* Select row scan counter */ -#define VGA_CRTC_MC_CMS 0x01 /* Compatibility mode support */ -#define VGA_CRTC_LINE_COMPARE 24 -#define VGA_CRTC_DATA 0x15 - -#endif /* !_DEV_VT_HW_VGA_VGA_REG_H_ */ diff --git a/sys/dev/vt/hw/vga/vt_vga.c b/sys/dev/vt/hw/vga/vt_vga.c new file mode 100644 index 0000000..15bed12 --- /dev/null +++ b/sys/dev/vt/hw/vga/vt_vga.c @@ -0,0 +1,690 @@ +/*- + * Copyright (c) 2005 Marcel Moolenaar + * All rights reserved. + * + * Copyright (c) 2009 The FreeBSD Foundation + * All rights reserved. + * + * Portions of this software were developed by Ed Schouten + * under sponsorship from the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include + +#include +#include + +#include + +#if defined(__amd64__) || defined(__i386__) +#include +#include +#include +#include +#endif /* __amd64__ || __i386__ */ + +struct vga_softc { + bus_space_tag_t vga_fb_tag; + bus_space_handle_t vga_fb_handle; + bus_space_tag_t vga_reg_tag; + bus_space_handle_t vga_reg_handle; + int vga_curcolor; +}; + +/* Convenience macros. */ +#define MEM_READ1(sc, ofs) \ + bus_space_read_1(sc->vga_fb_tag, sc->vga_fb_handle, ofs) +#define MEM_WRITE1(sc, ofs, val) \ + bus_space_write_1(sc->vga_fb_tag, sc->vga_fb_handle, ofs, val) +#define REG_READ1(sc, reg) \ + bus_space_read_1(sc->vga_reg_tag, sc->vga_reg_handle, reg) +#define REG_WRITE1(sc, reg, val) \ + bus_space_write_1(sc->vga_reg_tag, sc->vga_reg_handle, reg, val) + +#define VT_VGA_WIDTH 640 +#define VT_VGA_HEIGHT 480 +#define VT_VGA_MEMSIZE (VT_VGA_WIDTH * VT_VGA_HEIGHT / 8) + +static vd_probe_t vga_probe; +static vd_init_t vga_init; +static vd_blank_t vga_blank; +static vd_bitbltchr_t vga_bitbltchr; +static vd_maskbitbltchr_t vga_maskbitbltchr; +static vd_drawrect_t vga_drawrect; +static vd_setpixel_t vga_setpixel; +static vd_putchar_t vga_putchar; +static vd_postswitch_t vga_postswitch; + +static const struct vt_driver vt_vga_driver = { + .vd_name = "vga", + .vd_probe = vga_probe, + .vd_init = vga_init, + .vd_blank = vga_blank, + .vd_bitbltchr = vga_bitbltchr, + .vd_maskbitbltchr = vga_maskbitbltchr, + .vd_drawrect = vga_drawrect, + .vd_setpixel = vga_setpixel, + .vd_putchar = vga_putchar, + .vd_postswitch = vga_postswitch, + .vd_priority = VD_PRIORITY_GENERIC, +}; + +/* + * Driver supports both text mode and graphics mode. Make sure the + * buffer is always big enough to support both. + */ +static struct vga_softc vga_conssoftc; +VT_DRIVER_DECLARE(vt_vga, vt_vga_driver); + +static inline void +vga_setcolor(struct vt_device *vd, term_color_t color) +{ + struct vga_softc *sc = vd->vd_softc; + + if (sc->vga_curcolor != color) { + REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_SET_RESET); + REG_WRITE1(sc, VGA_GC_DATA, color); + sc->vga_curcolor = color; + } +} + +static void +vga_blank(struct vt_device *vd, term_color_t color) +{ + struct vga_softc *sc = vd->vd_softc; + u_int ofs; + + vga_setcolor(vd, color); + for (ofs = 0; ofs < VT_VGA_MEMSIZE; ofs++) + MEM_WRITE1(sc, ofs, 0xff); +} + +static inline void +vga_bitblt_put(struct vt_device *vd, u_long dst, term_color_t color, + uint8_t v) +{ + struct vga_softc *sc = vd->vd_softc; + + /* Skip empty writes, in order to avoid palette changes. */ + if (v != 0x00) { + vga_setcolor(vd, color); + /* + * When this MEM_READ1() gets disabled, all sorts of + * artifacts occur. This is because this read loads the + * set of 8 pixels that are about to be changed. There + * is one scenario where we can avoid the read, namely + * if all pixels are about to be overwritten anyway. + */ + if (v != 0xff) + MEM_READ1(sc, dst); + MEM_WRITE1(sc, dst, v); + } +} + +static void +vga_setpixel(struct vt_device *vd, int x, int y, term_color_t color) +{ + + vga_bitblt_put(vd, (y * VT_VGA_WIDTH / 8) + (x / 8), color, + 0x80 >> (x % 8)); +} + +static void +vga_drawrect(struct vt_device *vd, int x1, int y1, int x2, int y2, int fill, + term_color_t color) +{ + int x, y; + + for (y = y1; y <= y2; y++) { + if (fill || (y == y1) || (y == y2)) { + for (x = x1; x <= x2; x++) + vga_setpixel(vd, x, y, color); + } else { + vga_setpixel(vd, x1, y, color); + vga_setpixel(vd, x2, y, color); + } + } +} + +static inline void +vga_bitblt_draw(struct vt_device *vd, const uint8_t *src, + u_long ldst, uint8_t shift, unsigned int width, unsigned int height, + term_color_t color, int negate) +{ + u_long dst; + int w; + uint8_t b, r, out; + + for (; height > 0; height--) { + dst = ldst; + ldst += VT_VGA_WIDTH / 8; + r = 0; + for (w = width; w > 0; w -= 8) { + b = *src++; + if (negate) { + b = ~b; + /* Don't go too far. */ + if (w < 8) + b &= 0xff << (8 - w); + } + /* Reintroduce bits from previous column. */ + out = (b >> shift) | r; + r = b << (8 - shift); + vga_bitblt_put(vd, dst++, color, out); + } + /* Print the remainder. */ + vga_bitblt_put(vd, dst, color, r); + } +} + +static void +vga_bitbltchr(struct vt_device *vd, const uint8_t *src, const uint8_t *mask, + int bpl, vt_axis_t top, vt_axis_t left, unsigned int width, + unsigned int height, term_color_t fg, term_color_t bg) +{ + u_long dst, ldst; + int w; + + /* Don't try to put off screen pixels */ + if (((left + width) > VT_VGA_WIDTH) || ((top + height) > + VT_VGA_HEIGHT)) + return; + + dst = (VT_VGA_WIDTH * top + left) / 8; + + for (; height > 0; height--) { + ldst = dst; + for (w = width; w > 0; w -= 8) { + vga_bitblt_put(vd, ldst, fg, *src); + vga_bitblt_put(vd, ldst, bg, ~*src); + ldst++; + src++; + } + dst += VT_VGA_WIDTH / 8; + } +} + +/* Bitblt with mask support. Slow. */ +static void +vga_maskbitbltchr(struct vt_device *vd, const uint8_t *src, const uint8_t *mask, + int bpl, vt_axis_t top, vt_axis_t left, unsigned int width, + unsigned int height, term_color_t fg, term_color_t bg) +{ + struct vga_softc *sc = vd->vd_softc; + u_long dst; + uint8_t shift; + + dst = (VT_VGA_WIDTH * top + left) / 8; + shift = left % 8; + + /* Don't try to put off screen pixels */ + if (((left + width) > VT_VGA_WIDTH) || ((top + height) > + VT_VGA_HEIGHT)) + return; + + if (sc->vga_curcolor == fg) { + vga_bitblt_draw(vd, src, dst, shift, width, height, fg, 0); + vga_bitblt_draw(vd, src, dst, shift, width, height, bg, 1); + } else { + vga_bitblt_draw(vd, src, dst, shift, width, height, bg, 1); + vga_bitblt_draw(vd, src, dst, shift, width, height, fg, 0); + } +} + +/* + * Binary searchable table for Unicode to CP437 conversion. + */ + +struct unicp437 { + uint16_t unicode_base; + uint8_t cp437_base; + uint8_t length; +}; + +static const struct unicp437 cp437table[] = { + { 0x0020, 0x20, 0x5e }, { 0x00a0, 0x20, 0x00 }, + { 0x00a1, 0xad, 0x00 }, { 0x00a2, 0x9b, 0x00 }, + { 0x00a3, 0x9c, 0x00 }, { 0x00a5, 0x9d, 0x00 }, + { 0x00a7, 0x15, 0x00 }, { 0x00aa, 0xa6, 0x00 }, + { 0x00ab, 0xae, 0x00 }, { 0x00ac, 0xaa, 0x00 }, + { 0x00b0, 0xf8, 0x00 }, { 0x00b1, 0xf1, 0x00 }, + { 0x00b2, 0xfd, 0x00 }, { 0x00b5, 0xe6, 0x00 }, + { 0x00b6, 0x14, 0x00 }, { 0x00b7, 0xfa, 0x00 }, + { 0x00ba, 0xa7, 0x00 }, { 0x00bb, 0xaf, 0x00 }, + { 0x00bc, 0xac, 0x00 }, { 0x00bd, 0xab, 0x00 }, + { 0x00bf, 0xa8, 0x00 }, { 0x00c4, 0x8e, 0x01 }, + { 0x00c6, 0x92, 0x00 }, { 0x00c7, 0x80, 0x00 }, + { 0x00c9, 0x90, 0x00 }, { 0x00d1, 0xa5, 0x00 }, + { 0x00d6, 0x99, 0x00 }, { 0x00dc, 0x9a, 0x00 }, + { 0x00df, 0xe1, 0x00 }, { 0x00e0, 0x85, 0x00 }, + { 0x00e1, 0xa0, 0x00 }, { 0x00e2, 0x83, 0x00 }, + { 0x00e4, 0x84, 0x00 }, { 0x00e5, 0x86, 0x00 }, + { 0x00e6, 0x91, 0x00 }, { 0x00e7, 0x87, 0x00 }, + { 0x00e8, 0x8a, 0x00 }, { 0x00e9, 0x82, 0x00 }, + { 0x00ea, 0x88, 0x01 }, { 0x00ec, 0x8d, 0x00 }, + { 0x00ed, 0xa1, 0x00 }, { 0x00ee, 0x8c, 0x00 }, + { 0x00ef, 0x8b, 0x00 }, { 0x00f0, 0xeb, 0x00 }, + { 0x00f1, 0xa4, 0x00 }, { 0x00f2, 0x95, 0x00 }, + { 0x00f3, 0xa2, 0x00 }, { 0x00f4, 0x93, 0x00 }, + { 0x00f6, 0x94, 0x00 }, { 0x00f7, 0xf6, 0x00 }, + { 0x00f8, 0xed, 0x00 }, { 0x00f9, 0x97, 0x00 }, + { 0x00fa, 0xa3, 0x00 }, { 0x00fb, 0x96, 0x00 }, + { 0x00fc, 0x81, 0x00 }, { 0x00ff, 0x98, 0x00 }, + { 0x0192, 0x9f, 0x00 }, { 0x0393, 0xe2, 0x00 }, + { 0x0398, 0xe9, 0x00 }, { 0x03a3, 0xe4, 0x00 }, + { 0x03a6, 0xe8, 0x00 }, { 0x03a9, 0xea, 0x00 }, + { 0x03b1, 0xe0, 0x01 }, { 0x03b4, 0xeb, 0x00 }, + { 0x03b5, 0xee, 0x00 }, { 0x03bc, 0xe6, 0x00 }, + { 0x03c0, 0xe3, 0x00 }, { 0x03c3, 0xe5, 0x00 }, + { 0x03c4, 0xe7, 0x00 }, { 0x03c6, 0xed, 0x00 }, + { 0x03d5, 0xed, 0x00 }, { 0x2010, 0x2d, 0x00 }, + { 0x2014, 0x2d, 0x00 }, { 0x2018, 0x60, 0x00 }, + { 0x2019, 0x27, 0x00 }, { 0x201c, 0x22, 0x00 }, + { 0x201d, 0x22, 0x00 }, { 0x2022, 0x07, 0x00 }, + { 0x203c, 0x13, 0x00 }, { 0x207f, 0xfc, 0x00 }, + { 0x20a7, 0x9e, 0x00 }, { 0x20ac, 0xee, 0x00 }, + { 0x2126, 0xea, 0x00 }, { 0x2190, 0x1b, 0x00 }, + { 0x2191, 0x18, 0x00 }, { 0x2192, 0x1a, 0x00 }, + { 0x2193, 0x19, 0x00 }, { 0x2194, 0x1d, 0x00 }, + { 0x2195, 0x12, 0x00 }, { 0x21a8, 0x17, 0x00 }, + { 0x2202, 0xeb, 0x00 }, { 0x2208, 0xee, 0x00 }, + { 0x2211, 0xe4, 0x00 }, { 0x2212, 0x2d, 0x00 }, + { 0x2219, 0xf9, 0x00 }, { 0x221a, 0xfb, 0x00 }, + { 0x221e, 0xec, 0x00 }, { 0x221f, 0x1c, 0x00 }, + { 0x2229, 0xef, 0x00 }, { 0x2248, 0xf7, 0x00 }, + { 0x2261, 0xf0, 0x00 }, { 0x2264, 0xf3, 0x00 }, + { 0x2265, 0xf2, 0x00 }, { 0x2302, 0x7f, 0x00 }, + { 0x2310, 0xa9, 0x00 }, { 0x2320, 0xf4, 0x00 }, + { 0x2321, 0xf5, 0x00 }, { 0x2500, 0xc4, 0x00 }, + { 0x2502, 0xb3, 0x00 }, { 0x250c, 0xda, 0x00 }, + { 0x2510, 0xbf, 0x00 }, { 0x2514, 0xc0, 0x00 }, + { 0x2518, 0xd9, 0x00 }, { 0x251c, 0xc3, 0x00 }, + { 0x2524, 0xb4, 0x00 }, { 0x252c, 0xc2, 0x00 }, + { 0x2534, 0xc1, 0x00 }, { 0x253c, 0xc5, 0x00 }, + { 0x2550, 0xcd, 0x00 }, { 0x2551, 0xba, 0x00 }, + { 0x2552, 0xd5, 0x00 }, { 0x2553, 0xd6, 0x00 }, + { 0x2554, 0xc9, 0x00 }, { 0x2555, 0xb8, 0x00 }, + { 0x2556, 0xb7, 0x00 }, { 0x2557, 0xbb, 0x00 }, + { 0x2558, 0xd4, 0x00 }, { 0x2559, 0xd3, 0x00 }, + { 0x255a, 0xc8, 0x00 }, { 0x255b, 0xbe, 0x00 }, + { 0x255c, 0xbd, 0x00 }, { 0x255d, 0xbc, 0x00 }, + { 0x255e, 0xc6, 0x01 }, { 0x2560, 0xcc, 0x00 }, + { 0x2561, 0xb5, 0x00 }, { 0x2562, 0xb6, 0x00 }, + { 0x2563, 0xb9, 0x00 }, { 0x2564, 0xd1, 0x01 }, + { 0x2566, 0xcb, 0x00 }, { 0x2567, 0xcf, 0x00 }, + { 0x2568, 0xd0, 0x00 }, { 0x2569, 0xca, 0x00 }, + { 0x256a, 0xd8, 0x00 }, { 0x256b, 0xd7, 0x00 }, + { 0x256c, 0xce, 0x00 }, { 0x2580, 0xdf, 0x00 }, + { 0x2584, 0xdc, 0x00 }, { 0x2588, 0xdb, 0x00 }, + { 0x258c, 0xdd, 0x00 }, { 0x2590, 0xde, 0x00 }, + { 0x2591, 0xb0, 0x02 }, { 0x25a0, 0xfe, 0x00 }, + { 0x25ac, 0x16, 0x00 }, { 0x25b2, 0x1e, 0x00 }, + { 0x25ba, 0x10, 0x00 }, { 0x25bc, 0x1f, 0x00 }, + { 0x25c4, 0x11, 0x00 }, { 0x25cb, 0x09, 0x00 }, + { 0x25d8, 0x08, 0x00 }, { 0x25d9, 0x0a, 0x00 }, + { 0x263a, 0x01, 0x01 }, { 0x263c, 0x0f, 0x00 }, + { 0x2640, 0x0c, 0x00 }, { 0x2642, 0x0b, 0x00 }, + { 0x2660, 0x06, 0x00 }, { 0x2663, 0x05, 0x00 }, + { 0x2665, 0x03, 0x01 }, { 0x266a, 0x0d, 0x00 }, + { 0x266c, 0x0e, 0x00 }, +}; + +static uint8_t +vga_get_cp437(term_char_t c) +{ + int min, mid, max; + + min = 0; + max = (sizeof(cp437table) / sizeof(struct unicp437)) - 1; + + if (c < cp437table[0].unicode_base || + c > cp437table[max].unicode_base + cp437table[max].length) + return '?'; + + while (max >= min) { + mid = (min + max) / 2; + if (c < cp437table[mid].unicode_base) + max = mid - 1; + else if (c > cp437table[mid].unicode_base + + cp437table[mid].length) + min = mid + 1; + else + return (c - cp437table[mid].unicode_base + + cp437table[mid].cp437_base); + } + + return '?'; +} + +static void +vga_putchar(struct vt_device *vd, term_char_t c, + vt_axis_t top, vt_axis_t left, term_color_t fg, term_color_t bg) +{ + struct vga_softc *sc = vd->vd_softc; + uint8_t ch, attr; + + /* + * Convert character to CP437, which is the character set used + * by the VGA hardware by default. + */ + ch = vga_get_cp437(c); + + /* + * Convert colors to VGA attributes. + */ + attr = bg << 4 | fg; + + MEM_WRITE1(sc, 0x18000 + (top * 80 + left) * 2 + 0, ch); + MEM_WRITE1(sc, 0x18000 + (top * 80 + left) * 2 + 1, attr); +} + +static void +vga_initialize_graphics(struct vt_device *vd) +{ + struct vga_softc *sc = vd->vd_softc; + + /* Clock select. */ + REG_WRITE1(sc, VGA_GEN_MISC_OUTPUT_W, VGA_GEN_MO_VSP | VGA_GEN_MO_HSP | + VGA_GEN_MO_PB | VGA_GEN_MO_ER | VGA_GEN_MO_IOA); + /* Set sequencer clocking and memory mode. */ + REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_CLOCKING_MODE); + REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_CM_89); + REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MEMORY_MODE); + REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_MM_OE | VGA_SEQ_MM_EM); + + /* Set the graphics controller in graphics mode. */ + REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_MISCELLANEOUS); + REG_WRITE1(sc, VGA_GC_DATA, 0x04 + VGA_GC_MISC_GA); + /* Program the CRT controller. */ + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_HORIZ_TOTAL); + REG_WRITE1(sc, VGA_CRTC_DATA, 0x5f); /* 760 */ + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_HORIZ_DISP_END); + REG_WRITE1(sc, VGA_CRTC_DATA, 0x4f); /* 640 - 8 */ + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_HORIZ_BLANK); + REG_WRITE1(sc, VGA_CRTC_DATA, 0x50); /* 640 */ + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_HORIZ_BLANK); + REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_EHB_CR + 2); + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_HORIZ_RETRACE); + REG_WRITE1(sc, VGA_CRTC_DATA, 0x54); /* 672 */ + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_HORIZ_RETRACE); + REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_EHR_EHB + 0); + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_TOTAL); + REG_WRITE1(sc, VGA_CRTC_DATA, 0x0b); /* 523 */ + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_OVERFLOW); + REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_OF_VT9 | VGA_CRTC_OF_LC8 | + VGA_CRTC_OF_VBS8 | VGA_CRTC_OF_VRS8 | VGA_CRTC_OF_VDE8); + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MAX_SCAN_LINE); + REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_MSL_LC9); + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_START); + REG_WRITE1(sc, VGA_CRTC_DATA, 0xea); /* 480 + 10 */ + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_END); + REG_WRITE1(sc, VGA_CRTC_DATA, 0x0c); + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_DISPLAY_END); + REG_WRITE1(sc, VGA_CRTC_DATA, 0xdf); /* 480 - 1*/ + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_OFFSET); + REG_WRITE1(sc, VGA_CRTC_DATA, 0x28); + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_VERT_BLANK); + REG_WRITE1(sc, VGA_CRTC_DATA, 0xe7); /* 480 + 7 */ + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_VERT_BLANK); + REG_WRITE1(sc, VGA_CRTC_DATA, 0x04); + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL); + REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_MC_WB | VGA_CRTC_MC_AW | + VGA_CRTC_MC_SRS | VGA_CRTC_MC_CMS); + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_LINE_COMPARE); + REG_WRITE1(sc, VGA_CRTC_DATA, 0xff); /* 480 + 31 */ + + REG_WRITE1(sc, VGA_GEN_FEATURE_CTRL_W, 0); + + REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MAP_MASK); + REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_MM_EM3 | VGA_SEQ_MM_EM2 | + VGA_SEQ_MM_EM1 | VGA_SEQ_MM_EM0); + REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_CHAR_MAP_SELECT); + REG_WRITE1(sc, VGA_SEQ_DATA, 0); + + REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_SET_RESET); + REG_WRITE1(sc, VGA_GC_DATA, 0); + REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_ENABLE_SET_RESET); + REG_WRITE1(sc, VGA_GC_DATA, 0x0f); + REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_COLOR_COMPARE); + REG_WRITE1(sc, VGA_GC_DATA, 0); + REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_DATA_ROTATE); + REG_WRITE1(sc, VGA_GC_DATA, 0); + REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_READ_MAP_SELECT); + REG_WRITE1(sc, VGA_GC_DATA, 0); + REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_MODE); + REG_WRITE1(sc, VGA_GC_DATA, 0); + REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_COLOR_DONT_CARE); + REG_WRITE1(sc, VGA_GC_DATA, 0x0f); + REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_BIT_MASK); + REG_WRITE1(sc, VGA_GC_DATA, 0xff); +} + +static void +vga_initialize(struct vt_device *vd, int textmode) +{ + struct vga_softc *sc = vd->vd_softc; + uint8_t x; + + /* Make sure the VGA adapter is not in monochrome emulation mode. */ + x = REG_READ1(sc, VGA_GEN_MISC_OUTPUT_R); + REG_WRITE1(sc, VGA_GEN_MISC_OUTPUT_W, x | VGA_GEN_MO_IOA); + + /* Unprotect CRTC registers 0-7. */ + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_END); + x = REG_READ1(sc, VGA_CRTC_DATA); + REG_WRITE1(sc, VGA_CRTC_DATA, x & ~VGA_CRTC_VRE_PR); + + /* + * Wait for the vertical retrace. + * NOTE: this code reads the VGA_GEN_INPUT_STAT_1 register, which has + * the side-effect of clearing the internal flip-flip of the attribute + * controller's write register. This means that because this code is + * here, we know for sure that the first write to the attribute + * controller will be a write to the address register. Removing this + * code therefore also removes that guarantee and appropriate measures + * need to be taken. + */ + do { + x = REG_READ1(sc, VGA_GEN_INPUT_STAT_1); + x &= VGA_GEN_IS1_VR | VGA_GEN_IS1_DE; + } while (x != (VGA_GEN_IS1_VR | VGA_GEN_IS1_DE)); + + /* Now, disable the sync. signals. */ + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL); + x = REG_READ1(sc, VGA_CRTC_DATA); + REG_WRITE1(sc, VGA_CRTC_DATA, x & ~VGA_CRTC_MC_HR); + + /* Asynchronous sequencer reset. */ + REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_RESET); + REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_RST_SR); + + if (!textmode) + vga_initialize_graphics(vd); + + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_PRESET_ROW_SCAN); + REG_WRITE1(sc, VGA_CRTC_DATA, 0); + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_START); + REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_CS_COO); + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_END); + REG_WRITE1(sc, VGA_CRTC_DATA, 0); + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_ADDR_HIGH); + REG_WRITE1(sc, VGA_CRTC_DATA, 0); + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_ADDR_LOW); + REG_WRITE1(sc, VGA_CRTC_DATA, 0); + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_LOC_HIGH); + REG_WRITE1(sc, VGA_CRTC_DATA, 0); + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_LOC_LOW); + REG_WRITE1(sc, VGA_CRTC_DATA, 0x59); + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_UNDERLINE_LOC); + REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_UL_UL); + + if (textmode) { + /* Set the attribute controller to blink disable. */ + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_MODE_CONTROL); + REG_WRITE1(sc, VGA_AC_WRITE, 0); + } else { + /* Set the attribute controller in graphics mode. */ + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_MODE_CONTROL); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_MC_GA); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_HORIZ_PIXEL_PANNING); + REG_WRITE1(sc, VGA_AC_WRITE, 0); + } + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(0)); + REG_WRITE1(sc, VGA_AC_WRITE, 0); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(1)); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_R); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(2)); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_G); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(3)); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SG | VGA_AC_PAL_R); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(4)); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_B); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(5)); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_R | VGA_AC_PAL_B); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(6)); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_G | VGA_AC_PAL_B); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(7)); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_R | VGA_AC_PAL_G | VGA_AC_PAL_B); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(8)); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | + VGA_AC_PAL_SB); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(9)); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | + VGA_AC_PAL_SB | VGA_AC_PAL_R); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(10)); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | + VGA_AC_PAL_SB | VGA_AC_PAL_G); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(11)); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | + VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_G); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(12)); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | + VGA_AC_PAL_SB | VGA_AC_PAL_B); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(13)); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | + VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_B); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(14)); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | + VGA_AC_PAL_SB | VGA_AC_PAL_G | VGA_AC_PAL_B); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(15)); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | + VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_G | VGA_AC_PAL_B); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_OVERSCAN_COLOR); + REG_WRITE1(sc, VGA_AC_WRITE, 0); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_COLOR_PLANE_ENABLE); + REG_WRITE1(sc, VGA_AC_WRITE, 0x0f); + REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_COLOR_SELECT); + REG_WRITE1(sc, VGA_AC_WRITE, 0); + + if (!textmode) { + u_int ofs; + + /* + * Done. Clear the frame buffer. All bit planes are + * enabled, so a single-paged loop should clear all + * planes. + */ + for (ofs = 0; ofs < VT_VGA_MEMSIZE; ofs++) { + MEM_READ1(sc, ofs); + MEM_WRITE1(sc, ofs, 0); + } + } + + /* Re-enable the sequencer. */ + REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_RESET); + REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_RST_SR | VGA_SEQ_RST_NAR); + /* Re-enable the sync signals. */ + REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL); + x = REG_READ1(sc, VGA_CRTC_DATA); + REG_WRITE1(sc, VGA_CRTC_DATA, x | VGA_CRTC_MC_HR); + + if (!textmode) { + /* Switch to write mode 3, because we'll mainly do bitblt. */ + REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_MODE); + REG_WRITE1(sc, VGA_GC_DATA, 3); + REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_ENABLE_SET_RESET); + REG_WRITE1(sc, VGA_GC_DATA, 0x0f); + } +} + +static int +vga_probe(struct vt_device *vd) +{ + + return (CN_INTERNAL); +} + +static int +vga_init(struct vt_device *vd) +{ + struct vga_softc *sc; + int textmode; + + if (vd->vd_softc == NULL) + vd->vd_softc = (void *)&vga_conssoftc; + sc = vd->vd_softc; + textmode = 0; + +#if defined(__amd64__) || defined(__i386__) + sc->vga_fb_tag = X86_BUS_SPACE_MEM; + sc->vga_fb_handle = KERNBASE + VGA_MEM_BASE; + sc->vga_reg_tag = X86_BUS_SPACE_IO; + sc->vga_reg_handle = VGA_REG_BASE; +#elif defined(__ia64__) + sc->vga_fb_tag = IA64_BUS_SPACE_MEM; + sc->vga_fb_handle = IA64_PHYS_TO_RR6(VGA_MEM_BASE); + sc->vga_reg_tag = IA64_BUS_SPACE_IO; + sc->vga_reg_handle = VGA_REG_BASE; +#else +# error "Architecture not yet supported!" +#endif + + TUNABLE_INT_FETCH("hw.vga.textmode", &textmode); + if (textmode) { + vd->vd_flags |= VDF_TEXTMODE; + vd->vd_width = 80; + vd->vd_height = 25; + } else { + vd->vd_width = VT_VGA_WIDTH; + vd->vd_height = VT_VGA_HEIGHT; + } + vga_initialize(vd, textmode); + + return (CN_INTERNAL); +} + +static void +vga_postswitch(struct vt_device *vd) +{ + + /* Reinit VGA mode, to restore view after app which change mode. */ + vga_initialize(vd, (vd->vd_flags & VDF_TEXTMODE)); + /* Ask vt(9) to update chars on visible area. */ + vd->vd_flags |= VDF_INVALID; +} diff --git a/sys/dev/vt/hw/vga/vt_vga_reg.h b/sys/dev/vt/hw/vga/vt_vga_reg.h new file mode 100644 index 0000000..5bfb8ce --- /dev/null +++ b/sys/dev/vt/hw/vga/vt_vga_reg.h @@ -0,0 +1,220 @@ +/*- + * Copyright (c) 2005 Marcel Moolenaar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _DEV_VT_HW_VGA_VGA_REG_H_ +#define _DEV_VT_HW_VGA_VGA_REG_H_ + +/* + * The VGA adapter uses two I/O port blocks. One of these blocks, the CRT + * controller registers, can be located either at 0x3B0 or at 0x3D0 in I/O + * port space. This allows compatibility with the monochrome adapter, which + * has the CRT controller registers at 0x3B0. + * + * It is assumed that compatibility with the monochrome adapter is not of + * interest anymore. As such, the CRT controller can be located at 0x3D0 in + * I/O port space unconditionally. This means that the 2 I/O blocks are + * always adjacent and can therefore be treated as a single logical I/O port + * range. In practical terms: there only has to be a single tag and handle + * to access all registers. + * + * The following definitions are taken from or inspired by: + * Programmer's Guide to the EGA, VGA, and Super VGA Cards -- 3rd ed., + * Richard F. Ferraro, Addison-Wesley, ISBN 0-201-62490-7 + */ + +#define VGA_MEM_BASE 0xA0000 +#define VGA_MEM_SIZE 0x10000 +#define VGA_REG_BASE 0x3c0 +#define VGA_REG_SIZE 0x10+0x0c + +/* Attribute controller registers. */ +#define VGA_AC_WRITE 0x00 +#define VGA_AC_READ 0x01 +#define VGA_AC_PALETTE(x) (x) /* 0 <= x <= 15 */ +#define VGA_AC_PAL_SR 0x20 /* Secondary red */ +#define VGA_AC_PAL_SG 0x10 /* Secondary green */ +#define VGA_AC_PAL_SB 0x08 /* Secondary blue */ +#define VGA_AC_PAL_R 0x04 /* Red */ +#define VGA_AC_PAL_G 0x02 /* Green */ +#define VGA_AC_PAL_B 0x01 /* Blue */ +#define VGA_AC_MODE_CONTROL (32+16) +#define VGA_AC_MC_IPS 0x80 /* Internal palette size */ +#define VGA_AC_MC_PCS 0x40 /* Pixel clock select */ +#define VGA_AC_MC_PPC 0x20 /* Pixel panning compat. */ +#define VGA_AC_MC_BI 0x08 /* Blink/intensity */ +#define VGA_AC_MC_ELG 0x04 /* Enable line graphics cc. */ +#define VGA_AC_MC_DT 0x02 /* Display type */ +#define VGA_AC_MC_GA 0x01 /* Graphics/alphanumeric */ +#define VGA_AC_OVERSCAN_COLOR (32+17) +#define VGA_AC_COLOR_PLANE_ENABLE (32+18) +#define VGA_AC_HORIZ_PIXEL_PANNING (32+19) +#define VGA_AC_COLOR_SELECT (32+20) +#define VGA_AC_CS_C67 0x0C /* Color reg. addr. bits 6+7 */ +#define VGA_AC_CS_C45 0x03 /* Color reg. addr. bits 4+5 */ + +/* General registers. */ +#define VGA_GEN_MISC_OUTPUT_W 0x02 /* Write only. */ +#define VGA_GEN_MISC_OUTPUT_R 0x0c /* Read only. */ +#define VGA_GEN_MO_VSP 0x80 /* Vertical sync. polarity */ +#define VGA_GEN_MO_HSP 0x40 /* Horiz. sync. polarity */ +#define VGA_GEN_MO_PB 0x20 /* Page bit for odd/even */ +#define VGA_GEN_MO_CS 0x0C /* Clock select */ +#define VGA_GEN_MO_ER 0x02 /* Enable RAM */ +#define VGA_GEN_MO_IOA 0x01 /* Input/output address */ +#define VGA_GEN_INPUT_STAT_0 0x02 /* Read only. */ +#define VGA_GEN_FEATURE_CTRL_W 0x1a /* Write only. */ +#define VGA_GEN_FEATURE_CTRL_R 0x0a /* Read only. */ +#define VGA_GEN_INPUT_STAT_1 0x1a /* Read only. */ +#define VGA_GEN_IS1_VR 0x08 /* Vertical retrace */ +#define VGA_GEN_IS1_DE 0x01 /* Display enable not */ + +/* Sequencer registers. */ +#define VGA_SEQ_ADDRESS 0x04 +#define VGA_SEQ_RESET 0 +#define VGA_SEQ_RST_SR 0x02 /* Synchronous reset */ +#define VGA_SEQ_RST_NAR 0x01 /* No async. reset */ +#define VGA_SEQ_CLOCKING_MODE 1 +#define VGA_SEQ_CM_SO 0x20 /* Screen off */ +#define VGA_SEQ_CM_S4 0x10 /* Shift four */ +#define VGA_SEQ_CM_DC 0x08 /* Dot clock */ +#define VGA_SEQ_CM_SL 0x04 /* Shift load */ +#define VGA_SEQ_CM_89 0x01 /* 8/9 Dot clocks */ +#define VGA_SEQ_MAP_MASK 2 +#define VGA_SEQ_MM_EM3 0x08 /* Enable memory plane 3 */ +#define VGA_SEQ_MM_EM2 0x04 /* Enable memory plane 2 */ +#define VGA_SEQ_MM_EM1 0x02 /* Enable memory plane 1 */ +#define VGA_SEQ_MM_EM0 0x01 /* Enable memory plane 0 */ +#define VGA_SEQ_CHAR_MAP_SELECT 3 +#define VGA_SEQ_CMS_SAH 0x20 /* Char. A (bit 2) */ +#define VGA_SEQ_CMS_SBH 0x10 /* Char. B (bit 2) */ +#define VGA_SEQ_CMS_SA 0x0C /* Char. A (bit 0+1) */ +#define VGA_SEQ_CMS_SB 0x03 /* Char. B (bit 0+1) */ +#define VGA_SEQ_MEMORY_MODE 4 +#define VGA_SEQ_MM_C4 0x08 /* Chain four */ +#define VGA_SEQ_MM_OE 0x04 /* Odd/even */ +#define VGA_SEQ_MM_EM 0x02 /* Extended memory */ +#define VGA_SEQ_DATA 0x05 + +/* Color registers. */ +#define VGA_PEL_MASK 0x06 +#define VGA_PEL_ADDR_RD_MODE 0x07 /* Write only. */ +#define VGA_DAC_STATE 0x07 /* Read only. */ +#define VGA_PEL_ADDR_WR_MODE 0x08 +#define VGA_PEL_DATA 0x09 + +/* Graphics controller registers. */ +#define VGA_GC_ADDRESS 0x0e +#define VGA_GC_SET_RESET 0 +#define VGA_GC_ENABLE_SET_RESET 1 +#define VGA_GC_COLOR_COMPARE 2 +#define VGA_GC_DATA_ROTATE 3 +#define VGA_GC_DR_FS_XOR 0x18 /* Function select - XOR */ +#define VGA_GC_DR_FS_OR 0x10 /* Function select - OR */ +#define VGA_GC_DR_FS_AND 0x08 /* Function select - AND */ +#define VGA_GC_DR_RC 0x07 /* Rotate count */ +#define VGA_GC_READ_MAP_SELECT 4 +#define VGA_GC_MODE 5 +#define VGA_GC_MODE_SR 0x60 /* Shift register */ +#define VGA_GC_MODE_OE 0x10 /* Odd/even */ +#define VGA_GC_MODE_RM 0x08 /* Read mode */ +#define VGA_GC_MODE_WM 0x03 /* Write mode */ +#define VGA_GC_MISCELLANEOUS 6 +#define VGA_GC_MISC_MM 0x0C /* memory map */ +#define VGA_GC_MISC_COE 0x02 /* Chain odd/even */ +#define VGA_GC_MISC_GA 0x01 /* Graphics/text mode */ +#define VGA_GC_COLOR_DONT_CARE 7 +#define VGA_GC_BIT_MASK 8 +#define VGA_GC_DATA 0x0f + +/* CRT controller registers. */ +#define VGA_CRTC_ADDRESS 0x14 +#define VGA_CRTC_HORIZ_TOTAL 0 +#define VGA_CRTC_HORIZ_DISP_END 1 +#define VGA_CRTC_START_HORIZ_BLANK 2 +#define VGA_CRTC_END_HORIZ_BLANK 3 +#define VGA_CRTC_EHB_CR 0x80 /* Compatible read */ +#define VGA_CRTC_EHB_DES 0x60 /* Display enable skew */ +#define VGA_CRTC_EHB_EHB 0x1F /* End horizontal blank */ +#define VGA_CRTC_START_HORIZ_RETRACE 4 +#define VGA_CRTC_END_HORIZ_RETRACE 5 +#define VGA_CRTC_EHR_EHB 0x80 /* End horizontal blanking */ +#define VGA_CRTC_EHR_HRD 0x60 /* Horizontal retrace delay */ +#define VGA_CRTC_EHR_EHR 0x1F /* End horizontal retrace */ +#define VGA_CRTC_VERT_TOTAL 6 +#define VGA_CRTC_OVERFLOW 7 +#define VGA_CRTC_OF_VRS9 0x80 /* Vertical retrace start */ +#define VGA_CRTC_OF_VDE9 0x40 /* Vertical disp. enable end */ +#define VGA_CRTC_OF_VT9 0x20 /* Vertical total (bit 9) */ +#define VGA_CRTC_OF_LC8 0x10 /* Line compare */ +#define VGA_CRTC_OF_VBS8 0x08 /* Start vertical blanking */ +#define VGA_CRTC_OF_VRS8 0x04 /* Vertical retrace start */ +#define VGA_CRTC_OF_VDE8 0x02 /* Vertical disp. enable end */ +#define VGA_CRTC_OF_VT8 0x01 /* Vertical total (bit 8) */ +#define VGA_CRTC_PRESET_ROW_SCAN 8 +#define VGA_CRTC_PRS_BP 0x60 /* Byte panning */ +#define VGA_CRTC_PRS_PRS 0x1F /* Preset row scan */ +#define VGA_CRTC_MAX_SCAN_LINE 9 +#define VGA_CRTC_MSL_2T4 0x80 /* 200-to-400 line conversion */ +#define VGA_CRTC_MSL_LC9 0x40 /* Line compare (bit 9) */ +#define VGA_CRTC_MSL_VBS9 0x20 /* Start vertical blanking */ +#define VGA_CRTC_MSL_MSL 0x1F /* Maximum scan line */ +#define VGA_CRTC_CURSOR_START 10 +#define VGA_CRTC_CS_COO 0x20 /* Cursor on/off */ +#define VGA_CRTC_CS_CS 0x1F /* Cursor start */ +#define VGA_CRTC_CURSOR_END 11 +#define VGA_CRTC_CE_CSK 0x60 /* Cursor skew */ +#define VGA_CRTC_CE_CE 0x1F /* Cursor end */ +#define VGA_CRTC_START_ADDR_HIGH 12 +#define VGA_CRTC_START_ADDR_LOW 13 +#define VGA_CRTC_CURSOR_LOC_HIGH 14 +#define VGA_CRTC_CURSOR_LOC_LOW 15 +#define VGA_CRTC_VERT_RETRACE_START 16 +#define VGA_CRTC_VERT_RETRACE_END 17 +#define VGA_CRTC_VRE_PR 0x80 /* Protect register 0-7 */ +#define VGA_CRTC_VRE_BW 0x40 /* Bandwidth */ +#define VGA_CRTC_VRE_VRE 0x1F /* Vertical retrace end */ +#define VGA_CRTC_VERT_DISPLAY_END 18 +#define VGA_CRTC_OFFSET 19 +#define VGA_CRTC_UNDERLINE_LOC 20 +#define VGA_CRTC_UL_DW 0x40 /* Double word mode */ +#define VGA_CRTC_UL_CB4 0x20 /* Count by four */ +#define VGA_CRTC_UL_UL 0x1F /* Underline location */ +#define VGA_CRTC_START_VERT_BLANK 21 +#define VGA_CRTC_END_VERT_BLANK 22 +#define VGA_CRTC_MODE_CONTROL 23 +#define VGA_CRTC_MC_HR 0x80 /* hardware reset */ +#define VGA_CRTC_MC_WB 0x40 /* Word/byte mode */ +#define VGA_CRTC_MC_AW 0x20 /* Address wrap */ +#define VGA_CRTC_MC_CBT 0x08 /* Count by two */ +#define VGA_CRTC_MC_HRS 0x04 /* Horizontal retrace select */ +#define VGA_CRTC_MC_SRS 0x02 /* Select row scan counter */ +#define VGA_CRTC_MC_CMS 0x01 /* Compatibility mode support */ +#define VGA_CRTC_LINE_COMPARE 24 +#define VGA_CRTC_DATA 0x15 + +#endif /* !_DEV_VT_HW_VGA_VGA_REG_H_ */ diff --git a/sys/dev/vt/vt.h b/sys/dev/vt/vt.h index 176c053..b216499 100644 --- a/sys/dev/vt/vt.h +++ b/sys/dev/vt/vt.h @@ -50,11 +50,6 @@ #include "opt_syscons.h" #include "opt_splash.h" -#ifdef DEV_SC -#error "Build with both syscons and vt is not supported. Please enable only \ -one 'device sc' or 'device vt'" -#endif - #ifndef VT_MAXWINDOWS #ifdef MAXCONS #define VT_MAXWINDOWS MAXCONS diff --git a/sys/dev/vt/vt_consolectl.c b/sys/dev/vt/vt_consolectl.c index df8b341..32e3ba6 100644 --- a/sys/dev/vt/vt_consolectl.c +++ b/sys/dev/vt/vt_consolectl.c @@ -73,6 +73,8 @@ static void consolectl_drvinit(void *unused) { + if (!vty_enabled(VTY_VT)) + return; make_dev(&consolectl_cdevsw, 0, UID_ROOT, GID_WHEEL, 0600, "consolectl"); } diff --git a/sys/dev/vt/vt_core.c b/sys/dev/vt/vt_core.c index 476fb4e4..ad90463 100644 --- a/sys/dev/vt/vt_core.c +++ b/sys/dev/vt/vt_core.c @@ -215,6 +215,8 @@ static void vt_update_static(void *dummy) { + if (!vty_enabled(VTY_VT)) + return; if (main_vd->vd_driver != NULL) printf("VT: running with driver \"%s\".\n", main_vd->vd_driver->vd_name); @@ -959,6 +961,9 @@ vtterm_cnprobe(struct terminal *tm, struct consdev *cp) term_attr_t attr; term_char_t c; + if (!vty_enabled(VTY_VT)) + return; + if (vd->vd_flags & VDF_INITIALIZED) /* Initialization already done. */ return; @@ -1998,6 +2003,9 @@ vt_upgrade(struct vt_device *vd) struct vt_window *vw; unsigned int i; + if (!vty_enabled(VTY_VT)) + return; + for (i = 0; i < VT_MAXWINDOWS; i++) { vw = vd->vd_windows[i]; if (vw == NULL) { @@ -2063,6 +2071,9 @@ vt_allocate(struct vt_driver *drv, void *softc) struct vt_device *vd; struct winsize wsz; + if (!vty_enabled(VTY_VT)) + return; + if (main_vd->vd_driver == NULL) { main_vd->vd_driver = drv; printf("VT: initialize with new VT driver \"%s\".\n", diff --git a/sys/dev/vt/vt_sysmouse.c b/sys/dev/vt/vt_sysmouse.c index 92eee3c..21b2400 100644 --- a/sys/dev/vt/vt_sysmouse.c +++ b/sys/dev/vt/vt_sysmouse.c @@ -405,6 +405,8 @@ static void sysmouse_drvinit(void *unused) { + if (!vty_enabled(VTY_VT)) + return; mtx_init(&sysmouse_lock, "sysmouse", NULL, MTX_DEF); cv_init(&sysmouse_sleep, "sysmrd"); make_dev(&sysmouse_cdevsw, 0, UID_ROOT, GID_WHEEL, 0600, -- cgit v1.1