From f6e16ffb73a9c31570de40816e115e09814ea021 Mon Sep 17 00:00:00 2001 From: kevlo Date: Fri, 14 Feb 2014 03:45:49 +0000 Subject: MFC r259544, r259545, r259546, r259547, r259812, r259939, r260219, r260542, r261118, r261124, r261330: - Add support for the MediaTek/Ralink RT3593 chipset. - Various minor USB WLAN fixes and improvements. --- sys/dev/usb/usbdevs | 17 +- sys/dev/usb/wlan/if_run.c | 935 +++++++++++++++++++++++----- sys/dev/usb/wlan/if_runreg.h | 1404 ++++++++++++++++++++++-------------------- sys/dev/usb/wlan/if_runvar.h | 39 +- 4 files changed, 1549 insertions(+), 846 deletions(-) (limited to 'sys/dev/usb') diff --git a/sys/dev/usb/usbdevs b/sys/dev/usb/usbdevs index 3553057..d3de833 100644 --- a/sys/dev/usb/usbdevs +++ b/sys/dev/usb/usbdevs @@ -1183,6 +1183,7 @@ product ASUS USBN13 0x1784 USB-N13 product ASUS RT3070_1 0x1790 RT3070 product ASUS USBN10 0x1786 USB-N10 product ASUS RTL8192CU 0x17ab RTL8192CU +product ASUS USBN66 0x17ad USB-N66 product ASUS RTL8192SU 0x1791 RTL8192SU product ASUS A730W 0x4202 ASUS MyPal A730W product ASUS P535 0x420f ASUS P535 PDA @@ -1285,6 +1286,7 @@ product BELKIN F5U409 0x0409 F5U409 Serial product BELKIN F6C550AVR 0x0551 F6C550-AVR UPS product BELKIN F5U120 0x1203 F5U120-PC Hub product BELKIN RTL8188CU 0x1102 RTL8188CU Wireless Adapter +product BELKIN F9L1103 0x1103 F9L1103 Wireless Adapter product BELKIN RTL8192CU 0x2102 RTL8192CU Wireless Adapter product BELKIN F7D2102 0x2103 F7D2102 Wireless Adapter product BELKIN ZD1211B 0x4050 ZD1211B @@ -1598,6 +1600,8 @@ product DLINK RT3072 0x3c0a RT3072 product DLINK DWA140B3 0x3c15 DWA-140 rev B3 product DLINK DWA160B2 0x3c1a DWA-160 rev B2 product DLINK DWA127 0x3c1b DWA-127 Wireless Adapter +product DLINK DWA162 0x3c1f DWA-162 Wireless Adapter +product DLINK DWA140D1 0x3c20 DWA-140 rev D1 product DLINK DSB650C 0x4000 10Mbps Ethernet product DLINK DSB650TX1 0x4001 10/100 Ethernet product DLINK DSB650TX 0x4002 10/100 Ethernet @@ -1658,6 +1662,7 @@ product EDIMAX RTL8192SU_3 0x7622 RTL8192SU product EDIMAX RT2870_1 0x7711 RT2870 product EDIMAX EW7717 0x7717 EW-7717 product EDIMAX EW7718 0x7718 EW-7718 +product EDIMAX EW7733UND 0x7733 EW-7733UnD product EDIMAX EW7811UN 0x7811 EW-7811Un product EDIMAX RTL8192CU 0x7822 RTL8192CU @@ -3617,11 +3622,13 @@ product RALINK RT2573 0x2573 RT2501USB Wireless Adapter product RALINK RT2671 0x2671 RT2601USB Wireless Adapter product RALINK RT2770 0x2770 RT2770 product RALINK RT2870 0x2870 RT2870 +product RALINK RT_STOR 0x2878 USB Storage product RALINK RT3070 0x3070 RT3070 product RALINK RT3071 0x3071 RT3071 product RALINK RT3072 0x3072 RT3072 product RALINK RT3370 0x3370 RT3370 product RALINK RT3572 0x3572 RT3572 +product RALINK RT3573 0x3573 RT3573 product RALINK RT5370 0x5370 RT5370 product RALINK RT5572 0x5572 RT5572 product RALINK RT8070 0x8070 RT8070 @@ -3643,10 +3650,11 @@ product REALTEK RTL8171 0x8171 RTL8171 product REALTEK RTL8172 0x8172 RTL8172 product REALTEK RTL8173 0x8173 RTL8173 product REALTEK RTL8174 0x8174 RTL8174 -product REALTEK RTL8188CE_1 0x817e RTL8188CE -product REALTEK RTL8188CU_0 0x8176 RTL8188CU -product REALTEK RTL8188CU_1 0x817a RTL8188CU -product REALTEK RTL8188CU_2 0x817b RTL8188CU +product REALTEK RTL8188CU_0 0x8176 RTL8188CU +product REALTEK RTL8188EU 0x8179 RTL8188EU +product REALTEK RTL8188CE_1 0x817e RTL8188CE +product REALTEK RTL8188CU_1 0x817a RTL8188CU +product REALTEK RTL8188CU_2 0x817b RTL8188CU product REALTEK RTL8187 0x8187 RTL8187 Wireless Adapter product REALTEK RTL8187B_0 0x8189 RTL8187B Wireless Adapter product REALTEK RTL8187B_1 0x8197 RTL8187B Wireless Adapter @@ -4486,3 +4494,4 @@ product ZYXEL G202 0x3410 G-202 product ZYXEL RT2870_1 0x3416 RT2870 product ZYXEL RT2870_2 0x341a RT2870 product ZYXEL RTL8192CU 0x341f RTL8192CU +product ZYXEL NWD2705 0x3421 NWD2705 diff --git a/sys/dev/usb/wlan/if_run.c b/sys/dev/usb/wlan/if_run.c index 37e73a7..f5b8cb5 100644 --- a/sys/dev/usb/wlan/if_run.c +++ b/sys/dev/usb/wlan/if_run.c @@ -2,7 +2,7 @@ * Copyright (c) 2008,2010 Damien Bergamini * ported to FreeBSD by Akinori Furukoshi * USB Consulting, Hans Petter Selasky - * Copyright (c) 2013 Kevin Lo + * Copyright (c) 2013-2014 Kevin Lo * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -69,14 +69,15 @@ __FBSDID("$FreeBSD$"); #include #include "usbdevs.h" -#define USB_DEBUG_VAR run_debug +#define USB_DEBUG_VAR run_debug #include +#include #include #include #ifdef USB_DEBUG -#define RUN_DEBUG +#define RUN_DEBUG #endif #ifdef RUN_DEBUG @@ -86,17 +87,19 @@ SYSCTL_INT(_hw_usb_run, OID_AUTO, debug, CTLFLAG_RW, &run_debug, 0, "run debug level"); #endif -#define IEEE80211_HAS_ADDR4(wh) \ +#define IEEE80211_HAS_ADDR4(wh) \ (((wh)->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS) /* * Because of LOR in run_key_delete(), use atomic instead. * '& RUN_CMDQ_MASQ' is to loop cmdq[]. */ -#define RUN_CMDQ_GET(c) (atomic_fetchadd_32((c), 1) & RUN_CMDQ_MASQ) +#define RUN_CMDQ_GET(c) (atomic_fetchadd_32((c), 1) & RUN_CMDQ_MASQ) static const STRUCT_USB_HOST_ID run_devs[] = { -#define RUN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } +#define RUN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } +#define RUN_DEV_EJECT(v,p) \ + { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, 0) } RUN_DEV(ABOCOM, RT2770), RUN_DEV(ABOCOM, RT2870), RUN_DEV(ABOCOM, RT3070), @@ -135,6 +138,7 @@ static const STRUCT_USB_HOST_ID run_devs[] = { RUN_DEV(ASUS, RT2870_5), RUN_DEV(ASUS, USBN13), RUN_DEV(ASUS, RT3070_1), + RUN_DEV(ASUS, USBN66), RUN_DEV(ASUS, USB_N53), RUN_DEV(ASUS2, USBN11), RUN_DEV(AZUREWAVE, RT2870_1), @@ -142,6 +146,7 @@ static const STRUCT_USB_HOST_ID run_devs[] = { RUN_DEV(AZUREWAVE, RT3070_1), RUN_DEV(AZUREWAVE, RT3070_2), RUN_DEV(AZUREWAVE, RT3070_3), + RUN_DEV(BELKIN, F9L1103), RUN_DEV(BELKIN, F5D8053V3), RUN_DEV(BELKIN, F5D8055), RUN_DEV(BELKIN, F5D8055V2), @@ -174,6 +179,7 @@ static const STRUCT_USB_HOST_ID run_devs[] = { RUN_DEV(DLINK, DWA127), RUN_DEV(DLINK, DWA140B3), RUN_DEV(DLINK, DWA160B2), + RUN_DEV(DLINK, DWA162), RUN_DEV(DLINK2, DWA130), RUN_DEV(DLINK2, RT2870_1), RUN_DEV(DLINK2, RT2870_2), @@ -186,6 +192,7 @@ static const STRUCT_USB_HOST_ID run_devs[] = { RUN_DEV(DLINK2, RT3072_1), RUN_DEV(EDIMAX, EW7717), RUN_DEV(EDIMAX, EW7718), + RUN_DEV(EDIMAX, EW7733UND), RUN_DEV(EDIMAX, RT2870_1), RUN_DEV(ENCORE, RT3070_1), RUN_DEV(ENCORE, RT3070_2), @@ -257,6 +264,7 @@ static const STRUCT_USB_HOST_ID run_devs[] = { RUN_DEV(RALINK, RT3072), RUN_DEV(RALINK, RT3370), RUN_DEV(RALINK, RT3572), + RUN_DEV(RALINK, RT3573), RUN_DEV(RALINK, RT5370), RUN_DEV(RALINK, RT5572), RUN_DEV(RALINK, RT8070), @@ -306,6 +314,9 @@ static const STRUCT_USB_HOST_ID run_devs[] = { RUN_DEV(ZINWELL, RT3072_2), RUN_DEV(ZYXEL, RT2870_1), RUN_DEV(ZYXEL, RT2870_2), + RUN_DEV(ZYXEL, NWD2705), + RUN_DEV_EJECT(RALINK, RT_STOR), +#undef RUN_DEV_EJECT #undef RUN_DEV }; @@ -321,6 +332,9 @@ static usb_callback_t run_bulk_tx_callback3; static usb_callback_t run_bulk_tx_callback4; static usb_callback_t run_bulk_tx_callback5; +static void run_autoinst(void *, struct usb_device *, + struct usb_attach_arg *); +static int run_driver_loaded(struct module *, int, void *); static void run_bulk_tx_callbackN(struct usb_xfer *xfer, usb_error_t error, u_int index); static struct ieee80211vap *run_vap_create(struct ieee80211com *, @@ -344,6 +358,7 @@ static int run_write(struct run_softc *, uint16_t, uint32_t); static int run_write_region_1(struct run_softc *, uint16_t, const uint8_t *, int); static int run_set_region_4(struct run_softc *, uint16_t, uint32_t, int); +static int run_efuse_read(struct run_softc *, uint16_t, uint16_t *, int); static int run_efuse_read_2(struct run_softc *, uint16_t, uint16_t *); static int run_eeprom_read_2(struct run_softc *, uint16_t, uint16_t *); static int run_rt2870_rf_write(struct run_softc *, uint32_t); @@ -353,6 +368,8 @@ static int run_bbp_read(struct run_softc *, uint8_t, uint8_t *); static int run_bbp_write(struct run_softc *, uint8_t, uint8_t); static int run_mcu_cmd(struct run_softc *, uint8_t, uint16_t); static const char *run_get_rf(uint16_t); +static void run_rt3593_get_txpower(struct run_softc *); +static void run_get_txpower(struct run_softc *); static int run_read_eeprom(struct run_softc *); static struct ieee80211_node *run_node_alloc(struct ieee80211vap *, const uint8_t mac[IEEE80211_ADDR_LEN]); @@ -390,12 +407,14 @@ static int run_raw_xmit(struct ieee80211_node *, struct mbuf *, const struct ieee80211_bpf_params *); static void run_start(struct ifnet *); static int run_ioctl(struct ifnet *, u_long, caddr_t); +static void run_iq_calib(struct run_softc *, u_int); static void run_set_agc(struct run_softc *, uint8_t); static void run_select_chan_group(struct run_softc *, int); static void run_set_rx_antenna(struct run_softc *, int); static void run_rt2870_set_chan(struct run_softc *, u_int); static void run_rt3070_set_chan(struct run_softc *, u_int); static void run_rt3572_set_chan(struct run_softc *, u_int); +static void run_rt3593_set_chan(struct run_softc *, u_int); static void run_rt5390_set_chan(struct run_softc *, u_int); static void run_rt5592_set_chan(struct run_softc *, u_int); static int run_set_chan(struct run_softc *, struct ieee80211_channel *); @@ -424,10 +443,13 @@ static void run_update_promisc(struct ifnet *); static void run_rt5390_bbp_init(struct run_softc *); static int run_bbp_init(struct run_softc *); static int run_rt3070_rf_init(struct run_softc *); +static void run_rt3593_rf_init(struct run_softc *); static void run_rt5390_rf_init(struct run_softc *); static int run_rt3070_filter_calib(struct run_softc *, uint8_t, uint8_t, uint8_t *); static void run_rt3070_rf_setup(struct run_softc *); +static void run_rt3593_rf_setup(struct run_softc *); +static void run_rt5390_rf_setup(struct run_softc *); static int run_txrx_enable(struct run_softc *); static void run_adjust_freq_offset(struct run_softc *); static void run_init(void *); @@ -435,6 +457,30 @@ static void run_init_locked(struct run_softc *); static void run_stop(void *); static void run_delay(struct run_softc *, u_int); +static eventhandler_tag run_etag; + +static const struct rt2860_rate { + uint8_t rate; + uint8_t mcs; + enum ieee80211_phytype phy; + uint8_t ctl_ridx; + uint16_t sp_ack_dur; + uint16_t lp_ack_dur; +} rt2860_rates[] = { + { 2, 0, IEEE80211_T_DS, 0, 314, 314 }, + { 4, 1, IEEE80211_T_DS, 1, 258, 162 }, + { 11, 2, IEEE80211_T_DS, 2, 223, 127 }, + { 22, 3, IEEE80211_T_DS, 3, 213, 117 }, + { 12, 0, IEEE80211_T_OFDM, 4, 60, 60 }, + { 18, 1, IEEE80211_T_OFDM, 4, 52, 52 }, + { 24, 2, IEEE80211_T_OFDM, 6, 48, 48 }, + { 36, 3, IEEE80211_T_OFDM, 6, 44, 44 }, + { 48, 4, IEEE80211_T_OFDM, 8, 44, 44 }, + { 72, 5, IEEE80211_T_OFDM, 8, 40, 40 }, + { 96, 6, IEEE80211_T_OFDM, 8, 40, 40 }, + { 108, 7, IEEE80211_T_OFDM, 8, 40, 40 } +}; + static const struct { uint16_t reg; uint32_t val; @@ -497,6 +543,8 @@ static const struct { RT3070_DEF_RF },rt3572_def_rf[] = { RT3572_DEF_RF +},rt3593_def_rf[] = { + RT3593_DEF_RF },rt5390_def_rf[] = { RT5390_DEF_RF },rt5392_def_rf[] = { @@ -589,6 +637,46 @@ static const struct usb_config run_config[RUN_N_XFER] = { } }; +static void +run_autoinst(void *arg, struct usb_device *udev, + struct usb_attach_arg *uaa) +{ + struct usb_interface *iface; + struct usb_interface_descriptor *id; + + if (uaa->dev_state != UAA_DEV_READY) + return; + + iface = usbd_get_iface(udev, 0); + if (iface == NULL) + return; + id = iface->idesc; + if (id == NULL || id->bInterfaceClass != UICLASS_MASS) + return; + if (usbd_lookup_id_by_uaa(run_devs, sizeof(run_devs), uaa)) + return; + + if (usb_msc_eject(udev, 0, MSC_EJECT_STOPUNIT) == 0) + uaa->dev_state = UAA_DEV_EJECTING; +} + +static int +run_driver_loaded(struct module *mod, int what, void *arg) +{ + switch (what) { + case MOD_LOAD: + run_etag = EVENTHANDLER_REGISTER(usb_dev_configured, + run_autoinst, NULL, EVENTHANDLER_PRI_ANY); + break; + case MOD_UNLOAD: + EVENTHANDLER_DEREGISTER(usb_dev_configured, run_etag); + break; + default: + return (EOPNOTSUPP); + } + return (0); +} + static int run_match(device_t self) { @@ -710,7 +798,8 @@ run_attach(device_t self) setbit(&bands, IEEE80211_MODE_11B); setbit(&bands, IEEE80211_MODE_11G); if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850 || - sc->rf_rev == RT3070_RF_3052 || sc->rf_rev == RT5592_RF_5592) + sc->rf_rev == RT3070_RF_3052 || sc->rf_rev == RT3593_RF_3053 || + sc->rf_rev == RT5592_RF_5592) setbit(&bands, IEEE80211_MODE_11A); ieee80211_init_channels(ic, NULL, &bands); @@ -1061,9 +1150,11 @@ run_load_microcode(struct run_softc *sc) } /* write microcode image */ - run_write_region_1(sc, RT2870_FW_BASE, base, 4096); - run_write(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); - run_write(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); + if (sc->mac_ver != 0x3593) { + run_write_region_1(sc, RT2870_FW_BASE, base, 4096); + run_write(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); + run_write(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); + } req.bmRequestType = UT_WRITE_VENDOR_DEVICE; req.bRequest = RT2870_RESET; @@ -1078,15 +1169,16 @@ run_load_microcode(struct run_softc *sc) run_delay(sc, 10); + run_write(sc, RT2860_H2M_BBPAGENT, 0); run_write(sc, RT2860_H2M_MAILBOX, 0); + run_write(sc, RT2860_H2M_INTSRC, 0); if ((error = run_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0)) != 0) goto fail; /* wait until microcontroller is ready */ for (ntries = 0; ntries < 1000; ntries++) { - if ((error = run_read(sc, RT2860_SYS_CTRL, &tmp)) != 0) { + if ((error = run_read(sc, RT2860_SYS_CTRL, &tmp)) != 0) goto fail; - } if (tmp & RT2860_MCU_READY) break; run_delay(sc, 10); @@ -1248,9 +1340,8 @@ run_set_region_4(struct run_softc *sc, uint16_t reg, uint32_t val, int len) return (error); } -/* Read 16-bit from eFUSE ROM (RT3070 only.) */ static int -run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) +run_efuse_read(struct run_softc *sc, uint16_t addr, uint16_t *val, int count) { uint32_t tmp; uint16_t reg; @@ -1259,7 +1350,8 @@ run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) return (error); - addr *= 2; + if (count == 2) + addr *= 2; /*- * Read one 16-byte block into registers EFUSE_DATA[0-3]: * DATA0: F E D C @@ -1289,10 +1381,19 @@ run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) if ((error = run_read(sc, reg, &tmp)) != 0) return (error); - *val = (addr & 2) ? tmp >> 16 : tmp & 0xffff; + tmp >>= (8 * (addr & 0x3)); + *val = (addr & 1) ? tmp >> 16 : tmp & 0xffff; + return (0); } +/* Read 16-bit from eFUSE ROM for RT3xxx. */ +static int +run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) +{ + return (run_efuse_read(sc, addr, val, 2)); +} + static int run_eeprom_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) { @@ -1305,7 +1406,7 @@ run_eeprom_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) req.bRequest = RT2870_EEPROM_READ; USETW(req.wValue, 0); USETW(req.wIndex, addr); - USETW(req.wLength, sizeof tmp); + USETW(req.wLength, sizeof(tmp)); error = usbd_do_request(sc->sc_udev, &sc->sc_mtx, &req, &tmp); if (error == 0) @@ -1500,6 +1601,7 @@ run_get_rf(uint16_t rev) case RT3070_RF_3021: return "RT3021"; case RT3070_RF_3022: return "RT3022"; case RT3070_RF_3052: return "RT3052"; + case RT3593_RF_3053: return "RT3053"; case RT5592_RF_5592: return "RT5592"; case RT5390_RF_5370: return "RT5370"; case RT5390_RF_5372: return "RT5372"; @@ -1507,6 +1609,125 @@ run_get_rf(uint16_t rev) return ("unknown"); } +static void +run_rt3593_get_txpower(struct run_softc *sc) +{ + uint16_t addr, val; + int i; + + /* Read power settings for 2GHz channels. */ + for (i = 0; i < 14; i += 2) { + addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE1 : + RT2860_EEPROM_PWR2GHZ_BASE1; + run_srom_read(sc, addr + i / 2, &val); + sc->txpow1[i + 0] = (int8_t)(val & 0xff); + sc->txpow1[i + 1] = (int8_t)(val >> 8); + + addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE2 : + RT2860_EEPROM_PWR2GHZ_BASE2; + run_srom_read(sc, addr + i / 2, &val); + sc->txpow2[i + 0] = (int8_t)(val & 0xff); + sc->txpow2[i + 1] = (int8_t)(val >> 8); + + if (sc->ntxchains == 3) { + run_srom_read(sc, RT3593_EEPROM_PWR2GHZ_BASE3 + i / 2, + &val); + sc->txpow3[i + 0] = (int8_t)(val & 0xff); + sc->txpow3[i + 1] = (int8_t)(val >> 8); + } + } + /* Fix broken Tx power entries. */ + for (i = 0; i < 14; i++) { + if (sc->txpow1[i] > 31) + sc->txpow1[i] = 5; + if (sc->txpow2[i] > 31) + sc->txpow2[i] = 5; + if (sc->ntxchains == 3) { + if (sc->txpow3[i] > 31) + sc->txpow3[i] = 5; + } + } + /* Read power settings for 5GHz channels. */ + for (i = 0; i < 40; i += 2) { + run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); + sc->txpow1[i + 14] = (int8_t)(val & 0xff); + sc->txpow1[i + 15] = (int8_t)(val >> 8); + + run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); + sc->txpow2[i + 14] = (int8_t)(val & 0xff); + sc->txpow2[i + 15] = (int8_t)(val >> 8); + + if (sc->ntxchains == 3) { + run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE3 + i / 2, + &val); + sc->txpow3[i + 14] = (int8_t)(val & 0xff); + sc->txpow3[i + 15] = (int8_t)(val >> 8); + } + } +} + +static void +run_get_txpower(struct run_softc *sc) +{ + uint16_t val; + int i; + + /* Read power settings for 2GHz channels. */ + for (i = 0; i < 14; i += 2) { + run_srom_read(sc, RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2, &val); + sc->txpow1[i + 0] = (int8_t)(val & 0xff); + sc->txpow1[i + 1] = (int8_t)(val >> 8); + + if (sc->mac_ver != 0x5390) { + run_srom_read(sc, + RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2, &val); + sc->txpow2[i + 0] = (int8_t)(val & 0xff); + sc->txpow2[i + 1] = (int8_t)(val >> 8); + } + } + /* Fix broken Tx power entries. */ + for (i = 0; i < 14; i++) { + if (sc->mac_ver >= 0x5390) { + if (sc->txpow1[i] < 0 || sc->txpow1[i] > 27) + sc->txpow1[i] = 5; + } else { + if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31) + sc->txpow1[i] = 5; + } + if (sc->mac_ver > 0x5390) { + if (sc->txpow2[i] < 0 || sc->txpow2[i] > 27) + sc->txpow2[i] = 5; + } else if (sc->mac_ver < 0x5390) { + if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31) + sc->txpow2[i] = 5; + } + DPRINTF("chan %d: power1=%d, power2=%d\n", + rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i]); + } + /* Read power settings for 5GHz channels. */ + for (i = 0; i < 40; i += 2) { + run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); + sc->txpow1[i + 14] = (int8_t)(val & 0xff); + sc->txpow1[i + 15] = (int8_t)(val >> 8); + + run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); + sc->txpow2[i + 14] = (int8_t)(val & 0xff); + sc->txpow2[i + 15] = (int8_t)(val >> 8); + } + /* Fix broken Tx power entries. */ + for (i = 0; i < 40; i++ ) { + if (sc->mac_ver != 0x5592) { + if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) + sc->txpow1[14 + i] = 5; + if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) + sc->txpow2[14 + i] = 5; + } + DPRINTF("chan %d: power1=%d, power2=%d\n", + rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], + sc->txpow2[14 + i]); + } +} + static int run_read_eeprom(struct run_softc *sc) { @@ -1520,7 +1741,7 @@ run_read_eeprom(struct run_softc *sc) if (sc->mac_ver >= 0x3070) { run_read(sc, RT3070_EFUSE_CTRL, &tmp); DPRINTF("EFUSE_CTRL=0x%08x\n", tmp); - if (tmp & RT3070_SEL_EFUSE) + if ((tmp & RT3070_SEL_EFUSE) || sc->mac_ver == 0x3593) sc->sc_srom_read = run_efuse_read_2; } @@ -1539,7 +1760,7 @@ run_read_eeprom(struct run_softc *sc) sc->sc_bssid[4] = val & 0xff; sc->sc_bssid[5] = val >> 8; - if (sc->mac_ver < 0x5390) { + if (sc->mac_ver < 0x3593) { /* read vender BBP settings */ for (i = 0; i < 10; i++) { run_srom_read(sc, RT2860_EEPROM_BBP_BASE + i, &val); @@ -1562,16 +1783,22 @@ run_read_eeprom(struct run_softc *sc) } /* read RF frequency offset from EEPROM */ - run_srom_read(sc, RT2860_EEPROM_FREQ_LEDS, &val); + run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS : + RT3593_EEPROM_FREQ, &val); sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; DPRINTF("EEPROM freq offset %d\n", sc->freq & 0xff); + run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS : + RT3593_EEPROM_FREQ_LEDS, &val); if (val >> 8 != 0xff) { /* read LEDs operating mode */ sc->leds = val >> 8; - run_srom_read(sc, RT2860_EEPROM_LED1, &sc->led[0]); - run_srom_read(sc, RT2860_EEPROM_LED2, &sc->led[1]); - run_srom_read(sc, RT2860_EEPROM_LED3, &sc->led[2]); + run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED1 : + RT3593_EEPROM_LED1, &sc->led[0]); + run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED2 : + RT3593_EEPROM_LED2, &sc->led[1]); + run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED3 : + RT3593_EEPROM_LED3, &sc->led[2]); } else { /* broken EEPROM, use default settings */ sc->leds = 0x01; @@ -1589,6 +1816,8 @@ run_read_eeprom(struct run_softc *sc) run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val); if (val == 0xffff) { + device_printf(sc->sc_dev, + "invalid EEPROM antenna info, using default\n"); DPRINTF("invalid EEPROM antenna info, using default\n"); if (sc->mac_ver == 0x3572) { /* default to RF3052 2T2R */ @@ -1633,60 +1862,11 @@ run_read_eeprom(struct run_softc *sc) sc->rfswitch = val & 1; } - /* read power settings for 2GHz channels */ - for (i = 0; i < 14; i += 2) { - run_srom_read(sc, RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2, &val); - sc->txpow1[i + 0] = (int8_t)(val & 0xff); - sc->txpow1[i + 1] = (int8_t)(val >> 8); - - if (sc->mac_ver != 0x5390) { - run_srom_read(sc, - RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2, &val); - sc->txpow2[i + 0] = (int8_t)(val & 0xff); - sc->txpow2[i + 1] = (int8_t)(val >> 8); - } - } - /* fix broken Tx power entries */ - for (i = 0; i < 14; i++) { - if (sc->mac_ver >= 0x5390) { - if (sc->txpow1[i] < 0 || sc->txpow1[i] > 27) - sc->txpow1[i] = 5; - } else { - if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31) - sc->txpow1[i] = 5; - } - if (sc->mac_ver > 0x5390) { - if (sc->txpow2[i] < 0 || sc->txpow2[i] > 27) - sc->txpow2[i] = 5; - } else if (sc->mac_ver < 0x5390) { - if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31) - sc->txpow2[i] = 5; - } - DPRINTF("chan %d: power1=%d, power2=%d\n", - rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i]); - } - /* read power settings for 5GHz channels */ - for (i = 0; i < 40; i += 2) { - run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); - sc->txpow1[i + 14] = (int8_t)(val & 0xff); - sc->txpow1[i + 15] = (int8_t)(val >> 8); - - run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); - sc->txpow2[i + 14] = (int8_t)(val & 0xff); - sc->txpow2[i + 15] = (int8_t)(val >> 8); - } - /* fix broken Tx power entries */ - for (i = 0; i < 40; i++ ) { - if (sc->mac_ver != 0x5592) { - if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) - sc->txpow1[14 + i] = 5; - if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) - sc->txpow2[14 + i] = 5; - } - DPRINTF("chan %d: power1=%d, power2=%d\n", - rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], - sc->txpow2[14 + i]); - } + /* Read Tx power settings. */ + if (sc->mac_ver == 0x3593) + run_rt3593_get_txpower(sc); + else + run_get_txpower(sc); /* read Tx power compensation for each Tx rate */ run_srom_read(sc, RT2860_EEPROM_DELTAPWR, &val); @@ -1722,27 +1902,38 @@ run_read_eeprom(struct run_softc *sc) sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx]); } - /* read RSSI offsets and LNA gains from EEPROM */ - run_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ, &val); + /* Read RSSI offsets and LNA gains from EEPROM. */ + run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_2GHZ : + RT3593_EEPROM_RSSI1_2GHZ, &val); sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ sc->rssi_2ghz[1] = val >> 8; /* Ant B */ - run_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ, &val); + run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_2GHZ : + RT3593_EEPROM_RSSI2_2GHZ, &val); if (sc->mac_ver >= 0x3070) { - /* - * On RT3070 chips (limited to 2 Rx chains), this ROM - * field contains the Tx mixer gain for the 2GHz band. - */ - if ((val & 0xff) != 0xff) - sc->txmixgain_2ghz = val & 0x7; + if (sc->mac_ver == 0x3593) { + sc->txmixgain_2ghz = 0; + sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ + } else { + /* + * On RT3070 chips (limited to 2 Rx chains), this ROM + * field contains the Tx mixer gain for the 2GHz band. + */ + if ((val & 0xff) != 0xff) + sc->txmixgain_2ghz = val & 0x7; + } DPRINTF("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz); } else sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ + if (sc->mac_ver == 0x3593) + run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); sc->lna[2] = val >> 8; /* channel group 2 */ - run_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ, &val); + run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_5GHZ : + RT3593_EEPROM_RSSI1_5GHZ, &val); sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ sc->rssi_5ghz[1] = val >> 8; /* Ant B */ - run_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ, &val); + run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_5GHZ : + RT3593_EEPROM_RSSI2_5GHZ, &val); if (sc->mac_ver == 0x3572) { /* * On RT3572 chips (limited to 2 Rx chains), this ROM @@ -1753,9 +1944,14 @@ run_read_eeprom(struct run_softc *sc) DPRINTF("tx mixer gain=%u (5GHz)\n", sc->txmixgain_5ghz); } else sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ + if (sc->mac_ver == 0x3593) { + sc->txmixgain_5ghz = 0; + run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); + } sc->lna[3] = val >> 8; /* channel group 3 */ - run_srom_read(sc, RT2860_EEPROM_LNA, &val); + run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LNA : + RT3593_EEPROM_LNA, &val); sc->lna[0] = val & 0xff; /* channel group 0 */ sc->lna[1] = val >> 8; /* channel group 1 */ @@ -2570,9 +2766,11 @@ run_rx_frame(struct run_softc *sc, struct mbuf *m, uint32_t dmalen) rxwi = mtod(m, struct rt2860_rxwi *); len = le16toh(rxwi->len) & 0xfff; - rxwisize = (sc->mac_ver == 0x5592) ? - sizeof(struct rt2860_rxwi) + sizeof(uint64_t) : - sizeof(struct rt2860_rxwi); + rxwisize = sizeof(struct rt2860_rxwi); + if (sc->mac_ver == 0x5592) + rxwisize += sizeof(uint64_t); + else if (sc->mac_ver == 0x3593) + rxwisize += sizeof(uint32_t); if (__predict_false(len > dmalen)) { m_freem(m); ifp->if_ierrors++; @@ -2683,9 +2881,11 @@ run_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) uint16_t rxwisize; int xferlen; - rxwisize = (sc->mac_ver == 0x5592) ? - sizeof(struct rt2860_rxwi) + sizeof(uint64_t) : - sizeof(struct rt2860_rxwi); + rxwisize = sizeof(struct rt2860_rxwi); + if (sc->mac_ver == 0x5592) + rxwisize += sizeof(uint64_t); + else if (sc->mac_ver == 0x3593) + rxwisize += sizeof(uint32_t); usbd_xfer_status(xfer, &xferlen, NULL, NULL, NULL); @@ -2869,10 +3069,10 @@ tr_setup: STAILQ_REMOVE_HEAD(&pq->tx_qh, next); m = data->m; - size = (sc->mac_ver == 0x5592) ? - RUN_MAX_TXSZ + sizeof(uint32_t) : RUN_MAX_TXSZ; + size = (sc->mac_ver == 0x5592) ? + sizeof(data->desc) + sizeof(uint32_t) : sizeof(data->desc); if ((m->m_pkthdr.len + - sizeof(data->desc) + 3 + 8) > size) { + size + 3 + 8) > RUN_MAX_TXSZ) { DPRINTF("data overflow, %u bytes\n", m->m_pkthdr.len); @@ -2884,8 +3084,6 @@ tr_setup: } pc = usbd_xfer_get_frame(xfer, 0); - size = (sc->mac_ver == 0x5592) ? - sizeof(data->desc) + sizeof(uint32_t) : sizeof(data->desc); usbd_copy_in(pc, 0, &data->desc, size); usbd_m_copy_in(pc, size, m, 0, m->m_pkthdr.len); size += m->m_pkthdr.len; @@ -3599,6 +3797,107 @@ run_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) } static void +run_iq_calib(struct run_softc *sc, u_int chan) +{ + uint16_t val; + + /* Tx0 IQ gain. */ + run_bbp_write(sc, 158, 0x2c); + if (chan <= 14) + run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ, &val, 1); + else if (chan <= 64) { + run_efuse_read(sc, + RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ, + &val, 1); + } else if (chan <= 138) { + run_efuse_read(sc, + RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ, + &val, 1); + } else if (chan <= 165) { + run_efuse_read(sc, + RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ, + &val, 1); + } else + val = 0; + run_bbp_write(sc, 159, val); + + /* Tx0 IQ phase. */ + run_bbp_write(sc, 158, 0x2d); + if (chan <= 14) { + run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ, + &val, 1); + } else if (chan <= 64) { + run_efuse_read(sc, + RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ, + &val, 1); + } else if (chan <= 138) { + run_efuse_read(sc, + RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ, + &val, 1); + } else if (chan <= 165) { + run_efuse_read(sc, + RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ, + &val, 1); + } else + val = 0; + run_bbp_write(sc, 159, val); + + /* Tx1 IQ gain. */ + run_bbp_write(sc, 158, 0x4a); + if (chan <= 14) { + run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ, + &val, 1); + } else if (chan <= 64) { + run_efuse_read(sc, + RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ, + &val, 1); + } else if (chan <= 138) { + run_efuse_read(sc, + RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ, + &val, 1); + } else if (chan <= 165) { + run_efuse_read(sc, + RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ, + &val, 1); + } else + val = 0; + run_bbp_write(sc, 159, val); + + /* Tx1 IQ phase. */ + run_bbp_write(sc, 158, 0x4b); + if (chan <= 14) { + run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ, + &val, 1); + } else if (chan <= 64) { + run_efuse_read(sc, + RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ, + &val, 1); + } else if (chan <= 138) { + run_efuse_read(sc, + RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ, + &val, 1); + } else if (chan <= 165) { + run_efuse_read(sc, + RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ, + &val, 1); + } else + val = 0; + run_bbp_write(sc, 159, val); + + /* RF IQ compensation control. */ + run_bbp_write(sc, 158, 0x04); + run_efuse_read(sc, RT5390_EEPROM_RF_IQ_COMPENSATION_CTL, + &val, 1); + run_bbp_write(sc, 159, val); + + /* RF IQ imbalance compensation control. */ + run_bbp_write(sc, 158, 0x03); + run_efuse_read(sc, + RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL, &val, 1); + run_bbp_write(sc, 159, val); +} + +static void run_set_agc(struct run_softc *sc, uint8_t agc) { uint8_t bbp; @@ -3626,6 +3925,11 @@ run_select_chan_group(struct run_softc *sc, int group) if (sc->mac_ver < 0x3572) run_bbp_write(sc, 86, 0x00); + if (sc->mac_ver == 0x3593) { + run_bbp_write(sc, 77, 0x98); + run_bbp_write(sc, 83, (group == 0) ? 0x8a : 0x9a); + } + if (group == 0) { if (sc->ext_2ghz_lna) { if (sc->mac_ver >= 0x5390) @@ -3656,7 +3960,8 @@ run_select_chan_group(struct run_softc *sc, int group) } else if (sc->mac_ver >= 0x5390) run_bbp_write(sc, 75, 0x50); else { - run_bbp_write(sc, 82, 0x84); + run_bbp_write(sc, 82, + (sc->mac_ver == 0x3593) ? 0x62 : 0x84); run_bbp_write(sc, 75, 0x50); } } @@ -3682,7 +3987,8 @@ run_select_chan_group(struct run_softc *sc, int group) } else if (sc->mac_ver == 0x3572) run_bbp_write(sc, 82, 0x94); else - run_bbp_write(sc, 82, 0xf2); + run_bbp_write(sc, 82, + (sc->mac_ver == 0x3593) ? 0x82 : 0xf2); if (sc->ext_5ghz_lna) run_bbp_write(sc, 75, 0x46); else @@ -3696,12 +4002,18 @@ run_select_chan_group(struct run_softc *sc, int group) /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; + if (sc->mac_ver == 0x3593) + tmp |= 1 << 29 | 1 << 28; if (sc->nrxchains > 1) tmp |= RT2860_LNA_PE1_EN; if (group == 0) { /* 2GHz */ tmp |= RT2860_PA_PE_G0_EN; if (sc->ntxchains > 1) tmp |= RT2860_PA_PE_G1_EN; + if (sc->mac_ver == 0x3593) { + if (sc->ntxchains > 2) + tmp |= 1 << 25; + } } else { /* 5GHz */ tmp |= RT2860_PA_PE_A0_EN; if (sc->ntxchains > 1) @@ -3719,6 +4031,15 @@ run_select_chan_group(struct run_softc *sc, int group) run_bbp_write(sc, 196, 0x1a); } + if (sc->mac_ver == 0x3593) { + run_read(sc, RT2860_GPIO_CTRL, &tmp); + tmp &= ~0x01010000; + if (group == 0) + tmp |= 0x00010000; + tmp = (tmp & ~0x00009090) | 0x00000090; + run_write(sc, RT2860_GPIO_CTRL, tmp); + } + /* set initial AGC value */ if (group == 0) { /* 2GHz band */ if (sc->mac_ver >= 0x3070) @@ -3728,7 +4049,7 @@ run_select_chan_group(struct run_softc *sc, int group) } else { /* 5GHz band */ if (sc->mac_ver == 0x5592) agc = 0x24 + sc->lna[group] * 2; - else if (sc->mac_ver == 0x3572) + else if (sc->mac_ver == 0x3572 || sc->mac_ver == 0x3593) agc = 0x22 + (sc->lna[group] * 5) / 3; else agc = 0x32 + (sc->lna[group] * 5) / 3; @@ -4023,6 +4344,166 @@ run_rt3572_set_chan(struct run_softc *sc, u_int chan) } static void +run_rt3593_set_chan(struct run_softc *sc, u_int chan) +{ + int8_t txpow1, txpow2, txpow3; + uint8_t h20mhz, rf; + int i; + + /* find the settings for this channel (we know it exists) */ + for (i = 0; rt2860_rf2850[i].chan != chan; i++); + + /* use Tx power values from EEPROM */ + txpow1 = sc->txpow1[i]; + txpow2 = sc->txpow2[i]; + txpow3 = (sc->ntxchains == 3) ? sc->txpow3[i] : 0; + + if (chan <= 14) { + run_bbp_write(sc, 25, sc->bbp25); + run_bbp_write(sc, 26, sc->bbp26); + } else { + /* Enable IQ phase correction. */ + run_bbp_write(sc, 25, 0x09); + run_bbp_write(sc, 26, 0xff); + } + + run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); + run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); + run_rt3070_rf_read(sc, 11, &rf); + rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); + run_rt3070_rf_write(sc, 11, rf); + + /* Set pll_idoh. */ + run_rt3070_rf_read(sc, 11, &rf); + rf &= ~0x4c; + rf |= (chan <= 14) ? 0x44 : 0x48; + run_rt3070_rf_write(sc, 11, rf); + + if (chan <= 14) + rf = txpow1 & 0x1f; + else + rf = 0x40 | ((txpow1 & 0x18) << 1) | (txpow1 & 0x07); + run_rt3070_rf_write(sc, 53, rf); + + if (chan <= 14) + rf = txpow2 & 0x1f; + else + rf = 0x40 | ((txpow2 & 0x18) << 1) | (txpow2 & 0x07); + run_rt3070_rf_write(sc, 55, rf); + + if (chan <= 14) + rf = txpow3 & 0x1f; + else + rf = 0x40 | ((txpow3 & 0x18) << 1) | (txpow3 & 0x07); + run_rt3070_rf_write(sc, 54, rf); + + rf = RT3070_RF_BLOCK | RT3070_PLL_PD; + if (sc->ntxchains == 3) + rf |= RT3070_TX0_PD | RT3070_TX1_PD | RT3070_TX2_PD; + else + rf |= RT3070_TX0_PD | RT3070_TX1_PD; + rf |= RT3070_RX0_PD | RT3070_RX1_PD | RT3070_RX2_PD; + run_rt3070_rf_write(sc, 1, rf); + + run_adjust_freq_offset(sc); + + run_rt3070_rf_write(sc, 31, (chan <= 14) ? 0xa0 : 0x80); + + h20mhz = (sc->rf24_20mhz & 0x20) >> 5; + run_rt3070_rf_read(sc, 30, &rf); + rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); + run_rt3070_rf_write(sc, 30, rf); + + run_rt3070_rf_read(sc, 36, &rf); + if (chan <= 14) + rf |= 0x80; + else + rf &= ~0x80; + run_rt3070_rf_write(sc, 36, rf); + + /* Set vcolo_bs. */ + run_rt3070_rf_write(sc, 34, (chan <= 14) ? 0x3c : 0x20); + /* Set pfd_delay. */ + run_rt3070_rf_write(sc, 12, (chan <= 14) ? 0x1a : 0x12); + + /* Set vco bias current control. */ + run_rt3070_rf_read(sc, 6, &rf); + rf &= ~0xc0; + if (chan <= 14) + rf |= 0x40; + else if (chan <= 128) + rf |= 0x80; + else + rf |= 0x40; + run_rt3070_rf_write(sc, 6, rf); + + run_rt3070_rf_read(sc, 30, &rf); + rf = (rf & ~0x18) | 0x10; + run_rt3070_rf_write(sc, 30, rf); + + run_rt3070_rf_write(sc, 10, (chan <= 14) ? 0xd3 : 0xd8); + run_rt3070_rf_write(sc, 13, (chan <= 14) ? 0x12 : 0x23); + + run_rt3070_rf_read(sc, 51, &rf); + rf = (rf & ~0x03) | 0x01; + run_rt3070_rf_write(sc, 51, rf); + /* Set tx_mx1_cc. */ + run_rt3070_rf_read(sc, 51, &rf); + rf &= ~0x1c; + rf |= (chan <= 14) ? 0x14 : 0x10; + run_rt3070_rf_write(sc, 51, rf); + /* Set tx_mx1_ic. */ + run_rt3070_rf_read(sc, 51, &rf); + rf &= ~0xe0; + rf |= (chan <= 14) ? 0x60 : 0x40; + run_rt3070_rf_write(sc, 51, rf); + /* Set tx_lo1_ic. */ + run_rt3070_rf_read(sc, 49, &rf); + rf &= ~0x1c; + rf |= (chan <= 14) ? 0x0c : 0x08; + run_rt3070_rf_write(sc, 49, rf); + /* Set tx_lo1_en. */ + run_rt3070_rf_read(sc, 50, &rf); + run_rt3070_rf_write(sc, 50, rf & ~0x20); + /* Set drv_cc. */ + run_rt3070_rf_read(sc, 57, &rf); + rf &= ~0xfc; + rf |= (chan <= 14) ? 0x6c : 0x3c; + run_rt3070_rf_write(sc, 57, rf); + /* Set rx_mix1_ic, rxa_lnactr, lna_vc, lna_inbias_en and lna_en. */ + run_rt3070_rf_write(sc, 44, (chan <= 14) ? 0x93 : 0x9b); + /* Set drv_gnd_a, tx_vga_cc_a and tx_mx2_gain. */ + run_rt3070_rf_write(sc, 52, (chan <= 14) ? 0x45 : 0x05); + /* Enable VCO calibration. */ + run_rt3070_rf_read(sc, 3, &rf); + rf &= ~RT5390_VCOCAL; + rf |= (chan <= 14) ? RT5390_VCOCAL : 0xbe; + run_rt3070_rf_write(sc, 3, rf); + + if (chan <= 14) + rf = 0x23; + else if (chan <= 64) + rf = 0x36; + else if (chan <= 128) + rf = 0x32; + else + rf = 0x30; + run_rt3070_rf_write(sc, 39, rf); + if (chan <= 14) + rf = 0xbb; + else if (chan <= 64) + rf = 0xeb; + else if (chan <= 128) + rf = 0xb3; + else + rf = 0x9b; + run_rt3070_rf_write(sc, 45, rf); + + /* Set FEQ/AEQ control. */ + run_bbp_write(sc, 105, 0x34); +} + +static void run_rt5390_set_chan(struct run_softc *sc, u_int chan) { int8_t txpow1, txpow2; @@ -4310,6 +4791,8 @@ run_set_chan(struct run_softc *sc, struct ieee80211_channel *c) run_rt5592_set_chan(sc, chan); else if (sc->mac_ver >= 0x5390) run_rt5390_set_chan(sc, chan); + else if (sc->mac_ver == 0x3593) + run_rt3593_set_chan(sc, chan); else if (sc->mac_ver == 0x3572) run_rt3572_set_chan(sc, chan); else if (sc->mac_ver >= 0x3070) @@ -4332,6 +4815,10 @@ run_set_chan(struct run_softc *sc, struct ieee80211_channel *c) run_delay(sc, 10); + /* Perform IQ calibration. */ + if (sc->mac_ver >= 0x5392) + run_iq_calib(sc, chan); + return (0); } @@ -4629,8 +5116,8 @@ run_enable_tsf_sync(struct run_softc *sc) static void run_enable_mrr(struct run_softc *sc) { -#define CCK(mcs) (mcs) -#define OFDM(mcs) (1 << 3 | (mcs)) +#define CCK(mcs) (mcs) +#define OFDM(mcs) (1 << 3 | (mcs)) run_write(sc, RT2860_LG_FBK_CFG0, OFDM(6) << 28 | /* 54->48 */ OFDM(5) << 24 | /* 48->36 */ @@ -4849,11 +5336,20 @@ run_bbp_init(struct run_softc *sc) } } + if (sc->mac_ver == 0x3593) { + run_bbp_write(sc, 79, 0x13); + run_bbp_write(sc, 80, 0x05); + run_bbp_write(sc, 81, 0x33); + run_bbp_write(sc, 86, 0x46); + run_bbp_write(sc, 137, 0x0f); + } + /* fix BBP84 for RT2860E */ if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) run_bbp_write(sc, 84, 0x19); - if (sc->mac_ver >= 0x3070 && sc->mac_ver != 0x5592) { + if (sc->mac_ver >= 0x3070 && (sc->mac_ver != 0x3593 && + sc->mac_ver != 0x5592)) { run_bbp_write(sc, 79, 0x13); run_bbp_write(sc, 80, 0x05); run_bbp_write(sc, 81, 0x33); @@ -5009,6 +5505,55 @@ run_rt3070_rf_init(struct run_softc *sc) } static void +run_rt3593_rf_init(struct run_softc *sc) +{ + uint32_t tmp; + uint8_t rf; + int i; + + /* Disable the GPIO bits 4 and 7 for LNA PE control. */ + run_read(sc, RT3070_GPIO_SWITCH, &tmp); + tmp &= ~(1 << 4 | 1 << 7); + run_write(sc, RT3070_GPIO_SWITCH, tmp); + + /* Initialize RF registers to default value. */ + for (i = 0; i < nitems(rt3593_def_rf); i++) { + run_rt3070_rf_write(sc, rt3593_def_rf[i].reg, + rt3593_def_rf[i].val); + } + + /* Toggle RF R2 to initiate calibration. */ + run_rt3070_rf_write(sc, 2, RT5390_RESCAL); + + /* Initialize RF frequency offset. */ + run_adjust_freq_offset(sc); + + run_rt3070_rf_read(sc, 18, &rf); + run_rt3070_rf_write(sc, 18, rf | RT3593_AUTOTUNE_BYPASS); + + /* + * Increase voltage from 1.2V to 1.35V, wait for 1 msec to + * decrease voltage back to 1.2V. + */ + run_read(sc, RT3070_LDO_CFG0, &tmp); + tmp = (tmp & ~0x1f000000) | 0x0d000000; + run_write(sc, RT3070_LDO_CFG0, tmp); + run_delay(sc, 1); + tmp = (tmp & ~0x1f000000) | 0x01000000; + run_write(sc, RT3070_LDO_CFG0, tmp); + + sc->rf24_20mhz = 0x1f; + sc->rf24_40mhz = 0x2f; + + /* Save default BBP registers 25 and 26 values. */ + run_bbp_read(sc, 25, &sc->bbp25); + run_bbp_read(sc, 26, &sc->bbp26); + + run_read(sc, RT3070_OPT_14, &tmp); + run_write(sc, RT3070_OPT_14, tmp | 1); +} + +static void run_rt5390_rf_init(struct run_softc *sc) { uint32_t tmp; @@ -5143,49 +5688,7 @@ run_rt3070_rf_setup(struct run_softc *sc) uint8_t bbp, rf; int i; - if (sc->mac_ver >= 0x5390) { - if (sc->mac_rev >= 0x0211) { - /* Enable DC filter. */ - run_bbp_write(sc, 103, 0xc0); - - if (sc->mac_ver != 0x5592) { - /* Improve power consumption. */ - run_bbp_read(sc, 31, &bbp); - run_bbp_write(sc, 31, bbp & ~0x03); - } - } - - run_bbp_read(sc, 138, &bbp); - if (sc->ntxchains == 1) - bbp |= 0x20; /* turn off DAC1 */ - if (sc->nrxchains == 1) - bbp &= ~0x02; /* turn off ADC1 */ - run_bbp_write(sc, 138, bbp); - - run_rt3070_rf_read(sc, 38, &rf); - run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); - - run_rt3070_rf_read(sc, 39, &rf); - run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); - - /* Avoid data lost and CRC error. */ - run_bbp_read(sc, 4, &bbp); - run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); - - run_rt3070_rf_read(sc, 30, &rf); - rf = (rf & ~0x18) | 0x10; - run_rt3070_rf_write(sc, 30, rf); - - if (sc->mac_ver != 0x5592) { - run_write(sc, RT2860_TX_SW_CFG1, 0); - if (sc->mac_rev < 0x0211) { - run_write(sc, RT2860_TX_SW_CFG2, - sc->patch_dac ? 0x2c : 0x0f); - } else - run_write(sc, RT2860_TX_SW_CFG2, 0); - } - - } else if (sc->mac_ver == 0x3572) { + if (sc->mac_ver == 0x3572) { /* enable DC filter */ if (sc->mac_rev >= 0x0201) run_bbp_write(sc, 103, 0xc0); @@ -5249,7 +5752,7 @@ run_rt3070_rf_setup(struct run_softc *sc) } /* initialize RF registers from ROM for >=RT3071*/ - if (sc->mac_ver >= 0x3071 && sc->mac_ver < 0x5390) { + if (sc->mac_ver >= 0x3071) { for (i = 0; i < 10; i++) { if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) continue; @@ -5258,6 +5761,123 @@ run_rt3070_rf_setup(struct run_softc *sc) } } +static void +run_rt3593_rf_setup(struct run_softc *sc) +{ + uint8_t bbp, rf; + + if (sc->mac_rev >= 0x0211) { + /* Enable DC filter. */ + run_bbp_write(sc, 103, 0xc0); + } + run_write(sc, RT2860_TX_SW_CFG1, 0); + if (sc->mac_rev < 0x0211) { + run_write(sc, RT2860_TX_SW_CFG2, + sc->patch_dac ? 0x2c : 0x0f); + } else + run_write(sc, RT2860_TX_SW_CFG2, 0); + + run_rt3070_rf_read(sc, 50, &rf); + run_rt3070_rf_write(sc, 50, rf & ~RT3593_TX_LO2); + + run_rt3070_rf_read(sc, 51, &rf); + rf = (rf & ~(RT3593_TX_LO1 | 0x0c)) | + ((sc->txmixgain_2ghz & 0x07) << 2); + run_rt3070_rf_write(sc, 51, rf); + + run_rt3070_rf_read(sc, 38, &rf); + run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); + + run_rt3070_rf_read(sc, 39, &rf); + run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); + + run_rt3070_rf_read(sc, 1, &rf); + run_rt3070_rf_write(sc, 1, rf & ~(RT3070_RF_BLOCK | RT3070_PLL_PD)); + + run_rt3070_rf_read(sc, 30, &rf); + rf = (rf & ~0x18) | 0x10; + run_rt3070_rf_write(sc, 30, rf); + + /* Apply maximum likelihood detection for 2 stream case. */ + run_bbp_read(sc, 105, &bbp); + if (sc->nrxchains > 1) + run_bbp_write(sc, 105, bbp | RT5390_MLD); + + /* Avoid data lost and CRC error. */ + run_bbp_read(sc, 4, &bbp); + run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); + + run_bbp_write(sc, 92, 0x02); + run_bbp_write(sc, 82, 0x82); + run_bbp_write(sc, 106, 0x05); + run_bbp_write(sc, 104, 0x92); + run_bbp_write(sc, 88, 0x90); + run_bbp_write(sc, 148, 0xc8); + run_bbp_write(sc, 47, 0x48); + run_bbp_write(sc, 120, 0x50); + + run_bbp_write(sc, 163, 0x9d); + + /* SNR mapping. */ + run_bbp_write(sc, 142, 0x06); + run_bbp_write(sc, 143, 0xa0); + run_bbp_write(sc, 142, 0x07); + run_bbp_write(sc, 143, 0xa1); + run_bbp_write(sc, 142, 0x08); + run_bbp_write(sc, 143, 0xa2); + + run_bbp_write(sc, 31, 0x08); + run_bbp_write(sc, 68, 0x0b); + run_bbp_write(sc, 105, 0x04); +} + +static void +run_rt5390_rf_setup(struct run_softc *sc) +{ + uint8_t bbp, rf; + + if (sc->mac_rev >= 0x0211) { + /* Enable DC filter. */ + run_bbp_write(sc, 103, 0xc0); + + if (sc->mac_ver != 0x5592) { + /* Improve power consumption. */ + run_bbp_read(sc, 31, &bbp); + run_bbp_write(sc, 31, bbp & ~0x03); + } + } + + run_bbp_read(sc, 138, &bbp); + if (sc->ntxchains == 1) + bbp |= 0x20; /* turn off DAC1 */ + if (sc->nrxchains == 1) + bbp &= ~0x02; /* turn off ADC1 */ + run_bbp_write(sc, 138, bbp); + + run_rt3070_rf_read(sc, 38, &rf); + run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); + + run_rt3070_rf_read(sc, 39, &rf); + run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); + + /* Avoid data lost and CRC error. */ + run_bbp_read(sc, 4, &bbp); + run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); + + run_rt3070_rf_read(sc, 30, &rf); + rf = (rf & ~0x18) | 0x10; + run_rt3070_rf_write(sc, 30, rf); + + if (sc->mac_ver != 0x5592) { + run_write(sc, RT2860_TX_SW_CFG1, 0); + if (sc->mac_rev < 0x0211) { + run_write(sc, RT2860_TX_SW_CFG2, + sc->patch_dac ? 0x2c : 0x0f); + } else + run_write(sc, RT2860_TX_SW_CFG2, 0); + } +} + static int run_txrx_enable(struct run_softc *sc) { @@ -5410,6 +6030,9 @@ run_init_locked(struct run_softc *sc) run_write(sc, RT2860_LG_FBK_CFG0, 0xedcba322); } } + } else if (sc->mac_ver == 0x3593) { + run_write(sc, RT2860_TX_SW_CFG0, + 4 << RT2860_DLY_PAPE_EN_SHIFT | 2); } else if (sc->mac_ver >= 0x3070) { /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ run_write(sc, RT2860_TX_SW_CFG0, @@ -5467,7 +6090,7 @@ run_init_locked(struct run_softc *sc) run_write(sc, RT2860_WMM_TXOP1_CFG, 48 << 16 | 96); /* write vendor-specific BBP values (from EEPROM) */ - if (sc->mac_ver < 0x5390) { + if (sc->mac_ver < 0x3593) { for (i = 0; i < 10; i++) { if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) continue; @@ -5486,6 +6109,8 @@ run_init_locked(struct run_softc *sc) if (sc->mac_ver >= 0x5390) run_rt5390_rf_init(sc); + else if (sc->mac_ver == 0x3593) + run_rt3593_rf_init(sc); else if (sc->mac_ver >= 0x3070) run_rt3070_rf_init(sc); @@ -5504,7 +6129,11 @@ run_init_locked(struct run_softc *sc) bbp1 &= ~(1 << 3 | 1 << 4); run_bbp_write(sc, 1, bbp1); - if (sc->mac_ver >= 0x3070) + if (sc->mac_ver >= 0x5390) + run_rt5390_rf_setup(sc); + else if (sc->mac_ver == 0x3593) + run_rt3593_rf_setup(sc); + else if (sc->mac_ver >= 0x3070) run_rt3070_rf_setup(sc); /* select default channel */ @@ -5650,7 +6279,7 @@ static driver_t run_driver = { static devclass_t run_devclass; -DRIVER_MODULE(run, uhub, run_driver, run_devclass, NULL, NULL); +DRIVER_MODULE(run, uhub, run_driver, run_devclass, run_driver_loaded, NULL); MODULE_DEPEND(run, wlan, 1, 1, 1); MODULE_DEPEND(run, usb, 1, 1, 1); MODULE_DEPEND(run, firmware, 1, 1, 1); diff --git a/sys/dev/usb/wlan/if_runreg.h b/sys/dev/usb/wlan/if_runreg.h index 2fb7b8c..3ca01cd 100644 --- a/sys/dev/usb/wlan/if_runreg.h +++ b/sys/dev/usb/wlan/if_runreg.h @@ -22,689 +22,698 @@ #ifndef _IF_RUNREG_H_ #define _IF_RUNREG_H_ -#define RT2860_CONFIG_NO 1 -#define RT2860_IFACE_INDEX 0 +#define RT2860_CONFIG_NO 1 +#define RT2860_IFACE_INDEX 0 -#define RT3070_OPT_14 0x0114 +#define RT3070_OPT_14 0x0114 /* SCH/DMA registers */ -#define RT2860_INT_STATUS 0x0200 -#define RT2860_INT_MASK 0x0204 -#define RT2860_WPDMA_GLO_CFG 0x0208 -#define RT2860_WPDMA_RST_IDX 0x020c -#define RT2860_DELAY_INT_CFG 0x0210 -#define RT2860_WMM_AIFSN_CFG 0x0214 -#define RT2860_WMM_CWMIN_CFG 0x0218 -#define RT2860_WMM_CWMAX_CFG 0x021c -#define RT2860_WMM_TXOP0_CFG 0x0220 -#define RT2860_WMM_TXOP1_CFG 0x0224 -#define RT2860_GPIO_CTRL 0x0228 -#define RT2860_MCU_CMD_REG 0x022c -#define RT2860_TX_BASE_PTR(qid) (0x0230 + (qid) * 16) -#define RT2860_TX_MAX_CNT(qid) (0x0234 + (qid) * 16) -#define RT2860_TX_CTX_IDX(qid) (0x0238 + (qid) * 16) -#define RT2860_TX_DTX_IDX(qid) (0x023c + (qid) * 16) -#define RT2860_RX_BASE_PTR 0x0290 -#define RT2860_RX_MAX_CNT 0x0294 -#define RT2860_RX_CALC_IDX 0x0298 -#define RT2860_FS_DRX_IDX 0x029c -#define RT2860_USB_DMA_CFG 0x02a0 /* RT2870 only */ -#define RT2860_US_CYC_CNT 0x02a4 +#define RT2860_INT_STATUS 0x0200 +#define RT2860_INT_MASK 0x0204 +#define RT2860_WPDMA_GLO_CFG 0x0208 +#define RT2860_WPDMA_RST_IDX 0x020c +#define RT2860_DELAY_INT_CFG 0x0210 +#define RT2860_WMM_AIFSN_CFG 0x0214 +#define RT2860_WMM_CWMIN_CFG 0x0218 +#define RT2860_WMM_CWMAX_CFG 0x021c +#define RT2860_WMM_TXOP0_CFG 0x0220 +#define RT2860_WMM_TXOP1_CFG 0x0224 +#define RT2860_GPIO_CTRL 0x0228 +#define RT2860_MCU_CMD_REG 0x022c +#define RT2860_TX_BASE_PTR(qid) (0x0230 + (qid) * 16) +#define RT2860_TX_MAX_CNT(qid) (0x0234 + (qid) * 16) +#define RT2860_TX_CTX_IDX(qid) (0x0238 + (qid) * 16) +#define RT2860_TX_DTX_IDX(qid) (0x023c + (qid) * 16) +#define RT2860_RX_BASE_PTR 0x0290 +#define RT2860_RX_MAX_CNT 0x0294 +#define RT2860_RX_CALC_IDX 0x0298 +#define RT2860_FS_DRX_IDX 0x029c +#define RT2860_USB_DMA_CFG 0x02a0 /* RT2870 only */ +#define RT2860_US_CYC_CNT 0x02a4 /* PBF registers */ -#define RT2860_SYS_CTRL 0x0400 -#define RT2860_HOST_CMD 0x0404 -#define RT2860_PBF_CFG 0x0408 -#define RT2860_MAX_PCNT 0x040c -#define RT2860_BUF_CTRL 0x0410 -#define RT2860_MCU_INT_STA 0x0414 -#define RT2860_MCU_INT_ENA 0x0418 -#define RT2860_TXQ_IO(qid) (0x041c + (qid) * 4) -#define RT2860_RX0Q_IO 0x0424 -#define RT2860_BCN_OFFSET0 0x042c -#define RT2860_BCN_OFFSET1 0x0430 -#define RT2860_TXRXQ_STA 0x0434 -#define RT2860_TXRXQ_PCNT 0x0438 -#define RT2860_PBF_DBG 0x043c -#define RT2860_CAP_CTRL 0x0440 +#define RT2860_SYS_CTRL 0x0400 +#define RT2860_HOST_CMD 0x0404 +#define RT2860_PBF_CFG 0x0408 +#define RT2860_MAX_PCNT 0x040c +#define RT2860_BUF_CTRL 0x0410 +#define RT2860_MCU_INT_STA 0x0414 +#define RT2860_MCU_INT_ENA 0x0418 +#define RT2860_TXQ_IO(qid) (0x041c + (qid) * 4) +#define RT2860_RX0Q_IO 0x0424 +#define RT2860_BCN_OFFSET0 0x042c +#define RT2860_BCN_OFFSET1 0x0430 +#define RT2860_TXRXQ_STA 0x0434 +#define RT2860_TXRXQ_PCNT 0x0438 +#define RT2860_PBF_DBG 0x043c +#define RT2860_CAP_CTRL 0x0440 /* RT3070 registers */ -#define RT3070_RF_CSR_CFG 0x0500 -#define RT3070_EFUSE_CTRL 0x0580 -#define RT3070_EFUSE_DATA0 0x0590 -#define RT3070_EFUSE_DATA1 0x0594 -#define RT3070_EFUSE_DATA2 0x0598 -#define RT3070_EFUSE_DATA3 0x059c -#define RT3070_LDO_CFG0 0x05d4 -#define RT3070_GPIO_SWITCH 0x05dc +#define RT3070_RF_CSR_CFG 0x0500 +#define RT3070_EFUSE_CTRL 0x0580 +#define RT3070_EFUSE_DATA0 0x0590 +#define RT3070_EFUSE_DATA1 0x0594 +#define RT3070_EFUSE_DATA2 0x0598 +#define RT3070_EFUSE_DATA3 0x059c +#define RT3070_LDO_CFG0 0x05d4 +#define RT3070_GPIO_SWITCH 0x05dc /* RT5592 registers */ -#define RT5592_DEBUG_INDEX 0x05e8 +#define RT5592_DEBUG_INDEX 0x05e8 /* MAC registers */ -#define RT2860_ASIC_VER_ID 0x1000 -#define RT2860_MAC_SYS_CTRL 0x1004 -#define RT2860_MAC_ADDR_DW0 0x1008 -#define RT2860_MAC_ADDR_DW1 0x100c -#define RT2860_MAC_BSSID_DW0 0x1010 -#define RT2860_MAC_BSSID_DW1 0x1014 -#define RT2860_MAX_LEN_CFG 0x1018 -#define RT2860_BBP_CSR_CFG 0x101c -#define RT2860_RF_CSR_CFG0 0x1020 -#define RT2860_RF_CSR_CFG1 0x1024 -#define RT2860_RF_CSR_CFG2 0x1028 -#define RT2860_LED_CFG 0x102c +#define RT2860_ASIC_VER_ID 0x1000 +#define RT2860_MAC_SYS_CTRL 0x1004 +#define RT2860_MAC_ADDR_DW0 0x1008 +#define RT2860_MAC_ADDR_DW1 0x100c +#define RT2860_MAC_BSSID_DW0 0x1010 +#define RT2860_MAC_BSSID_DW1 0x1014 +#define RT2860_MAX_LEN_CFG 0x1018 +#define RT2860_BBP_CSR_CFG 0x101c +#define RT2860_RF_CSR_CFG0 0x1020 +#define RT2860_RF_CSR_CFG1 0x1024 +#define RT2860_RF_CSR_CFG2 0x1028 +#define RT2860_LED_CFG 0x102c /* undocumented registers */ -#define RT2860_DEBUG 0x10f4 +#define RT2860_DEBUG 0x10f4 /* MAC Timing control registers */ -#define RT2860_XIFS_TIME_CFG 0x1100 -#define RT2860_BKOFF_SLOT_CFG 0x1104 -#define RT2860_NAV_TIME_CFG 0x1108 -#define RT2860_CH_TIME_CFG 0x110c -#define RT2860_PBF_LIFE_TIMER 0x1110 -#define RT2860_BCN_TIME_CFG 0x1114 -#define RT2860_TBTT_SYNC_CFG 0x1118 -#define RT2860_TSF_TIMER_DW0 0x111c -#define RT2860_TSF_TIMER_DW1 0x1120 -#define RT2860_TBTT_TIMER 0x1124 -#define RT2860_INT_TIMER_CFG 0x1128 -#define RT2860_INT_TIMER_EN 0x112c -#define RT2860_CH_IDLE_TIME 0x1130 +#define RT2860_XIFS_TIME_CFG 0x1100 +#define RT2860_BKOFF_SLOT_CFG 0x1104 +#define RT2860_NAV_TIME_CFG 0x1108 +#define RT2860_CH_TIME_CFG 0x110c +#define RT2860_PBF_LIFE_TIMER 0x1110 +#define RT2860_BCN_TIME_CFG 0x1114 +#define RT2860_TBTT_SYNC_CFG 0x1118 +#define RT2860_TSF_TIMER_DW0 0x111c +#define RT2860_TSF_TIMER_DW1 0x1120 +#define RT2860_TBTT_TIMER 0x1124 +#define RT2860_INT_TIMER_CFG 0x1128 +#define RT2860_INT_TIMER_EN 0x112c +#define RT2860_CH_IDLE_TIME 0x1130 /* MAC Power Save configuration registers */ -#define RT2860_MAC_STATUS_REG 0x1200 -#define RT2860_PWR_PIN_CFG 0x1204 -#define RT2860_AUTO_WAKEUP_CFG 0x1208 +#define RT2860_MAC_STATUS_REG 0x1200 +#define RT2860_PWR_PIN_CFG 0x1204 +#define RT2860_AUTO_WAKEUP_CFG 0x1208 /* MAC TX configuration registers */ -#define RT2860_EDCA_AC_CFG(aci) (0x1300 + (aci) * 4) -#define RT2860_EDCA_TID_AC_MAP 0x1310 -#define RT2860_TX_PWR_CFG(ridx) (0x1314 + (ridx) * 4) -#define RT2860_TX_PIN_CFG 0x1328 -#define RT2860_TX_BAND_CFG 0x132c -#define RT2860_TX_SW_CFG0 0x1330 -#define RT2860_TX_SW_CFG1 0x1334 -#define RT2860_TX_SW_CFG2 0x1338 -#define RT2860_TXOP_THRES_CFG 0x133c -#define RT2860_TXOP_CTRL_CFG 0x1340 -#define RT2860_TX_RTS_CFG 0x1344 -#define RT2860_TX_TIMEOUT_CFG 0x1348 -#define RT2860_TX_RTY_CFG 0x134c -#define RT2860_TX_LINK_CFG 0x1350 -#define RT2860_HT_FBK_CFG0 0x1354 -#define RT2860_HT_FBK_CFG1 0x1358 -#define RT2860_LG_FBK_CFG0 0x135c -#define RT2860_LG_FBK_CFG1 0x1360 -#define RT2860_CCK_PROT_CFG 0x1364 -#define RT2860_OFDM_PROT_CFG 0x1368 -#define RT2860_MM20_PROT_CFG 0x136c -#define RT2860_MM40_PROT_CFG 0x1370 -#define RT2860_GF20_PROT_CFG 0x1374 -#define RT2860_GF40_PROT_CFG 0x1378 -#define RT2860_EXP_CTS_TIME 0x137c -#define RT2860_EXP_ACK_TIME 0x1380 +#define RT2860_EDCA_AC_CFG(aci) (0x1300 + (aci) * 4) +#define RT2860_EDCA_TID_AC_MAP 0x1310 +#define RT2860_TX_PWR_CFG(ridx) (0x1314 + (ridx) * 4) +#define RT2860_TX_PIN_CFG 0x1328 +#define RT2860_TX_BAND_CFG 0x132c +#define RT2860_TX_SW_CFG0 0x1330 +#define RT2860_TX_SW_CFG1 0x1334 +#define RT2860_TX_SW_CFG2 0x1338 +#define RT2860_TXOP_THRES_CFG 0x133c +#define RT2860_TXOP_CTRL_CFG 0x1340 +#define RT2860_TX_RTS_CFG 0x1344 +#define RT2860_TX_TIMEOUT_CFG 0x1348 +#define RT2860_TX_RTY_CFG 0x134c +#define RT2860_TX_LINK_CFG 0x1350 +#define RT2860_HT_FBK_CFG0 0x1354 +#define RT2860_HT_FBK_CFG1 0x1358 +#define RT2860_LG_FBK_CFG0 0x135c +#define RT2860_LG_FBK_CFG1 0x1360 +#define RT2860_CCK_PROT_CFG 0x1364 +#define RT2860_OFDM_PROT_CFG 0x1368 +#define RT2860_MM20_PROT_CFG 0x136c +#define RT2860_MM40_PROT_CFG 0x1370 +#define RT2860_GF20_PROT_CFG 0x1374 +#define RT2860_GF40_PROT_CFG 0x1378 +#define RT2860_EXP_CTS_TIME 0x137c +#define RT2860_EXP_ACK_TIME 0x1380 /* MAC RX configuration registers */ -#define RT2860_RX_FILTR_CFG 0x1400 -#define RT2860_AUTO_RSP_CFG 0x1404 -#define RT2860_LEGACY_BASIC_RATE 0x1408 -#define RT2860_HT_BASIC_RATE 0x140c -#define RT2860_HT_CTRL_CFG 0x1410 -#define RT2860_SIFS_COST_CFG 0x1414 -#define RT2860_RX_PARSER_CFG 0x1418 +#define RT2860_RX_FILTR_CFG 0x1400 +#define RT2860_AUTO_RSP_CFG 0x1404 +#define RT2860_LEGACY_BASIC_RATE 0x1408 +#define RT2860_HT_BASIC_RATE 0x140c +#define RT2860_HT_CTRL_CFG 0x1410 +#define RT2860_SIFS_COST_CFG 0x1414 +#define RT2860_RX_PARSER_CFG 0x1418 /* MAC Security configuration registers */ -#define RT2860_TX_SEC_CNT0 0x1500 -#define RT2860_RX_SEC_CNT0 0x1504 -#define RT2860_CCMP_FC_MUTE 0x1508 +#define RT2860_TX_SEC_CNT0 0x1500 +#define RT2860_RX_SEC_CNT0 0x1504 +#define RT2860_CCMP_FC_MUTE 0x1508 /* MAC HCCA/PSMP configuration registers */ -#define RT2860_TXOP_HLDR_ADDR0 0x1600 -#define RT2860_TXOP_HLDR_ADDR1 0x1604 -#define RT2860_TXOP_HLDR_ET 0x1608 -#define RT2860_QOS_CFPOLL_RA_DW0 0x160c -#define RT2860_QOS_CFPOLL_A1_DW1 0x1610 -#define RT2860_QOS_CFPOLL_QC 0x1614 +#define RT2860_TXOP_HLDR_ADDR0 0x1600 +#define RT2860_TXOP_HLDR_ADDR1 0x1604 +#define RT2860_TXOP_HLDR_ET 0x1608 +#define RT2860_QOS_CFPOLL_RA_DW0 0x160c +#define RT2860_QOS_CFPOLL_A1_DW1 0x1610 +#define RT2860_QOS_CFPOLL_QC 0x1614 /* MAC Statistics Counters */ -#define RT2860_RX_STA_CNT0 0x1700 -#define RT2860_RX_STA_CNT1 0x1704 -#define RT2860_RX_STA_CNT2 0x1708 -#define RT2860_TX_STA_CNT0 0x170c -#define RT2860_TX_STA_CNT1 0x1710 -#define RT2860_TX_STA_CNT2 0x1714 -#define RT2860_TX_STAT_FIFO 0x1718 +#define RT2860_RX_STA_CNT0 0x1700 +#define RT2860_RX_STA_CNT1 0x1704 +#define RT2860_RX_STA_CNT2 0x1708 +#define RT2860_TX_STA_CNT0 0x170c +#define RT2860_TX_STA_CNT1 0x1710 +#define RT2860_TX_STA_CNT2 0x1714 +#define RT2860_TX_STAT_FIFO 0x1718 /* RX WCID search table */ -#define RT2860_WCID_ENTRY(wcid) (0x1800 + (wcid) * 8) +#define RT2860_WCID_ENTRY(wcid) (0x1800 + (wcid) * 8) -#define RT2860_FW_BASE 0x2000 -#define RT2870_FW_BASE 0x3000 +#define RT2860_FW_BASE 0x2000 +#define RT2870_FW_BASE 0x3000 /* Pair-wise key table */ -#define RT2860_PKEY(wcid) (0x4000 + (wcid) * 32) +#define RT2860_PKEY(wcid) (0x4000 + (wcid) * 32) /* IV/EIV table */ -#define RT2860_IVEIV(wcid) (0x6000 + (wcid) * 8) +#define RT2860_IVEIV(wcid) (0x6000 + (wcid) * 8) /* WCID attribute table */ -#define RT2860_WCID_ATTR(wcid) (0x6800 + (wcid) * 4) +#define RT2860_WCID_ATTR(wcid) (0x6800 + (wcid) * 4) /* Shared Key Table */ -#define RT2860_SKEY(vap, kidx) (0x6c00 + (vap) * 128 + (kidx) * 32) +#define RT2860_SKEY(vap, kidx) (0x6c00 + (vap) * 128 + (kidx) * 32) /* Shared Key Mode */ -#define RT2860_SKEY_MODE_0_7 0x7000 -#define RT2860_SKEY_MODE_8_15 0x7004 -#define RT2860_SKEY_MODE_16_23 0x7008 -#define RT2860_SKEY_MODE_24_31 0x700c +#define RT2860_SKEY_MODE_0_7 0x7000 +#define RT2860_SKEY_MODE_8_15 0x7004 +#define RT2860_SKEY_MODE_16_23 0x7008 +#define RT2860_SKEY_MODE_24_31 0x700c /* Shared Memory between MCU and host */ -#define RT2860_H2M_MAILBOX 0x7010 -#define RT2860_H2M_MAILBOX_CID 0x7014 -#define RT2860_H2M_MAILBOX_STATUS 0x701c -#define RT2860_H2M_INTSRC 0x7024 -#define RT2860_H2M_BBPAGENT 0x7028 -#define RT2860_BCN_BASE(vap) (0x7800 + (vap) * 512) +#define RT2860_H2M_MAILBOX 0x7010 +#define RT2860_H2M_MAILBOX_CID 0x7014 +#define RT2860_H2M_MAILBOX_STATUS 0x701c +#define RT2860_H2M_INTSRC 0x7024 +#define RT2860_H2M_BBPAGENT 0x7028 +#define RT2860_BCN_BASE(vap) (0x7800 + (vap) * 512) /* possible flags for register RT2860_PCI_EECTRL */ -#define RT2860_C (1 << 0) -#define RT2860_S (1 << 1) -#define RT2860_D (1 << 2) -#define RT2860_SHIFT_D 2 -#define RT2860_Q (1 << 3) -#define RT2860_SHIFT_Q 3 +#define RT2860_C (1 << 0) +#define RT2860_S (1 << 1) +#define RT2860_D (1 << 2) +#define RT2860_SHIFT_D 2 +#define RT2860_Q (1 << 3) +#define RT2860_SHIFT_Q 3 /* possible flags for registers INT_STATUS/INT_MASK */ -#define RT2860_TX_COHERENT (1 << 17) -#define RT2860_RX_COHERENT (1 << 16) -#define RT2860_MAC_INT_4 (1 << 15) -#define RT2860_MAC_INT_3 (1 << 14) -#define RT2860_MAC_INT_2 (1 << 13) -#define RT2860_MAC_INT_1 (1 << 12) -#define RT2860_MAC_INT_0 (1 << 11) -#define RT2860_TX_RX_COHERENT (1 << 10) -#define RT2860_MCU_CMD_INT (1 << 9) -#define RT2860_TX_DONE_INT5 (1 << 8) -#define RT2860_TX_DONE_INT4 (1 << 7) -#define RT2860_TX_DONE_INT3 (1 << 6) -#define RT2860_TX_DONE_INT2 (1 << 5) -#define RT2860_TX_DONE_INT1 (1 << 4) -#define RT2860_TX_DONE_INT0 (1 << 3) -#define RT2860_RX_DONE_INT (1 << 2) -#define RT2860_TX_DLY_INT (1 << 1) -#define RT2860_RX_DLY_INT (1 << 0) +#define RT2860_TX_COHERENT (1 << 17) +#define RT2860_RX_COHERENT (1 << 16) +#define RT2860_MAC_INT_4 (1 << 15) +#define RT2860_MAC_INT_3 (1 << 14) +#define RT2860_MAC_INT_2 (1 << 13) +#define RT2860_MAC_INT_1 (1 << 12) +#define RT2860_MAC_INT_0 (1 << 11) +#define RT2860_TX_RX_COHERENT (1 << 10) +#define RT2860_MCU_CMD_INT (1 << 9) +#define RT2860_TX_DONE_INT5 (1 << 8) +#define RT2860_TX_DONE_INT4 (1 << 7) +#define RT2860_TX_DONE_INT3 (1 << 6) +#define RT2860_TX_DONE_INT2 (1 << 5) +#define RT2860_TX_DONE_INT1 (1 << 4) +#define RT2860_TX_DONE_INT0 (1 << 3) +#define RT2860_RX_DONE_INT (1 << 2) +#define RT2860_TX_DLY_INT (1 << 1) +#define RT2860_RX_DLY_INT (1 << 0) /* possible flags for register WPDMA_GLO_CFG */ -#define RT2860_HDR_SEG_LEN_SHIFT 8 -#define RT2860_BIG_ENDIAN (1 << 7) -#define RT2860_TX_WB_DDONE (1 << 6) -#define RT2860_WPDMA_BT_SIZE_SHIFT 4 -#define RT2860_WPDMA_BT_SIZE16 0 -#define RT2860_WPDMA_BT_SIZE32 1 -#define RT2860_WPDMA_BT_SIZE64 2 -#define RT2860_WPDMA_BT_SIZE128 3 -#define RT2860_RX_DMA_BUSY (1 << 3) -#define RT2860_RX_DMA_EN (1 << 2) -#define RT2860_TX_DMA_BUSY (1 << 1) -#define RT2860_TX_DMA_EN (1 << 0) +#define RT2860_HDR_SEG_LEN_SHIFT 8 +#define RT2860_BIG_ENDIAN (1 << 7) +#define RT2860_TX_WB_DDONE (1 << 6) +#define RT2860_WPDMA_BT_SIZE_SHIFT 4 +#define RT2860_WPDMA_BT_SIZE16 0 +#define RT2860_WPDMA_BT_SIZE32 1 +#define RT2860_WPDMA_BT_SIZE64 2 +#define RT2860_WPDMA_BT_SIZE128 3 +#define RT2860_RX_DMA_BUSY (1 << 3) +#define RT2860_RX_DMA_EN (1 << 2) +#define RT2860_TX_DMA_BUSY (1 << 1) +#define RT2860_TX_DMA_EN (1 << 0) /* possible flags for register DELAY_INT_CFG */ -#define RT2860_TXDLY_INT_EN (1U << 31) -#define RT2860_TXMAX_PINT_SHIFT 24 -#define RT2860_TXMAX_PTIME_SHIFT 16 -#define RT2860_RXDLY_INT_EN (1 << 15) -#define RT2860_RXMAX_PINT_SHIFT 8 -#define RT2860_RXMAX_PTIME_SHIFT 0 +#define RT2860_TXDLY_INT_EN (1U << 31) +#define RT2860_TXMAX_PINT_SHIFT 24 +#define RT2860_TXMAX_PTIME_SHIFT 16 +#define RT2860_RXDLY_INT_EN (1 << 15) +#define RT2860_RXMAX_PINT_SHIFT 8 +#define RT2860_RXMAX_PTIME_SHIFT 0 /* possible flags for register GPIO_CTRL */ -#define RT2860_GPIO_D_SHIFT 8 -#define RT2860_GPIO_O_SHIFT 0 +#define RT2860_GPIO_D_SHIFT 8 +#define RT2860_GPIO_O_SHIFT 0 /* possible flags for register USB_DMA_CFG */ -#define RT2860_USB_TX_BUSY (1U << 31) -#define RT2860_USB_RX_BUSY (1 << 30) -#define RT2860_USB_EPOUT_VLD_SHIFT 24 -#define RT2860_USB_TX_EN (1 << 23) -#define RT2860_USB_RX_EN (1 << 22) -#define RT2860_USB_RX_AGG_EN (1 << 21) -#define RT2860_USB_TXOP_HALT (1 << 20) -#define RT2860_USB_TX_CLEAR (1 << 19) -#define RT2860_USB_PHY_WD_EN (1 << 16) -#define RT2860_USB_PHY_MAN_RST (1 << 15) -#define RT2860_USB_RX_AGG_LMT(x) ((x) << 8) /* in unit of 1KB */ -#define RT2860_USB_RX_AGG_TO(x) ((x) & 0xff) /* in unit of 33ns */ +#define RT2860_USB_TX_BUSY (1U << 31) +#define RT2860_USB_RX_BUSY (1 << 30) +#define RT2860_USB_EPOUT_VLD_SHIFT 24 +#define RT2860_USB_TX_EN (1 << 23) +#define RT2860_USB_RX_EN (1 << 22) +#define RT2860_USB_RX_AGG_EN (1 << 21) +#define RT2860_USB_TXOP_HALT (1 << 20) +#define RT2860_USB_TX_CLEAR (1 << 19) +#define RT2860_USB_PHY_WD_EN (1 << 16) +#define RT2860_USB_PHY_MAN_RST (1 << 15) +#define RT2860_USB_RX_AGG_LMT(x) ((x) << 8) /* in unit of 1KB */ +#define RT2860_USB_RX_AGG_TO(x) ((x) & 0xff) /* in unit of 33ns */ /* possible flags for register US_CYC_CNT */ -#define RT2860_TEST_EN (1 << 24) -#define RT2860_TEST_SEL_SHIFT 16 -#define RT2860_BT_MODE_EN (1 << 8) -#define RT2860_US_CYC_CNT_SHIFT 0 +#define RT2860_TEST_EN (1 << 24) +#define RT2860_TEST_SEL_SHIFT 16 +#define RT2860_BT_MODE_EN (1 << 8) +#define RT2860_US_CYC_CNT_SHIFT 0 /* possible flags for register SYS_CTRL */ -#define RT2860_HST_PM_SEL (1 << 16) -#define RT2860_CAP_MODE (1 << 14) -#define RT2860_PME_OEN (1 << 13) -#define RT2860_CLKSELECT (1 << 12) -#define RT2860_PBF_CLK_EN (1 << 11) -#define RT2860_MAC_CLK_EN (1 << 10) -#define RT2860_DMA_CLK_EN (1 << 9) -#define RT2860_MCU_READY (1 << 7) -#define RT2860_ASY_RESET (1 << 4) -#define RT2860_PBF_RESET (1 << 3) -#define RT2860_MAC_RESET (1 << 2) -#define RT2860_DMA_RESET (1 << 1) -#define RT2860_MCU_RESET (1 << 0) +#define RT2860_HST_PM_SEL (1 << 16) +#define RT2860_CAP_MODE (1 << 14) +#define RT2860_PME_OEN (1 << 13) +#define RT2860_CLKSELECT (1 << 12) +#define RT2860_PBF_CLK_EN (1 << 11) +#define RT2860_MAC_CLK_EN (1 << 10) +#define RT2860_DMA_CLK_EN (1 << 9) +#define RT2860_MCU_READY (1 << 7) +#define RT2860_ASY_RESET (1 << 4) +#define RT2860_PBF_RESET (1 << 3) +#define RT2860_MAC_RESET (1 << 2) +#define RT2860_DMA_RESET (1 << 1) +#define RT2860_MCU_RESET (1 << 0) /* possible values for register HOST_CMD */ -#define RT2860_MCU_CMD_SLEEP 0x30 -#define RT2860_MCU_CMD_WAKEUP 0x31 -#define RT2860_MCU_CMD_LEDS 0x50 -#define RT2860_MCU_CMD_LED_RSSI 0x51 -#define RT2860_MCU_CMD_LED1 0x52 -#define RT2860_MCU_CMD_LED2 0x53 -#define RT2860_MCU_CMD_LED3 0x54 -#define RT2860_MCU_CMD_RFRESET 0x72 -#define RT2860_MCU_CMD_ANTSEL 0x73 -#define RT2860_MCU_CMD_BBP 0x80 -#define RT2860_MCU_CMD_PSLEVEL 0x83 +#define RT2860_MCU_CMD_SLEEP 0x30 +#define RT2860_MCU_CMD_WAKEUP 0x31 +#define RT2860_MCU_CMD_LEDS 0x50 +#define RT2860_MCU_CMD_LED_RSSI 0x51 +#define RT2860_MCU_CMD_LED1 0x52 +#define RT2860_MCU_CMD_LED2 0x53 +#define RT2860_MCU_CMD_LED3 0x54 +#define RT2860_MCU_CMD_RFRESET 0x72 +#define RT2860_MCU_CMD_ANTSEL 0x73 +#define RT2860_MCU_CMD_BBP 0x80 +#define RT2860_MCU_CMD_PSLEVEL 0x83 /* possible flags for register PBF_CFG */ -#define RT2860_TX1Q_NUM_SHIFT 21 -#define RT2860_TX2Q_NUM_SHIFT 16 -#define RT2860_NULL0_MODE (1 << 15) -#define RT2860_NULL1_MODE (1 << 14) -#define RT2860_RX_DROP_MODE (1 << 13) -#define RT2860_TX0Q_MANUAL (1 << 12) -#define RT2860_TX1Q_MANUAL (1 << 11) -#define RT2860_TX2Q_MANUAL (1 << 10) -#define RT2860_RX0Q_MANUAL (1 << 9) -#define RT2860_HCCA_EN (1 << 8) -#define RT2860_TX0Q_EN (1 << 4) -#define RT2860_TX1Q_EN (1 << 3) -#define RT2860_TX2Q_EN (1 << 2) -#define RT2860_RX0Q_EN (1 << 1) +#define RT2860_TX1Q_NUM_SHIFT 21 +#define RT2860_TX2Q_NUM_SHIFT 16 +#define RT2860_NULL0_MODE (1 << 15) +#define RT2860_NULL1_MODE (1 << 14) +#define RT2860_RX_DROP_MODE (1 << 13) +#define RT2860_TX0Q_MANUAL (1 << 12) +#define RT2860_TX1Q_MANUAL (1 << 11) +#define RT2860_TX2Q_MANUAL (1 << 10) +#define RT2860_RX0Q_MANUAL (1 << 9) +#define RT2860_HCCA_EN (1 << 8) +#define RT2860_TX0Q_EN (1 << 4) +#define RT2860_TX1Q_EN (1 << 3) +#define RT2860_TX2Q_EN (1 << 2) +#define RT2860_RX0Q_EN (1 << 1) /* possible flags for register BUF_CTRL */ -#define RT2860_WRITE_TXQ(qid) (1 << (11 - (qid))) -#define RT2860_NULL0_KICK (1 << 7) -#define RT2860_NULL1_KICK (1 << 6) -#define RT2860_BUF_RESET (1 << 5) -#define RT2860_READ_TXQ(qid) (1 << (3 - (qid)) -#define RT2860_READ_RX0Q (1 << 0) +#define RT2860_WRITE_TXQ(qid) (1 << (11 - (qid))) +#define RT2860_NULL0_KICK (1 << 7) +#define RT2860_NULL1_KICK (1 << 6) +#define RT2860_BUF_RESET (1 << 5) +#define RT2860_READ_TXQ(qid) (1 << (3 - (qid)) +#define RT2860_READ_RX0Q (1 << 0) /* possible flags for registers MCU_INT_STA/MCU_INT_ENA */ -#define RT2860_MCU_MAC_INT_8 (1 << 24) -#define RT2860_MCU_MAC_INT_7 (1 << 23) -#define RT2860_MCU_MAC_INT_6 (1 << 22) -#define RT2860_MCU_MAC_INT_4 (1 << 20) -#define RT2860_MCU_MAC_INT_3 (1 << 19) -#define RT2860_MCU_MAC_INT_2 (1 << 18) -#define RT2860_MCU_MAC_INT_1 (1 << 17) -#define RT2860_MCU_MAC_INT_0 (1 << 16) -#define RT2860_DTX0_INT (1 << 11) -#define RT2860_DTX1_INT (1 << 10) -#define RT2860_DTX2_INT (1 << 9) -#define RT2860_DRX0_INT (1 << 8) -#define RT2860_HCMD_INT (1 << 7) -#define RT2860_N0TX_INT (1 << 6) -#define RT2860_N1TX_INT (1 << 5) -#define RT2860_BCNTX_INT (1 << 4) -#define RT2860_MTX0_INT (1 << 3) -#define RT2860_MTX1_INT (1 << 2) -#define RT2860_MTX2_INT (1 << 1) -#define RT2860_MRX0_INT (1 << 0) +#define RT2860_MCU_MAC_INT_8 (1 << 24) +#define RT2860_MCU_MAC_INT_7 (1 << 23) +#define RT2860_MCU_MAC_INT_6 (1 << 22) +#define RT2860_MCU_MAC_INT_4 (1 << 20) +#define RT2860_MCU_MAC_INT_3 (1 << 19) +#define RT2860_MCU_MAC_INT_2 (1 << 18) +#define RT2860_MCU_MAC_INT_1 (1 << 17) +#define RT2860_MCU_MAC_INT_0 (1 << 16) +#define RT2860_DTX0_INT (1 << 11) +#define RT2860_DTX1_INT (1 << 10) +#define RT2860_DTX2_INT (1 << 9) +#define RT2860_DRX0_INT (1 << 8) +#define RT2860_HCMD_INT (1 << 7) +#define RT2860_N0TX_INT (1 << 6) +#define RT2860_N1TX_INT (1 << 5) +#define RT2860_BCNTX_INT (1 << 4) +#define RT2860_MTX0_INT (1 << 3) +#define RT2860_MTX1_INT (1 << 2) +#define RT2860_MTX2_INT (1 << 1) +#define RT2860_MRX0_INT (1 << 0) /* possible flags for register TXRXQ_PCNT */ -#define RT2860_RX0Q_PCNT_MASK 0xff000000 -#define RT2860_TX2Q_PCNT_MASK 0x00ff0000 -#define RT2860_TX1Q_PCNT_MASK 0x0000ff00 -#define RT2860_TX0Q_PCNT_MASK 0x000000ff +#define RT2860_RX0Q_PCNT_MASK 0xff000000 +#define RT2860_TX2Q_PCNT_MASK 0x00ff0000 +#define RT2860_TX1Q_PCNT_MASK 0x0000ff00 +#define RT2860_TX0Q_PCNT_MASK 0x000000ff /* possible flags for register CAP_CTRL */ -#define RT2860_CAP_ADC_FEQ (1U << 31) -#define RT2860_CAP_START (1 << 30) -#define RT2860_MAN_TRIG (1 << 29) -#define RT2860_TRIG_OFFSET_SHIFT 16 -#define RT2860_START_ADDR_SHIFT 0 +#define RT2860_CAP_ADC_FEQ (1U << 31) +#define RT2860_CAP_START (1 << 30) +#define RT2860_MAN_TRIG (1 << 29) +#define RT2860_TRIG_OFFSET_SHIFT 16 +#define RT2860_START_ADDR_SHIFT 0 /* possible flags for register RF_CSR_CFG */ -#define RT3070_RF_KICK (1 << 17) -#define RT3070_RF_WRITE (1 << 16) +#define RT3070_RF_KICK (1 << 17) +#define RT3070_RF_WRITE (1 << 16) /* possible flags for register EFUSE_CTRL */ -#define RT3070_SEL_EFUSE (1U << 31) -#define RT3070_EFSROM_KICK (1 << 30) -#define RT3070_EFSROM_AIN_MASK 0x03ff0000 -#define RT3070_EFSROM_AIN_SHIFT 16 -#define RT3070_EFSROM_MODE_MASK 0x000000c0 -#define RT3070_EFUSE_AOUT_MASK 0x0000003f +#define RT3070_SEL_EFUSE (1U << 31) +#define RT3070_EFSROM_KICK (1 << 30) +#define RT3070_EFSROM_AIN_MASK 0x03ff0000 +#define RT3070_EFSROM_AIN_SHIFT 16 +#define RT3070_EFSROM_MODE_MASK 0x000000c0 +#define RT3070_EFUSE_AOUT_MASK 0x0000003f /* possible flag for register DEBUG_INDEX */ -#define RT5592_SEL_XTAL (1U << 31) +#define RT5592_SEL_XTAL (1U << 31) /* possible flags for register MAC_SYS_CTRL */ -#define RT2860_RX_TS_EN (1 << 7) -#define RT2860_WLAN_HALT_EN (1 << 6) -#define RT2860_PBF_LOOP_EN (1 << 5) -#define RT2860_CONT_TX_TEST (1 << 4) -#define RT2860_MAC_RX_EN (1 << 3) -#define RT2860_MAC_TX_EN (1 << 2) -#define RT2860_BBP_HRST (1 << 1) -#define RT2860_MAC_SRST (1 << 0) +#define RT2860_RX_TS_EN (1 << 7) +#define RT2860_WLAN_HALT_EN (1 << 6) +#define RT2860_PBF_LOOP_EN (1 << 5) +#define RT2860_CONT_TX_TEST (1 << 4) +#define RT2860_MAC_RX_EN (1 << 3) +#define RT2860_MAC_TX_EN (1 << 2) +#define RT2860_BBP_HRST (1 << 1) +#define RT2860_MAC_SRST (1 << 0) /* possible flags for register MAC_BSSID_DW1 */ -#define RT2860_MULTI_BCN_NUM_SHIFT 18 -#define RT2860_MULTI_BSSID_MODE_SHIFT 16 +#define RT2860_MULTI_BCN_NUM_SHIFT 18 +#define RT2860_MULTI_BSSID_MODE_SHIFT 16 /* possible flags for register MAX_LEN_CFG */ -#define RT2860_MIN_MPDU_LEN_SHIFT 16 -#define RT2860_MAX_PSDU_LEN_SHIFT 12 -#define RT2860_MAX_PSDU_LEN8K 0 -#define RT2860_MAX_PSDU_LEN16K 1 -#define RT2860_MAX_PSDU_LEN32K 2 -#define RT2860_MAX_PSDU_LEN64K 3 -#define RT2860_MAX_MPDU_LEN_SHIFT 0 +#define RT2860_MIN_MPDU_LEN_SHIFT 16 +#define RT2860_MAX_PSDU_LEN_SHIFT 12 +#define RT2860_MAX_PSDU_LEN8K 0 +#define RT2860_MAX_PSDU_LEN16K 1 +#define RT2860_MAX_PSDU_LEN32K 2 +#define RT2860_MAX_PSDU_LEN64K 3 +#define RT2860_MAX_MPDU_LEN_SHIFT 0 /* possible flags for registers BBP_CSR_CFG/H2M_BBPAGENT */ -#define RT2860_BBP_RW_PARALLEL (1 << 19) -#define RT2860_BBP_PAR_DUR_112_5 (1 << 18) -#define RT2860_BBP_CSR_KICK (1 << 17) -#define RT2860_BBP_CSR_READ (1 << 16) -#define RT2860_BBP_ADDR_SHIFT 8 -#define RT2860_BBP_DATA_SHIFT 0 +#define RT2860_BBP_RW_PARALLEL (1 << 19) +#define RT2860_BBP_PAR_DUR_112_5 (1 << 18) +#define RT2860_BBP_CSR_KICK (1 << 17) +#define RT2860_BBP_CSR_READ (1 << 16) +#define RT2860_BBP_ADDR_SHIFT 8 +#define RT2860_BBP_DATA_SHIFT 0 /* possible flags for register RF_CSR_CFG0 */ -#define RT2860_RF_REG_CTRL (1U << 31) -#define RT2860_RF_LE_SEL1 (1 << 30) -#define RT2860_RF_LE_STBY (1 << 29) -#define RT2860_RF_REG_WIDTH_SHIFT 24 -#define RT2860_RF_REG_0_SHIFT 0 +#define RT2860_RF_REG_CTRL (1U << 31) +#define RT2860_RF_LE_SEL1 (1 << 30) +#define RT2860_RF_LE_STBY (1 << 29) +#define RT2860_RF_REG_WIDTH_SHIFT 24 +#define RT2860_RF_REG_0_SHIFT 0 /* possible flags for register RF_CSR_CFG1 */ -#define RT2860_RF_DUR_5 (1 << 24) -#define RT2860_RF_REG_1_SHIFT 0 +#define RT2860_RF_DUR_5 (1 << 24) +#define RT2860_RF_REG_1_SHIFT 0 /* possible flags for register LED_CFG */ -#define RT2860_LED_POL (1 << 30) -#define RT2860_Y_LED_MODE_SHIFT 28 -#define RT2860_G_LED_MODE_SHIFT 26 -#define RT2860_R_LED_MODE_SHIFT 24 -#define RT2860_LED_MODE_OFF 0 -#define RT2860_LED_MODE_BLINK_TX 1 -#define RT2860_LED_MODE_SLOW_BLINK 2 -#define RT2860_LED_MODE_ON 3 -#define RT2860_SLOW_BLK_TIME_SHIFT 16 -#define RT2860_LED_OFF_TIME_SHIFT 8 -#define RT2860_LED_ON_TIME_SHIFT 0 +#define RT2860_LED_POL (1 << 30) +#define RT2860_Y_LED_MODE_SHIFT 28 +#define RT2860_G_LED_MODE_SHIFT 26 +#define RT2860_R_LED_MODE_SHIFT 24 +#define RT2860_LED_MODE_OFF 0 +#define RT2860_LED_MODE_BLINK_TX 1 +#define RT2860_LED_MODE_SLOW_BLINK 2 +#define RT2860_LED_MODE_ON 3 +#define RT2860_SLOW_BLK_TIME_SHIFT 16 +#define RT2860_LED_OFF_TIME_SHIFT 8 +#define RT2860_LED_ON_TIME_SHIFT 0 /* possible flags for register XIFS_TIME_CFG */ -#define RT2860_BB_RXEND_EN (1 << 29) -#define RT2860_EIFS_TIME_SHIFT 20 -#define RT2860_OFDM_XIFS_TIME_SHIFT 16 -#define RT2860_OFDM_SIFS_TIME_SHIFT 8 -#define RT2860_CCK_SIFS_TIME_SHIFT 0 +#define RT2860_BB_RXEND_EN (1 << 29) +#define RT2860_EIFS_TIME_SHIFT 20 +#define RT2860_OFDM_XIFS_TIME_SHIFT 16 +#define RT2860_OFDM_SIFS_TIME_SHIFT 8 +#define RT2860_CCK_SIFS_TIME_SHIFT 0 /* possible flags for register BKOFF_SLOT_CFG */ -#define RT2860_CC_DELAY_TIME_SHIFT 8 -#define RT2860_SLOT_TIME 0 +#define RT2860_CC_DELAY_TIME_SHIFT 8 +#define RT2860_SLOT_TIME 0 /* possible flags for register NAV_TIME_CFG */ -#define RT2860_NAV_UPD (1U << 31) -#define RT2860_NAV_UPD_VAL_SHIFT 16 -#define RT2860_NAV_CLR_EN (1 << 15) -#define RT2860_NAV_TIMER_SHIFT 0 +#define RT2860_NAV_UPD (1U << 31) +#define RT2860_NAV_UPD_VAL_SHIFT 16 +#define RT2860_NAV_CLR_EN (1 << 15) +#define RT2860_NAV_TIMER_SHIFT 0 /* possible flags for register CH_TIME_CFG */ -#define RT2860_EIFS_AS_CH_BUSY (1 << 4) -#define RT2860_NAV_AS_CH_BUSY (1 << 3) -#define RT2860_RX_AS_CH_BUSY (1 << 2) -#define RT2860_TX_AS_CH_BUSY (1 << 1) -#define RT2860_CH_STA_TIMER_EN (1 << 0) +#define RT2860_EIFS_AS_CH_BUSY (1 << 4) +#define RT2860_NAV_AS_CH_BUSY (1 << 3) +#define RT2860_RX_AS_CH_BUSY (1 << 2) +#define RT2860_TX_AS_CH_BUSY (1 << 1) +#define RT2860_CH_STA_TIMER_EN (1 << 0) /* possible values for register BCN_TIME_CFG */ -#define RT2860_TSF_INS_COMP_SHIFT 24 -#define RT2860_BCN_TX_EN (1 << 20) -#define RT2860_TBTT_TIMER_EN (1 << 19) -#define RT2860_TSF_SYNC_MODE_SHIFT 17 -#define RT2860_TSF_SYNC_MODE_DIS 0 -#define RT2860_TSF_SYNC_MODE_STA 1 -#define RT2860_TSF_SYNC_MODE_IBSS 2 -#define RT2860_TSF_SYNC_MODE_HOSTAP 3 -#define RT2860_TSF_TIMER_EN (1 << 16) -#define RT2860_BCN_INTVAL_SHIFT 0 +#define RT2860_TSF_INS_COMP_SHIFT 24 +#define RT2860_BCN_TX_EN (1 << 20) +#define RT2860_TBTT_TIMER_EN (1 << 19) +#define RT2860_TSF_SYNC_MODE_SHIFT 17 +#define RT2860_TSF_SYNC_MODE_DIS 0 +#define RT2860_TSF_SYNC_MODE_STA 1 +#define RT2860_TSF_SYNC_MODE_IBSS 2 +#define RT2860_TSF_SYNC_MODE_HOSTAP 3 +#define RT2860_TSF_TIMER_EN (1 << 16) +#define RT2860_BCN_INTVAL_SHIFT 0 /* possible flags for register TBTT_SYNC_CFG */ -#define RT2860_BCN_CWMIN_SHIFT 20 -#define RT2860_BCN_AIFSN_SHIFT 16 -#define RT2860_BCN_EXP_WIN_SHIFT 8 -#define RT2860_TBTT_ADJUST_SHIFT 0 +#define RT2860_BCN_CWMIN_SHIFT 20 +#define RT2860_BCN_AIFSN_SHIFT 16 +#define RT2860_BCN_EXP_WIN_SHIFT 8 +#define RT2860_TBTT_ADJUST_SHIFT 0 /* possible flags for register INT_TIMER_CFG */ -#define RT2860_GP_TIMER_SHIFT 16 -#define RT2860_PRE_TBTT_TIMER_SHIFT 0 +#define RT2860_GP_TIMER_SHIFT 16 +#define RT2860_PRE_TBTT_TIMER_SHIFT 0 /* possible flags for register INT_TIMER_EN */ -#define RT2860_GP_TIMER_EN (1 << 1) -#define RT2860_PRE_TBTT_INT_EN (1 << 0) +#define RT2860_GP_TIMER_EN (1 << 1) +#define RT2860_PRE_TBTT_INT_EN (1 << 0) /* possible flags for register MAC_STATUS_REG */ -#define RT2860_RX_STATUS_BUSY (1 << 1) -#define RT2860_TX_STATUS_BUSY (1 << 0) +#define RT2860_RX_STATUS_BUSY (1 << 1) +#define RT2860_TX_STATUS_BUSY (1 << 0) /* possible flags for register PWR_PIN_CFG */ -#define RT2860_IO_ADDA_PD (1 << 3) -#define RT2860_IO_PLL_PD (1 << 2) -#define RT2860_IO_RA_PE (1 << 1) -#define RT2860_IO_RF_PE (1 << 0) +#define RT2860_IO_ADDA_PD (1 << 3) +#define RT2860_IO_PLL_PD (1 << 2) +#define RT2860_IO_RA_PE (1 << 1) +#define RT2860_IO_RF_PE (1 << 0) /* possible flags for register AUTO_WAKEUP_CFG */ -#define RT2860_AUTO_WAKEUP_EN (1 << 15) -#define RT2860_SLEEP_TBTT_NUM_SHIFT 8 -#define RT2860_WAKEUP_LEAD_TIME_SHIFT 0 +#define RT2860_AUTO_WAKEUP_EN (1 << 15) +#define RT2860_SLEEP_TBTT_NUM_SHIFT 8 +#define RT2860_WAKEUP_LEAD_TIME_SHIFT 0 /* possible flags for register TX_PIN_CFG */ -#define RT2860_TRSW_POL (1 << 19) -#define RT2860_TRSW_EN (1 << 18) -#define RT2860_RFTR_POL (1 << 17) -#define RT2860_RFTR_EN (1 << 16) -#define RT2860_LNA_PE_G1_POL (1 << 15) -#define RT2860_LNA_PE_A1_POL (1 << 14) -#define RT2860_LNA_PE_G0_POL (1 << 13) -#define RT2860_LNA_PE_A0_POL (1 << 12) -#define RT2860_LNA_PE_G1_EN (1 << 11) -#define RT2860_LNA_PE_A1_EN (1 << 10) -#define RT2860_LNA_PE1_EN (RT2860_LNA_PE_A1_EN | RT2860_LNA_PE_G1_EN) -#define RT2860_LNA_PE_G0_EN (1 << 9) -#define RT2860_LNA_PE_A0_EN (1 << 8) -#define RT2860_LNA_PE0_EN (RT2860_LNA_PE_A0_EN | RT2860_LNA_PE_G0_EN) -#define RT2860_PA_PE_G1_POL (1 << 7) -#define RT2860_PA_PE_A1_POL (1 << 6) -#define RT2860_PA_PE_G0_POL (1 << 5) -#define RT2860_PA_PE_A0_POL (1 << 4) -#define RT2860_PA_PE_G1_EN (1 << 3) -#define RT2860_PA_PE_A1_EN (1 << 2) -#define RT2860_PA_PE_G0_EN (1 << 1) -#define RT2860_PA_PE_A0_EN (1 << 0) +#define RT2860_TRSW_POL (1 << 19) +#define RT2860_TRSW_EN (1 << 18) +#define RT2860_RFTR_POL (1 << 17) +#define RT2860_RFTR_EN (1 << 16) +#define RT2860_LNA_PE_G1_POL (1 << 15) +#define RT2860_LNA_PE_A1_POL (1 << 14) +#define RT2860_LNA_PE_G0_POL (1 << 13) +#define RT2860_LNA_PE_A0_POL (1 << 12) +#define RT2860_LNA_PE_G1_EN (1 << 11) +#define RT2860_LNA_PE_A1_EN (1 << 10) +#define RT2860_LNA_PE1_EN (RT2860_LNA_PE_A1_EN | RT2860_LNA_PE_G1_EN) +#define RT2860_LNA_PE_G0_EN (1 << 9) +#define RT2860_LNA_PE_A0_EN (1 << 8) +#define RT2860_LNA_PE0_EN (RT2860_LNA_PE_A0_EN | RT2860_LNA_PE_G0_EN) +#define RT2860_PA_PE_G1_POL (1 << 7) +#define RT2860_PA_PE_A1_POL (1 << 6) +#define RT2860_PA_PE_G0_POL (1 << 5) +#define RT2860_PA_PE_A0_POL (1 << 4) +#define RT2860_PA_PE_G1_EN (1 << 3) +#define RT2860_PA_PE_A1_EN (1 << 2) +#define RT2860_PA_PE_G0_EN (1 << 1) +#define RT2860_PA_PE_A0_EN (1 << 0) /* possible flags for register TX_BAND_CFG */ -#define RT2860_5G_BAND_SEL_N (1 << 2) -#define RT2860_5G_BAND_SEL_P (1 << 1) -#define RT2860_TX_BAND_SEL (1 << 0) +#define RT2860_5G_BAND_SEL_N (1 << 2) +#define RT2860_5G_BAND_SEL_P (1 << 1) +#define RT2860_TX_BAND_SEL (1 << 0) /* possible flags for register TX_SW_CFG0 */ -#define RT2860_DLY_RFTR_EN_SHIFT 24 -#define RT2860_DLY_TRSW_EN_SHIFT 16 -#define RT2860_DLY_PAPE_EN_SHIFT 8 -#define RT2860_DLY_TXPE_EN_SHIFT 0 +#define RT2860_DLY_RFTR_EN_SHIFT 24 +#define RT2860_DLY_TRSW_EN_SHIFT 16 +#define RT2860_DLY_PAPE_EN_SHIFT 8 +#define RT2860_DLY_TXPE_EN_SHIFT 0 /* possible flags for register TX_SW_CFG1 */ -#define RT2860_DLY_RFTR_DIS_SHIFT 16 -#define RT2860_DLY_TRSW_DIS_SHIFT 8 -#define RT2860_DLY_PAPE_DIS SHIFT 0 +#define RT2860_DLY_RFTR_DIS_SHIFT 16 +#define RT2860_DLY_TRSW_DIS_SHIFT 8 +#define RT2860_DLY_PAPE_DIS SHIFT 0 /* possible flags for register TX_SW_CFG2 */ -#define RT2860_DLY_LNA_EN_SHIFT 24 -#define RT2860_DLY_LNA_DIS_SHIFT 16 -#define RT2860_DLY_DAC_EN_SHIFT 8 -#define RT2860_DLY_DAC_DIS_SHIFT 0 +#define RT2860_DLY_LNA_EN_SHIFT 24 +#define RT2860_DLY_LNA_DIS_SHIFT 16 +#define RT2860_DLY_DAC_EN_SHIFT 8 +#define RT2860_DLY_DAC_DIS_SHIFT 0 /* possible flags for register TXOP_THRES_CFG */ -#define RT2860_TXOP_REM_THRES_SHIFT 24 -#define RT2860_CF_END_THRES_SHIFT 16 -#define RT2860_RDG_IN_THRES 8 -#define RT2860_RDG_OUT_THRES 0 +#define RT2860_TXOP_REM_THRES_SHIFT 24 +#define RT2860_CF_END_THRES_SHIFT 16 +#define RT2860_RDG_IN_THRES 8 +#define RT2860_RDG_OUT_THRES 0 /* possible flags for register TXOP_CTRL_CFG */ -#define RT2860_EXT_CW_MIN_SHIFT 16 -#define RT2860_EXT_CCA_DLY_SHIFT 8 -#define RT2860_EXT_CCA_EN (1 << 7) -#define RT2860_LSIG_TXOP_EN (1 << 6) -#define RT2860_TXOP_TRUN_EN_MIMOPS (1 << 4) -#define RT2860_TXOP_TRUN_EN_TXOP (1 << 3) -#define RT2860_TXOP_TRUN_EN_RATE (1 << 2) -#define RT2860_TXOP_TRUN_EN_AC (1 << 1) -#define RT2860_TXOP_TRUN_EN_TIMEOUT (1 << 0) +#define RT2860_EXT_CW_MIN_SHIFT 16 +#define RT2860_EXT_CCA_DLY_SHIFT 8 +#define RT2860_EXT_CCA_EN (1 << 7) +#define RT2860_LSIG_TXOP_EN (1 << 6) +#define RT2860_TXOP_TRUN_EN_MIMOPS (1 << 4) +#define RT2860_TXOP_TRUN_EN_TXOP (1 << 3) +#define RT2860_TXOP_TRUN_EN_RATE (1 << 2) +#define RT2860_TXOP_TRUN_EN_AC (1 << 1) +#define RT2860_TXOP_TRUN_EN_TIMEOUT (1 << 0) /* possible flags for register TX_RTS_CFG */ -#define RT2860_RTS_FBK_EN (1 << 24) -#define RT2860_RTS_THRES_SHIFT 8 -#define RT2860_RTS_RTY_LIMIT_SHIFT 0 +#define RT2860_RTS_FBK_EN (1 << 24) +#define RT2860_RTS_THRES_SHIFT 8 +#define RT2860_RTS_RTY_LIMIT_SHIFT 0 /* possible flags for register TX_TIMEOUT_CFG */ -#define RT2860_TXOP_TIMEOUT_SHIFT 16 -#define RT2860_RX_ACK_TIMEOUT_SHIFT 8 -#define RT2860_MPDU_LIFE_TIME_SHIFT 4 +#define RT2860_TXOP_TIMEOUT_SHIFT 16 +#define RT2860_RX_ACK_TIMEOUT_SHIFT 8 +#define RT2860_MPDU_LIFE_TIME_SHIFT 4 /* possible flags for register TX_RTY_CFG */ -#define RT2860_TX_AUTOFB_EN (1 << 30) -#define RT2860_AGG_RTY_MODE_TIMER (1 << 29) -#define RT2860_NAG_RTY_MODE_TIMER (1 << 28) -#define RT2860_LONG_RTY_THRES_SHIFT 16 -#define RT2860_LONG_RTY_LIMIT_SHIFT 8 -#define RT2860_SHORT_RTY_LIMIT_SHIFT 0 +#define RT2860_TX_AUTOFB_EN (1 << 30) +#define RT2860_AGG_RTY_MODE_TIMER (1 << 29) +#define RT2860_NAG_RTY_MODE_TIMER (1 << 28) +#define RT2860_LONG_RTY_THRES_SHIFT 16 +#define RT2860_LONG_RTY_LIMIT_SHIFT 8 +#define RT2860_SHORT_RTY_LIMIT_SHIFT 0 /* possible flags for register TX_LINK_CFG */ -#define RT2860_REMOTE_MFS_SHIFT 24 -#define RT2860_REMOTE_MFB_SHIFT 16 -#define RT2860_TX_CFACK_EN (1 << 12) -#define RT2860_TX_RDG_EN (1 << 11) -#define RT2860_TX_MRQ_EN (1 << 10) -#define RT2860_REMOTE_UMFS_EN (1 << 9) -#define RT2860_TX_MFB_EN (1 << 8) -#define RT2860_REMOTE_MFB_LT_SHIFT 0 +#define RT2860_REMOTE_MFS_SHIFT 24 +#define RT2860_REMOTE_MFB_SHIFT 16 +#define RT2860_TX_CFACK_EN (1 << 12) +#define RT2860_TX_RDG_EN (1 << 11) +#define RT2860_TX_MRQ_EN (1 << 10) +#define RT2860_REMOTE_UMFS_EN (1 << 9) +#define RT2860_TX_MFB_EN (1 << 8) +#define RT2860_REMOTE_MFB_LT_SHIFT 0 /* possible flags for registers *_PROT_CFG */ -#define RT2860_RTSTH_EN (1 << 26) -#define RT2860_TXOP_ALLOW_GF40 (1 << 25) -#define RT2860_TXOP_ALLOW_GF20 (1 << 24) -#define RT2860_TXOP_ALLOW_MM40 (1 << 23) -#define RT2860_TXOP_ALLOW_MM20 (1 << 22) -#define RT2860_TXOP_ALLOW_OFDM (1 << 21) -#define RT2860_TXOP_ALLOW_CCK (1 << 20) -#define RT2860_TXOP_ALLOW_ALL (0x3f << 20) -#define RT2860_PROT_NAV_SHORT (1 << 18) -#define RT2860_PROT_NAV_LONG (2 << 18) -#define RT2860_PROT_CTRL_RTS_CTS (1 << 16) -#define RT2860_PROT_CTRL_CTS (2 << 16) +#define RT2860_RTSTH_EN (1 << 26) +#define RT2860_TXOP_ALLOW_GF40 (1 << 25) +#define RT2860_TXOP_ALLOW_GF20 (1 << 24) +#define RT2860_TXOP_ALLOW_MM40 (1 << 23) +#define RT2860_TXOP_ALLOW_MM20 (1 << 22) +#define RT2860_TXOP_ALLOW_OFDM (1 << 21) +#define RT2860_TXOP_ALLOW_CCK (1 << 20) +#define RT2860_TXOP_ALLOW_ALL (0x3f << 20) +#define RT2860_PROT_NAV_SHORT (1 << 18) +#define RT2860_PROT_NAV_LONG (2 << 18) +#define RT2860_PROT_CTRL_RTS_CTS (1 << 16) +#define RT2860_PROT_CTRL_CTS (2 << 16) /* possible flags for registers EXP_{CTS,ACK}_TIME */ -#define RT2860_EXP_OFDM_TIME_SHIFT 16 -#define RT2860_EXP_CCK_TIME_SHIFT 0 +#define RT2860_EXP_OFDM_TIME_SHIFT 16 +#define RT2860_EXP_CCK_TIME_SHIFT 0 /* possible flags for register RX_FILTR_CFG */ -#define RT2860_DROP_CTRL_RSV (1 << 16) -#define RT2860_DROP_BAR (1 << 15) -#define RT2860_DROP_BA (1 << 14) -#define RT2860_DROP_PSPOLL (1 << 13) -#define RT2860_DROP_RTS (1 << 12) -#define RT2860_DROP_CTS (1 << 11) -#define RT2860_DROP_ACK (1 << 10) -#define RT2860_DROP_CFEND (1 << 9) -#define RT2860_DROP_CFACK (1 << 8) -#define RT2860_DROP_DUPL (1 << 7) -#define RT2860_DROP_BC (1 << 6) -#define RT2860_DROP_MC (1 << 5) -#define RT2860_DROP_VER_ERR (1 << 4) -#define RT2860_DROP_NOT_MYBSS (1 << 3) -#define RT2860_DROP_UC_NOME (1 << 2) -#define RT2860_DROP_PHY_ERR (1 << 1) -#define RT2860_DROP_CRC_ERR (1 << 0) +#define RT2860_DROP_CTRL_RSV (1 << 16) +#define RT2860_DROP_BAR (1 << 15) +#define RT2860_DROP_BA (1 << 14) +#define RT2860_DROP_PSPOLL (1 << 13) +#define RT2860_DROP_RTS (1 << 12) +#define RT2860_DROP_CTS (1 << 11) +#define RT2860_DROP_ACK (1 << 10) +#define RT2860_DROP_CFEND (1 << 9) +#define RT2860_DROP_CFACK (1 << 8) +#define RT2860_DROP_DUPL (1 << 7) +#define RT2860_DROP_BC (1 << 6) +#define RT2860_DROP_MC (1 << 5) +#define RT2860_DROP_VER_ERR (1 << 4) +#define RT2860_DROP_NOT_MYBSS (1 << 3) +#define RT2860_DROP_UC_NOME (1 << 2) +#define RT2860_DROP_PHY_ERR (1 << 1) +#define RT2860_DROP_CRC_ERR (1 << 0) /* possible flags for register AUTO_RSP_CFG */ -#define RT2860_CTRL_PWR_BIT (1 << 7) -#define RT2860_BAC_ACK_POLICY (1 << 6) -#define RT2860_CCK_SHORT_EN (1 << 4) -#define RT2860_CTS_40M_REF_EN (1 << 3) -#define RT2860_CTS_40M_MODE_EN (1 << 2) -#define RT2860_BAC_ACKPOLICY_EN (1 << 1) -#define RT2860_AUTO_RSP_EN (1 << 0) +#define RT2860_CTRL_PWR_BIT (1 << 7) +#define RT2860_BAC_ACK_POLICY (1 << 6) +#define RT2860_CCK_SHORT_EN (1 << 4) +#define RT2860_CTS_40M_REF_EN (1 << 3) +#define RT2860_CTS_40M_MODE_EN (1 << 2) +#define RT2860_BAC_ACKPOLICY_EN (1 << 1) +#define RT2860_AUTO_RSP_EN (1 << 0) /* possible flags for register SIFS_COST_CFG */ -#define RT2860_OFDM_SIFS_COST_SHIFT 8 -#define RT2860_CCK_SIFS_COST_SHIFT 0 +#define RT2860_OFDM_SIFS_COST_SHIFT 8 +#define RT2860_CCK_SIFS_COST_SHIFT 0 /* possible flags for register TXOP_HLDR_ET */ -#define RT2860_TXOP_ETM1_EN (1 << 25) -#define RT2860_TXOP_ETM0_EN (1 << 24) -#define RT2860_TXOP_ETM_THRES_SHIFT 16 -#define RT2860_TXOP_ETO_EN (1 << 8) -#define RT2860_TXOP_ETO_THRES_SHIFT 1 -#define RT2860_PER_RX_RST_EN (1 << 0) +#define RT2860_TXOP_ETM1_EN (1 << 25) +#define RT2860_TXOP_ETM0_EN (1 << 24) +#define RT2860_TXOP_ETM_THRES_SHIFT 16 +#define RT2860_TXOP_ETO_EN (1 << 8) +#define RT2860_TXOP_ETO_THRES_SHIFT 1 +#define RT2860_PER_RX_RST_EN (1 << 0) /* possible flags for register TX_STAT_FIFO */ -#define RT2860_TXQ_MCS_SHIFT 16 -#define RT2860_TXQ_WCID_SHIFT 8 -#define RT2860_TXQ_ACKREQ (1 << 7) -#define RT2860_TXQ_AGG (1 << 6) -#define RT2860_TXQ_OK (1 << 5) -#define RT2860_TXQ_PID_SHIFT 1 -#define RT2860_TXQ_VLD (1 << 0) +#define RT2860_TXQ_MCS_SHIFT 16 +#define RT2860_TXQ_WCID_SHIFT 8 +#define RT2860_TXQ_ACKREQ (1 << 7) +#define RT2860_TXQ_AGG (1 << 6) +#define RT2860_TXQ_OK (1 << 5) +#define RT2860_TXQ_PID_SHIFT 1 +#define RT2860_TXQ_VLD (1 << 0) /* possible flags for register WCID_ATTR */ -#define RT2860_MODE_NOSEC 0 -#define RT2860_MODE_WEP40 1 -#define RT2860_MODE_WEP104 2 -#define RT2860_MODE_TKIP 3 -#define RT2860_MODE_AES_CCMP 4 -#define RT2860_MODE_CKIP40 5 -#define RT2860_MODE_CKIP104 6 -#define RT2860_MODE_CKIP128 7 -#define RT2860_RX_PKEY_EN (1 << 0) +#define RT2860_MODE_NOSEC 0 +#define RT2860_MODE_WEP40 1 +#define RT2860_MODE_WEP104 2 +#define RT2860_MODE_TKIP 3 +#define RT2860_MODE_AES_CCMP 4 +#define RT2860_MODE_CKIP40 5 +#define RT2860_MODE_CKIP104 6 +#define RT2860_MODE_CKIP128 7 +#define RT2860_RX_PKEY_EN (1 << 0) /* possible flags for register H2M_MAILBOX */ -#define RT2860_H2M_BUSY (1 << 24) -#define RT2860_TOKEN_NO_INTR 0xff - +#define RT2860_H2M_BUSY (1 << 24) +#define RT2860_TOKEN_NO_INTR 0xff /* possible flags for MCU command RT2860_MCU_CMD_LEDS */ -#define RT2860_LED_RADIO (1 << 13) -#define RT2860_LED_LINK_2GHZ (1 << 14) -#define RT2860_LED_LINK_5GHZ (1 << 15) - +#define RT2860_LED_RADIO (1 << 13) +#define RT2860_LED_LINK_2GHZ (1 << 14) +#define RT2860_LED_LINK_5GHZ (1 << 15) /* possible flags for RT3020 RF register 1 */ -#define RT3070_RF_BLOCK (1 << 0) -#define RT3070_PLL_PD (1 << 1) -#define RT3070_RX0_PD (1 << 2) -#define RT3070_TX0_PD (1 << 3) -#define RT3070_RX1_PD (1 << 4) -#define RT3070_TX1_PD (1 << 5) +#define RT3070_RF_BLOCK (1 << 0) +#define RT3070_PLL_PD (1 << 1) +#define RT3070_RX0_PD (1 << 2) +#define RT3070_TX0_PD (1 << 3) +#define RT3070_RX1_PD (1 << 4) +#define RT3070_TX1_PD (1 << 5) +#define RT3070_RX2_PD (1 << 6) +#define RT3070_TX2_PD (1 << 7) /* possible flags for RT3020 RF register 15 */ -#define RT3070_TX_LO2 (1 << 3) +#define RT3070_TX_LO2 (1 << 3) /* possible flags for RT3020 RF register 17 */ -#define RT3070_TX_LO1 (1 << 3) +#define RT3070_TX_LO1 (1 << 3) /* possible flags for RT3020 RF register 20 */ -#define RT3070_RX_LO1 (1 << 3) +#define RT3070_RX_LO1 (1 << 3) /* possible flags for RT3020 RF register 21 */ -#define RT3070_RX_LO2 (1 << 3) +#define RT3070_RX_LO2 (1 << 3) + +/* possible flags for RT3053 RF register 18 */ +#define RT3593_AUTOTUNE_BYPASS (1 << 6) + +/* possible flags for RT3053 RF register 50 */ +#define RT3593_TX_LO2 (1 << 4) + +/* possible flags for RT3053 RF register 51 */ +#define RT3593_TX_LO1 (1 << 4) /* Possible flags for RT5390 RF register 2. */ #define RT5390_RESCAL (1 << 7) @@ -729,21 +738,21 @@ struct rt2860_txd { uint32_t sdp0; /* Segment Data Pointer 0 */ uint16_t sdl1; /* Segment Data Length 1 */ -#define RT2860_TX_BURST (1 << 15) -#define RT2860_TX_LS1 (1 << 14) /* SDP1 is the last segment */ +#define RT2860_TX_BURST (1 << 15) +#define RT2860_TX_LS1 (1 << 14) /* SDP1 is the last segment */ uint16_t sdl0; /* Segment Data Length 0 */ -#define RT2860_TX_DDONE (1 << 15) -#define RT2860_TX_LS0 (1 << 14) /* SDP0 is the last segment */ +#define RT2860_TX_DDONE (1 << 15) +#define RT2860_TX_LS0 (1 << 14) /* SDP0 is the last segment */ uint32_t sdp1; /* Segment Data Pointer 1 */ uint8_t reserved[3]; uint8_t flags; -#define RT2860_TX_QSEL_SHIFT 1 -#define RT2860_TX_QSEL_MGMT (0 << 1) -#define RT2860_TX_QSEL_HCCA (1 << 1) -#define RT2860_TX_QSEL_EDCA (2 << 1) -#define RT2860_TX_WIV (1 << 0) +#define RT2860_TX_QSEL_SHIFT 1 +#define RT2860_TX_QSEL_MGMT (0 << 1) +#define RT2860_TX_QSEL_HCCA (1 << 1) +#define RT2860_TX_QSEL_EDCA (2 << 1) +#define RT2860_TX_WIV (1 << 0) } __packed; /* RT2870 TX descriptor */ @@ -756,38 +765,38 @@ struct rt2870_txd { /* TX Wireless Information */ struct rt2860_txwi { uint8_t flags; -#define RT2860_TX_MPDU_DSITY_SHIFT 5 -#define RT2860_TX_AMPDU (1 << 4) -#define RT2860_TX_TS (1 << 3) -#define RT2860_TX_CFACK (1 << 2) -#define RT2860_TX_MMPS (1 << 1) -#define RT2860_TX_FRAG (1 << 0) +#define RT2860_TX_MPDU_DSITY_SHIFT 5 +#define RT2860_TX_AMPDU (1 << 4) +#define RT2860_TX_TS (1 << 3) +#define RT2860_TX_CFACK (1 << 2) +#define RT2860_TX_MMPS (1 << 1) +#define RT2860_TX_FRAG (1 << 0) uint8_t txop; -#define RT2860_TX_TXOP_HT 0 -#define RT2860_TX_TXOP_PIFS 1 -#define RT2860_TX_TXOP_SIFS 2 -#define RT2860_TX_TXOP_BACKOFF 3 +#define RT2860_TX_TXOP_HT 0 +#define RT2860_TX_TXOP_PIFS 1 +#define RT2860_TX_TXOP_SIFS 2 +#define RT2860_TX_TXOP_BACKOFF 3 uint16_t phy; -#define RT2860_PHY_MODE 0xc000 -#define RT2860_PHY_CCK (0 << 14) -#define RT2860_PHY_OFDM (1 << 14) -#define RT2860_PHY_HT (2 << 14) -#define RT2860_PHY_HT_GF (3 << 14) -#define RT2860_PHY_SGI (1 << 8) -#define RT2860_PHY_BW40 (1 << 7) -#define RT2860_PHY_MCS 0x7f -#define RT2860_PHY_SHPRE (1 << 3) +#define RT2860_PHY_MODE 0xc000 +#define RT2860_PHY_CCK (0 << 14) +#define RT2860_PHY_OFDM (1 << 14) +#define RT2860_PHY_HT (2 << 14) +#define RT2860_PHY_HT_GF (3 << 14) +#define RT2860_PHY_SGI (1 << 8) +#define RT2860_PHY_BW40 (1 << 7) +#define RT2860_PHY_MCS 0x7f +#define RT2860_PHY_SHPRE (1 << 3) uint8_t xflags; -#define RT2860_TX_BAWINSIZE_SHIFT 2 -#define RT2860_TX_NSEQ (1 << 1) -#define RT2860_TX_ACK (1 << 0) +#define RT2860_TX_BAWINSIZE_SHIFT 2 +#define RT2860_TX_NSEQ (1 << 1) +#define RT2860_TX_ACK (1 << 0) uint8_t wcid; /* Wireless Client ID */ uint16_t len; -#define RT2860_TX_PID_SHIFT 12 +#define RT2860_TX_PID_SHIFT 12 uint32_t iv; uint32_t eiv; @@ -798,28 +807,28 @@ struct rt2860_rxd { uint32_t sdp0; uint16_t sdl1; /* unused */ uint16_t sdl0; -#define RT2860_RX_DDONE (1 << 15) -#define RT2860_RX_LS0 (1 << 14) +#define RT2860_RX_DDONE (1 << 15) +#define RT2860_RX_LS0 (1 << 14) uint32_t sdp1; /* unused */ uint32_t flags; -#define RT2860_RX_DEC (1 << 16) -#define RT2860_RX_AMPDU (1 << 15) -#define RT2860_RX_L2PAD (1 << 14) -#define RT2860_RX_RSSI (1 << 13) -#define RT2860_RX_HTC (1 << 12) -#define RT2860_RX_AMSDU (1 << 11) -#define RT2860_RX_MICERR (1 << 10) -#define RT2860_RX_ICVERR (1 << 9) -#define RT2860_RX_CRCERR (1 << 8) -#define RT2860_RX_MYBSS (1 << 7) -#define RT2860_RX_BC (1 << 6) -#define RT2860_RX_MC (1 << 5) -#define RT2860_RX_UC2ME (1 << 4) -#define RT2860_RX_FRAG (1 << 3) -#define RT2860_RX_NULL (1 << 2) -#define RT2860_RX_DATA (1 << 1) -#define RT2860_RX_BA (1 << 0) +#define RT2860_RX_DEC (1 << 16) +#define RT2860_RX_AMPDU (1 << 15) +#define RT2860_RX_L2PAD (1 << 14) +#define RT2860_RX_RSSI (1 << 13) +#define RT2860_RX_HTC (1 << 12) +#define RT2860_RX_AMSDU (1 << 11) +#define RT2860_RX_MICERR (1 << 10) +#define RT2860_RX_ICVERR (1 << 9) +#define RT2860_RX_CRCERR (1 << 8) +#define RT2860_RX_MYBSS (1 << 7) +#define RT2860_RX_BC (1 << 6) +#define RT2860_RX_MC (1 << 5) +#define RT2860_RX_UC2ME (1 << 4) +#define RT2860_RX_FRAG (1 << 3) +#define RT2860_RX_NULL (1 << 2) +#define RT2860_RX_DATA (1 << 1) +#define RT2860_RX_BA (1 << 0) } __packed; /* RT2870 RX descriptor */ @@ -832,11 +841,11 @@ struct rt2870_rxd { struct rt2860_rxwi { uint8_t wcid; uint8_t keyidx; -#define RT2860_RX_UDF_SHIFT 5 -#define RT2860_RX_BSS_IDX_SHIFT 2 +#define RT2860_RX_UDF_SHIFT 5 +#define RT2860_RX_BSS_IDX_SHIFT 2 uint16_t len; -#define RT2860_RX_TID_SHIFT 12 +#define RT2860_RX_TID_SHIFT 12 uint16_t seq; uint16_t phy; @@ -846,90 +855,111 @@ struct rt2860_rxwi { uint16_t reserved2; } __packed; -#define RT2860_RF_2820 0x0001 /* 2T3R */ -#define RT2860_RF_2850 0x0002 /* dual-band 2T3R */ -#define RT2860_RF_2720 0x0003 /* 1T2R */ -#define RT2860_RF_2750 0x0004 /* dual-band 1T2R */ -#define RT3070_RF_3020 0x0005 /* 1T1R */ -#define RT3070_RF_2020 0x0006 /* b/g */ -#define RT3070_RF_3021 0x0007 /* 1T2R */ -#define RT3070_RF_3022 0x0008 /* 2T2R */ -#define RT3070_RF_3052 0x0009 /* dual-band 2T2R */ -#define RT5592_RF_5592 0x000f /* dual-band 2T2R */ -#define RT5390_RF_5370 0x5370 /* 1T1R */ -#define RT5390_RF_5372 0x5372 /* 2T2R */ +#define RT2860_RF_2820 0x0001 /* 2T3R */ +#define RT2860_RF_2850 0x0002 /* dual-band 2T3R */ +#define RT2860_RF_2720 0x0003 /* 1T2R */ +#define RT2860_RF_2750 0x0004 /* dual-band 1T2R */ +#define RT3070_RF_3020 0x0005 /* 1T1R */ +#define RT3070_RF_2020 0x0006 /* b/g */ +#define RT3070_RF_3021 0x0007 /* 1T2R */ +#define RT3070_RF_3022 0x0008 /* 2T2R */ +#define RT3070_RF_3052 0x0009 /* dual-band 2T2R */ +#define RT3593_RF_3053 0x000d /* dual-band 3T3R */ +#define RT5592_RF_5592 0x000f /* dual-band 2T2R */ +#define RT5390_RF_5370 0x5370 /* 1T1R */ +#define RT5390_RF_5372 0x5372 /* 2T2R */ /* USB commands for RT2870 only */ -#define RT2870_RESET 1 -#define RT2870_WRITE_2 2 -#define RT2870_WRITE_REGION_1 6 -#define RT2870_READ_REGION_1 7 -#define RT2870_EEPROM_READ 9 - -#define RT2860_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ - -#define RT2860_EEPROM_VERSION 0x01 -#define RT2860_EEPROM_MAC01 0x02 -#define RT2860_EEPROM_MAC23 0x03 -#define RT2860_EEPROM_MAC45 0x04 -#define RT2860_EEPROM_PCIE_PSLEVEL 0x11 -#define RT2860_EEPROM_REV 0x12 -#define RT2860_EEPROM_ANTENNA 0x1a -#define RT2860_EEPROM_CONFIG 0x1b -#define RT2860_EEPROM_COUNTRY 0x1c -#define RT2860_EEPROM_FREQ_LEDS 0x1d -#define RT2860_EEPROM_LED1 0x1e -#define RT2860_EEPROM_LED2 0x1f -#define RT2860_EEPROM_LED3 0x20 -#define RT2860_EEPROM_LNA 0x22 -#define RT2860_EEPROM_RSSI1_2GHZ 0x23 -#define RT2860_EEPROM_RSSI2_2GHZ 0x24 -#define RT2860_EEPROM_RSSI1_5GHZ 0x25 -#define RT2860_EEPROM_RSSI2_5GHZ 0x26 -#define RT2860_EEPROM_DELTAPWR 0x28 -#define RT2860_EEPROM_PWR2GHZ_BASE1 0x29 -#define RT2860_EEPROM_PWR2GHZ_BASE2 0x30 -#define RT2860_EEPROM_TSSI1_2GHZ 0x37 -#define RT2860_EEPROM_TSSI2_2GHZ 0x38 -#define RT2860_EEPROM_TSSI3_2GHZ 0x39 -#define RT2860_EEPROM_TSSI4_2GHZ 0x3a -#define RT2860_EEPROM_TSSI5_2GHZ 0x3b -#define RT2860_EEPROM_PWR5GHZ_BASE1 0x3c -#define RT2860_EEPROM_PWR5GHZ_BASE2 0x53 -#define RT2860_EEPROM_TSSI1_5GHZ 0x6a -#define RT2860_EEPROM_TSSI2_5GHZ 0x6b -#define RT2860_EEPROM_TSSI3_5GHZ 0x6c -#define RT2860_EEPROM_TSSI4_5GHZ 0x6d -#define RT2860_EEPROM_TSSI5_5GHZ 0x6e -#define RT2860_EEPROM_RPWR 0x6f -#define RT2860_EEPROM_BBP_BASE 0x78 -#define RT3071_EEPROM_RF_BASE 0x82 - -#define RT2860_RIDX_CCK1 0 -#define RT2860_RIDX_CCK11 3 -#define RT2860_RIDX_OFDM6 4 -#define RT2860_RIDX_MAX 12 -static const struct rt2860_rate { - uint8_t rate; - uint8_t mcs; - enum ieee80211_phytype phy; - uint8_t ctl_ridx; - uint16_t sp_ack_dur; - uint16_t lp_ack_dur; -} rt2860_rates[] = { - { 2, 0, IEEE80211_T_DS, 0, 314, 314 }, - { 4, 1, IEEE80211_T_DS, 1, 258, 162 }, - { 11, 2, IEEE80211_T_DS, 2, 223, 127 }, - { 22, 3, IEEE80211_T_DS, 3, 213, 117 }, - { 12, 0, IEEE80211_T_OFDM, 4, 60, 60 }, - { 18, 1, IEEE80211_T_OFDM, 4, 52, 52 }, - { 24, 2, IEEE80211_T_OFDM, 6, 48, 48 }, - { 36, 3, IEEE80211_T_OFDM, 6, 44, 44 }, - { 48, 4, IEEE80211_T_OFDM, 8, 44, 44 }, - { 72, 5, IEEE80211_T_OFDM, 8, 40, 40 }, - { 96, 6, IEEE80211_T_OFDM, 8, 40, 40 }, - { 108, 7, IEEE80211_T_OFDM, 8, 40, 40 } -}; +#define RT2870_RESET 1 +#define RT2870_WRITE_2 2 +#define RT2870_WRITE_REGION_1 6 +#define RT2870_READ_REGION_1 7 +#define RT2870_EEPROM_READ 9 + +#define RT2860_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ + +#define RT2860_EEPROM_VERSION 0x01 +#define RT2860_EEPROM_MAC01 0x02 +#define RT2860_EEPROM_MAC23 0x03 +#define RT2860_EEPROM_MAC45 0x04 +#define RT2860_EEPROM_PCIE_PSLEVEL 0x11 +#define RT2860_EEPROM_REV 0x12 +#define RT2860_EEPROM_ANTENNA 0x1a +#define RT2860_EEPROM_CONFIG 0x1b +#define RT2860_EEPROM_COUNTRY 0x1c +#define RT2860_EEPROM_FREQ_LEDS 0x1d +#define RT2860_EEPROM_LED1 0x1e +#define RT2860_EEPROM_LED2 0x1f +#define RT2860_EEPROM_LED3 0x20 +#define RT2860_EEPROM_LNA 0x22 +#define RT2860_EEPROM_RSSI1_2GHZ 0x23 +#define RT2860_EEPROM_RSSI2_2GHZ 0x24 +#define RT2860_EEPROM_RSSI1_5GHZ 0x25 +#define RT2860_EEPROM_RSSI2_5GHZ 0x26 +#define RT2860_EEPROM_DELTAPWR 0x28 +#define RT2860_EEPROM_PWR2GHZ_BASE1 0x29 +#define RT2860_EEPROM_PWR2GHZ_BASE2 0x30 +#define RT2860_EEPROM_TSSI1_2GHZ 0x37 +#define RT2860_EEPROM_TSSI2_2GHZ 0x38 +#define RT2860_EEPROM_TSSI3_2GHZ 0x39 +#define RT2860_EEPROM_TSSI4_2GHZ 0x3a +#define RT2860_EEPROM_TSSI5_2GHZ 0x3b +#define RT2860_EEPROM_PWR5GHZ_BASE1 0x3c +#define RT2860_EEPROM_PWR5GHZ_BASE2 0x53 +#define RT2860_EEPROM_TSSI1_5GHZ 0x6a +#define RT2860_EEPROM_TSSI2_5GHZ 0x6b +#define RT2860_EEPROM_TSSI3_5GHZ 0x6c +#define RT2860_EEPROM_TSSI4_5GHZ 0x6d +#define RT2860_EEPROM_TSSI5_5GHZ 0x6e +#define RT2860_EEPROM_RPWR 0x6f +#define RT2860_EEPROM_BBP_BASE 0x78 +#define RT3071_EEPROM_RF_BASE 0x82 + +/* EEPROM registers for RT3593. */ +#define RT3593_EEPROM_FREQ_LEDS 0x21 +#define RT3593_EEPROM_FREQ 0x22 +#define RT3593_EEPROM_LED1 0x22 +#define RT3593_EEPROM_LED2 0x23 +#define RT3593_EEPROM_LED3 0x24 +#define RT3593_EEPROM_LNA 0x26 +#define RT3593_EEPROM_LNA_5GHZ 0x27 +#define RT3593_EEPROM_RSSI1_2GHZ 0x28 +#define RT3593_EEPROM_RSSI2_2GHZ 0x29 +#define RT3593_EEPROM_RSSI1_5GHZ 0x2a +#define RT3593_EEPROM_RSSI2_5GHZ 0x2b +#define RT3593_EEPROM_PWR2GHZ_BASE1 0x30 +#define RT3593_EEPROM_PWR2GHZ_BASE2 0x37 +#define RT3593_EEPROM_PWR2GHZ_BASE3 0x3e +#define RT3593_EEPROM_PWR5GHZ_BASE1 0x4b +#define RT3593_EEPROM_PWR5GHZ_BASE2 0x65 +#define RT3593_EEPROM_PWR5GHZ_BASE3 0x7f + +/* + * EEPROM IQ calibration. + */ +#define RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ 0x130 +#define RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ 0x131 +#define RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ 0x133 +#define RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ 0x134 +#define RT5390_EEPROM_RF_IQ_COMPENSATION_CTL 0x13c +#define RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL 0x13d +#define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ 0x144 +#define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ 0x145 +#define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ 0x146 +#define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ 0x147 +#define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ 0x148 +#define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ 0x149 +#define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ 0x14a +#define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ 0x14b +#define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ 0x14c +#define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ 0x14d +#define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ 0x14e +#define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ 0x14f + +#define RT2860_RIDX_CCK1 0 +#define RT2860_RIDX_CCK11 3 +#define RT2860_RIDX_OFDM6 4 +#define RT2860_RIDX_MAX 12 /* * Control and status registers access macros. @@ -968,7 +998,7 @@ static const struct rt2860_rate { /* * Default values for MAC registers; values taken from the reference driver. */ -#define RT2870_DEF_MAC \ +#define RT2870_DEF_MAC \ { RT2860_BCN_OFFSET0, 0xf8f0e8e0 }, \ { RT2860_BCN_OFFSET1, 0x6f77d0c8 }, \ { RT2860_LEGACY_BASIC_RATE, 0x0000013f }, \ @@ -1005,7 +1035,7 @@ static const struct rt2860_rate { /* * Default values for BBP registers; values taken from the reference driver. */ -#define RT2860_DEF_BBP \ +#define RT2860_DEF_BBP \ { 65, 0x2c }, \ { 66, 0x38 }, \ { 68, 0x0b }, \ @@ -1023,7 +1053,7 @@ static const struct rt2860_rate { { 105, 0x05 }, \ { 106, 0x35 } -#define RT5390_DEF_BBP \ +#define RT5390_DEF_BBP \ { 31, 0x08 }, \ { 65, 0x2c }, \ { 66, 0x38 }, \ @@ -1047,7 +1077,7 @@ static const struct rt2860_rate { { 106, 0x03 }, \ { 128, 0x12 } -#define RT5592_DEF_BBP \ +#define RT5592_DEF_BBP \ { 20, 0x06 }, \ { 31, 0x08 }, \ { 65, 0x2c }, \ @@ -1082,7 +1112,7 @@ static const struct rt2860_rate { /* * Default settings for RF registers; values derived from the reference driver. */ -#define RT2860_RF2850 \ +#define RT2860_RF2850 \ { 1, 0x98402ecc, 0x984c0786, 0x9816b455, 0x9800510b }, \ { 2, 0x98402ecc, 0x984c0786, 0x98168a55, 0x9800519f }, \ { 3, 0x98402ecc, 0x984c078a, 0x98168a55, 0x9800518b }, \ @@ -1144,7 +1174,7 @@ static const struct rt2860_rate { { 212, 0x95002ccc, 0x9500493e, 0x9509be55, 0x950c0a1b }, \ { 216, 0x95002ccc, 0x95004982, 0x9509be55, 0x950c0a23 } -#define RT3070_RF3052 \ +#define RT3070_RF3052 \ { 0xf1, 2, 2 }, \ { 0xf1, 2, 7 }, \ { 0xf2, 2, 2 }, \ @@ -1199,7 +1229,7 @@ static const struct rt2860_rate { { 0x61, 0, 7 }, \ { 0x61, 0, 9 } -#define RT5592_RF5592_20MHZ \ +#define RT5592_RF5592_20MHZ \ { 0x1e2, 4, 10, 3 }, \ { 0x1e3, 4, 10, 3 }, \ { 0x1e4, 4, 10, 3 }, \ @@ -1254,7 +1284,7 @@ static const struct rt2860_rate { { 0xa5, 8, 12, 1 }, \ { 0xa6, 0, 12, 1 } -#define RT5592_RF5592_40MHZ \ +#define RT5592_RF5592_40MHZ \ { 0xf1, 2, 10, 3 }, \ { 0xf1, 7, 10, 3 }, \ { 0xf2, 2, 10, 3 }, \ @@ -1309,7 +1339,7 @@ static const struct rt2860_rate { { 0x52, 8, 12, 1 }, \ { 0x53, 0, 12, 1 } -#define RT3070_DEF_RF \ +#define RT3070_DEF_RF \ { 4, 0x40 }, \ { 5, 0x03 }, \ { 6, 0x02 }, \ @@ -1330,7 +1360,7 @@ static const struct rt2860_rate { { 25, 0x03 }, \ { 29, 0x1f } -#define RT3572_DEF_RF \ +#define RT3572_DEF_RF \ { 0, 0x70 }, \ { 1, 0x81 }, \ { 2, 0xf1 }, \ @@ -1363,7 +1393,41 @@ static const struct rt2860_rate { { 30, 0x09 }, \ { 31, 0x10 } -#define RT5390_DEF_RF \ +#define RT3593_DEF_RF \ + { 1, 0x03 }, \ + { 3, 0x80 }, \ + { 5, 0x00 }, \ + { 6, 0x40 }, \ + { 8, 0xf1 }, \ + { 9, 0x02 }, \ + { 10, 0xd3 }, \ + { 11, 0x40 }, \ + { 12, 0x4e }, \ + { 13, 0x12 }, \ + { 18, 0x40 }, \ + { 22, 0x20 }, \ + { 30, 0x10 }, \ + { 31, 0x80 }, \ + { 32, 0x78 }, \ + { 33, 0x3b }, \ + { 34, 0x3c }, \ + { 35, 0xe0 }, \ + { 38, 0x86 }, \ + { 39, 0x23 }, \ + { 44, 0xd3 }, \ + { 45, 0xbb }, \ + { 46, 0x60 }, \ + { 49, 0x81 }, \ + { 50, 0x86 }, \ + { 51, 0x75 }, \ + { 52, 0x45 }, \ + { 53, 0x18 }, \ + { 54, 0x18 }, \ + { 55, 0x18 }, \ + { 56, 0xdb }, \ + { 57, 0x6e } + +#define RT5390_DEF_RF \ { 1, 0x0f }, \ { 2, 0x80 }, \ { 3, 0x88 }, \ @@ -1422,7 +1486,7 @@ static const struct rt2860_rate { { 62, 0x00 }, \ { 63, 0x00 } -#define RT5392_DEF_RF \ +#define RT5392_DEF_RF \ { 1, 0x17 }, \ { 3, 0x88 }, \ { 5, 0x10 }, \ @@ -1482,7 +1546,7 @@ static const struct rt2860_rate { { 62, 0x39 }, \ { 63, 0x07 } -#define RT5592_DEF_RF \ +#define RT5592_DEF_RF \ { 1, 0x3f }, \ { 3, 0x08 }, \ { 5, 0x10 }, \ @@ -1505,7 +1569,7 @@ static const struct rt2860_rate { { 53, 0x22 }, \ { 63, 0x07 } -#define RT5592_2GHZ_DEF_RF \ +#define RT5592_2GHZ_DEF_RF \ { 10, 0x90 }, \ { 11, 0x4a }, \ { 12, 0x52 }, \ @@ -1536,7 +1600,7 @@ static const struct rt2860_rate { { 61, 0x91 }, \ { 62, 0x39 } -#define RT5592_5GHZ_DEF_RF \ +#define RT5592_5GHZ_DEF_RF \ { 10, 0x97 }, \ { 11, 0x40 }, \ { 25, 0xbf }, \ @@ -1553,7 +1617,7 @@ static const struct rt2860_rate { { 60, 0x05 }, \ { 61, 0x01 } -#define RT5592_CHAN_5GHZ \ +#define RT5592_CHAN_5GHZ \ { 36, 64, 12, 0x2e }, \ { 100, 165, 12, 0x0e }, \ { 36, 64, 13, 0x22 }, \ diff --git a/sys/dev/usb/wlan/if_runvar.h b/sys/dev/usb/wlan/if_runvar.h index cc6f44c..63d9422 100644 --- a/sys/dev/usb/wlan/if_runvar.h +++ b/sys/dev/usb/wlan/if_runvar.h @@ -23,25 +23,25 @@ #ifndef _IF_RUNVAR_H_ #define _IF_RUNVAR_H_ -#define RUN_MAX_RXSZ \ +#define RUN_MAX_RXSZ \ MIN(4096, MJUMPAGESIZE) /* NB: "11" is the maximum number of padding bytes needed for Tx */ -#define RUN_MAX_TXSZ \ +#define RUN_MAX_TXSZ \ (sizeof (struct rt2870_txd) + \ sizeof (struct rt2860_txwi) + \ MCLBYTES + 11) -#define RUN_TX_TIMEOUT 5000 /* ms */ +#define RUN_TX_TIMEOUT 5000 /* ms */ /* Tx ring count was 8/endpoint, now 32 for all 4 (or 6) endpoints. */ -#define RUN_TX_RING_COUNT 32 -#define RUN_RX_RING_COUNT 1 +#define RUN_TX_RING_COUNT 32 +#define RUN_RX_RING_COUNT 1 -#define RT2870_WCID_MAX 64 -#define RUN_AID2WCID(aid) ((aid) & 0xff) +#define RT2870_WCID_MAX 64 +#define RUN_AID2WCID(aid) ((aid) & 0xff) -#define RUN_VAP_MAX 8 +#define RUN_VAP_MAX 8 struct run_rx_radiotap_header { struct ieee80211_radiotap_header wr_ihdr; @@ -54,7 +54,7 @@ struct run_rx_radiotap_header { uint8_t wr_antsignal; } __packed __aligned(8); -#define RUN_RX_RADIOTAP_PRESENT \ +#define RUN_RX_RADIOTAP_PRESENT \ (1 << IEEE80211_RADIOTAP_FLAGS | \ 1 << IEEE80211_RADIOTAP_RATE | \ 1 << IEEE80211_RADIOTAP_CHANNEL | \ @@ -73,7 +73,7 @@ struct run_tx_radiotap_header { #define IEEE80211_RADIOTAP_HWQUEUE 15 -#define RUN_TX_RADIOTAP_PRESENT \ +#define RUN_TX_RADIOTAP_PRESENT \ (1 << IEEE80211_RADIOTAP_FLAGS | \ 1 << IEEE80211_RADIOTAP_RATE | \ 1 << IEEE80211_RADIOTAP_CHANNEL | \ @@ -122,7 +122,7 @@ struct run_vap { uint8_t rvp_id; }; -#define RUN_VAP(vap) ((struct run_vap *)(vap)) +#define RUN_VAP(vap) ((struct run_vap *)(vap)) /* * There are 7 bulk endpoints: 1 for RX @@ -183,6 +183,7 @@ struct run_softc { uint8_t txmixgain_5ghz; int8_t txpow1[54]; int8_t txpow2[54]; + int8_t txpow3[54]; int8_t rssi_2ghz[3]; int8_t rssi_5ghz[3]; uint8_t lna[4]; @@ -206,19 +207,19 @@ struct run_softc { struct task ratectl_task; struct usb_callout ratectl_ch; uint8_t ratectl_run; -#define RUN_RATECTL_OFF 0 +#define RUN_RATECTL_OFF 0 /* need to be power of 2, otherwise RUN_CMDQ_GET fails */ -#define RUN_CMDQ_MAX 16 -#define RUN_CMDQ_MASQ (RUN_CMDQ_MAX - 1) +#define RUN_CMDQ_MAX 16 +#define RUN_CMDQ_MASQ (RUN_CMDQ_MAX - 1) struct run_cmdq cmdq[RUN_CMDQ_MAX]; struct task cmdq_task; uint32_t cmdq_store; uint8_t cmdq_exec; uint8_t cmdq_run; uint8_t cmdq_key_set; -#define RUN_CMDQ_ABORT 0 -#define RUN_CMDQ_GO 1 +#define RUN_CMDQ_ABORT 0 +#define RUN_CMDQ_GO 1 struct usb_xfer *sc_xfer[RUN_N_XFER]; @@ -250,8 +251,8 @@ struct run_softc { int sc_txtap_len; }; -#define RUN_LOCK(sc) mtx_lock(&(sc)->sc_mtx) -#define RUN_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) -#define RUN_LOCK_ASSERT(sc, t) mtx_assert(&(sc)->sc_mtx, t) +#define RUN_LOCK(sc) mtx_lock(&(sc)->sc_mtx) +#define RUN_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) +#define RUN_LOCK_ASSERT(sc, t) mtx_assert(&(sc)->sc_mtx, t) #endif /* _IF_RUNVAR_H_ */ -- cgit v1.1