From b87dbd50a9466acbbb5b8c14050293d0d0ac4a04 Mon Sep 17 00:00:00 2001 From: groudier Date: Sun, 3 Sep 2000 12:36:21 +0000 Subject: PR: kern/20895 PR kern/20895: - Add FE_DAC new feature flag to distinguish between 64 bit PCI addressing (DAC cycles) and 64 bit PCI interface (64 bit Memory BARs). - Properly deal with chips that have a 32 bit PCI interface but support and may generate DAC. (Only SYM53C895A for now). PR misc/17584 (at least partially addressed): - Try detecting hardware combinations that trigger spurious PCI master parity error detections by the PCI chip. This work-around is implemented in the `snooptest' routine and consists in retrying with PCI master parity checking disabled if such an error is reported by the PCI chip during this test. Other: - Fix a tiny bug in WIDE negotiation that was very unlikely to be triggerred. The BUS width was wrongly compared against chip's max. offset. --- sys/dev/sym/sym_defs.h | 5 ++-- sys/dev/sym/sym_hipd.c | 67 ++++++++++++++++++++++++++++++++------------------ 2 files changed, 46 insertions(+), 26 deletions(-) (limited to 'sys/dev/sym') diff --git a/sys/dev/sym/sym_defs.h b/sys/dev/sym/sym_defs.h index d07aa94..d101277 100644 --- a/sys/dev/sym/sym_defs.h +++ b/sys/dev/sym/sym_defs.h @@ -113,18 +113,19 @@ struct sym_pci_chip { #define FE_RAM (1<<14) /* On chip RAM present */ #define FE_CLK80 (1<<15) /* Board clock is 80 MHz */ #define FE_RAM8K (1<<16) /* On chip RAM sized 8Kb */ -#define FE_64BIT (1<<17) /* Supports 64-bit addressing */ +#define FE_64BIT (1<<17) /* 64-bit PCI BUS interface */ #define FE_IO256 (1<<18) /* Requires full 256 bytes in PCI space */ #define FE_NOPM (1<<19) /* Scripts handles phase mismatch */ #define FE_LEDC (1<<20) /* Hardware control of LED */ #define FE_ULTRA3 (1<<21) /* Ultra 3 - 80 Mtrans/sec DT */ -#define FE_PCI66 (1<<22) /* 66MHz PCI support */ +#define FE_66MHZ (1<<22) /* 66MHz PCI support */ #define FE_CRC (1<<23) /* CRC support */ #define FE_DIFF (1<<24) /* SCSI HVD support */ #define FE_DFBC (1<<25) /* Have DFBC register */ #define FE_LCKFRQ (1<<26) /* Have LCKFRQ */ #define FE_C10 (1<<27) /* Various C10 core (mis)features */ #define FE_U3EN (1<<28) /* U3EN bit usable */ +#define FE_DAC (1<<29) /* Support PCI DAC (64 bit addressing) */ #define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP) #define FE_CACHE0_SET (FE_CACHE_SET & ~FE_ERL) diff --git a/sys/dev/sym/sym_hipd.c b/sys/dev/sym/sym_hipd.c index d5d7cd8..534b890 100644 --- a/sys/dev/sym/sym_hipd.c +++ b/sys/dev/sym/sym_hipd.c @@ -57,7 +57,7 @@ /* $FreeBSD$ */ -#define SYM_DRIVER_NAME "sym-1.6.4-20000701" +#define SYM_DRIVER_NAME "sym-1.6.5-20000902" /* #define SYM_DEBUG_GENERIC_SUPPORT */ @@ -2211,7 +2211,7 @@ sym_find_firmware(struct sym_pci_chip *chip) if (chip->features & FE_LDSTR) return &sym_fw2; #ifdef SYM_CONF_GENERIC_SUPPORT - else if (!(chip->features & (FE_PFEN|FE_NOPM|FE_64BIT))) + else if (!(chip->features & (FE_PFEN|FE_NOPM|FE_DAC))) return &sym_fw1; #endif else @@ -2787,9 +2787,9 @@ static int sym_prepare_setting(hcb_p np, struct sym_nvram *nvram) } /* - * 64 bit (53C895A or 53C896) ? + * 64 bit addressing (895A/896/1010) ? */ - if (np->features & FE_64BIT) + if (np->features & FE_DAC) #if BITS_PER_LONG > 32 np->rv_ccntl1 |= (XTIMOD | EXTIBMV); #else @@ -3438,12 +3438,11 @@ static void sym_init (hcb_p np, int reason) np->rv_ccntl0 |= DPR; /* - * If 64 bit (895A/896/1010) write CCNTL1 to enable 40 bit - * address table indirect addressing for MOVE. - * Also write CCNTL0 if 64 bit chip, since this register seems - * to only be used by 64 bit cores. + * Write CCNTL0/CCNTL1 for chips capable of 64 bit addressing + * and/or hardware phase mismatch, since only such chips + * seem to support those IO registers. */ - if (np->features & FE_64BIT) { + if (np->features & (FE_DAC|FE_NOPM)) { OUTB (nc_ccntl0, np->rv_ccntl0); OUTB (nc_ccntl1, np->rv_ccntl1); } @@ -6047,8 +6046,8 @@ static void sym_wide_nego(hcb_p np, tcb_p tp, ccb_p cp) /* * check values against driver limits. */ - if (wide > np->maxoffs) - {chg = 1; wide = np->maxoffs;} + if (wide > np->maxwide) + {chg = 1; wide = np->maxwide;} if (req) { if (wide > tp->tinfo.user.width) {chg = 1; wide = tp->tinfo.user.width;} @@ -6913,12 +6912,18 @@ static int sym_regtest (hcb_p np) static int sym_snooptest (hcb_p np) { - u32 sym_rd, sym_wr, sym_bk, host_rd, host_wr, pc; + u32 sym_rd, sym_wr, sym_bk, host_rd, host_wr, pc, dstat; int i, err=0; #ifndef SYM_CONF_IOMAPPED err |= sym_regtest (np); if (err) return (err); #endif +restart_test: + /* + * Enable Master Parity Checking as we intend + * to enable it for normal operations. + */ + OUTB (nc_ctest4, (np->rv_ctest4 & MPEE)); /* * init */ @@ -6941,6 +6946,27 @@ static int sym_snooptest (hcb_p np) for (i=0; i=SYM_SNOOP_TIMEOUT) { + printf ("CACHE TEST FAILED: timeout.\n"); + return (0x20); + }; + /* + * Check for fatal DMA errors. + */ + dstat = INB (nc_dstat); +#if 1 /* Band aiding for broken hardwares that fail PCI parity */ + if ((dstat & MDPE) && (np->rv_ctest4 & MPEE)) { + printf ("%s: PCI DATA PARITY ERROR DETECTED - " + "DISABLING MASTER DATA PARITY CHECKING.\n", + sym_name(np)); + np->rv_ctest4 &= ~MPEE; + goto restart_test; + } +#endif + if (dstat & (MDPE|BF|IID)) { + printf ("CACHE TEST FAILED: DMA error (dstat=0x%02x).", dstat); + return (0x80); + } /* * Save termination position. */ @@ -6953,13 +6979,6 @@ static int sym_snooptest (hcb_p np) sym_bk = INL (nc_temp); /* - * check for timeout - */ - if (i>=SYM_SNOOP_TIMEOUT) { - printf ("CACHE TEST FAILED: timeout.\n"); - return (0x20); - }; - /* * Check termination position. */ if (pc != SCRIPTB0_BA (np, snoopend)+8) { @@ -8717,25 +8736,25 @@ static struct sym_pci_chip sym_pci_dev_table[] = { #endif {PCI_ID_SYM53C896, 0xff, "896", 6, 31, 7, 4, FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| - FE_RAM|FE_RAM8K|FE_64BIT|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ} + FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ} , {PCI_ID_SYM53C895A, 0xff, "895a", 6, 31, 7, 4, FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| - FE_RAM|FE_RAM8K|FE_64BIT|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ} + FE_RAM|FE_RAM8K|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ} , {PCI_ID_LSI53C1010, 0x00, "1010-33", 6, 31, 7, 8, FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN| - FE_RAM|FE_RAM8K|FE_64BIT|FE_IO256|FE_NOPM|FE_LEDC|FE_PCI66|FE_CRC| + FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC| FE_C10} , {PCI_ID_LSI53C1010, 0xff, "1010-33", 6, 31, 7, 8, FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN| - FE_RAM|FE_RAM8K|FE_64BIT|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC| + FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC| FE_C10|FE_U3EN} , {PCI_ID_LSI53C1010_2, 0xff, "1010-66", 6, 31, 7, 8, FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN| - FE_RAM|FE_RAM8K|FE_64BIT|FE_IO256|FE_NOPM|FE_LEDC|FE_PCI66|FE_CRC| + FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_66MHZ|FE_CRC| FE_C10|FE_U3EN} , {PCI_ID_LSI53C1510D, 0xff, "1510d", 6, 31, 7, 4, -- cgit v1.1