From 6698e7dea2102dc38ec391c1e3a13cdf853699af Mon Sep 17 00:00:00 2001 From: sam Date: Fri, 29 Jun 2007 22:47:18 +0000 Subject: Neterion Xframe 10GbE Server/Storage adapter driver. The nxge driver provides support for Neterion Xframe-I and Xframe-II adapters. The driver supports TCP Segmentation Offload (TSO/LSO), Jumbo frames (5 buffer mode), Header separation (2 and 3 Receive buffer modes), VLAN, and Promiscuous mode. Submitted by: Neterion Reviewed by: rwatson Approved by: re (kensmith) --- sys/dev/nxge/xgehal/xge-queue.c | 460 ++ sys/dev/nxge/xgehal/xgehal-channel-fp.c | 299 ++ sys/dev/nxge/xgehal/xgehal-channel.c | 759 ++++ sys/dev/nxge/xgehal/xgehal-config.c | 761 ++++ sys/dev/nxge/xgehal/xgehal-device-fp.c | 1432 ++++++ sys/dev/nxge/xgehal/xgehal-device.c | 7247 +++++++++++++++++++++++++++++++ sys/dev/nxge/xgehal/xgehal-driver.c | 300 ++ sys/dev/nxge/xgehal/xgehal-fifo-fp.c | 1175 +++++ sys/dev/nxge/xgehal/xgehal-fifo.c | 568 +++ sys/dev/nxge/xgehal/xgehal-mgmt.c | 1772 ++++++++ sys/dev/nxge/xgehal/xgehal-mgmtaux.c | 1731 ++++++++ sys/dev/nxge/xgehal/xgehal-mm.c | 436 ++ sys/dev/nxge/xgehal/xgehal-ring-fp.c | 852 ++++ sys/dev/nxge/xgehal/xgehal-ring.c | 669 +++ sys/dev/nxge/xgehal/xgehal-stats.c | 1019 +++++ 15 files changed, 19480 insertions(+) create mode 100644 sys/dev/nxge/xgehal/xge-queue.c create mode 100644 sys/dev/nxge/xgehal/xgehal-channel-fp.c create mode 100644 sys/dev/nxge/xgehal/xgehal-channel.c create mode 100644 sys/dev/nxge/xgehal/xgehal-config.c create mode 100644 sys/dev/nxge/xgehal/xgehal-device-fp.c create mode 100644 sys/dev/nxge/xgehal/xgehal-device.c create mode 100644 sys/dev/nxge/xgehal/xgehal-driver.c create mode 100644 sys/dev/nxge/xgehal/xgehal-fifo-fp.c create mode 100644 sys/dev/nxge/xgehal/xgehal-fifo.c create mode 100644 sys/dev/nxge/xgehal/xgehal-mgmt.c create mode 100644 sys/dev/nxge/xgehal/xgehal-mgmtaux.c create mode 100644 sys/dev/nxge/xgehal/xgehal-mm.c create mode 100644 sys/dev/nxge/xgehal/xgehal-ring-fp.c create mode 100644 sys/dev/nxge/xgehal/xgehal-ring.c create mode 100644 sys/dev/nxge/xgehal/xgehal-stats.c (limited to 'sys/dev/nxge/xgehal') diff --git a/sys/dev/nxge/xgehal/xge-queue.c b/sys/dev/nxge/xgehal/xge-queue.c new file mode 100644 index 0000000..925f44f --- /dev/null +++ b/sys/dev/nxge/xgehal/xge-queue.c @@ -0,0 +1,460 @@ +/*- + * Copyright (c) 2002-2007 Neterion, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * FileName : xge-queue.c + * + * Description: serialized event queue + * + * Created: 7 June 2004 + */ + +#include + +/** + * xge_queue_item_data - Get item's data. + * @item: Queue item. + * + * Returns: item data(variable size). Note that xge_queue_t + * contains items comprized of a fixed xge_queue_item_t "header" + * and a variable size data. This function returns the variable + * user-defined portion of the queue item. + */ +void* xge_queue_item_data(xge_queue_item_t *item) +{ + return (char *)item + sizeof(xge_queue_item_t); +} + +/* + * __queue_consume - (Lockless) dequeue an item from the specified queue. + * + * @queue: Event queue. + * See xge_queue_consume(). + */ +static xge_queue_status_e +__queue_consume(xge_queue_t *queue, int data_max_size, xge_queue_item_t *item) +{ + int real_size; + xge_queue_item_t *elem; + + if (xge_list_is_empty(&queue->list_head)) + return XGE_QUEUE_IS_EMPTY; + + elem = (xge_queue_item_t *)queue->list_head.next; + if (elem->data_size > data_max_size) + return XGE_QUEUE_NOT_ENOUGH_SPACE; + + xge_list_remove(&elem->item); + real_size = elem->data_size + sizeof(xge_queue_item_t); + if (queue->head_ptr == elem) { + queue->head_ptr = (char *)queue->head_ptr + real_size; + xge_debug_queue(XGE_TRACE, + "event_type: %d removing from the head: " + "0x"XGE_OS_LLXFMT":0x"XGE_OS_LLXFMT":0x"XGE_OS_LLXFMT + ":0x"XGE_OS_LLXFMT" elem 0x"XGE_OS_LLXFMT" length %d", + elem->event_type, + (u64)(ulong_t)queue->start_ptr, + (u64)(ulong_t)queue->head_ptr, + (u64)(ulong_t)queue->tail_ptr, + (u64)(ulong_t)queue->end_ptr, + (u64)(ulong_t)elem, + real_size); + } else if ((char *)queue->tail_ptr - real_size == (char*)elem) { + queue->tail_ptr = (char *)queue->tail_ptr - real_size; + xge_debug_queue(XGE_TRACE, + "event_type: %d removing from the tail: " + "0x"XGE_OS_LLXFMT":0x"XGE_OS_LLXFMT":0x"XGE_OS_LLXFMT + ":0x"XGE_OS_LLXFMT" elem 0x"XGE_OS_LLXFMT" length %d", + elem->event_type, + (u64)(ulong_t)queue->start_ptr, + (u64)(ulong_t)queue->head_ptr, + (u64)(ulong_t)queue->tail_ptr, + (u64)(ulong_t)queue->end_ptr, + (u64)(ulong_t)elem, + real_size); + } else { + xge_debug_queue(XGE_TRACE, + "event_type: %d removing from the list: " + "0x"XGE_OS_LLXFMT":0x"XGE_OS_LLXFMT":0x"XGE_OS_LLXFMT + ":0x"XGE_OS_LLXFMT" elem 0x"XGE_OS_LLXFMT" length %d", + elem->event_type, + (u64)(ulong_t)queue->start_ptr, + (u64)(ulong_t)queue->head_ptr, + (u64)(ulong_t)queue->tail_ptr, + (u64)(ulong_t)queue->end_ptr, + (u64)(ulong_t)elem, + real_size); + } + xge_assert(queue->tail_ptr >= queue->head_ptr); + xge_assert(queue->tail_ptr >= queue->start_ptr && + queue->tail_ptr <= queue->end_ptr); + xge_assert(queue->head_ptr >= queue->start_ptr && + queue->head_ptr < queue->end_ptr); + xge_os_memcpy(item, elem, sizeof(xge_queue_item_t)); + xge_os_memcpy(xge_queue_item_data(item), xge_queue_item_data(elem), + elem->data_size); + + if (xge_list_is_empty(&queue->list_head)) { + /* reset buffer pointers just to be clean */ + queue->head_ptr = queue->tail_ptr = queue->start_ptr; + } + return XGE_QUEUE_OK; +} + +/** + * xge_queue_produce - Enqueue an item (see xge_queue_item_t{}) + * into the specified queue. + * @queueh: Queue handle. + * @event_type: Event type. One of the enumerated event types + * that both consumer and producer "understand". + * For an example, please refer to xge_hal_event_e. + * @context: Opaque (void*) "context", for instance event producer object. + * @is_critical: For critical event, e.g. ECC. + * @data_size: Size of the @data. + * @data: User data of variable @data_size that is _copied_ into + * the new queue item (see xge_queue_item_t{}). Upon return + * from the call the @data memory can be re-used or released. + * + * Enqueue a new item. + * + * Returns: XGE_QUEUE_OK - success. + * XGE_QUEUE_IS_FULL - Queue is full. + * XGE_QUEUE_OUT_OF_MEMORY - Memory allocation failed. + * + * See also: xge_queue_item_t{}, xge_queue_consume(). + */ +xge_queue_status_e +xge_queue_produce(xge_queue_h queueh, int event_type, void *context, + int is_critical, const int data_size, void *data) +{ + xge_queue_t *queue = (xge_queue_t *)queueh; + int real_size = data_size + sizeof(xge_queue_item_t); + xge_queue_item_t *elem; + unsigned long flags = 0; + + xge_assert(real_size <= XGE_QUEUE_BUF_SIZE); + + xge_os_spin_lock_irq(&queue->lock, flags); + + if (is_critical && !queue->has_critical_event) { + unsigned char item_buf[sizeof(xge_queue_item_t) + + XGE_DEFAULT_EVENT_MAX_DATA_SIZE]; + xge_queue_item_t *item = (xge_queue_item_t *)(void *)item_buf; + xge_os_memzero(item_buf, (sizeof(xge_queue_item_t) + + XGE_DEFAULT_EVENT_MAX_DATA_SIZE)); + + while (__queue_consume(queue, + XGE_DEFAULT_EVENT_MAX_DATA_SIZE, + item) != XGE_QUEUE_IS_EMPTY) + ; /* do nothing */ + } + +try_again: + if ((char *)queue->tail_ptr + real_size <= (char *)queue->end_ptr) { + elem = (xge_queue_item_t *) queue->tail_ptr; + queue->tail_ptr = (void *)((char *)queue->tail_ptr + real_size); + xge_debug_queue(XGE_TRACE, + "event_type: %d adding to the tail: " + "0x"XGE_OS_LLXFMT":0x"XGE_OS_LLXFMT":0x"XGE_OS_LLXFMT + ":0x"XGE_OS_LLXFMT" elem 0x"XGE_OS_LLXFMT" length %d", + event_type, + (u64)(ulong_t)queue->start_ptr, + (u64)(ulong_t)queue->head_ptr, + (u64)(ulong_t)queue->tail_ptr, + (u64)(ulong_t)queue->end_ptr, + (u64)(ulong_t)elem, + real_size); + } else if ((char *)queue->head_ptr - real_size >= + (char *)queue->start_ptr) { + elem = (xge_queue_item_t *) ((char *)queue->head_ptr - real_size); + queue->head_ptr = elem; + xge_debug_queue(XGE_TRACE, + "event_type: %d adding to the head: " + "0x"XGE_OS_LLXFMT":0x"XGE_OS_LLXFMT":0x"XGE_OS_LLXFMT + ":0x"XGE_OS_LLXFMT" length %d", + event_type, + (u64)(ulong_t)queue->start_ptr, + (u64)(ulong_t)queue->head_ptr, + (u64)(ulong_t)queue->tail_ptr, + (u64)(ulong_t)queue->end_ptr, + real_size); + } else { + xge_queue_status_e status; + + if (queue->pages_current >= queue->pages_max) { + xge_os_spin_unlock_irq(&queue->lock, flags); + return XGE_QUEUE_IS_FULL; + } + + if (queue->has_critical_event) { + xge_os_spin_unlock_irq(&queue->lock, flags); + return XGE_QUEUE_IS_FULL; + } + + /* grow */ + status = __io_queue_grow(queueh); + if (status != XGE_QUEUE_OK) { + xge_os_spin_unlock_irq(&queue->lock, flags); + return status; + } + + goto try_again; + } + xge_assert(queue->tail_ptr >= queue->head_ptr); + xge_assert(queue->tail_ptr >= queue->start_ptr && + queue->tail_ptr <= queue->end_ptr); + xge_assert(queue->head_ptr >= queue->start_ptr && + queue->head_ptr < queue->end_ptr); + elem->data_size = data_size; + elem->event_type = (xge_hal_event_e) event_type; + elem->is_critical = is_critical; + if (is_critical) + queue->has_critical_event = 1; + elem->context = context; + xge_os_memcpy(xge_queue_item_data(elem), data, data_size); + xge_list_insert_before(&elem->item, &queue->list_head); + xge_os_spin_unlock_irq(&queue->lock, flags); + + /* no lock taken! */ + queue->queued_func(queue->queued_data, event_type); + + return XGE_QUEUE_OK; +} + + +/** + * xge_queue_create - Create protected first-in-first-out queue. + * @pdev: PCI device handle. + * @irqh: PCI device IRQ handle. + * @pages_initial: Number of pages to be initially allocated at the + * time of queue creation. + * @pages_max: Max number of pages that can be allocated in the queue. + * @queued: Optional callback function to be called each time a new item is + * added to the queue. + * @queued_data: Argument to the callback function. + * + * Create protected (fifo) queue. + * + * Returns: Pointer to xge_queue_t structure, + * NULL - on failure. + * + * See also: xge_queue_item_t{}, xge_queue_destroy(). + */ +xge_queue_h +xge_queue_create(pci_dev_h pdev, pci_irq_h irqh, int pages_initial, + int pages_max, xge_queued_f queued, void *queued_data) +{ + xge_queue_t *queue; + + if ((queue = (xge_queue_t *) xge_os_malloc(pdev, sizeof(xge_queue_t))) == NULL) + return NULL; + + queue->queued_func = queued; + queue->queued_data = queued_data; + queue->pdev = pdev; + queue->irqh = irqh; + queue->pages_current = pages_initial; + queue->start_ptr = xge_os_malloc(pdev, queue->pages_current * + XGE_QUEUE_BUF_SIZE); + if (queue->start_ptr == NULL) { + xge_os_free(pdev, queue, sizeof(xge_queue_t)); + return NULL; + } + queue->head_ptr = queue->tail_ptr = queue->start_ptr; + queue->end_ptr = (char *)queue->start_ptr + + queue->pages_current * XGE_QUEUE_BUF_SIZE; + xge_os_spin_lock_init_irq(&queue->lock, irqh); + queue->pages_initial = pages_initial; + queue->pages_max = pages_max; + xge_list_init(&queue->list_head); + + return queue; +} + +/** + * xge_queue_destroy - Destroy xge_queue_t object. + * @queueh: Queue handle. + * + * Destroy the specified xge_queue_t object. + * + * See also: xge_queue_item_t{}, xge_queue_create(). + */ +void xge_queue_destroy(xge_queue_h queueh) +{ + xge_queue_t *queue = (xge_queue_t *)queueh; + xge_os_spin_lock_destroy_irq(&queue->lock, queue->irqh); + if (!xge_list_is_empty(&queue->list_head)) { + xge_debug_queue(XGE_ERR, "destroying non-empty queue 0x" + XGE_OS_LLXFMT, (u64)(ulong_t)queue); + } + xge_os_free(queue->pdev, queue->start_ptr, queue->pages_current * + XGE_QUEUE_BUF_SIZE); + + xge_os_free(queue->pdev, queue, sizeof(xge_queue_t)); +} + +/* + * __io_queue_grow - Dynamically increases the size of the queue. + * @queueh: Queue handle. + * + * This function is called in the case of no slot avaialble in the queue + * to accomodate the newly received event. + * Note that queue cannot grow beyond the max size specified for the + * queue. + * + * Returns XGE_QUEUE_OK: On success. + * XGE_QUEUE_OUT_OF_MEMORY : No memory is available. + */ +xge_queue_status_e +__io_queue_grow(xge_queue_h queueh) +{ + xge_queue_t *queue = (xge_queue_t *)queueh; + void *newbuf, *oldbuf; + xge_list_t *item; + xge_queue_item_t *elem; + + xge_debug_queue(XGE_TRACE, "queue 0x"XGE_OS_LLXFMT":%d is growing", + (u64)(ulong_t)queue, queue->pages_current); + + newbuf = xge_os_malloc(queue->pdev, + (queue->pages_current + 1) * XGE_QUEUE_BUF_SIZE); + if (newbuf == NULL) + return XGE_QUEUE_OUT_OF_MEMORY; + + xge_os_memcpy(newbuf, queue->start_ptr, + queue->pages_current * XGE_QUEUE_BUF_SIZE); + oldbuf = queue->start_ptr; + + /* adjust queue sizes */ + queue->start_ptr = newbuf; + queue->end_ptr = (char *)newbuf + + (queue->pages_current + 1) * XGE_QUEUE_BUF_SIZE; + queue->tail_ptr = (char *)newbuf + ((char *)queue->tail_ptr - + (char *)oldbuf); + queue->head_ptr = (char *)newbuf + ((char *)queue->head_ptr - + (char *)oldbuf); + xge_assert(!xge_list_is_empty(&queue->list_head)); + queue->list_head.next = (xge_list_t *) (void *)((char *)newbuf + + ((char *)queue->list_head.next - (char *)oldbuf)); + queue->list_head.prev = (xge_list_t *) (void *)((char *)newbuf + + ((char *)queue->list_head.prev - (char *)oldbuf)); + /* adjust queue list */ + xge_list_for_each(item, &queue->list_head) { + elem = xge_container_of(item, xge_queue_item_t, item); + if (elem->item.next != &queue->list_head) { + elem->item.next = + (xge_list_t*)(void *)((char *)newbuf + + ((char *)elem->item.next - (char *)oldbuf)); + } + if (elem->item.prev != &queue->list_head) { + elem->item.prev = + (xge_list_t*) (void *)((char *)newbuf + + ((char *)elem->item.prev - (char *)oldbuf)); + } + } + xge_os_free(queue->pdev, oldbuf, + queue->pages_current * XGE_QUEUE_BUF_SIZE); + queue->pages_current++; + + return XGE_QUEUE_OK; +} + +/** + * xge_queue_consume - Dequeue an item from the specified queue. + * @queueh: Queue handle. + * @data_max_size: Maximum expected size of the item. + * @item: Memory area into which the item is _copied_ upon return + * from the function. + * + * Dequeue an item from the queue. The caller is required to provide + * enough space for the item. + * + * Returns: XGE_QUEUE_OK - success. + * XGE_QUEUE_IS_EMPTY - Queue is empty. + * XGE_QUEUE_NOT_ENOUGH_SPACE - Requested item size(@data_max_size) + * is too small to accomodate an item from the queue. + * + * See also: xge_queue_item_t{}, xge_queue_produce(). + */ +xge_queue_status_e +xge_queue_consume(xge_queue_h queueh, int data_max_size, xge_queue_item_t *item) +{ + xge_queue_t *queue = (xge_queue_t *)queueh; + unsigned long flags = 0; + xge_queue_status_e status; + + xge_os_spin_lock_irq(&queue->lock, flags); + status = __queue_consume(queue, data_max_size, item); + xge_os_spin_unlock_irq(&queue->lock, flags); + + return status; +} + + +/** + * xge_queue_flush - Flush, or empty, the queue. + * @queueh: Queue handle. + * + * Flush the queue, i.e. make it empty by consuming all events + * without invoking the event processing logic (callbacks, etc.) + */ +void xge_queue_flush(xge_queue_h queueh) +{ + unsigned char item_buf[sizeof(xge_queue_item_t) + + XGE_DEFAULT_EVENT_MAX_DATA_SIZE]; + xge_queue_item_t *item = (xge_queue_item_t *)(void *)item_buf; + xge_os_memzero(item_buf, (sizeof(xge_queue_item_t) + + XGE_DEFAULT_EVENT_MAX_DATA_SIZE)); + + /* flush queue by consuming all enqueued items */ + while (xge_queue_consume(queueh, + XGE_DEFAULT_EVENT_MAX_DATA_SIZE, + item) != XGE_QUEUE_IS_EMPTY) { + /* do nothing */ + xge_debug_queue(XGE_TRACE, "item "XGE_OS_LLXFMT"(%d) flushed", + item, item->event_type); + } + (void) __queue_get_reset_critical (queueh); +} + +/* + * __queue_get_reset_critical - Check for critical events in the queue, + * @qh: Queue handle. + * + * Check for critical event(s) in the queue, and reset the + * "has-critical-event" flag upon return. + * Returns: 1 - if the queue contains atleast one critical event. + * 0 - If there are no critical events in the queue. + */ +int __queue_get_reset_critical (xge_queue_h qh) { + xge_queue_t* queue = (xge_queue_t*)qh; + int c = queue->has_critical_event; + + queue->has_critical_event = 0; + return c; +} diff --git a/sys/dev/nxge/xgehal/xgehal-channel-fp.c b/sys/dev/nxge/xgehal/xgehal-channel-fp.c new file mode 100644 index 0000000..0417ca0 --- /dev/null +++ b/sys/dev/nxge/xgehal/xgehal-channel-fp.c @@ -0,0 +1,299 @@ +/*- + * Copyright (c) 2002-2007 Neterion, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * FileName : xgehal-channel-fp.c + * + * Description: HAL channel object functionality (fast path) + * + * Created: 10 June 2004 + */ + +#ifdef XGE_DEBUG_FP +#include +#endif + +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e +__hal_channel_dtr_alloc(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh) +{ + void **tmp_arr; + xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; +#if defined(XGE_HAL_RX_MULTI_FREE_IRQ) || defined(XGE_HAL_TX_MULTI_FREE_IRQ) + unsigned long flags = 0; +#endif + + if (channel->reserve_length - channel->reserve_top > + channel->reserve_threshold) { + +_alloc_after_swap: + *dtrh = channel->reserve_arr[--channel->reserve_length]; + + xge_debug_channel(XGE_TRACE, "dtrh 0x"XGE_OS_LLXFMT" allocated, " + "channel %d:%d:%d, reserve_idx %d", + (unsigned long long)(ulong_t)*dtrh, + channel->type, channel->post_qid, + channel->compl_qid, channel->reserve_length); + + return XGE_HAL_OK; + } + +#if defined(XGE_HAL_RX_MULTI_FREE_IRQ) || defined(XGE_HAL_TX_MULTI_FREE_IRQ) + xge_os_spin_lock_irq(&channel->free_lock, flags); +#elif defined(XGE_HAL_RX_MULTI_FREE) || defined(XGE_HAL_TX_MULTI_FREE) + xge_os_spin_lock(&channel->free_lock); +#endif + + /* switch between empty and full arrays */ + + /* the idea behind such a design is that by having free and reserved + * arrays separated we basically separated irq and non-irq parts. + * i.e. no additional lock need to be done when we free a resource */ + + if (channel->reserve_initial - channel->free_length > + channel->reserve_threshold) { + + tmp_arr = channel->reserve_arr; + channel->reserve_arr = channel->free_arr; + channel->reserve_length = channel->reserve_initial; + channel->free_arr = tmp_arr; + channel->reserve_top = channel->free_length; + channel->free_length = channel->reserve_initial; + + channel->stats.reserve_free_swaps_cnt++; + + xge_debug_channel(XGE_TRACE, + "switch on channel %d:%d:%d, reserve_length %d, " + "free_length %d", channel->type, channel->post_qid, + channel->compl_qid, channel->reserve_length, + channel->free_length); + +#if defined(XGE_HAL_RX_MULTI_FREE_IRQ) || defined(XGE_HAL_TX_MULTI_FREE_IRQ) + xge_os_spin_unlock_irq(&channel->free_lock, flags); +#elif defined(XGE_HAL_RX_MULTI_FREE) || defined(XGE_HAL_TX_MULTI_FREE) + xge_os_spin_unlock(&channel->free_lock); +#endif + + goto _alloc_after_swap; + } + +#if defined(XGE_HAL_RX_MULTI_FREE_IRQ) || defined(XGE_HAL_TX_MULTI_FREE_IRQ) + xge_os_spin_unlock_irq(&channel->free_lock, flags); +#elif defined(XGE_HAL_RX_MULTI_FREE) || defined(XGE_HAL_TX_MULTI_FREE) + xge_os_spin_unlock(&channel->free_lock); +#endif + + xge_debug_channel(XGE_TRACE, "channel %d:%d:%d is empty!", + channel->type, channel->post_qid, + channel->compl_qid); + + channel->stats.full_cnt++; + + *dtrh = NULL; + return XGE_HAL_INF_OUT_OF_DESCRIPTORS; +} + +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void +__hal_channel_dtr_restore(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, + int offset) +{ + xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; + + /* restore a previously allocated dtrh at current offset and update + * the available reserve length accordingly. If dtrh is null just + * update the reserve length, only */ + + if (dtrh) { + channel->reserve_arr[channel->reserve_length + offset] = dtrh; + xge_debug_channel(XGE_TRACE, "dtrh 0x"XGE_OS_LLXFMT" restored for " + "channel %d:%d:%d, offset %d at reserve index %d, ", + (unsigned long long)(ulong_t)dtrh, channel->type, + channel->post_qid, channel->compl_qid, offset, + channel->reserve_length + offset); + } + else { + channel->reserve_length += offset; + xge_debug_channel(XGE_TRACE, "channel %d:%d:%d, restored " + "for offset %d, new reserve_length %d, free length %d", + channel->type, channel->post_qid, channel->compl_qid, + offset, channel->reserve_length, channel->free_length); + } +} + +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void +__hal_channel_dtr_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh) +{ + xge_hal_channel_t *channel = (xge_hal_channel_t*)channelh; + + xge_assert(channel->work_arr[channel->post_index] == NULL); + + channel->work_arr[channel->post_index++] = dtrh; + + /* wrap-around */ + if (channel->post_index == channel->length) + channel->post_index = 0; +} + +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void +__hal_channel_dtr_try_complete(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh) +{ + xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; + + xge_assert(channel->work_arr); + xge_assert(channel->compl_index < channel->length); + + *dtrh = channel->work_arr[channel->compl_index]; +} + +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void +__hal_channel_dtr_complete(xge_hal_channel_h channelh) +{ + xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; + + channel->work_arr[channel->compl_index] = NULL; + + /* wrap-around */ + if (++channel->compl_index == channel->length) + channel->compl_index = 0; + + channel->stats.total_compl_cnt++; +} + +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void +__hal_channel_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh) +{ + xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; + + channel->free_arr[--channel->free_length] = dtrh; + + xge_debug_channel(XGE_TRACE, "dtrh 0x"XGE_OS_LLXFMT" freed, " + "channel %d:%d:%d, new free_length %d", + (unsigned long long)(ulong_t)dtrh, + channel->type, channel->post_qid, + channel->compl_qid, channel->free_length); +} + +/** + * xge_hal_channel_dtr_count + * @channelh: Channel handle. Obtained via xge_hal_channel_open(). + * + * Retreive number of DTRs available. This function can not be called + * from data path. + */ +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int +xge_hal_channel_dtr_count(xge_hal_channel_h channelh) +{ + xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; + + return ((channel->reserve_length - channel->reserve_top) + + (channel->reserve_initial - channel->free_length) - + channel->reserve_threshold); +} + +/** + * xge_hal_channel_userdata - Get user-specified channel context. + * @channelh: Channel handle. Obtained via xge_hal_channel_open(). + * + * Returns: per-channel "user data", which can be any ULD-defined context. + * The %userdata "gets" into the channel at open time + * (see xge_hal_channel_open()). + * + * See also: xge_hal_channel_open(). + */ +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void* +xge_hal_channel_userdata(xge_hal_channel_h channelh) +{ + xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; + + return channel->userdata; +} + +/** + * xge_hal_channel_id - Get channel ID. + * @channelh: Channel handle. Obtained via xge_hal_channel_open(). + * + * Returns: channel ID. For link layer channel id is the number + * in the range from 0 to 7 that identifies hardware ring or fifo, + * depending on the channel type. + */ +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int +xge_hal_channel_id(xge_hal_channel_h channelh) +{ + xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; + + return channel->post_qid; +} + +/** + * xge_hal_check_alignment - Check buffer alignment and calculate the + * "misaligned" portion. + * @dma_pointer: DMA address of the buffer. + * @size: Buffer size, in bytes. + * @alignment: Alignment "granularity" (see below), in bytes. + * @copy_size: Maximum number of bytes to "extract" from the buffer + * (in order to spost it as a separate scatter-gather entry). See below. + * + * Check buffer alignment and calculate "misaligned" portion, if exists. + * The buffer is considered aligned if its address is multiple of + * the specified @alignment. If this is the case, + * xge_hal_check_alignment() returns zero. + * Otherwise, xge_hal_check_alignment() uses the last argument, + * @copy_size, + * to calculate the size to "extract" from the buffer. The @copy_size + * may or may not be equal @alignment. The difference between these two + * arguments is that the @alignment is used to make the decision: aligned + * or not aligned. While the @copy_size is used to calculate the portion + * of the buffer to "extract", i.e. to post as a separate entry in the + * transmit descriptor. For example, the combination + * @alignment=8 and @copy_size=64 will work okay on AMD Opteron boxes. + * + * Note: @copy_size should be a multiple of @alignment. In many practical + * cases @copy_size and @alignment will probably be equal. + * + * See also: xge_hal_fifo_dtr_buffer_set_aligned(). + */ +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int +xge_hal_check_alignment(dma_addr_t dma_pointer, int size, int alignment, + int copy_size) +{ + int misaligned_size; + + misaligned_size = (int)(dma_pointer & (alignment - 1)); + if (!misaligned_size) { + return 0; + } + + if (size > copy_size) { + misaligned_size = (int)(dma_pointer & (copy_size - 1)); + misaligned_size = copy_size - misaligned_size; + } else { + misaligned_size = size; + } + + return misaligned_size; +} + diff --git a/sys/dev/nxge/xgehal/xgehal-channel.c b/sys/dev/nxge/xgehal/xgehal-channel.c new file mode 100644 index 0000000..dad39f2 --- /dev/null +++ b/sys/dev/nxge/xgehal/xgehal-channel.c @@ -0,0 +1,759 @@ +/*- + * Copyright (c) 2002-2007 Neterion, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * FileName : xgehal-channel.c + * + * Description: chipset channel abstraction + * + * Created: 10 May 2004 + */ + +#include +#include +#include +#include +#include +#ifdef XGEHAL_RNIC +#include +#include "xgehal-iov.h" +#endif + +/* + * __hal_channel_dtr_next_reservelist + * + * Walking through the all available DTRs. + */ +static xge_hal_status_e +__hal_channel_dtr_next_reservelist(xge_hal_channel_h channelh, + xge_hal_dtr_h *dtrh) +{ + xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; + + if (channel->reserve_top >= channel->reserve_length) { + return XGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS; + } + + *dtrh = channel->reserve_arr[channel->reserve_top++]; + + return XGE_HAL_OK; +} + +/* + * __hal_channel_dtr_next_freelist + * + * Walking through the "freed" DTRs. + */ +static xge_hal_status_e +__hal_channel_dtr_next_freelist(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh) +{ + xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; + + if (channel->reserve_initial == channel->free_length) { + return XGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS; + } + + *dtrh = channel->free_arr[channel->free_length++]; + + return XGE_HAL_OK; +} + +/* + * __hal_channel_dtr_next_not_completed - Get the _next_ posted but + * not completed descriptor. + * + * Walking through the "not completed" DTRs. + */ +static xge_hal_status_e +__hal_channel_dtr_next_not_completed(xge_hal_channel_h channelh, + xge_hal_dtr_h *dtrh) +{ +#ifndef XGEHAL_RNIC + xge_hal_ring_rxd_1_t *rxdp; /* doesn't matter 1, 3 or 5... */ +#endif + + __hal_channel_dtr_try_complete(channelh, dtrh); + if (*dtrh == NULL) { + return XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS; + } + +#ifndef XGEHAL_RNIC + rxdp = (xge_hal_ring_rxd_1_t *)*dtrh; + xge_assert(rxdp->host_control!=0); +#endif + + __hal_channel_dtr_complete(channelh); + + return XGE_HAL_OK; +} + +xge_hal_channel_t* +__hal_channel_allocate(xge_hal_device_h devh, int post_qid, +#ifdef XGEHAL_RNIC + u32 vp_id, +#endif + xge_hal_channel_type_e type) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + xge_hal_channel_t *channel; + int size = 0; + + switch(type) { + case XGE_HAL_CHANNEL_TYPE_FIFO: + xge_assert(post_qid + 1 >= XGE_HAL_MIN_FIFO_NUM && + post_qid + 1 <= XGE_HAL_MAX_FIFO_NUM); + size = sizeof(xge_hal_fifo_t); + break; + case XGE_HAL_CHANNEL_TYPE_RING: + xge_assert(post_qid + 1 >= XGE_HAL_MIN_RING_NUM && + post_qid + 1 <= XGE_HAL_MAX_RING_NUM); + size = sizeof(xge_hal_ring_t); + break; +#ifdef XGEHAL_RNIC + case XGE_HAL_CHANNEL_TYPE_SEND_QUEUE: + size = sizeof(__hal_sq_t); + break; + case XGE_HAL_CHANNEL_TYPE_RECEIVE_QUEUE: + size = sizeof(__hal_srq_t); + break; + case XGE_HAL_CHANNEL_TYPE_COMPLETION_QUEUE: + size = sizeof(__hal_cqrq_t); + break; + case XGE_HAL_CHANNEL_TYPE_UP_MESSAGE_QUEUE: + size = sizeof(__hal_umq_t); + break; + case XGE_HAL_CHANNEL_TYPE_DOWN_MESSAGE_QUEUE: + size = sizeof(__hal_dmq_t); + break; +#endif + default : + xge_assert(size); + break; + + } + + + /* allocate FIFO channel */ + channel = (xge_hal_channel_t *) xge_os_malloc(hldev->pdev, size); + if (channel == NULL) { + return NULL; + } + xge_os_memzero(channel, size); + + channel->pdev = hldev->pdev; + channel->regh0 = hldev->regh0; + channel->regh1 = hldev->regh1; + channel->type = type; + channel->devh = devh; +#ifdef XGEHAL_RNIC + channel->vp_id = vp_id; +#endif + channel->post_qid = post_qid; + channel->compl_qid = 0; + + return channel; +} + +void __hal_channel_free(xge_hal_channel_t *channel) +{ + int size = 0; + + xge_assert(channel->pdev); + + switch(channel->type) { + case XGE_HAL_CHANNEL_TYPE_FIFO: + size = sizeof(xge_hal_fifo_t); + break; + case XGE_HAL_CHANNEL_TYPE_RING: + size = sizeof(xge_hal_ring_t); + break; +#ifdef XGEHAL_RNIC + case XGE_HAL_CHANNEL_TYPE_SEND_QUEUE: + size = sizeof(__hal_sq_t); + break; + case XGE_HAL_CHANNEL_TYPE_RECEIVE_QUEUE: + size = sizeof(__hal_srq_t); + break; + case XGE_HAL_CHANNEL_TYPE_COMPLETION_QUEUE: + size = sizeof(__hal_cqrq_t); + break; + case XGE_HAL_CHANNEL_TYPE_UP_MESSAGE_QUEUE: + size = sizeof(__hal_umq_t); + break; + case XGE_HAL_CHANNEL_TYPE_DOWN_MESSAGE_QUEUE: + size = sizeof(__hal_dmq_t); + break; +#else + case XGE_HAL_CHANNEL_TYPE_SEND_QUEUE: + case XGE_HAL_CHANNEL_TYPE_RECEIVE_QUEUE: + case XGE_HAL_CHANNEL_TYPE_COMPLETION_QUEUE: + case XGE_HAL_CHANNEL_TYPE_UP_MESSAGE_QUEUE: + case XGE_HAL_CHANNEL_TYPE_DOWN_MESSAGE_QUEUE: + xge_assert(size); + break; +#endif + default: + break; + } + + xge_os_free(channel->pdev, channel, size); +} + +xge_hal_status_e +__hal_channel_initialize (xge_hal_channel_h channelh, + xge_hal_channel_attr_t *attr, void **reserve_arr, + int reserve_initial, int reserve_max, int reserve_threshold) +{ + xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; + xge_hal_device_t *hldev; + + hldev = (xge_hal_device_t *)channel->devh; + + channel->dtr_term = attr->dtr_term; + channel->dtr_init = attr->dtr_init; + channel->callback = attr->callback; + channel->userdata = attr->userdata; + channel->flags = attr->flags; + channel->per_dtr_space = attr->per_dtr_space; + + channel->reserve_arr = reserve_arr; + channel->reserve_initial = reserve_initial; + channel->reserve_max = reserve_max; + channel->reserve_length = channel->reserve_initial; + channel->reserve_threshold = reserve_threshold; + channel->reserve_top = 0; + channel->saved_arr = (void **) xge_os_malloc(hldev->pdev, + sizeof(void*)*channel->reserve_max); + if (channel->saved_arr == NULL) { + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + xge_os_memzero(channel->saved_arr, sizeof(void*)*channel->reserve_max); + channel->free_arr = channel->saved_arr; + channel->free_length = channel->reserve_initial; + channel->work_arr = (void **) xge_os_malloc(hldev->pdev, + sizeof(void*)*channel->reserve_max); + if (channel->work_arr == NULL) { + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + xge_os_memzero(channel->work_arr, + sizeof(void*)*channel->reserve_max); + channel->post_index = 0; + channel->compl_index = 0; + channel->length = channel->reserve_initial; + + channel->orig_arr = (void **) xge_os_malloc(hldev->pdev, + sizeof(void*)*channel->reserve_max); + if (channel->orig_arr == NULL) + return XGE_HAL_ERR_OUT_OF_MEMORY; + + xge_os_memzero(channel->orig_arr, sizeof(void*)*channel->reserve_max); + +#if defined(XGE_HAL_RX_MULTI_FREE_IRQ) || defined(XGE_HAL_TX_MULTI_FREE_IRQ) + xge_os_spin_lock_init_irq(&channel->free_lock, hldev->irqh); +#elif defined(XGE_HAL_RX_MULTI_FREE) || defined(XGE_HAL_TX_MULTI_FREE) + xge_os_spin_lock_init(&channel->free_lock, hldev->pdev); +#endif + + return XGE_HAL_OK; +} + +void __hal_channel_terminate(xge_hal_channel_h channelh) +{ + xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; + xge_hal_device_t *hldev; + + hldev = (xge_hal_device_t *)channel->devh; + + xge_assert(channel->pdev); + /* undo changes made at channel_initialize() */ + if (channel->work_arr) { + xge_os_free(channel->pdev, channel->work_arr, + sizeof(void*)*channel->reserve_max); + channel->work_arr = NULL; + } + + if (channel->saved_arr) { + xge_os_free(channel->pdev, channel->saved_arr, + sizeof(void*)*channel->reserve_max); + channel->saved_arr = NULL; + } + + if (channel->orig_arr) { + xge_os_free(channel->pdev, channel->orig_arr, + sizeof(void*)*channel->reserve_max); + channel->orig_arr = NULL; + } + +#if defined(XGE_HAL_RX_MULTI_FREE_IRQ) || defined(XGE_HAL_TX_MULTI_FREE_IRQ) + xge_os_spin_lock_destroy_irq(&channel->free_lock, hldev->irqh); +#elif defined(XGE_HAL_RX_MULTI_FREE) || defined(XGE_HAL_TX_MULTI_FREE) + xge_os_spin_lock_destroy(&channel->free_lock, hldev->pdev); +#endif +} + +/** + * xge_hal_channel_open - Open communication channel. + * @devh: HAL device, pointer to xge_hal_device_t structure. + * @attr: Contains attributes required to open + * the channel. + * @channelh: The channel handle. On success (XGE_HAL_OK) HAL fills + * this "out" parameter with a valid channel handle. + * @reopen: See xge_hal_channel_reopen_e{}. + * + * Open communication channel with the device. + * + * HAL uses (persistent) channel configuration to allocate both channel + * and Xframe Tx and Rx descriptors. + * Notes: + * 1) The channel config data is fed into HAL prior to + * xge_hal_channel_open(). + * + * 2) The corresponding hardware queues must be already configured and + * enabled. + * + * 3) Either down or up queue may be omitted, in which case the channel + * is treated as _unidirectional_. + * + * 4) Post and completion queue may be the same, in which case the channel + * is said to have "in-band completions". + * + * Note that free_channels list is not protected. i.e. caller must provide + * safe context. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_CHANNEL_NOT_FOUND - Unable to locate the channel. + * XGE_HAL_ERR_OUT_OF_MEMORY - Memory allocation failed. + * + * See also: xge_hal_channel_attr_t{}. + * Usage: See ex_open{}. + */ +xge_hal_status_e +xge_hal_channel_open(xge_hal_device_h devh, + xge_hal_channel_attr_t *attr, + xge_hal_channel_h *channelh, + xge_hal_channel_reopen_e reopen) +{ + xge_list_t *item; + int i; + xge_hal_status_e status = XGE_HAL_OK; + xge_hal_channel_t *channel = NULL; + xge_hal_device_t *device = (xge_hal_device_t *)devh; + + xge_assert(device); + xge_assert(attr); + + *channelh = NULL; + +#ifdef XGEHAL_RNIC + if((attr->type == XGE_HAL_CHANNEL_TYPE_FIFO) || + (attr->type == XGE_HAL_CHANNEL_TYPE_RING)) { +#endif + /* find channel */ + xge_list_for_each(item, &device->free_channels) { + xge_hal_channel_t *tmp; + + tmp = xge_container_of(item, xge_hal_channel_t, item); + if (tmp->type == attr->type && + tmp->post_qid == attr->post_qid && + tmp->compl_qid == attr->compl_qid) { + channel = tmp; + break; + } + } + + if (channel == NULL) { + return XGE_HAL_ERR_CHANNEL_NOT_FOUND; + } + +#ifdef XGEHAL_RNIC + } + else { + channel = __hal_channel_allocate(devh, attr->post_qid, +#ifdef XGEHAL_RNIC + attr->vp_id, +#endif + attr->type); + if (channel == NULL) { + xge_debug_device(XGE_ERR, + "__hal_channel_allocate failed"); + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + } +#endif + +#ifndef XGEHAL_RNIC + xge_assert((channel->type == XGE_HAL_CHANNEL_TYPE_FIFO) || + (channel->type == XGE_HAL_CHANNEL_TYPE_RING)); +#endif + +#ifdef XGEHAL_RNIC + if((reopen == XGE_HAL_CHANNEL_OC_NORMAL) || + ((channel->type != XGE_HAL_CHANNEL_TYPE_FIFO) && + (channel->type != XGE_HAL_CHANNEL_TYPE_RING))) { +#else + if (reopen == XGE_HAL_CHANNEL_OC_NORMAL) { +#endif + /* allocate memory, initialize pointers, etc */ + switch(channel->type) { + case XGE_HAL_CHANNEL_TYPE_FIFO: + status = __hal_fifo_open(channel, attr); + break; + case XGE_HAL_CHANNEL_TYPE_RING: + status = __hal_ring_open(channel, attr); + break; +#ifdef XGEHAL_RNIC + case XGE_HAL_CHANNEL_TYPE_SEND_QUEUE: + status = __hal_sq_open(channel, attr); + break; + case XGE_HAL_CHANNEL_TYPE_RECEIVE_QUEUE: + status = __hal_srq_open(channel, attr); + break; + case XGE_HAL_CHANNEL_TYPE_COMPLETION_QUEUE: + status = __hal_cqrq_open(channel, attr); + break; + case XGE_HAL_CHANNEL_TYPE_UP_MESSAGE_QUEUE: + status = __hal_umq_open(channel, attr); + break; + case XGE_HAL_CHANNEL_TYPE_DOWN_MESSAGE_QUEUE: + status = __hal_dmq_open(channel, attr); + break; +#else + case XGE_HAL_CHANNEL_TYPE_SEND_QUEUE: + case XGE_HAL_CHANNEL_TYPE_RECEIVE_QUEUE: + case XGE_HAL_CHANNEL_TYPE_COMPLETION_QUEUE: + case XGE_HAL_CHANNEL_TYPE_UP_MESSAGE_QUEUE: + case XGE_HAL_CHANNEL_TYPE_DOWN_MESSAGE_QUEUE: + status = XGE_HAL_FAIL; + break; +#endif + default: + break; + } + + if (status == XGE_HAL_OK) { + for (i = 0; i < channel->reserve_initial; i++) { + channel->orig_arr[i] = + channel->reserve_arr[i]; + } + } + else + return status; + } else { + xge_assert(reopen == XGE_HAL_CHANNEL_RESET_ONLY); + + for (i = 0; i < channel->reserve_initial; i++) { + channel->reserve_arr[i] = channel->orig_arr[i]; + channel->free_arr[i] = NULL; + } + channel->free_length = channel->reserve_initial; + channel->reserve_length = channel->reserve_initial; + channel->reserve_top = 0; + channel->post_index = 0; + channel->compl_index = 0; + if (channel->type == XGE_HAL_CHANNEL_TYPE_RING) { + status = __hal_ring_initial_replenish(channel, + reopen); + if (status != XGE_HAL_OK) + return status; + } + } + + /* move channel to the open state list */ + + switch(channel->type) { + case XGE_HAL_CHANNEL_TYPE_FIFO: + xge_list_remove(&channel->item); + xge_list_insert(&channel->item, &device->fifo_channels); + break; + case XGE_HAL_CHANNEL_TYPE_RING: + xge_list_remove(&channel->item); + xge_list_insert(&channel->item, &device->ring_channels); + break; +#ifdef XGEHAL_RNIC + case XGE_HAL_CHANNEL_TYPE_SEND_QUEUE: + xge_list_insert(&channel->item, + &device->virtual_paths[attr->vp_id].sq_channels); + device->virtual_paths[attr->vp_id].stats.no_sqs++; + break; + case XGE_HAL_CHANNEL_TYPE_RECEIVE_QUEUE: + xge_list_insert(&channel->item, + &device->virtual_paths[attr->vp_id].srq_channels); + device->virtual_paths[attr->vp_id].stats.no_srqs++; + break; + case XGE_HAL_CHANNEL_TYPE_COMPLETION_QUEUE: + xge_list_insert(&channel->item, + &device->virtual_paths[attr->vp_id].cqrq_channels); + device->virtual_paths[attr->vp_id].stats.no_cqrqs++; + break; + case XGE_HAL_CHANNEL_TYPE_UP_MESSAGE_QUEUE: + xge_list_init(&channel->item); + device->virtual_paths[attr->vp_id].umq_channelh = channel; + break; + case XGE_HAL_CHANNEL_TYPE_DOWN_MESSAGE_QUEUE: + xge_list_init(&channel->item); + device->virtual_paths[attr->vp_id].dmq_channelh = channel; + break; +#else + case XGE_HAL_CHANNEL_TYPE_SEND_QUEUE: + case XGE_HAL_CHANNEL_TYPE_RECEIVE_QUEUE: + case XGE_HAL_CHANNEL_TYPE_COMPLETION_QUEUE: + case XGE_HAL_CHANNEL_TYPE_UP_MESSAGE_QUEUE: + case XGE_HAL_CHANNEL_TYPE_DOWN_MESSAGE_QUEUE: + xge_assert(channel->type == XGE_HAL_CHANNEL_TYPE_FIFO || + channel->type == XGE_HAL_CHANNEL_TYPE_RING); + break; +#endif + default: + break; + } + channel->is_open = 1; + /* + * The magic check the argument validity, has to be + * removed before 03/01/2005. + */ + channel->magic = XGE_HAL_MAGIC; + + *channelh = channel; + + return XGE_HAL_OK; +} + +/** + * xge_hal_channel_abort - Abort the channel. + * @channelh: Channel handle. + * @reopen: See xge_hal_channel_reopen_e{}. + * + * Terminate (via xge_hal_channel_dtr_term_f{}) all channel descriptors. + * Currently used internally only by HAL, as part of its + * xge_hal_channel_close() and xge_hal_channel_open() in case + * of fatal error. + * + * See also: xge_hal_channel_dtr_term_f{}. + */ +void xge_hal_channel_abort(xge_hal_channel_h channelh, + xge_hal_channel_reopen_e reopen) +{ + xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; + xge_hal_dtr_h dtr; +#ifdef XGE_OS_MEMORY_CHECK + int check_cnt = 0; +#endif + int free_length_sav; + int reserve_top_sav; + + if (channel->dtr_term == NULL) { + return; + } + + free_length_sav = channel->free_length; + while (__hal_channel_dtr_next_freelist(channelh, &dtr) == XGE_HAL_OK) { +#ifdef XGE_OS_MEMORY_CHECK +#ifdef XGE_DEBUG_ASSERT + if (channel->type == XGE_HAL_CHANNEL_TYPE_FIFO) { + xge_assert(!__hal_fifo_txdl_priv(dtr)->allocated); + } else { + if (channel->type == XGE_HAL_CHANNEL_TYPE_RING) { + xge_assert(!__hal_ring_rxd_priv((xge_hal_ring_t * ) channelh, dtr)->allocated); + } + } +#endif + check_cnt++; +#endif + channel->dtr_term(channel, dtr, XGE_HAL_DTR_STATE_FREED, + channel->userdata, reopen); + } + channel->free_length = free_length_sav; + + while (__hal_channel_dtr_next_not_completed(channelh, &dtr) == + XGE_HAL_OK) { +#ifdef XGE_OS_MEMORY_CHECK +#ifdef XGE_DEBUG_ASSERT + if (channel->type == XGE_HAL_CHANNEL_TYPE_FIFO) { + xge_assert(__hal_fifo_txdl_priv(dtr)->allocated); + } else { + if (channel->type == XGE_HAL_CHANNEL_TYPE_RING) { + xge_assert(__hal_ring_rxd_priv((xge_hal_ring_t * ) channelh, dtr) + ->allocated); + } + } +#endif + check_cnt++; +#endif + channel->dtr_term(channel, dtr, XGE_HAL_DTR_STATE_POSTED, + channel->userdata, reopen); + + } + + reserve_top_sav = channel->reserve_top; + while (__hal_channel_dtr_next_reservelist(channelh, &dtr) == + XGE_HAL_OK) { +#ifdef XGE_OS_MEMORY_CHECK +#ifdef XGE_DEBUG_ASSERT + if (channel->type == XGE_HAL_CHANNEL_TYPE_FIFO) { + xge_assert(!__hal_fifo_txdl_priv(dtr)->allocated); + } else { + if (channel->type == XGE_HAL_CHANNEL_TYPE_RING) { + xge_assert(!__hal_ring_rxd_priv((xge_hal_ring_t * ) channelh, dtr)->allocated); + } + } +#endif + check_cnt++; +#endif + channel->dtr_term(channel, dtr, XGE_HAL_DTR_STATE_AVAIL, + channel->userdata, reopen); + } + channel->reserve_top = reserve_top_sav; + + xge_assert(channel->reserve_length == + (channel->free_length + channel->reserve_top)); + +#ifdef XGE_OS_MEMORY_CHECK + xge_assert(check_cnt == channel->reserve_initial); +#endif + +} + +/** + * xge_hal_channel_close - Close communication channel. + * @channelh: The channel handle. + * @reopen: See xge_hal_channel_reopen_e{}. + * + * Will close previously opened channel and deallocate associated resources. + * Channel must be opened otherwise assert will be generated. + * Note that free_channels list is not protected. i.e. caller must provide + * safe context. + */ +void xge_hal_channel_close(xge_hal_channel_h channelh, + xge_hal_channel_reopen_e reopen) +{ + xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; + xge_hal_device_t *hldev; + xge_list_t *item; +#ifdef XGEHAL_RNIC + u32 vp_id; +#endif + xge_assert(channel); + xge_assert(channel->type < XGE_HAL_CHANNEL_TYPE_MAX); + + hldev = (xge_hal_device_t *)channel->devh; + channel->is_open = 0; + channel->magic = XGE_HAL_DEAD; + +#ifdef XGEHAL_RNIC + vp_id = channel->vp_id; + + if((channel->type == XGE_HAL_CHANNEL_TYPE_FIFO) || + (channel->type == XGE_HAL_CHANNEL_TYPE_RING)) { +#endif + /* sanity check: make sure channel is not in free list */ + xge_list_for_each(item, &hldev->free_channels) { + xge_hal_channel_t *tmp; + + tmp = xge_container_of(item, xge_hal_channel_t, item); + xge_assert(!tmp->is_open); + if (channel == tmp) { + return; + } + } +#ifdef XGEHAL_RNIC + } +#endif + + xge_hal_channel_abort(channel, reopen); + +#ifndef XGEHAL_RNIC + xge_assert((channel->type == XGE_HAL_CHANNEL_TYPE_FIFO) || + (channel->type == XGE_HAL_CHANNEL_TYPE_RING)); +#endif + + if (reopen == XGE_HAL_CHANNEL_OC_NORMAL) { + /* de-allocate */ + switch(channel->type) { + case XGE_HAL_CHANNEL_TYPE_FIFO: + __hal_fifo_close(channelh); + break; + case XGE_HAL_CHANNEL_TYPE_RING: + __hal_ring_close(channelh); + break; +#ifdef XGEHAL_RNIC + case XGE_HAL_CHANNEL_TYPE_SEND_QUEUE: + __hal_sq_close(channelh); + hldev->virtual_paths[vp_id].stats.no_sqs--; + break; + case XGE_HAL_CHANNEL_TYPE_RECEIVE_QUEUE: + __hal_srq_close(channelh); + hldev->virtual_paths[vp_id].stats.no_srqs--; + break; + case XGE_HAL_CHANNEL_TYPE_COMPLETION_QUEUE: + __hal_cqrq_close(channelh); + hldev->virtual_paths[vp_id].stats.no_cqrqs--; + break; + case XGE_HAL_CHANNEL_TYPE_UP_MESSAGE_QUEUE: + __hal_umq_close(channelh); + break; + case XGE_HAL_CHANNEL_TYPE_DOWN_MESSAGE_QUEUE: + __hal_dmq_close(channelh); + break; +#else + case XGE_HAL_CHANNEL_TYPE_SEND_QUEUE: + case XGE_HAL_CHANNEL_TYPE_RECEIVE_QUEUE: + case XGE_HAL_CHANNEL_TYPE_COMPLETION_QUEUE: + case XGE_HAL_CHANNEL_TYPE_UP_MESSAGE_QUEUE: + case XGE_HAL_CHANNEL_TYPE_DOWN_MESSAGE_QUEUE: + xge_assert(channel->type == XGE_HAL_CHANNEL_TYPE_FIFO || + channel->type == XGE_HAL_CHANNEL_TYPE_RING); + break; +#endif + default: + break; + } + } + else + xge_assert(reopen == XGE_HAL_CHANNEL_RESET_ONLY); + + /* move channel back to free state list */ + xge_list_remove(&channel->item); +#ifdef XGEHAL_RNIC + if((channel->type == XGE_HAL_CHANNEL_TYPE_FIFO) || + (channel->type == XGE_HAL_CHANNEL_TYPE_RING)) { +#endif + xge_list_insert(&channel->item, &hldev->free_channels); + + if (xge_list_is_empty(&hldev->fifo_channels) && + xge_list_is_empty(&hldev->ring_channels)) { + /* clear msix_idx in case of following HW reset */ + hldev->reset_needed_after_close = 1; + } +#ifdef XGEHAL_RNIC + } + else { + __hal_channel_free(channel); + } +#endif + +} diff --git a/sys/dev/nxge/xgehal/xgehal-config.c b/sys/dev/nxge/xgehal/xgehal-config.c new file mode 100644 index 0000000..45a82e9 --- /dev/null +++ b/sys/dev/nxge/xgehal/xgehal-config.c @@ -0,0 +1,761 @@ +/*- + * Copyright (c) 2002-2007 Neterion, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * FileName : xgehal-config.c + * + * Description: configuration functionality + * + * Created: 14 May 2004 + */ + +#include +#include + +/* + * __hal_tti_config_check - Check tti configuration + * @new_config: tti configuration information + * + * Returns: XGE_HAL_OK - success, + * otherwise one of the xge_hal_status_e{} enumerated error codes. + */ +static xge_hal_status_e +__hal_tti_config_check (xge_hal_tti_config_t *new_config) +{ + if ((new_config->urange_a < XGE_HAL_MIN_TX_URANGE_A) || + (new_config->urange_a > XGE_HAL_MAX_TX_URANGE_A)) { + return XGE_HAL_BADCFG_TX_URANGE_A; + } + + if ((new_config->ufc_a < XGE_HAL_MIN_TX_UFC_A) || + (new_config->ufc_a > XGE_HAL_MAX_TX_UFC_A)) { + return XGE_HAL_BADCFG_TX_UFC_A; + } + + if ((new_config->urange_b < XGE_HAL_MIN_TX_URANGE_B) || + (new_config->urange_b > XGE_HAL_MAX_TX_URANGE_B)) { + return XGE_HAL_BADCFG_TX_URANGE_B; + } + + if ((new_config->ufc_b < XGE_HAL_MIN_TX_UFC_B) || + (new_config->ufc_b > XGE_HAL_MAX_TX_UFC_B)) { + return XGE_HAL_BADCFG_TX_UFC_B; + } + + if ((new_config->urange_c < XGE_HAL_MIN_TX_URANGE_C) || + (new_config->urange_c > XGE_HAL_MAX_TX_URANGE_C)) { + return XGE_HAL_BADCFG_TX_URANGE_C; + } + + if ((new_config->ufc_c < XGE_HAL_MIN_TX_UFC_C) || + (new_config->ufc_c > XGE_HAL_MAX_TX_UFC_C)) { + return XGE_HAL_BADCFG_TX_UFC_C; + } + + if ((new_config->ufc_d < XGE_HAL_MIN_TX_UFC_D) || + (new_config->ufc_d > XGE_HAL_MAX_TX_UFC_D)) { + return XGE_HAL_BADCFG_TX_UFC_D; + } + + if ((new_config->timer_val_us < XGE_HAL_MIN_TX_TIMER_VAL) || + (new_config->timer_val_us > XGE_HAL_MAX_TX_TIMER_VAL)) { + return XGE_HAL_BADCFG_TX_TIMER_VAL; + } + + if ((new_config->timer_ci_en < XGE_HAL_MIN_TX_TIMER_CI_EN) || + (new_config->timer_ci_en > XGE_HAL_MAX_TX_TIMER_CI_EN)) { + return XGE_HAL_BADCFG_TX_TIMER_CI_EN; + } + + if ((new_config->timer_ac_en < XGE_HAL_MIN_TX_TIMER_AC_EN) || + (new_config->timer_ac_en > XGE_HAL_MAX_TX_TIMER_AC_EN)) { + return XGE_HAL_BADCFG_TX_TIMER_AC_EN; + } + + return XGE_HAL_OK; +} + +/* + * __hal_rti_config_check - Check rti configuration + * @new_config: rti configuration information + * + * Returns: XGE_HAL_OK - success, + * otherwise one of the xge_hal_status_e{} enumerated error codes. + */ +static xge_hal_status_e +__hal_rti_config_check (xge_hal_rti_config_t *new_config) +{ + if ((new_config->urange_a < XGE_HAL_MIN_RX_URANGE_A) || + (new_config->urange_a > XGE_HAL_MAX_RX_URANGE_A)) { + return XGE_HAL_BADCFG_RX_URANGE_A; + } + + if ((new_config->ufc_a < XGE_HAL_MIN_RX_UFC_A) || + (new_config->ufc_a > XGE_HAL_MAX_RX_UFC_A)) { + return XGE_HAL_BADCFG_RX_UFC_A; + } + + if ((new_config->urange_b < XGE_HAL_MIN_RX_URANGE_B) || + (new_config->urange_b > XGE_HAL_MAX_RX_URANGE_B)) { + return XGE_HAL_BADCFG_RX_URANGE_B; + } + + if ((new_config->ufc_b < XGE_HAL_MIN_RX_UFC_B) || + (new_config->ufc_b > XGE_HAL_MAX_RX_UFC_B)) { + return XGE_HAL_BADCFG_RX_UFC_B; + } + + if ((new_config->urange_c < XGE_HAL_MIN_RX_URANGE_C) || + (new_config->urange_c > XGE_HAL_MAX_RX_URANGE_C)) { + return XGE_HAL_BADCFG_RX_URANGE_C; + } + + if ((new_config->ufc_c < XGE_HAL_MIN_RX_UFC_C) || + (new_config->ufc_c > XGE_HAL_MAX_RX_UFC_C)) { + return XGE_HAL_BADCFG_RX_UFC_C; + } + + if ((new_config->ufc_d < XGE_HAL_MIN_RX_UFC_D) || + (new_config->ufc_d > XGE_HAL_MAX_RX_UFC_D)) { + return XGE_HAL_BADCFG_RX_UFC_D; + } + + if ((new_config->timer_val_us < XGE_HAL_MIN_RX_TIMER_VAL) || + (new_config->timer_val_us > XGE_HAL_MAX_RX_TIMER_VAL)) { + return XGE_HAL_BADCFG_RX_TIMER_VAL; + } + + if ((new_config->timer_ac_en < XGE_HAL_MIN_RX_TIMER_AC_EN) || + (new_config->timer_ac_en > XGE_HAL_MAX_RX_TIMER_AC_EN)) { + return XGE_HAL_BADCFG_RX_TIMER_AC_EN; + } + + return XGE_HAL_OK; +} + + +/* + * __hal_fifo_queue_check - Check fifo queue configuration + * @new_config: fifo queue configuration information + * + * Returns: XGE_HAL_OK - success, + * otherwise one of the xge_hal_status_e{} enumerated error codes. + */ +static xge_hal_status_e +__hal_fifo_queue_check (xge_hal_fifo_config_t *new_config, + xge_hal_fifo_queue_t *new_queue) +{ + int i; + + if ((new_queue->initial < XGE_HAL_MIN_FIFO_QUEUE_LENGTH) || + (new_queue->initial > XGE_HAL_MAX_FIFO_QUEUE_LENGTH)) { + return XGE_HAL_BADCFG_FIFO_QUEUE_INITIAL_LENGTH; + } + + /* FIXME: queue "grow" feature is not supported. + * Use "initial" queue size as the "maximum"; + * Remove the next line when fixed. */ + new_queue->max = new_queue->initial; + + if ((new_queue->max < XGE_HAL_MIN_FIFO_QUEUE_LENGTH) || + (new_queue->max > XGE_HAL_MAX_FIFO_QUEUE_LENGTH)) { + return XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH; + } + + if (new_queue->max < new_config->reserve_threshold) { + return XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD; + } + + if ((new_queue->intr < XGE_HAL_MIN_FIFO_QUEUE_INTR) || + (new_queue->intr > XGE_HAL_MAX_FIFO_QUEUE_INTR)) { + return XGE_HAL_BADCFG_FIFO_QUEUE_INTR; + } + + if ((new_queue->intr_vector < XGE_HAL_MIN_FIFO_QUEUE_INTR_VECTOR) || + (new_queue->intr_vector > XGE_HAL_MAX_FIFO_QUEUE_INTR_VECTOR)) { + return XGE_HAL_BADCFG_FIFO_QUEUE_INTR_VECTOR; + } + + for(i = 0; i < XGE_HAL_MAX_FIFO_TTI_NUM; i++) { + /* + * Validate the tti configuration parameters only if + * the TTI feature is enabled. + */ + if (new_queue->tti[i].enabled) { + xge_hal_status_e status; + + if ((status = __hal_tti_config_check( + &new_queue->tti[i])) != XGE_HAL_OK) { + return status; + } + } + } + + return XGE_HAL_OK; +} + +/* + * __hal_ring_queue_check - Check ring queue configuration + * @new_config: ring queue configuration information + * + * Returns: XGE_HAL_OK - success, + * otherwise one of the xge_hal_status_e{} enumerated error codes. + */ +static xge_hal_status_e +__hal_ring_queue_check (xge_hal_ring_queue_t *new_config) +{ + + if ((new_config->initial < XGE_HAL_MIN_RING_QUEUE_BLOCKS) || + (new_config->initial > XGE_HAL_MAX_RING_QUEUE_BLOCKS)) { + return XGE_HAL_BADCFG_RING_QUEUE_INITIAL_BLOCKS; + } + + /* FIXME: queue "grow" feature is not supported. + * Use "initial" queue size as the "maximum"; + * Remove the next line when fixed. */ + new_config->max = new_config->initial; + + if ((new_config->max < XGE_HAL_MIN_RING_QUEUE_BLOCKS) || + (new_config->max > XGE_HAL_MAX_RING_QUEUE_BLOCKS)) { + return XGE_HAL_BADCFG_RING_QUEUE_MAX_BLOCKS; + } + + if ((new_config->buffer_mode != XGE_HAL_RING_QUEUE_BUFFER_MODE_1) && + (new_config->buffer_mode != XGE_HAL_RING_QUEUE_BUFFER_MODE_3) && + (new_config->buffer_mode != XGE_HAL_RING_QUEUE_BUFFER_MODE_5)) { + return XGE_HAL_BADCFG_RING_QUEUE_BUFFER_MODE; + } + + /* + * Herc has less DRAM; the check is done later inside + * device_initialize() + */ + if (((new_config->dram_size_mb < XGE_HAL_MIN_RING_QUEUE_SIZE) || + (new_config->dram_size_mb > XGE_HAL_MAX_RING_QUEUE_SIZE_XENA)) && + new_config->dram_size_mb != XGE_HAL_DEFAULT_USE_HARDCODE) + return XGE_HAL_BADCFG_RING_QUEUE_SIZE; + + if ((new_config->backoff_interval_us < + XGE_HAL_MIN_BACKOFF_INTERVAL_US) || + (new_config->backoff_interval_us > + XGE_HAL_MAX_BACKOFF_INTERVAL_US)) { + return XGE_HAL_BADCFG_BACKOFF_INTERVAL_US; + } + + if ((new_config->max_frm_len < XGE_HAL_MIN_MAX_FRM_LEN) || + (new_config->max_frm_len > XGE_HAL_MAX_MAX_FRM_LEN)) { + return XGE_HAL_BADCFG_MAX_FRM_LEN; + } + + if ((new_config->priority < XGE_HAL_MIN_RING_PRIORITY) || + (new_config->priority > XGE_HAL_MAX_RING_PRIORITY)) { + return XGE_HAL_BADCFG_RING_PRIORITY; + } + + if ((new_config->rth_en < XGE_HAL_MIN_RING_RTH_EN) || + (new_config->rth_en > XGE_HAL_MAX_RING_RTH_EN)) { + return XGE_HAL_BADCFG_RING_RTH_EN; + } + + if ((new_config->rts_mac_en < XGE_HAL_MIN_RING_RTS_MAC_EN) || + (new_config->rts_mac_en > XGE_HAL_MAX_RING_RTS_MAC_EN)) { + return XGE_HAL_BADCFG_RING_RTS_MAC_EN; + } + + if ((new_config->rts_mac_en < XGE_HAL_MIN_RING_RTS_PORT_EN) || + (new_config->rts_mac_en > XGE_HAL_MAX_RING_RTS_PORT_EN)) { + return XGE_HAL_BADCFG_RING_RTS_PORT_EN; + } + + if ((new_config->intr_vector < XGE_HAL_MIN_RING_QUEUE_INTR_VECTOR) || + (new_config->intr_vector > XGE_HAL_MAX_RING_QUEUE_INTR_VECTOR)) { + return XGE_HAL_BADCFG_RING_QUEUE_INTR_VECTOR; + } + + if (new_config->indicate_max_pkts < + XGE_HAL_MIN_RING_INDICATE_MAX_PKTS || + new_config->indicate_max_pkts > + XGE_HAL_MAX_RING_INDICATE_MAX_PKTS) { + return XGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS; + } + + return __hal_rti_config_check(&new_config->rti); +} + +/* + * __hal_mac_config_check - Check mac configuration + * @new_config: mac configuration information + * + * Returns: XGE_HAL_OK - success, + * otherwise one of the xge_hal_status_e{} enumerated error codes. + */ +static xge_hal_status_e +__hal_mac_config_check (xge_hal_mac_config_t *new_config) +{ + if ((new_config->tmac_util_period < XGE_HAL_MIN_TMAC_UTIL_PERIOD) || + (new_config->tmac_util_period > XGE_HAL_MAX_TMAC_UTIL_PERIOD)) { + return XGE_HAL_BADCFG_TMAC_UTIL_PERIOD; + } + + if ((new_config->rmac_util_period < XGE_HAL_MIN_RMAC_UTIL_PERIOD) || + (new_config->rmac_util_period > XGE_HAL_MAX_RMAC_UTIL_PERIOD)) { + return XGE_HAL_BADCFG_RMAC_UTIL_PERIOD; + } + + if ((new_config->rmac_bcast_en < XGE_HAL_MIN_RMAC_BCAST_EN) || + (new_config->rmac_bcast_en > XGE_HAL_MAX_RMAC_BCAST_EN)) { + return XGE_HAL_BADCFG_RMAC_BCAST_EN; + } + + if ((new_config->rmac_pause_gen_en < XGE_HAL_MIN_RMAC_PAUSE_GEN_EN) || + (new_config->rmac_pause_gen_en>XGE_HAL_MAX_RMAC_PAUSE_GEN_EN)) { + return XGE_HAL_BADCFG_RMAC_PAUSE_GEN_EN; + } + + if ((new_config->rmac_pause_rcv_en < XGE_HAL_MIN_RMAC_PAUSE_RCV_EN) || + (new_config->rmac_pause_rcv_en>XGE_HAL_MAX_RMAC_PAUSE_RCV_EN)) { + return XGE_HAL_BADCFG_RMAC_PAUSE_RCV_EN; + } + + if ((new_config->rmac_pause_time < XGE_HAL_MIN_RMAC_HIGH_PTIME) || + (new_config->rmac_pause_time > XGE_HAL_MAX_RMAC_HIGH_PTIME)) { + return XGE_HAL_BADCFG_RMAC_HIGH_PTIME; + } + + if ((new_config->media < XGE_HAL_MIN_MEDIA) || + (new_config->media > XGE_HAL_MAX_MEDIA)) { + return XGE_HAL_BADCFG_MEDIA; + } + + if ((new_config->mc_pause_threshold_q0q3 < + XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q0Q3) || + (new_config->mc_pause_threshold_q0q3 > + XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q0Q3)) { + return XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q0Q3; + } + + if ((new_config->mc_pause_threshold_q4q7 < + XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q4Q7) || + (new_config->mc_pause_threshold_q4q7 > + XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q4Q7)) { + return XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q4Q7; + } + + return XGE_HAL_OK; +} + +/* + * __hal_fifo_config_check - Check fifo configuration + * @new_config: fifo configuration information + * + * Returns: XGE_HAL_OK - success, + * otherwise one of the xge_hal_status_e{} enumerated error codes. + */ +static xge_hal_status_e +__hal_fifo_config_check (xge_hal_fifo_config_t *new_config) +{ + int i; + int total_fifo_length = 0; + + /* + * recompute max_frags to be multiple of 4, + * which means, multiple of 128 for TxDL + */ + new_config->max_frags = ((new_config->max_frags + 3) >> 2) << 2; + + if ((new_config->max_frags < XGE_HAL_MIN_FIFO_FRAGS) || + (new_config->max_frags > XGE_HAL_MAX_FIFO_FRAGS)) { + return XGE_HAL_BADCFG_FIFO_FRAGS; + } + + if ((new_config->reserve_threshold < + XGE_HAL_MIN_FIFO_RESERVE_THRESHOLD) || + (new_config->reserve_threshold > + XGE_HAL_MAX_FIFO_RESERVE_THRESHOLD)) { + return XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD; + } + + if ((new_config->memblock_size < XGE_HAL_MIN_FIFO_MEMBLOCK_SIZE) || + (new_config->memblock_size > XGE_HAL_MAX_FIFO_MEMBLOCK_SIZE)) { + return XGE_HAL_BADCFG_FIFO_MEMBLOCK_SIZE; + } + + for(i = 0; i < XGE_HAL_MAX_FIFO_NUM; i++) { + xge_hal_status_e status; + + if (!new_config->queue[i].configured) + continue; + + if ((status = __hal_fifo_queue_check(new_config, + &new_config->queue[i])) != XGE_HAL_OK) { + return status; + } + + total_fifo_length += new_config->queue[i].max; + } + + if(total_fifo_length > XGE_HAL_MAX_FIFO_QUEUE_LENGTH){ + return XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH; + } + + return XGE_HAL_OK; +} + +/* + * __hal_ring_config_check - Check ring configuration + * @new_config: Ring configuration information + * + * Returns: XGE_HAL_OK - success, + * otherwise one of the xge_hal_status_e{} enumerated error codes. + */ +static xge_hal_status_e +__hal_ring_config_check (xge_hal_ring_config_t *new_config) +{ + int i; + + if ((new_config->memblock_size < XGE_HAL_MIN_RING_MEMBLOCK_SIZE) || + (new_config->memblock_size > XGE_HAL_MAX_RING_MEMBLOCK_SIZE)) { + return XGE_HAL_BADCFG_RING_MEMBLOCK_SIZE; + } + + for(i = 0; i < XGE_HAL_MAX_RING_NUM; i++) { + xge_hal_status_e status; + + if (!new_config->queue[i].configured) + continue; + + if ((status = __hal_ring_queue_check(&new_config->queue[i])) + != XGE_HAL_OK) { + return status; + } + } + + return XGE_HAL_OK; +} + + +/* + * __hal_device_config_check_common - Check device configuration. + * @new_config: Device configuration information + * + * Check part of configuration that is common to + * Xframe-I and Xframe-II. + * + * Returns: XGE_HAL_OK - success, + * otherwise one of the xge_hal_status_e{} enumerated error codes. + * + * See also: __hal_device_config_check_xena(). + */ +xge_hal_status_e +__hal_device_config_check_common (xge_hal_device_config_t *new_config) +{ + xge_hal_status_e status; + + if ((new_config->mtu < XGE_HAL_MIN_MTU) || + (new_config->mtu > XGE_HAL_MAX_MTU)) { + return XGE_HAL_BADCFG_MAX_MTU; + } + + if ((new_config->bimodal_interrupts < XGE_HAL_BIMODAL_INTR_MIN) || + (new_config->bimodal_interrupts > XGE_HAL_BIMODAL_INTR_MAX)) { + return XGE_HAL_BADCFG_BIMODAL_INTR; + } + + if (new_config->bimodal_interrupts && + ((new_config->bimodal_timer_lo_us < XGE_HAL_BIMODAL_TIMER_LO_US_MIN) || + (new_config->bimodal_timer_lo_us > XGE_HAL_BIMODAL_TIMER_LO_US_MAX))) { + return XGE_HAL_BADCFG_BIMODAL_TIMER_LO_US; + } + + if (new_config->bimodal_interrupts && + ((new_config->bimodal_timer_hi_us < XGE_HAL_BIMODAL_TIMER_HI_US_MIN) || + (new_config->bimodal_timer_hi_us > XGE_HAL_BIMODAL_TIMER_HI_US_MAX))) { + return XGE_HAL_BADCFG_BIMODAL_TIMER_HI_US; + } + + if ((new_config->no_isr_events < XGE_HAL_NO_ISR_EVENTS_MIN) || + (new_config->no_isr_events > XGE_HAL_NO_ISR_EVENTS_MAX)) { + return XGE_HAL_BADCFG_NO_ISR_EVENTS; + } + + if ((new_config->isr_polling_cnt < XGE_HAL_MIN_ISR_POLLING_CNT) || + (new_config->isr_polling_cnt > XGE_HAL_MAX_ISR_POLLING_CNT)) { + return XGE_HAL_BADCFG_ISR_POLLING_CNT; + } + + if (new_config->latency_timer && + new_config->latency_timer != XGE_HAL_USE_BIOS_DEFAULT_LATENCY) { + if ((new_config->latency_timer < XGE_HAL_MIN_LATENCY_TIMER) || + (new_config->latency_timer > XGE_HAL_MAX_LATENCY_TIMER)) { + return XGE_HAL_BADCFG_LATENCY_TIMER; + } + } + + if (new_config->max_splits_trans != XGE_HAL_USE_BIOS_DEFAULT_SPLITS) { + if ((new_config->max_splits_trans < + XGE_HAL_ONE_SPLIT_TRANSACTION) || + (new_config->max_splits_trans > + XGE_HAL_THIRTYTWO_SPLIT_TRANSACTION)) + return XGE_HAL_BADCFG_MAX_SPLITS_TRANS; + } + + if (new_config->mmrb_count != XGE_HAL_DEFAULT_BIOS_MMRB_COUNT) + { + if ((new_config->mmrb_count < XGE_HAL_MIN_MMRB_COUNT) || + (new_config->mmrb_count > XGE_HAL_MAX_MMRB_COUNT)) { + return XGE_HAL_BADCFG_MMRB_COUNT; + } + } + + if ((new_config->shared_splits < XGE_HAL_MIN_SHARED_SPLITS) || + (new_config->shared_splits > XGE_HAL_MAX_SHARED_SPLITS)) { + return XGE_HAL_BADCFG_SHARED_SPLITS; + } + + if (new_config->stats_refresh_time_sec != + XGE_HAL_STATS_REFRESH_DISABLE) { + if ((new_config->stats_refresh_time_sec < + XGE_HAL_MIN_STATS_REFRESH_TIME) || + (new_config->stats_refresh_time_sec > + XGE_HAL_MAX_STATS_REFRESH_TIME)) { + return XGE_HAL_BADCFG_STATS_REFRESH_TIME; + } + } + + if ((new_config->intr_mode != XGE_HAL_INTR_MODE_IRQLINE) && + (new_config->intr_mode != XGE_HAL_INTR_MODE_MSI) && + (new_config->intr_mode != XGE_HAL_INTR_MODE_MSIX)) { + return XGE_HAL_BADCFG_INTR_MODE; + } + + if ((new_config->sched_timer_us < XGE_HAL_SCHED_TIMER_MIN) || + (new_config->sched_timer_us > XGE_HAL_SCHED_TIMER_MAX)) { + return XGE_HAL_BADCFG_SCHED_TIMER_US; + } + + if ((new_config->sched_timer_one_shot != + XGE_HAL_SCHED_TIMER_ON_SHOT_DISABLE) && + (new_config->sched_timer_one_shot != + XGE_HAL_SCHED_TIMER_ON_SHOT_ENABLE)) { + return XGE_HAL_BADCFG_SCHED_TIMER_ON_SHOT; + } + + /* + * Check adaptive schema parameters. Note that there are two + * configuration variables needs to be enabled in ULD: + * + * a) sched_timer_us should not be zero; + * b) rxufca_hi_lim should not be equal to rxufca_lo_lim. + * + * The code bellow checking for those conditions. + */ + if (new_config->sched_timer_us && + new_config->rxufca_hi_lim != new_config->rxufca_lo_lim) { + if ((new_config->rxufca_intr_thres < + XGE_HAL_RXUFCA_INTR_THRES_MIN) || + (new_config->rxufca_intr_thres > + XGE_HAL_RXUFCA_INTR_THRES_MAX)) { + return XGE_HAL_BADCFG_RXUFCA_INTR_THRES; + } + + if ((new_config->rxufca_hi_lim < XGE_HAL_RXUFCA_HI_LIM_MIN) || + (new_config->rxufca_hi_lim > XGE_HAL_RXUFCA_HI_LIM_MAX)) { + return XGE_HAL_BADCFG_RXUFCA_HI_LIM; + } + + if ((new_config->rxufca_lo_lim < XGE_HAL_RXUFCA_LO_LIM_MIN) || + (new_config->rxufca_lo_lim > XGE_HAL_RXUFCA_LO_LIM_MAX) || + (new_config->rxufca_lo_lim > new_config->rxufca_hi_lim)) { + return XGE_HAL_BADCFG_RXUFCA_LO_LIM; + } + + if ((new_config->rxufca_lbolt_period < + XGE_HAL_RXUFCA_LBOLT_PERIOD_MIN) || + (new_config->rxufca_lbolt_period > + XGE_HAL_RXUFCA_LBOLT_PERIOD_MAX)) { + return XGE_HAL_BADCFG_RXUFCA_LBOLT_PERIOD; + } + } + + if ((new_config->link_valid_cnt < XGE_HAL_LINK_VALID_CNT_MIN) || + (new_config->link_valid_cnt > XGE_HAL_LINK_VALID_CNT_MAX)) { + return XGE_HAL_BADCFG_LINK_VALID_CNT; + } + + if ((new_config->link_retry_cnt < XGE_HAL_LINK_RETRY_CNT_MIN) || + (new_config->link_retry_cnt > XGE_HAL_LINK_RETRY_CNT_MAX)) { + return XGE_HAL_BADCFG_LINK_RETRY_CNT; + } + + if (new_config->link_valid_cnt > new_config->link_retry_cnt) + return XGE_HAL_BADCFG_LINK_VALID_CNT; + + if (new_config->link_stability_period != XGE_HAL_DEFAULT_USE_HARDCODE) { + if ((new_config->link_stability_period < + XGE_HAL_MIN_LINK_STABILITY_PERIOD) || + (new_config->link_stability_period > + XGE_HAL_MAX_LINK_STABILITY_PERIOD)) { + return XGE_HAL_BADCFG_LINK_STABILITY_PERIOD; + } + } + + if (new_config->device_poll_millis != + XGE_HAL_DEFAULT_USE_HARDCODE) { + if ((new_config->device_poll_millis < + XGE_HAL_MIN_DEVICE_POLL_MILLIS) || + (new_config->device_poll_millis > + XGE_HAL_MAX_DEVICE_POLL_MILLIS)) { + return XGE_HAL_BADCFG_DEVICE_POLL_MILLIS; + } + } + + if ((new_config->rts_port_en < XGE_HAL_MIN_RING_RTS_PORT_EN) || + (new_config->rts_port_en > XGE_HAL_MAX_RING_RTS_PORT_EN)) { + return XGE_HAL_BADCFG_RTS_PORT_EN; + } + + if ((new_config->rts_qos_en < XGE_HAL_RTS_QOS_DISABLE) || + (new_config->rts_qos_en > XGE_HAL_RTS_QOS_ENABLE)) { + return XGE_HAL_BADCFG_RTS_QOS_EN; + } + +#if defined(XGE_HAL_CONFIG_LRO) + if (new_config->lro_sg_size != + XGE_HAL_DEFAULT_USE_HARDCODE) { + if ((new_config->lro_sg_size < XGE_HAL_LRO_MIN_SG_SIZE) || + (new_config->lro_sg_size > XGE_HAL_LRO_MAX_SG_SIZE)) { + return XGE_HAL_BADCFG_LRO_SG_SIZE; + } + } + + if (new_config->lro_frm_len != + XGE_HAL_DEFAULT_USE_HARDCODE) { + if ((new_config->lro_frm_len < XGE_HAL_LRO_MIN_FRM_LEN) || + (new_config->lro_frm_len > XGE_HAL_LRO_MAX_FRM_LEN)) { + return XGE_HAL_BADCFG_LRO_FRM_LEN; + } + } +#endif + + if ((status = __hal_ring_config_check(&new_config->ring)) + != XGE_HAL_OK) { + return status; + } + + if ((status = __hal_mac_config_check(&new_config->mac)) != + XGE_HAL_OK) { + return status; + } + + if ((status = __hal_fifo_config_check(&new_config->fifo)) != + XGE_HAL_OK) { + return status; + } + + return XGE_HAL_OK; +} + +/* + * __hal_device_config_check_xena - Check Xframe-I configuration + * @new_config: Device configuration. + * + * Check part of configuration that is relevant only to Xframe-I. + * + * Returns: XGE_HAL_OK - success, + * otherwise one of the xge_hal_status_e{} enumerated error codes. + * + * See also: __hal_device_config_check_common(). + */ +xge_hal_status_e +__hal_device_config_check_xena (xge_hal_device_config_t *new_config) +{ + if ((new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_33) && + (new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_66) && + (new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_100) && + (new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_133) && + (new_config->pci_freq_mherz != XGE_HAL_PCI_FREQ_MHERZ_266) && + (new_config->pci_freq_mherz != XGE_HAL_DEFAULT_USE_HARDCODE)) { + return XGE_HAL_BADCFG_PCI_FREQ_MHERZ; + } + + return XGE_HAL_OK; +} + +/* + * __hal_device_config_check_herc - Check device configuration + * @new_config: Device configuration. + * + * Check part of configuration that is relevant only to Xframe-II. + * + * Returns: XGE_HAL_OK - success, + * otherwise one of the xge_hal_status_e{} enumerated error codes. + * + * See also: __hal_device_config_check_common(). + */ +xge_hal_status_e +__hal_device_config_check_herc (xge_hal_device_config_t *new_config) +{ + return XGE_HAL_OK; +} + + +/* + * __hal_driver_config_check - Check HAL configuration + * @new_config: Driver configuration information + * + * Returns: XGE_HAL_OK - success, + * otherwise one of the xge_hal_status_e{} enumerated error codes. + */ +xge_hal_status_e +__hal_driver_config_check (xge_hal_driver_config_t *new_config) +{ + if ((new_config->queue_size_initial < + XGE_HAL_MIN_QUEUE_SIZE_INITIAL) || + (new_config->queue_size_initial > + XGE_HAL_MAX_QUEUE_SIZE_INITIAL)) { + return XGE_HAL_BADCFG_QUEUE_SIZE_INITIAL; + } + + if ((new_config->queue_size_max < XGE_HAL_MIN_QUEUE_SIZE_MAX) || + (new_config->queue_size_max > XGE_HAL_MAX_QUEUE_SIZE_MAX)) { + return XGE_HAL_BADCFG_QUEUE_SIZE_MAX; + } + +#ifdef XGE_TRACE_INTO_CIRCULAR_ARR + if ((new_config->tracebuf_size < XGE_HAL_MIN_CIRCULAR_ARR) || + (new_config->tracebuf_size > XGE_HAL_MAX_CIRCULAR_ARR)) { + return XGE_HAL_BADCFG_TRACEBUF_SIZE; + } + if ((new_config->tracebuf_timestamp_en < XGE_HAL_MIN_TIMESTAMP_EN) || + (new_config->tracebuf_timestamp_en > XGE_HAL_MAX_TIMESTAMP_EN)) { + return XGE_HAL_BADCFG_TRACEBUF_SIZE; + } +#endif + + return XGE_HAL_OK; +} diff --git a/sys/dev/nxge/xgehal/xgehal-device-fp.c b/sys/dev/nxge/xgehal/xgehal-device-fp.c new file mode 100644 index 0000000..5e2faf1 --- /dev/null +++ b/sys/dev/nxge/xgehal/xgehal-device-fp.c @@ -0,0 +1,1432 @@ +/*- + * Copyright (c) 2002-2007 Neterion, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * FileName : xgehal-device-fp.c + * + * Description: HAL device object functionality (fast path) + * + * Created: 10 June 2004 + */ + +#ifdef XGE_DEBUG_FP +#include +#endif + +#include +#include + +/** + * xge_hal_device_bar0 - Get BAR0 mapped address. + * @hldev: HAL device handle. + * + * Returns: BAR0 address of the specified device. + */ +__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char * +xge_hal_device_bar0(xge_hal_device_t *hldev) +{ + return hldev->bar0; +} + +/** + * xge_hal_device_isrbar0 - Get BAR0 mapped address. + * @hldev: HAL device handle. + * + * Returns: BAR0 address of the specified device. + */ +__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char * +xge_hal_device_isrbar0(xge_hal_device_t *hldev) +{ + return hldev->isrbar0; +} + +/** + * xge_hal_device_bar1 - Get BAR1 mapped address. + * @hldev: HAL device handle. + * + * Returns: BAR1 address of the specified device. + */ +__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char * +xge_hal_device_bar1(xge_hal_device_t *hldev) +{ + return hldev->bar1; +} + +/** + * xge_hal_device_bar0_set - Set BAR0 mapped address. + * @hldev: HAL device handle. + * @bar0: BAR0 mapped address. + * * Set BAR0 address in the HAL device object. + */ +__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void +xge_hal_device_bar0_set(xge_hal_device_t *hldev, char *bar0) +{ + xge_assert(bar0); + hldev->bar0 = bar0; +} + +/** + * xge_hal_device_isrbar0_set - Set BAR0 mapped address. + * @hldev: HAL device handle. + * @isrbar0: BAR0 mapped address. + * * Set BAR0 address in the HAL device object. + */ +__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void +xge_hal_device_isrbar0_set(xge_hal_device_t *hldev, char *isrbar0) +{ + xge_assert(isrbar0); + hldev->isrbar0 = isrbar0; +} + +/** + * xge_hal_device_bar1_set - Set BAR1 mapped address. + * @hldev: HAL device handle. + * @channelh: Channel handle. + * @bar1: BAR1 mapped address. + * + * Set BAR1 address for the given channel. + */ +__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void +xge_hal_device_bar1_set(xge_hal_device_t *hldev, xge_hal_channel_h channelh, + char *bar1) +{ + xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh; + + xge_assert(bar1); + xge_assert(fifo); + + /* Initializing the BAR1 address as the start of + * the FIFO queue pointer and as a location of FIFO control + * word. */ + fifo->hw_pair = + (xge_hal_fifo_hw_pair_t *) (bar1 + + (fifo->channel.post_qid * XGE_HAL_FIFO_HW_PAIR_OFFSET)); + hldev->bar1 = bar1; +} + + +/** + * xge_hal_device_rev - Get Device revision number. + * @hldev: HAL device handle. + * + * Returns: Device revision number + */ +__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE int +xge_hal_device_rev(xge_hal_device_t *hldev) +{ + return hldev->revision; +} + + +/** + * xge_hal_device_begin_irq - Begin IRQ processing. + * @hldev: HAL device handle. + * @reason: "Reason" for the interrupt, the value of Xframe's + * general_int_status register. + * + * The function performs two actions, It first checks whether (shared IRQ) the + * interrupt was raised by the device. Next, it masks the device interrupts. + * + * Note: + * xge_hal_device_begin_irq() does not flush MMIO writes through the + * bridge. Therefore, two back-to-back interrupts are potentially possible. + * It is the responsibility of the ULD to make sure that only one + * xge_hal_device_continue_irq() runs at a time. + * + * Returns: 0, if the interrupt is not "ours" (note that in this case the + * device remain enabled). + * Otherwise, xge_hal_device_begin_irq() returns 64bit general adapter + * status. + * See also: xge_hal_device_handle_irq() + */ +__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e +xge_hal_device_begin_irq(xge_hal_device_t *hldev, u64 *reason) +{ + u64 val64; + xge_hal_pci_bar0_t *isrbar0 = (xge_hal_pci_bar0_t *)hldev->isrbar0; + + hldev->stats.sw_dev_info_stats.total_intr_cnt++; + + val64 = xge_os_pio_mem_read64(hldev->pdev, + hldev->regh0, &isrbar0->general_int_status); + if (xge_os_unlikely(!val64)) { + /* not Xframe interrupt */ + hldev->stats.sw_dev_info_stats.not_xge_intr_cnt++; + *reason = 0; + return XGE_HAL_ERR_WRONG_IRQ; + } + + if (xge_os_unlikely(val64 == XGE_HAL_ALL_FOXES)) { + u64 adapter_status = + xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->adapter_status); + if (adapter_status == XGE_HAL_ALL_FOXES) { + (void) xge_queue_produce(hldev->queueh, + XGE_HAL_EVENT_SLOT_FREEZE, + hldev, + 1, /* critical: slot freeze */ + sizeof(u64), + (void*)&adapter_status); + *reason = 0; + return XGE_HAL_ERR_CRITICAL; + } + } + + *reason = val64; + + /* separate fast path, i.e. no errors */ + if (val64 & XGE_HAL_GEN_INTR_RXTRAFFIC) { + hldev->stats.sw_dev_info_stats.rx_traffic_intr_cnt++; + return XGE_HAL_OK; + } + if (val64 & XGE_HAL_GEN_INTR_TXTRAFFIC) { + hldev->stats.sw_dev_info_stats.tx_traffic_intr_cnt++; + return XGE_HAL_OK; + } + + hldev->stats.sw_dev_info_stats.not_traffic_intr_cnt++; + if (xge_os_unlikely(val64 & XGE_HAL_GEN_INTR_TXPIC)) { + xge_hal_status_e status; + hldev->stats.sw_dev_info_stats.txpic_intr_cnt++; + status = __hal_device_handle_txpic(hldev, val64); + if (status != XGE_HAL_OK) { + return status; + } + } + + if (xge_os_unlikely(val64 & XGE_HAL_GEN_INTR_TXDMA)) { + xge_hal_status_e status; + hldev->stats.sw_dev_info_stats.txdma_intr_cnt++; + status = __hal_device_handle_txdma(hldev, val64); + if (status != XGE_HAL_OK) { + return status; + } + } + + if (xge_os_unlikely(val64 & XGE_HAL_GEN_INTR_TXMAC)) { + xge_hal_status_e status; + hldev->stats.sw_dev_info_stats.txmac_intr_cnt++; + status = __hal_device_handle_txmac(hldev, val64); + if (status != XGE_HAL_OK) { + return status; + } + } + + if (xge_os_unlikely(val64 & XGE_HAL_GEN_INTR_TXXGXS)) { + xge_hal_status_e status; + hldev->stats.sw_dev_info_stats.txxgxs_intr_cnt++; + status = __hal_device_handle_txxgxs(hldev, val64); + if (status != XGE_HAL_OK) { + return status; + } + } + + if (xge_os_unlikely(val64 & XGE_HAL_GEN_INTR_RXPIC)) { + xge_hal_status_e status; + hldev->stats.sw_dev_info_stats.rxpic_intr_cnt++; + status = __hal_device_handle_rxpic(hldev, val64); + if (status != XGE_HAL_OK) { + return status; + } + } + + if (xge_os_unlikely(val64 & XGE_HAL_GEN_INTR_RXDMA)) { + xge_hal_status_e status; + hldev->stats.sw_dev_info_stats.rxdma_intr_cnt++; + status = __hal_device_handle_rxdma(hldev, val64); + if (status != XGE_HAL_OK) { + return status; + } + } + + if (xge_os_unlikely(val64 & XGE_HAL_GEN_INTR_RXMAC)) { + xge_hal_status_e status; + hldev->stats.sw_dev_info_stats.rxmac_intr_cnt++; + status = __hal_device_handle_rxmac(hldev, val64); + if (status != XGE_HAL_OK) { + return status; + } + } + + if (xge_os_unlikely(val64 & XGE_HAL_GEN_INTR_RXXGXS)) { + xge_hal_status_e status; + hldev->stats.sw_dev_info_stats.rxxgxs_intr_cnt++; + status = __hal_device_handle_rxxgxs(hldev, val64); + if (status != XGE_HAL_OK) { + return status; + } + } + + if (xge_os_unlikely(val64 & XGE_HAL_GEN_INTR_MC)) { + xge_hal_status_e status; + hldev->stats.sw_dev_info_stats.mc_intr_cnt++; + status = __hal_device_handle_mc(hldev, val64); + if (status != XGE_HAL_OK) { + return status; + } + } + + return XGE_HAL_OK; +} + +/** + * xge_hal_device_clear_rx - Acknowledge (that is, clear) the + * condition that has caused the RX interrupt. + * @hldev: HAL device handle. + * + * Acknowledge (that is, clear) the condition that has caused + * the Rx interrupt. + * See also: xge_hal_device_begin_irq(), xge_hal_device_continue_irq(), + * xge_hal_device_clear_tx(), xge_hal_device_mask_rx(). + */ +__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void +xge_hal_device_clear_rx(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *isrbar0 = (xge_hal_pci_bar0_t *)hldev->isrbar0; + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + 0xFFFFFFFFFFFFFFFFULL, + &isrbar0->rx_traffic_int); +} + +/** + * xge_hal_device_clear_tx - Acknowledge (that is, clear) the + * condition that has caused the TX interrupt. + * @hldev: HAL device handle. + * + * Acknowledge (that is, clear) the condition that has caused + * the Tx interrupt. + * See also: xge_hal_device_begin_irq(), xge_hal_device_continue_irq(), + * xge_hal_device_clear_rx(), xge_hal_device_mask_tx(). + */ +__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void +xge_hal_device_clear_tx(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *isrbar0 = (xge_hal_pci_bar0_t *)hldev->isrbar0; + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + 0xFFFFFFFFFFFFFFFFULL, + &isrbar0->tx_traffic_int); +} + +/** + * xge_hal_device_poll_rx_channel - Poll Rx channel for completed + * descriptors and process the same. + * @channel: HAL channel. + * @got_rx: Buffer to return the flag set if receive interrupt is occured + * + * The function polls the Rx channel for the completed descriptors and calls + * the upper-layer driver (ULD) via supplied completion callback. + * + * Returns: XGE_HAL_OK, if the polling is completed successful. + * XGE_HAL_COMPLETIONS_REMAIN: There are still more completed + * descriptors available which are yet to be processed. + * + * See also: xge_hal_device_poll_tx_channel() + */ +__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e +xge_hal_device_poll_rx_channel(xge_hal_channel_t *channel, int *got_rx) +{ + xge_hal_status_e ret = XGE_HAL_OK; + xge_hal_dtr_h first_dtrh; + xge_hal_device_t *hldev = (xge_hal_device_t *)channel->devh; + u8 t_code; + int got_bytes; + + /* for each opened rx channel */ + got_bytes = *got_rx = 0; + ((xge_hal_ring_t *)channel)->cmpl_cnt = 0; + channel->poll_bytes = 0; + if ((ret = xge_hal_ring_dtr_next_completed (channel, &first_dtrh, + &t_code)) == XGE_HAL_OK) { + if (channel->callback(channel, first_dtrh, + t_code, channel->userdata) != XGE_HAL_OK) { + (*got_rx) += ((xge_hal_ring_t *)channel)->cmpl_cnt + 1; + got_bytes += channel->poll_bytes + 1; + ret = XGE_HAL_COMPLETIONS_REMAIN; + } else { + (*got_rx) += ((xge_hal_ring_t *)channel)->cmpl_cnt + 1; + got_bytes += channel->poll_bytes + 1; + } + } + + if (*got_rx) { + hldev->irq_workload_rxd[channel->post_qid] += *got_rx; + hldev->irq_workload_rxcnt[channel->post_qid] ++; + } + hldev->irq_workload_rxlen[channel->post_qid] += got_bytes; + + return ret; +} + +/** + * xge_hal_device_poll_tx_channel - Poll Tx channel for completed + * descriptors and process the same. + * @channel: HAL channel. + * @got_tx: Buffer to return the flag set if transmit interrupt is occured + * + * The function polls the Tx channel for the completed descriptors and calls + * the upper-layer driver (ULD) via supplied completion callback. + * + * Returns: XGE_HAL_OK, if the polling is completed successful. + * XGE_HAL_COMPLETIONS_REMAIN: There are still more completed + * descriptors available which are yet to be processed. + * + * See also: xge_hal_device_poll_rx_channel(). + */ +__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e +xge_hal_device_poll_tx_channel(xge_hal_channel_t *channel, int *got_tx) +{ + xge_hal_dtr_h first_dtrh; + xge_hal_device_t *hldev = (xge_hal_device_t *)channel->devh; + u8 t_code; + int got_bytes; + + /* for each opened tx channel */ + got_bytes = *got_tx = 0; + channel->poll_bytes = 0; + if (xge_hal_fifo_dtr_next_completed (channel, &first_dtrh, + &t_code) == XGE_HAL_OK) { + if (channel->callback(channel, first_dtrh, + t_code, channel->userdata) != XGE_HAL_OK) { + (*got_tx)++; + got_bytes += channel->poll_bytes + 1; + return XGE_HAL_COMPLETIONS_REMAIN; + } + (*got_tx)++; + got_bytes += channel->poll_bytes + 1; + } + + if (*got_tx) { + hldev->irq_workload_txd[channel->post_qid] += *got_tx; + hldev->irq_workload_txcnt[channel->post_qid] ++; + } + hldev->irq_workload_txlen[channel->post_qid] += got_bytes; + + return XGE_HAL_OK; +} + +/** + * xge_hal_device_poll_rx_channels - Poll Rx channels for completed + * descriptors and process the same. + * @hldev: HAL device handle. + * @got_rx: Buffer to return flag set if receive is ready + * + * The function polls the Rx channels for the completed descriptors and calls + * the upper-layer driver (ULD) via supplied completion callback. + * + * Returns: XGE_HAL_OK, if the polling is completed successful. + * XGE_HAL_COMPLETIONS_REMAIN: There are still more completed + * descriptors available which are yet to be processed. + * + * See also: xge_hal_device_poll_tx_channels(), xge_hal_device_continue_irq(). + */ +__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e +xge_hal_device_poll_rx_channels(xge_hal_device_t *hldev, int *got_rx) +{ + xge_list_t *item; + xge_hal_channel_t *channel; + + /* for each opened rx channel */ + xge_list_for_each(item, &hldev->ring_channels) { + if (hldev->terminating) + return XGE_HAL_OK; + channel = xge_container_of(item, xge_hal_channel_t, item); + (void) xge_hal_device_poll_rx_channel(channel, got_rx); + } + + return XGE_HAL_OK; +} + +/** + * xge_hal_device_poll_tx_channels - Poll Tx channels for completed + * descriptors and process the same. + * @hldev: HAL device handle. + * @got_tx: Buffer to return flag set if transmit is ready + * + * The function polls the Tx channels for the completed descriptors and calls + * the upper-layer driver (ULD) via supplied completion callback. + * + * Returns: XGE_HAL_OK, if the polling is completed successful. + * XGE_HAL_COMPLETIONS_REMAIN: There are still more completed + * descriptors available which are yet to be processed. + * + * See also: xge_hal_device_poll_rx_channels(), xge_hal_device_continue_irq(). + */ +__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e +xge_hal_device_poll_tx_channels(xge_hal_device_t *hldev, int *got_tx) +{ + xge_list_t *item; + xge_hal_channel_t *channel; + + /* for each opened tx channel */ + xge_list_for_each(item, &hldev->fifo_channels) { + if (hldev->terminating) + return XGE_HAL_OK; + channel = xge_container_of(item, xge_hal_channel_t, item); + (void) xge_hal_device_poll_tx_channel(channel, got_tx); + } + + return XGE_HAL_OK; +} + +/** + * xge_hal_device_mask_tx - Mask Tx interrupts. + * @hldev: HAL device handle. + * + * Mask Tx device interrupts. + * + * See also: xge_hal_device_unmask_tx(), xge_hal_device_mask_rx(), + * xge_hal_device_clear_tx(). + */ +__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void +xge_hal_device_mask_tx(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *isrbar0 = (xge_hal_pci_bar0_t *)hldev->isrbar0; + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + 0xFFFFFFFFFFFFFFFFULL, + &isrbar0->tx_traffic_mask); +} + +/** + * xge_hal_device_mask_rx - Mask Rx interrupts. + * @hldev: HAL device handle. + * + * Mask Rx device interrupts. + * + * See also: xge_hal_device_unmask_rx(), xge_hal_device_mask_tx(), + * xge_hal_device_clear_rx(). + */ +__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void +xge_hal_device_mask_rx(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *isrbar0 = (xge_hal_pci_bar0_t *)hldev->isrbar0; + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + 0xFFFFFFFFFFFFFFFFULL, + &isrbar0->rx_traffic_mask); +} + +/** + * xge_hal_device_mask_all - Mask all device interrupts. + * @hldev: HAL device handle. + * + * Mask all device interrupts. + * + * See also: xge_hal_device_unmask_all() + */ +__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void +xge_hal_device_mask_all(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *isrbar0 = (xge_hal_pci_bar0_t *)hldev->isrbar0; + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + 0xFFFFFFFFFFFFFFFFULL, + &isrbar0->general_int_mask); +} + +/** + * xge_hal_device_unmask_tx - Unmask Tx interrupts. + * @hldev: HAL device handle. + * + * Unmask Tx device interrupts. + * + * See also: xge_hal_device_mask_tx(), xge_hal_device_clear_tx(). + */ +__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void +xge_hal_device_unmask_tx(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *isrbar0 = (xge_hal_pci_bar0_t *)hldev->isrbar0; + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + 0x0ULL, + &isrbar0->tx_traffic_mask); +} + +/** + * xge_hal_device_unmask_rx - Unmask Rx interrupts. + * @hldev: HAL device handle. + * + * Unmask Rx device interrupts. + * + * See also: xge_hal_device_mask_rx(), xge_hal_device_clear_rx(). + */ +__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void +xge_hal_device_unmask_rx(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *isrbar0 = (xge_hal_pci_bar0_t *)hldev->isrbar0; + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + 0x0ULL, + &isrbar0->rx_traffic_mask); +} + +/** + * xge_hal_device_unmask_all - Unmask all device interrupts. + * @hldev: HAL device handle. + * + * Unmask all device interrupts. + * + * See also: xge_hal_device_mask_all() + */ +__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void +xge_hal_device_unmask_all(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *isrbar0 = (xge_hal_pci_bar0_t *)hldev->isrbar0; + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + 0x0ULL, + &isrbar0->general_int_mask); +} + + +/** + * xge_hal_device_continue_irq - Continue handling IRQ: process all + * completed descriptors. + * @hldev: HAL device handle. + * + * Process completed descriptors and unmask the device interrupts. + * + * The xge_hal_device_continue_irq() walks all open channels + * and calls upper-layer driver (ULD) via supplied completion + * callback. Note that the completion callback is specified at channel open + * time, see xge_hal_channel_open(). + * + * Note that the xge_hal_device_continue_irq is part of the _fast_ path. + * To optimize the processing, the function does _not_ check for + * errors and alarms. + * + * The latter is done in a polling fashion, via xge_hal_device_poll(). + * + * Returns: XGE_HAL_OK. + * + * See also: xge_hal_device_handle_irq(), xge_hal_device_poll(), + * xge_hal_ring_dtr_next_completed(), + * xge_hal_fifo_dtr_next_completed(), xge_hal_channel_callback_f{}. + */ +__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e +xge_hal_device_continue_irq(xge_hal_device_t *hldev) +{ + int got_rx = 1, got_tx = 1; + int isr_polling_cnt = hldev->config.isr_polling_cnt; + int count = 0; + + do + { + if (got_rx) + (void) xge_hal_device_poll_rx_channels(hldev, &got_rx); + if (got_tx && hldev->tti_enabled) + (void) xge_hal_device_poll_tx_channels(hldev, &got_tx); + + if (!got_rx && !got_tx) + break; + + count += (got_rx + got_tx); + }while (isr_polling_cnt--); + + if (!count) + hldev->stats.sw_dev_info_stats.not_traffic_intr_cnt++; + + return XGE_HAL_OK; +} + +/** + * xge_hal_device_handle_irq - Handle device IRQ. + * @hldev: HAL device handle. + * + * Perform the complete handling of the line interrupt. The function + * performs two calls. + * First it uses xge_hal_device_begin_irq() to check the reason for + * the interrupt and mask the device interrupts. + * Second, it calls xge_hal_device_continue_irq() to process all + * completed descriptors and re-enable the interrupts. + * + * Returns: XGE_HAL_OK - success; + * XGE_HAL_ERR_WRONG_IRQ - (shared) IRQ produced by other device. + * + * See also: xge_hal_device_begin_irq(), xge_hal_device_continue_irq(). + */ +__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e +xge_hal_device_handle_irq(xge_hal_device_t *hldev) +{ + u64 reason; + xge_hal_status_e status; + + xge_hal_device_mask_all(hldev); + + status = xge_hal_device_begin_irq(hldev, &reason); + if (status != XGE_HAL_OK) { + xge_hal_device_unmask_all(hldev); + return status; + } + + if (reason & XGE_HAL_GEN_INTR_RXTRAFFIC) { + xge_hal_device_clear_rx(hldev); + } + + status = xge_hal_device_continue_irq(hldev); + + xge_hal_device_clear_tx(hldev); + + xge_hal_device_unmask_all(hldev); + + return status; +} + +#if defined(XGE_HAL_CONFIG_LRO) + + +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int +__hal_lro_check_for_session_match(lro_t *lro, tcplro_t *tcp, iplro_t *ip) +{ + + /* Match Source address field */ + if ((lro->ip_hdr->saddr != ip->saddr)) + return XGE_HAL_FAIL; + + /* Match Destination address field */ + if ((lro->ip_hdr->daddr != ip->daddr)) + return XGE_HAL_FAIL; + + /* Match Source Port field */ + if ((lro->tcp_hdr->source != tcp->source)) + return XGE_HAL_FAIL; + + /* Match Destination Port field */ + if ((lro->tcp_hdr->dest != tcp->dest)) + return XGE_HAL_FAIL; + + return XGE_HAL_OK; +} + +/* + * __hal_tcp_seg_len: Find the tcp seg len. + * @ip: ip header. + * @tcp: tcp header. + * returns: Tcp seg length. + */ +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16 +__hal_tcp_seg_len(iplro_t *ip, tcplro_t *tcp) +{ + u16 ret; + + ret = (xge_os_ntohs(ip->tot_len) - + ((ip->version_ihl & 0x0F)<<2) - + ((tcp->doff_res)>>2)); + return (ret); +} + +/* + * __hal_ip_lro_capable: Finds whether ip is lro capable. + * @ip: ip header. + * @ext_info: descriptor info. + */ +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e +__hal_ip_lro_capable(iplro_t *ip, + xge_hal_dtr_info_t *ext_info) +{ + +#ifdef XGE_LL_DEBUG_DUMP_PKT + { + u16 i; + u8 ch, *iph = (u8 *)ip; + + xge_debug_ring(XGE_TRACE, "Dump Ip:" ); + for (i =0; i < 40; i++) { + ch = ntohs(*((u8 *)(iph + i)) ); + printf("i:%d %02x, ",i,ch); + } + } +#endif + + if (ip->version_ihl != IP_FAST_PATH_HDR_MASK) { + xge_debug_ring(XGE_ERR, "iphdr !=45 :%d",ip->version_ihl); + return XGE_HAL_FAIL; + } + + if (ext_info->proto & XGE_HAL_FRAME_PROTO_IP_FRAGMENTED) { + xge_debug_ring(XGE_ERR, "IP fragmented"); + return XGE_HAL_FAIL; + } + + return XGE_HAL_OK; +} + +/* + * __hal_tcp_lro_capable: Finds whether tcp is lro capable. + * @ip: ip header. + * @tcp: tcp header. + */ +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e +__hal_tcp_lro_capable(iplro_t *ip, tcplro_t *tcp, lro_t *lro, int *ts_off) +{ +#ifdef XGE_LL_DEBUG_DUMP_PKT + { + u8 ch; + u16 i; + + xge_debug_ring(XGE_TRACE, "Dump Tcp:" ); + for (i =0; i < 20; i++) { + ch = ntohs(*((u8 *)((u8 *)tcp + i)) ); + xge_os_printf("i:%d %02x, ",i,ch); + } + } +#endif + if ((TCP_FAST_PATH_HDR_MASK2 != tcp->ctrl) && + (TCP_FAST_PATH_HDR_MASK3 != tcp->ctrl)) + goto _exit_fail; + + *ts_off = -1; + if (TCP_FAST_PATH_HDR_MASK1 != tcp->doff_res) { + u16 tcp_hdr_len = tcp->doff_res >> 2; /* TCP header len */ + u16 off = 20; /* Start of tcp options */ + int i, diff; + + /* Does Packet can contain time stamp */ + if (tcp_hdr_len < 32) { + /* + * If the session is not opened, we can consider + * this packet for LRO + */ + if (lro == NULL) + return XGE_HAL_OK; + + goto _exit_fail; + } + + /* Ignore No-operation 0x1 */ + while (((u8 *)tcp)[off] == 0x1) + off++; + + /* Next option == Timestamp */ + if (((u8 *)tcp)[off] != 0x8) { + /* + * If the session ie not opened, we can consider + * this packet for LRO + */ + if (lro == NULL) + return XGE_HAL_OK; + + goto _exit_fail; + } + + *ts_off = off; + if (lro == NULL) + return XGE_HAL_OK; + + /* + * Now the session is opened. If the LRO frame doesn't + * have time stamp, we cannot consider current packet for + * LRO. + */ + if (lro->ts_off == -1) { + xge_debug_ring(XGE_ERR, "Pkt received with time stamp after session opened with no time stamp : %02x %02x", tcp->doff_res, tcp->ctrl); + return XGE_HAL_FAIL; + } + + /* + * If the difference is greater than three, then there are + * more options possible. + * else, there are two cases: + * case 1: remaining are padding bytes. + * case 2: remaining can contain options or padding + */ + off += ((u8 *)tcp)[off+1]; + diff = tcp_hdr_len - off; + if (diff > 3) { + /* + * Probably contains more options. + */ + xge_debug_ring(XGE_ERR, "tcphdr not fastpth : pkt received with tcp options in addition to time stamp after the session is opened %02x %02x ", tcp->doff_res, tcp->ctrl); + return XGE_HAL_FAIL; + } + + for (i = 0; i < diff; i++) { + u8 byte = ((u8 *)tcp)[off+i]; + + /* Ignore No-operation 0x1 */ + if ((byte == 0x0) || (byte == 0x1)) + continue; + xge_debug_ring(XGE_ERR, "tcphdr not fastpth : pkt received with tcp options in addition to time stamp after the session is opened %02x %02x ", tcp->doff_res, tcp->ctrl); + return XGE_HAL_FAIL; + } + + /* + * Update the time stamp of LRO frame. + */ + xge_os_memcpy(((char *)lro->tcp_hdr + lro->ts_off + 2), + (char *)((char *)tcp + (*ts_off) + 2), 8); + } + + return XGE_HAL_OK; + +_exit_fail: + xge_debug_ring(XGE_ERR, "tcphdr not fastpth %02x %02x", tcp->doff_res, tcp->ctrl); + return XGE_HAL_FAIL; + +} + +/* + * __hal_lro_capable: Finds whether frame is lro capable. + * @buffer: Ethernet frame. + * @ip: ip frame. + * @tcp: tcp frame. + * @ext_info: Descriptor info. + */ +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e +__hal_lro_capable( u8 *buffer, + iplro_t **ip, + tcplro_t **tcp, + xge_hal_dtr_info_t *ext_info) +{ + u8 ip_off, ip_length; + + if (!(ext_info->proto & XGE_HAL_FRAME_PROTO_TCP)) { + xge_debug_ring(XGE_ERR, "Cant do lro %d", ext_info->proto); + return XGE_HAL_FAIL; + } + + if ( !*ip ) + { +#ifdef XGE_LL_DEBUG_DUMP_PKT + { + u8 ch; + u16 i; + + xge_os_printf("Dump Eth:" ); + for (i =0; i < 60; i++) { + ch = ntohs(*((u8 *)(buffer + i)) ); + xge_os_printf("i:%d %02x, ",i,ch); + } + } +#endif + + switch (ext_info->frame) { + case XGE_HAL_FRAME_TYPE_DIX: + ip_off = XGE_HAL_HEADER_ETHERNET_II_802_3_SIZE; + break; + case XGE_HAL_FRAME_TYPE_LLC: + ip_off = (XGE_HAL_HEADER_ETHERNET_II_802_3_SIZE + + XGE_HAL_HEADER_802_2_SIZE); + break; + case XGE_HAL_FRAME_TYPE_SNAP: + ip_off = (XGE_HAL_HEADER_ETHERNET_II_802_3_SIZE + + XGE_HAL_HEADER_SNAP_SIZE); + break; + default: // XGE_HAL_FRAME_TYPE_IPX, etc. + return XGE_HAL_FAIL; + } + + + if (ext_info->proto & XGE_HAL_FRAME_PROTO_VLAN_TAGGED) { + ip_off += XGE_HAL_HEADER_VLAN_SIZE; + } + + /* Grab ip, tcp headers */ + *ip = (iplro_t *)((char*)buffer + ip_off); + } /* !*ip */ + + ip_length = (u8)((*ip)->version_ihl & 0x0F); + ip_length = ip_length <<2; + *tcp = (tcplro_t *)((char *)*ip + ip_length); + + xge_debug_ring(XGE_TRACE, "ip_length:%d ip:"XGE_OS_LLXFMT + " tcp:"XGE_OS_LLXFMT"", (int)ip_length, + (unsigned long long)(ulong_t)*ip, (unsigned long long)(ulong_t)*tcp); + + return XGE_HAL_OK; + +} + + +/* + * __hal_open_lro_session: Open a new LRO session. + * @buffer: Ethernet frame. + * @ip: ip header. + * @tcp: tcp header. + * @lro: lro pointer + * @ext_info: Descriptor info. + * @hldev: Hal context. + * @ring_lro: LRO descriptor per rx ring. + * @slot: Bucket no. + * @tcp_seg_len: Length of tcp segment. + * @ts_off: time stamp offset in the packet. + */ +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void +__hal_open_lro_session (u8 *buffer, iplro_t *ip, tcplro_t *tcp, lro_t **lro, + xge_hal_device_t *hldev, xge_hal_lro_desc_t *ring_lro, int slot, + u32 tcp_seg_len, int ts_off) +{ + + lro_t *lro_new = &ring_lro->lro_pool[slot]; + + lro_new->in_use = 1; + lro_new->ll_hdr = buffer; + lro_new->ip_hdr = ip; + lro_new->tcp_hdr = tcp; + lro_new->tcp_next_seq_num = tcp_seg_len + xge_os_ntohl( + tcp->seq); + lro_new->tcp_seq_num = tcp->seq; + lro_new->tcp_ack_num = tcp->ack_seq; + lro_new->sg_num = 1; + lro_new->total_length = xge_os_ntohs(ip->tot_len); + lro_new->frags_len = 0; + lro_new->ts_off = ts_off; + + hldev->stats.sw_dev_info_stats.tot_frms_lroised++; + hldev->stats.sw_dev_info_stats.tot_lro_sessions++; + + *lro = ring_lro->lro_recent = lro_new; + return; +} +/* + * __hal_lro_get_free_slot: Get a free LRO bucket. + * @ring_lro: LRO descriptor per ring. + */ +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int +__hal_lro_get_free_slot (xge_hal_lro_desc_t *ring_lro) +{ + int i; + + for (i = 0; i < XGE_HAL_LRO_MAX_BUCKETS; i++) { + lro_t *lro_temp = &ring_lro->lro_pool[i]; + + if (!lro_temp->in_use) + return i; + } + return -1; +} + +/* + * __hal_get_lro_session: Gets matching LRO session or creates one. + * @eth_hdr: Ethernet header. + * @ip: ip header. + * @tcp: tcp header. + * @lro: lro pointer + * @ext_info: Descriptor info. + * @hldev: Hal context. + * @ring_lro: LRO descriptor per rx ring + */ +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e +__hal_get_lro_session (u8 *eth_hdr, + iplro_t *ip, + tcplro_t *tcp, + lro_t **lro, + xge_hal_dtr_info_t *ext_info, + xge_hal_device_t *hldev, + xge_hal_lro_desc_t *ring_lro, + lro_t **lro_end3 /* Valid only when ret=END_3 */) +{ + lro_t *lro_match; + int i, free_slot = -1; + u32 tcp_seg_len; + int ts_off = -1; + + *lro = lro_match = NULL; + /* + * Compare the incoming frame with the lro session left from the + * previous call. There is a good chance that this incoming frame + * matches the lro session. + */ + if (ring_lro->lro_recent && ring_lro->lro_recent->in_use) { + if (__hal_lro_check_for_session_match(ring_lro->lro_recent, + tcp, ip) + == XGE_HAL_OK) + lro_match = ring_lro->lro_recent; + } + + if (!lro_match) { + /* + * Search in the pool of LROs for the session that matches + * the incoming frame. + */ + for (i = 0; i < XGE_HAL_LRO_MAX_BUCKETS; i++) { + lro_t *lro_temp = &ring_lro->lro_pool[i]; + + if (!lro_temp->in_use) { + if (free_slot == -1) + free_slot = i; + continue; + } + + if (__hal_lro_check_for_session_match(lro_temp, tcp, + ip) == XGE_HAL_OK) { + lro_match = lro_temp; + break; + } + } + } + + + if (lro_match) { + /* + * Matching LRO Session found + */ + *lro = lro_match; + + if (lro_match->tcp_next_seq_num != xge_os_ntohl(tcp->seq)) { + xge_debug_ring(XGE_ERR, "**retransmit **" + "found***"); + hldev->stats.sw_dev_info_stats.lro_out_of_seq_pkt_cnt++; + return XGE_HAL_INF_LRO_END_2; + } + + if (XGE_HAL_OK != __hal_ip_lro_capable(ip, ext_info)) + { + return XGE_HAL_INF_LRO_END_2; + } + + if (XGE_HAL_OK != __hal_tcp_lro_capable(ip, tcp, lro_match, + &ts_off)) { + /* + * Close the current session and open a new + * LRO session with this packet, + * provided it has tcp payload + */ + tcp_seg_len = __hal_tcp_seg_len(ip, tcp); + if (tcp_seg_len == 0) + { + return XGE_HAL_INF_LRO_END_2; + } + + /* Get a free bucket */ + free_slot = __hal_lro_get_free_slot(ring_lro); + if (free_slot == -1) + { + return XGE_HAL_INF_LRO_END_2; + } + + /* + * Open a new LRO session + */ + __hal_open_lro_session (eth_hdr, ip, tcp, lro_end3, + hldev, ring_lro, free_slot, tcp_seg_len, + ts_off); + + return XGE_HAL_INF_LRO_END_3; + } + + /* + * The frame is good, in-sequence, can be LRO-ed; + * take its (latest) ACK - unless it is a dupack. + * Note: to be exact need to check window size as well.. + */ + if (lro_match->tcp_ack_num == tcp->ack_seq && + lro_match->tcp_seq_num == tcp->seq) { + hldev->stats.sw_dev_info_stats.lro_dup_pkt_cnt++; + return XGE_HAL_INF_LRO_END_2; + } + + lro_match->tcp_seq_num = tcp->seq; + lro_match->tcp_ack_num = tcp->ack_seq; + lro_match->frags_len += __hal_tcp_seg_len(ip, tcp); + + ring_lro->lro_recent = lro_match; + + return XGE_HAL_INF_LRO_CONT; + } + + /* ********** New Session ***************/ + if (free_slot == -1) + return XGE_HAL_INF_LRO_UNCAPABLE; + + if (XGE_HAL_FAIL == __hal_ip_lro_capable(ip, ext_info)) + return XGE_HAL_INF_LRO_UNCAPABLE; + + if (XGE_HAL_FAIL == __hal_tcp_lro_capable(ip, tcp, NULL, &ts_off)) + return XGE_HAL_INF_LRO_UNCAPABLE; + + xge_debug_ring(XGE_TRACE, "Creating lro session."); + + /* + * Open a LRO session, provided the packet contains payload. + */ + tcp_seg_len = __hal_tcp_seg_len(ip, tcp); + if (tcp_seg_len == 0) + return XGE_HAL_INF_LRO_UNCAPABLE; + + __hal_open_lro_session (eth_hdr, ip, tcp, lro, hldev, ring_lro, free_slot, + tcp_seg_len, ts_off); + + return XGE_HAL_INF_LRO_BEGIN; +} + +/* + * __hal_lro_under_optimal_thresh: Finds whether combined session is optimal. + * @ip: ip header. + * @tcp: tcp header. + * @lro: lro pointer + * @hldev: Hal context. + */ +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e +__hal_lro_under_optimal_thresh (iplro_t *ip, + tcplro_t *tcp, + lro_t *lro, + xge_hal_device_t *hldev) +{ + if (!lro) return XGE_HAL_FAIL; + + if ((lro->total_length + __hal_tcp_seg_len(ip, tcp) ) > + hldev->config.lro_frm_len) { + xge_debug_ring(XGE_TRACE, "Max LRO frame len exceeded:" + "max length %d ", hldev->config.lro_frm_len); + hldev->stats.sw_dev_info_stats.lro_frm_len_exceed_cnt++; + return XGE_HAL_FAIL; + } + + if (lro->sg_num == hldev->config.lro_sg_size) { + xge_debug_ring(XGE_TRACE, "Max sg count exceeded:" + "max sg %d ", hldev->config.lro_sg_size); + hldev->stats.sw_dev_info_stats.lro_sg_exceed_cnt++; + return XGE_HAL_FAIL; + } + + return XGE_HAL_OK; +} + +/* + * __hal_collapse_ip_hdr: Collapses ip header. + * @ip: ip header. + * @tcp: tcp header. + * @lro: lro pointer + * @hldev: Hal context. + */ +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e +__hal_collapse_ip_hdr ( iplro_t *ip, + tcplro_t *tcp, + lro_t *lro, + xge_hal_device_t *hldev) +{ + + lro->total_length += __hal_tcp_seg_len(ip, tcp); + + /* May be we have to handle time stamps or more options */ + + return XGE_HAL_OK; + +} + +/* + * __hal_collapse_tcp_hdr: Collapses tcp header. + * @ip: ip header. + * @tcp: tcp header. + * @lro: lro pointer + * @hldev: Hal context. + */ +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e +__hal_collapse_tcp_hdr ( iplro_t *ip, + tcplro_t *tcp, + lro_t *lro, + xge_hal_device_t *hldev) +{ + lro->tcp_next_seq_num += __hal_tcp_seg_len(ip, tcp); + return XGE_HAL_OK; + +} + +/* + * __hal_append_lro: Appends new frame to existing LRO session. + * @ip: ip header. + * @tcp: IN tcp header, OUT tcp payload. + * @seg_len: tcp payload length. + * @lro: lro pointer + * @hldev: Hal context. + */ +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e +__hal_append_lro(iplro_t *ip, + tcplro_t **tcp, + u32 *seg_len, + lro_t *lro, + xge_hal_device_t *hldev) +{ + (void) __hal_collapse_ip_hdr(ip, *tcp, lro, hldev); + (void) __hal_collapse_tcp_hdr(ip, *tcp, lro, hldev); + // Update mbuf chain will be done in ll driver. + // xge_hal_accumulate_large_rx on success of appending new frame to + // lro will return to ll driver tcpdata pointer, and tcp payload length. + // along with return code lro frame appended. + + lro->sg_num++; + *seg_len = __hal_tcp_seg_len(ip, *tcp); + *tcp = (tcplro_t *)((char *)*tcp + (((*tcp)->doff_res)>>2)); + + return XGE_HAL_OK; + +} + +/** + * __xge_hal_accumulate_large_rx: LRO a given frame + * frames + * @ring: rx ring number + * @eth_hdr: ethernet header. + * @ip_hdr: ip header (optional) + * @tcp: tcp header. + * @seglen: packet length. + * @p_lro: lro pointer. + * @ext_info: descriptor info, see xge_hal_dtr_info_t{}. + * @hldev: HAL device. + * @lro_end3: for lro_end3 output + * + * LRO the newly received frame, i.e. attach it (if possible) to the + * already accumulated (i.e., already LRO-ed) received frames (if any), + * to form one super-sized frame for the subsequent processing + * by the stack. + */ +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e +xge_hal_lro_process_rx(int ring, u8 *eth_hdr, u8 *ip_hdr, tcplro_t **tcp, + u32 *seglen, lro_t **p_lro, + xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev, + lro_t **lro_end3) +{ + iplro_t *ip = (iplro_t *)ip_hdr; + xge_hal_status_e ret; + lro_t *lro; + + xge_debug_ring(XGE_TRACE, "Entered accumu lro. "); + if (XGE_HAL_OK != __hal_lro_capable(eth_hdr, &ip, (tcplro_t **)tcp, + ext_info)) + return XGE_HAL_INF_LRO_UNCAPABLE; + + /* + * This function shall get matching LRO or else + * create one and return it + */ + ret = __hal_get_lro_session(eth_hdr, ip, (tcplro_t *)*tcp, + p_lro, ext_info, hldev, &hldev->lro_desc[ring], + lro_end3); + xge_debug_ring(XGE_TRACE, "ret from get_lro:%d ",ret); + lro = *p_lro; + if (XGE_HAL_INF_LRO_CONT == ret) { + if (XGE_HAL_OK == __hal_lro_under_optimal_thresh(ip, + (tcplro_t *)*tcp, lro, hldev)) { + (void) __hal_append_lro(ip,(tcplro_t **) tcp, seglen, + lro, hldev); + hldev->stats.sw_dev_info_stats.tot_frms_lroised++; + + if (lro->sg_num >= hldev->config.lro_sg_size) { + hldev->stats.sw_dev_info_stats.lro_sg_exceed_cnt++; + ret = XGE_HAL_INF_LRO_END_1; + } + + } else ret = XGE_HAL_INF_LRO_END_2; + } + + /* + * Since its time to flush, + * update ip header so that it can be sent up + */ + if ((ret == XGE_HAL_INF_LRO_END_1) || + (ret == XGE_HAL_INF_LRO_END_2) || + (ret == XGE_HAL_INF_LRO_END_3)) { + lro->ip_hdr->tot_len = xge_os_htons((*p_lro)->total_length); + lro->ip_hdr->check = xge_os_htons(0); + lro->ip_hdr->check = XGE_LL_IP_FAST_CSUM(((u8 *)(lro->ip_hdr)), + (lro->ip_hdr->version_ihl & 0x0F)); + lro->tcp_hdr->ack_seq = lro->tcp_ack_num; + } + + return (ret); +} + +/** + * xge_hal_accumulate_large_rx: LRO a given frame + * frames + * @buffer: Ethernet frame. + * @tcp: tcp header. + * @seglen: packet length. + * @p_lro: lro pointer. + * @ext_info: descriptor info, see xge_hal_dtr_info_t{}. + * @hldev: HAL device. + * @lro_end3: for lro_end3 output + * + * LRO the newly received frame, i.e. attach it (if possible) to the + * already accumulated (i.e., already LRO-ed) received frames (if any), + * to form one super-sized frame for the subsequent processing + * by the stack. + */ +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e +xge_hal_accumulate_large_rx(u8 *buffer, tcplro_t **tcp, u32 *seglen, +lro_t **p_lro, xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev, +lro_t **lro_end3) +{ + int ring = 0; + return xge_hal_lro_process_rx(ring, buffer, NULL, tcp, seglen, p_lro, + ext_info, hldev, lro_end3); +} + +/** + * xge_hal_lro_close_session: Close LRO session + * @lro: LRO Session. + * @hldev: HAL Context. + */ +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void +xge_hal_lro_close_session (lro_t *lro) +{ + lro->in_use = 0; +} + +/** + * xge_hal_lro_next_session: Returns next LRO session in the list or NULL + * if none exists. + * @hldev: HAL Context. + * @ring: rx ring number. + */ +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t * +xge_hal_lro_next_session (xge_hal_device_t *hldev, int ring) +{ +xge_hal_lro_desc_t *ring_lro = &hldev->lro_desc[ring]; + int i; + int start_idx = ring_lro->lro_next_idx; + + for(i = start_idx; i < XGE_HAL_LRO_MAX_BUCKETS; i++) { + lro_t *lro = &ring_lro->lro_pool[i]; + + if (!lro->in_use) + continue; + + lro->ip_hdr->tot_len = xge_os_htons(lro->total_length); + lro->ip_hdr->check = xge_os_htons(0); + lro->ip_hdr->check = XGE_LL_IP_FAST_CSUM(((u8 *)(lro->ip_hdr)), + (lro->ip_hdr->version_ihl & 0x0F)); + ring_lro->lro_next_idx = i + 1; + return lro; + } + + ring_lro->lro_next_idx = 0; + return NULL; + +} + +__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t * +xge_hal_lro_get_next_session(xge_hal_device_t *hldev) +{ + int ring = 0; /* assume default ring=0 */ + return xge_hal_lro_next_session(hldev, ring); +} +#endif diff --git a/sys/dev/nxge/xgehal/xgehal-device.c b/sys/dev/nxge/xgehal/xgehal-device.c new file mode 100644 index 0000000..0ba7562 --- /dev/null +++ b/sys/dev/nxge/xgehal/xgehal-device.c @@ -0,0 +1,7247 @@ +/*- + * Copyright (c) 2002-2007 Neterion, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * FileName : xgehal-device.c + * + * Description: HAL device object functionality + * + * Created: 10 May 2004 + */ + +#include +#include +#include +#include +#include +#include + +#define SWITCH_SIGN 0xA5A5A5A5A5A5A5A5ULL +#define END_SIGN 0x0 + +#ifdef XGE_HAL_HERC_EMULATION +#undef XGE_HAL_PROCESS_LINK_INT_IN_ISR +#endif + +/* + * Jenkins hash key length(in bytes) + */ +#define XGE_HAL_JHASH_MSG_LEN 50 + +/* + * mix(a,b,c) used in Jenkins hash algorithm + */ +#define mix(a,b,c) { \ + a -= b; a -= c; a ^= (c>>13); \ + b -= c; b -= a; b ^= (a<<8); \ + c -= a; c -= b; c ^= (b>>13); \ + a -= b; a -= c; a ^= (c>>12); \ + b -= c; b -= a; b ^= (a<<16); \ + c -= a; c -= b; c ^= (b>>5); \ + a -= b; a -= c; a ^= (c>>3); \ + b -= c; b -= a; b ^= (a<<10); \ + c -= a; c -= b; c ^= (b>>15); \ +} + + +/* + * __hal_device_event_queued + * @data: pointer to xge_hal_device_t structure + * + * Will be called when new event succesfully queued. + */ +void +__hal_device_event_queued(void *data, int event_type) +{ + xge_assert(((xge_hal_device_t*)data)->magic == XGE_HAL_MAGIC); + if (g_xge_hal_driver->uld_callbacks.event_queued) { + g_xge_hal_driver->uld_callbacks.event_queued(data, event_type); + } +} + +/* + * __hal_pio_mem_write32_upper + * + * Endiann-aware implementation of xge_os_pio_mem_write32(). + * Since Xframe has 64bit registers, we differintiate uppper and lower + * parts. + */ +void +__hal_pio_mem_write32_upper(pci_dev_h pdev, pci_reg_h regh, u32 val, void *addr) +{ +#if defined(XGE_OS_HOST_BIG_ENDIAN) && !defined(XGE_OS_PIO_LITTLE_ENDIAN) + xge_os_pio_mem_write32(pdev, regh, val, addr); +#else + xge_os_pio_mem_write32(pdev, regh, val, (void *)((char *)addr + 4)); +#endif +} + +/* + * __hal_pio_mem_write32_upper + * + * Endiann-aware implementation of xge_os_pio_mem_write32(). + * Since Xframe has 64bit registers, we differintiate uppper and lower + * parts. + */ +void +__hal_pio_mem_write32_lower(pci_dev_h pdev, pci_reg_h regh, u32 val, + void *addr) +{ +#if defined(XGE_OS_HOST_BIG_ENDIAN) && !defined(XGE_OS_PIO_LITTLE_ENDIAN) + xge_os_pio_mem_write32(pdev, regh, val, + (void *) ((char *)addr + 4)); +#else + xge_os_pio_mem_write32(pdev, regh, val, addr); +#endif +} + +/* + * __hal_device_register_poll + * @hldev: pointer to xge_hal_device_t structure + * @reg: register to poll for + * @op: 0 - bit reset, 1 - bit set + * @mask: mask for logical "and" condition based on %op + * @max_millis: maximum time to try to poll in milliseconds + * + * Will poll certain register for specified amount of time. + * Will poll until masked bit is not cleared. + */ +xge_hal_status_e +__hal_device_register_poll(xge_hal_device_t *hldev, u64 *reg, + int op, u64 mask, int max_millis) +{ + u64 val64; + int i = 0; + xge_hal_status_e ret = XGE_HAL_FAIL; + + xge_os_udelay(10); + + do { + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, reg); + if (op == 0 && !(val64 & mask)) + return XGE_HAL_OK; + else if (op == 1 && (val64 & mask) == mask) + return XGE_HAL_OK; + xge_os_udelay(100); + } while (++i <= 9); + + do { + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, reg); + if (op == 0 && !(val64 & mask)) + return XGE_HAL_OK; + else if (op == 1 && (val64 & mask) == mask) + return XGE_HAL_OK; + xge_os_udelay(1000); + } while (++i < max_millis); + + return ret; +} + +/* + * __hal_device_wait_quiescent + * @hldev: the device + * @hw_status: hw_status in case of error + * + * Will wait until device is quiescent for some blocks. + */ +static xge_hal_status_e +__hal_device_wait_quiescent(xge_hal_device_t *hldev, u64 *hw_status) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + + /* poll and wait first */ +#ifdef XGE_HAL_HERC_EMULATION + (void) __hal_device_register_poll(hldev, &bar0->adapter_status, 1, + (XGE_HAL_ADAPTER_STATUS_TDMA_READY | + XGE_HAL_ADAPTER_STATUS_RDMA_READY | + XGE_HAL_ADAPTER_STATUS_PFC_READY | + XGE_HAL_ADAPTER_STATUS_TMAC_BUF_EMPTY | + XGE_HAL_ADAPTER_STATUS_PIC_QUIESCENT | + XGE_HAL_ADAPTER_STATUS_MC_DRAM_READY | + XGE_HAL_ADAPTER_STATUS_MC_QUEUES_READY | + XGE_HAL_ADAPTER_STATUS_M_PLL_LOCK), + XGE_HAL_DEVICE_QUIESCENT_WAIT_MAX_MILLIS); +#else + (void) __hal_device_register_poll(hldev, &bar0->adapter_status, 1, + (XGE_HAL_ADAPTER_STATUS_TDMA_READY | + XGE_HAL_ADAPTER_STATUS_RDMA_READY | + XGE_HAL_ADAPTER_STATUS_PFC_READY | + XGE_HAL_ADAPTER_STATUS_TMAC_BUF_EMPTY | + XGE_HAL_ADAPTER_STATUS_PIC_QUIESCENT | + XGE_HAL_ADAPTER_STATUS_MC_DRAM_READY | + XGE_HAL_ADAPTER_STATUS_MC_QUEUES_READY | + XGE_HAL_ADAPTER_STATUS_M_PLL_LOCK | + XGE_HAL_ADAPTER_STATUS_P_PLL_LOCK), + XGE_HAL_DEVICE_QUIESCENT_WAIT_MAX_MILLIS); +#endif + + return xge_hal_device_status(hldev, hw_status); +} + +/** + * xge_hal_device_is_slot_freeze + * @devh: the device + * + * Returns non-zero if the slot is freezed. + * The determination is made based on the adapter_status + * register which will never give all FFs, unless PCI read + * cannot go through. + */ +int +xge_hal_device_is_slot_freeze(xge_hal_device_h devh) +{ + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u16 device_id; + u64 adapter_status = + xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->adapter_status); + xge_os_pci_read16(hldev->pdev,hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, device_id), + &device_id); +#ifdef TX_DEBUG + if (adapter_status == XGE_HAL_ALL_FOXES) + { + u64 dummy; + dummy = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->pcc_enable); + printf(">>> Slot is frozen!\n"); + brkpoint(0); + } +#endif + return((adapter_status == XGE_HAL_ALL_FOXES) || (device_id == 0xffff)); +} + + +/* + * __hal_device_led_actifity_fix + * @hldev: pointer to xge_hal_device_t structure + * + * SXE-002: Configure link and activity LED to turn it off + */ +static void +__hal_device_led_actifity_fix(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u16 subid; + u64 val64; + + xge_os_pci_read16(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, subsystem_id), &subid); + + /* + * In the case of Herc, there is a new register named beacon control + * is added which was not present in Xena. + * Beacon control register in Herc is at the same offset as + * gpio control register in Xena. It means they are one and same in + * the case of Xena. Also, gpio control register offset in Herc and + * Xena is different. + * The current register map represents Herc(It means we have + * both beacon and gpio control registers in register map). + * WRT transition from Xena to Herc, all the code in Xena which was + * using gpio control register for LED handling would have to + * use beacon control register in Herc and the rest of the code + * which uses gpio control in Xena would use the same register + * in Herc. + * WRT LED handling(following code), In the case of Herc, beacon + * control register has to be used. This is applicable for Xena also, + * since it represents the gpio control register in Xena. + */ + if ((subid & 0xFF) >= 0x07) { + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->beacon_control); + val64 |= 0x0000800000000000ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &bar0->beacon_control); + val64 = 0x0411040400000000ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + (void *) ((u8 *)bar0 + 0x2700)); + } +} + +/* Constants for Fixing the MacAddress problem seen mostly on + * Alpha machines. + */ +static u64 xena_fix_mac[] = { + 0x0060000000000000ULL, 0x0060600000000000ULL, + 0x0040600000000000ULL, 0x0000600000000000ULL, + 0x0020600000000000ULL, 0x0060600000000000ULL, + 0x0020600000000000ULL, 0x0060600000000000ULL, + 0x0020600000000000ULL, 0x0060600000000000ULL, + 0x0020600000000000ULL, 0x0060600000000000ULL, + 0x0020600000000000ULL, 0x0060600000000000ULL, + 0x0020600000000000ULL, 0x0060600000000000ULL, + 0x0020600000000000ULL, 0x0060600000000000ULL, + 0x0020600000000000ULL, 0x0060600000000000ULL, + 0x0020600000000000ULL, 0x0060600000000000ULL, + 0x0020600000000000ULL, 0x0060600000000000ULL, + 0x0020600000000000ULL, 0x0000600000000000ULL, + 0x0040600000000000ULL, 0x0060600000000000ULL, + END_SIGN +}; + +/* + * __hal_device_fix_mac + * @hldev: HAL device handle. + * + * Fix for all "FFs" MAC address problems observed on Alpha platforms. + */ +static void +__hal_device_xena_fix_mac(xge_hal_device_t *hldev) +{ + int i = 0; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + + /* + * In the case of Herc, there is a new register named beacon control + * is added which was not present in Xena. + * Beacon control register in Herc is at the same offset as + * gpio control register in Xena. It means they are one and same in + * the case of Xena. Also, gpio control register offset in Herc and + * Xena is different. + * The current register map represents Herc(It means we have + * both beacon and gpio control registers in register map). + * WRT transition from Xena to Herc, all the code in Xena which was + * using gpio control register for LED handling would have to + * use beacon control register in Herc and the rest of the code + * which uses gpio control in Xena would use the same register + * in Herc. + * In the following code(xena_fix_mac), beacon control register has + * to be used in the case of Xena, since it represents gpio control + * register. In the case of Herc, there is no change required. + */ + while (xena_fix_mac[i] != END_SIGN) { + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + xena_fix_mac[i++], &bar0->beacon_control); + xge_os_mdelay(1); + } +} + +/* + * xge_hal_device_bcast_enable + * @hldev: HAL device handle. + * + * Enable receiving broadcasts. + * The host must first write RMAC_CFG_KEY "key" + * register, and then - MAC_CFG register. + */ +void +xge_hal_device_bcast_enable(xge_hal_device_h devh) +{ + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->mac_cfg); + val64 |= XGE_HAL_MAC_RMAC_BCAST_ENABLE; + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); + + __hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0, + (u32)(val64 >> 32), &bar0->mac_cfg); + + xge_debug_device(XGE_TRACE, "mac_cfg 0x"XGE_OS_LLXFMT": broadcast %s", + (unsigned long long)val64, + hldev->config.mac.rmac_bcast_en ? "enabled" : "disabled"); +} + +/* + * xge_hal_device_bcast_disable + * @hldev: HAL device handle. + * + * Disable receiving broadcasts. + * The host must first write RMAC_CFG_KEY "key" + * register, and then - MAC_CFG register. + */ +void +xge_hal_device_bcast_disable(xge_hal_device_h devh) +{ + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->mac_cfg); + + val64 &= ~(XGE_HAL_MAC_RMAC_BCAST_ENABLE); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); + + __hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0, + (u32)(val64 >> 32), &bar0->mac_cfg); + + xge_debug_device(XGE_TRACE, "mac_cfg 0x"XGE_OS_LLXFMT": broadcast %s", + (unsigned long long)val64, + hldev->config.mac.rmac_bcast_en ? "enabled" : "disabled"); +} + +/* + * __hal_device_shared_splits_configure + * @hldev: HAL device handle. + * + * TxDMA will stop Read request if the number of read split had exceeded + * the limit set by shared_splits + */ +static void +__hal_device_shared_splits_configure(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->pic_control); + val64 |= + XGE_HAL_PIC_CNTL_SHARED_SPLITS(hldev->config.shared_splits); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->pic_control); + xge_debug_device(XGE_TRACE, "%s", "shared splits configured"); +} + +/* + * __hal_device_rmac_padding_configure + * @hldev: HAL device handle. + * + * Configure RMAC frame padding. Depends on configuration, it + * can be send to host or removed by MAC. + */ +static void +__hal_device_rmac_padding_configure(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->mac_cfg); + val64 &= ( ~XGE_HAL_MAC_RMAC_ALL_ADDR_ENABLE ); + val64 &= ( ~XGE_HAL_MAC_CFG_RMAC_PROM_ENABLE ); + val64 |= XGE_HAL_MAC_CFG_TMAC_APPEND_PAD; + + /* + * If the RTH enable bit is not set, strip the FCS + */ + if (!hldev->config.rth_en || + !(xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->rts_rth_cfg) & XGE_HAL_RTS_RTH_EN)) { + val64 |= XGE_HAL_MAC_CFG_RMAC_STRIP_FCS; + } + + val64 &= ( ~XGE_HAL_MAC_CFG_RMAC_STRIP_PAD ); + val64 |= XGE_HAL_MAC_RMAC_DISCARD_PFRM; + + __hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0, + (u32)(val64 >> 32), (char*)&bar0->mac_cfg); + xge_os_mdelay(1); + + xge_debug_device(XGE_TRACE, + "mac_cfg 0x"XGE_OS_LLXFMT": frame padding configured", + (unsigned long long)val64); +} + +/* + * __hal_device_pause_frames_configure + * @hldev: HAL device handle. + * + * Set Pause threshold. + * + * Pause frame is generated if the amount of data outstanding + * on any queue exceeded the ratio of + * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256 + */ +static void +__hal_device_pause_frames_configure(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + int i; + u64 val64; + + switch (hldev->config.mac.media) { + case XGE_HAL_MEDIA_SR: + case XGE_HAL_MEDIA_SW: + val64=0xfffbfffbfffbfffbULL; + break; + case XGE_HAL_MEDIA_LR: + case XGE_HAL_MEDIA_LW: + val64=0xffbbffbbffbbffbbULL; + break; + case XGE_HAL_MEDIA_ER: + case XGE_HAL_MEDIA_EW: + default: + val64=0xffbbffbbffbbffbbULL; + break; + } + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &bar0->mc_pause_thresh_q0q3); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &bar0->mc_pause_thresh_q4q7); + + /* Set the time value to be inserted in the pause frame generated + * by Xframe */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->rmac_pause_cfg); + if (hldev->config.mac.rmac_pause_gen_en) + val64 |= XGE_HAL_RMAC_PAUSE_GEN_EN; + else + val64 &= ~(XGE_HAL_RMAC_PAUSE_GEN_EN); + if (hldev->config.mac.rmac_pause_rcv_en) + val64 |= XGE_HAL_RMAC_PAUSE_RCV_EN; + else + val64 &= ~(XGE_HAL_RMAC_PAUSE_RCV_EN); + val64 &= ~(XGE_HAL_RMAC_PAUSE_HG_PTIME(0xffff)); + val64 |= XGE_HAL_RMAC_PAUSE_HG_PTIME(hldev->config.mac.rmac_pause_time); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rmac_pause_cfg); + + val64 = 0; + for (i = 0; i<4; i++) { + val64 |= + (((u64)0xFF00|hldev->config.mac.mc_pause_threshold_q0q3) + <<(i*2*8)); + } + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->mc_pause_thresh_q0q3); + + val64 = 0; + for (i = 0; i<4; i++) { + val64 |= + (((u64)0xFF00|hldev->config.mac.mc_pause_threshold_q4q7) + <<(i*2*8)); + } + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->mc_pause_thresh_q4q7); + xge_debug_device(XGE_TRACE, "%s", "pause frames configured"); +} + +/* + * Herc's clock rate doubled, unless the slot is 33MHz. + */ +unsigned int __hal_fix_time_ival_herc(xge_hal_device_t *hldev, + unsigned int time_ival) +{ + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA) + return time_ival; + + xge_assert(xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC); + + if (hldev->bus_frequency != XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN && + hldev->bus_frequency != XGE_HAL_PCI_BUS_FREQUENCY_33MHZ) + time_ival *= 2; + + return time_ival; +} + + +/* + * __hal_device_bus_master_disable + * @hldev: HAL device handle. + * + * Disable bus mastership. + */ +static void +__hal_device_bus_master_disable (xge_hal_device_t *hldev) +{ + u16 cmd; + u16 bus_master = 4; + + xge_os_pci_read16(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, command), &cmd); + cmd &= ~bus_master; + xge_os_pci_write16(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, command), cmd); +} + +/* + * __hal_device_bus_master_enable + * @hldev: HAL device handle. + * + * Disable bus mastership. + */ +static void +__hal_device_bus_master_enable (xge_hal_device_t *hldev) +{ + u16 cmd; + u16 bus_master = 4; + + xge_os_pci_read16(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, command), &cmd); + + /* already enabled? do nothing */ + if (cmd & bus_master) + return; + + cmd |= bus_master; + xge_os_pci_write16(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, command), cmd); +} +/* + * __hal_device_intr_mgmt + * @hldev: HAL device handle. + * @mask: mask indicating which Intr block must be modified. + * @flag: if true - enable, otherwise - disable interrupts. + * + * Disable or enable device interrupts. Mask is used to specify + * which hardware blocks should produce interrupts. For details + * please refer to Xframe User Guide. + */ +static void +__hal_device_intr_mgmt(xge_hal_device_t *hldev, u64 mask, int flag) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64 = 0, temp64 = 0; + u64 gim, gim_saved; + + gim_saved = gim = xge_os_pio_mem_read64(hldev->pdev, + hldev->regh0, &bar0->general_int_mask); + + /* Top level interrupt classification */ + /* PIC Interrupts */ + if ((mask & (XGE_HAL_TX_PIC_INTR/* | XGE_HAL_RX_PIC_INTR*/))) { + /* Enable PIC Intrs in the general intr mask register */ + val64 = XGE_HAL_TXPIC_INT_M/* | XGE_HAL_PIC_RX_INT_M*/; + if (flag) { + gim &= ~((u64) val64); + temp64 = xge_os_pio_mem_read64(hldev->pdev, + hldev->regh0, &bar0->pic_int_mask); + + temp64 &= ~XGE_HAL_PIC_INT_TX; +#ifdef XGE_HAL_PROCESS_LINK_INT_IN_ISR + if (xge_hal_device_check_id(hldev) == + XGE_HAL_CARD_HERC) { + temp64 &= ~XGE_HAL_PIC_INT_MISC; + } +#endif + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + temp64, &bar0->pic_int_mask); +#ifdef XGE_HAL_PROCESS_LINK_INT_IN_ISR + if (xge_hal_device_check_id(hldev) == + XGE_HAL_CARD_HERC) { + /* + * Unmask only Link Up interrupt + */ + temp64 = xge_os_pio_mem_read64(hldev->pdev, + hldev->regh0, &bar0->misc_int_mask); + temp64 &= ~XGE_HAL_MISC_INT_REG_LINK_UP_INT; + xge_os_pio_mem_write64(hldev->pdev, + hldev->regh0, temp64, + &bar0->misc_int_mask); + xge_debug_device(XGE_TRACE, + "unmask link up flag "XGE_OS_LLXFMT, + (unsigned long long)temp64); + } +#endif + } else { /* flag == 0 */ + +#ifdef XGE_HAL_PROCESS_LINK_INT_IN_ISR + if (xge_hal_device_check_id(hldev) == + XGE_HAL_CARD_HERC) { + /* + * Mask both Link Up and Down interrupts + */ + temp64 = xge_os_pio_mem_read64(hldev->pdev, + hldev->regh0, &bar0->misc_int_mask); + temp64 |= XGE_HAL_MISC_INT_REG_LINK_UP_INT; + temp64 |= XGE_HAL_MISC_INT_REG_LINK_DOWN_INT; + xge_os_pio_mem_write64(hldev->pdev, + hldev->regh0, temp64, + &bar0->misc_int_mask); + xge_debug_device(XGE_TRACE, + "mask link up/down flag "XGE_OS_LLXFMT, + (unsigned long long)temp64); + } +#endif + /* Disable PIC Intrs in the general intr mask + * register */ + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_ALL_INTRS_DIS, + &bar0->pic_int_mask); + gim |= val64; + } + } + + /* DMA Interrupts */ + /* Enabling/Disabling Tx DMA interrupts */ + if (mask & XGE_HAL_TX_DMA_INTR) { + /* Enable TxDMA Intrs in the general intr mask register */ + val64 = XGE_HAL_TXDMA_INT_M; + if (flag) { + gim &= ~((u64) val64); + /* Enable all TxDMA interrupts */ + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + 0x0, &bar0->txdma_int_mask); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + 0x0, &bar0->pfc_err_mask); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + 0x0, &bar0->tda_err_mask); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + 0x0, &bar0->pcc_err_mask); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + 0x0, &bar0->tti_err_mask); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + 0x0, &bar0->lso_err_mask); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + 0x0, &bar0->tpa_err_mask); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + 0x0, &bar0->sm_err_mask); + + } else { /* flag == 0 */ + + /* Disable TxDMA Intrs in the general intr mask + * register */ + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_ALL_INTRS_DIS, + &bar0->txdma_int_mask); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_ALL_INTRS_DIS, + &bar0->pfc_err_mask); + + gim |= val64; + } + } + + /* Enabling/Disabling Rx DMA interrupts */ + if (mask & XGE_HAL_RX_DMA_INTR) { + /* Enable RxDMA Intrs in the general intr mask register */ + val64 = XGE_HAL_RXDMA_INT_M; + if (flag) { + + gim &= ~((u64) val64); + /* All RxDMA block interrupts are disabled for now + * TODO */ + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_ALL_INTRS_DIS, + &bar0->rxdma_int_mask); + + } else { /* flag == 0 */ + + /* Disable RxDMA Intrs in the general intr mask + * register */ + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_ALL_INTRS_DIS, + &bar0->rxdma_int_mask); + + gim |= val64; + } + } + + /* MAC Interrupts */ + /* Enabling/Disabling MAC interrupts */ + if (mask & (XGE_HAL_TX_MAC_INTR | XGE_HAL_RX_MAC_INTR)) { + val64 = XGE_HAL_TXMAC_INT_M | XGE_HAL_RXMAC_INT_M; + if (flag) { + + gim &= ~((u64) val64); + + /* All MAC block error inter. are disabled for now. */ + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_ALL_INTRS_DIS, &bar0->mac_int_mask); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_ALL_INTRS_DIS, &bar0->mac_rmac_err_mask); + + } else { /* flag == 0 */ + + /* Disable MAC Intrs in the general intr mask + * register */ + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_ALL_INTRS_DIS, &bar0->mac_int_mask); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_ALL_INTRS_DIS, &bar0->mac_rmac_err_mask); + + gim |= val64; + } + } + + /* XGXS Interrupts */ + if (mask & (XGE_HAL_TX_XGXS_INTR | XGE_HAL_RX_XGXS_INTR)) { + val64 = XGE_HAL_TXXGXS_INT_M | XGE_HAL_RXXGXS_INT_M; + if (flag) { + + gim &= ~((u64) val64); + /* All XGXS block error interrupts are disabled for now + * TODO */ + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_ALL_INTRS_DIS, &bar0->xgxs_int_mask); + + } else { /* flag == 0 */ + + /* Disable MC Intrs in the general intr mask register */ + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_ALL_INTRS_DIS, &bar0->xgxs_int_mask); + + gim |= val64; + } + } + + /* Memory Controller(MC) interrupts */ + if (mask & XGE_HAL_MC_INTR) { + val64 = XGE_HAL_MC_INT_M; + if (flag) { + + gim &= ~((u64) val64); + + /* Enable all MC blocks error interrupts */ + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + 0x0ULL, &bar0->mc_int_mask); + + } else { /* flag == 0 */ + + /* Disable MC Intrs in the general intr mask + * register */ + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_ALL_INTRS_DIS, &bar0->mc_int_mask); + + gim |= val64; + } + } + + + /* Tx traffic interrupts */ + if (mask & XGE_HAL_TX_TRAFFIC_INTR) { + val64 = XGE_HAL_TXTRAFFIC_INT_M; + if (flag) { + + gim &= ~((u64) val64); + + /* Enable all the Tx side interrupts */ + /* '0' Enables all 64 TX interrupt levels. */ + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, 0x0, + &bar0->tx_traffic_mask); + + } else { /* flag == 0 */ + + /* Disable Tx Traffic Intrs in the general intr mask + * register. */ + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_ALL_INTRS_DIS, + &bar0->tx_traffic_mask); + gim |= val64; + } + } + + /* Rx traffic interrupts */ + if (mask & XGE_HAL_RX_TRAFFIC_INTR) { + val64 = XGE_HAL_RXTRAFFIC_INT_M; + if (flag) { + gim &= ~((u64) val64); + /* '0' Enables all 8 RX interrupt levels. */ + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, 0x0, + &bar0->rx_traffic_mask); + + } else { /* flag == 0 */ + + /* Disable Rx Traffic Intrs in the general intr mask + * register. + */ + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_ALL_INTRS_DIS, + &bar0->rx_traffic_mask); + + gim |= val64; + } + } + + /* Sched Timer interrupt */ + if (mask & XGE_HAL_SCHED_INTR) { + if (flag) { + temp64 = xge_os_pio_mem_read64(hldev->pdev, + hldev->regh0, &bar0->txpic_int_mask); + temp64 &= ~XGE_HAL_TXPIC_INT_SCHED_INTR; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + temp64, &bar0->txpic_int_mask); + + xge_hal_device_sched_timer(hldev, + hldev->config.sched_timer_us, + hldev->config.sched_timer_one_shot); + } else { + temp64 = xge_os_pio_mem_read64(hldev->pdev, + hldev->regh0, &bar0->txpic_int_mask); + temp64 |= XGE_HAL_TXPIC_INT_SCHED_INTR; + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + temp64, &bar0->txpic_int_mask); + + xge_hal_device_sched_timer(hldev, + XGE_HAL_SCHED_TIMER_DISABLED, + XGE_HAL_SCHED_TIMER_ON_SHOT_ENABLE); + } + } + + if (gim != gim_saved) { + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, gim, + &bar0->general_int_mask); + xge_debug_device(XGE_TRACE, "general_int_mask updated " + XGE_OS_LLXFMT" => "XGE_OS_LLXFMT, + (unsigned long long)gim_saved, (unsigned long long)gim); + } +} + +/* + * __hal_device_bimodal_configure + * @hldev: HAL device handle. + * + * Bimodal parameters initialization. + */ +static void +__hal_device_bimodal_configure(xge_hal_device_t *hldev) +{ + int i; + + for (i=0; iconfig.ring.queue[i].configured) + continue; + rti = &hldev->config.ring.queue[i].rti; + tti = &hldev->bimodal_tti[i]; + + tti->enabled = 1; + tti->urange_a = hldev->bimodal_urange_a_en * 10; + tti->urange_b = 20; + tti->urange_c = 30; + tti->ufc_a = hldev->bimodal_urange_a_en * 8; + tti->ufc_b = 16; + tti->ufc_c = 32; + tti->ufc_d = 64; + tti->timer_val_us = hldev->bimodal_timer_val_us; + tti->timer_ac_en = 1; + tti->timer_ci_en = 0; + + rti->urange_a = 10; + rti->urange_b = 20; + rti->urange_c = 30; + rti->ufc_a = 1; /* <= for netpipe type of tests */ + rti->ufc_b = 4; + rti->ufc_c = 4; + rti->ufc_d = 4; /* <= 99% of a bandwidth traffic counts here */ + rti->timer_ac_en = 1; + rti->timer_val_us = 5; /* for optimal bus efficiency usage */ + } +} + +/* + * __hal_device_tti_apply + * @hldev: HAL device handle. + * + * apply TTI configuration. + */ +static xge_hal_status_e +__hal_device_tti_apply(xge_hal_device_t *hldev, xge_hal_tti_config_t *tti, + int num, int runtime) +{ + u64 val64, data1 = 0, data2 = 0; + xge_hal_pci_bar0_t *bar0; + + if (runtime) + bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->isrbar0; + else + bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + + if (tti->timer_val_us) { + unsigned int tx_interval; + + if (hldev->config.pci_freq_mherz) { + tx_interval = hldev->config.pci_freq_mherz * + tti->timer_val_us / 64; + tx_interval = + __hal_fix_time_ival_herc(hldev, + tx_interval); + } else { + tx_interval = tti->timer_val_us; + } + data1 |= XGE_HAL_TTI_DATA1_MEM_TX_TIMER_VAL(tx_interval); + if (tti->timer_ac_en) { + data1 |= XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_EN; + } + if (tti->timer_ci_en) { + data1 |= XGE_HAL_TTI_DATA1_MEM_TX_TIMER_CI_EN; + } + + if (!runtime) { + xge_debug_device(XGE_TRACE, "TTI[%d] timer enabled to %d, ci %s", + num, tx_interval, tti->timer_ci_en ? + "enabled": "disabled"); + } + } + + if (tti->urange_a || + tti->urange_b || + tti->urange_c || + tti->ufc_a || + tti->ufc_b || + tti->ufc_c || + tti->ufc_d ) { + data1 |= XGE_HAL_TTI_DATA1_MEM_TX_URNG_A(tti->urange_a) | + XGE_HAL_TTI_DATA1_MEM_TX_URNG_B(tti->urange_b) | + XGE_HAL_TTI_DATA1_MEM_TX_URNG_C(tti->urange_c); + + data2 |= XGE_HAL_TTI_DATA2_MEM_TX_UFC_A(tti->ufc_a) | + XGE_HAL_TTI_DATA2_MEM_TX_UFC_B(tti->ufc_b) | + XGE_HAL_TTI_DATA2_MEM_TX_UFC_C(tti->ufc_c) | + XGE_HAL_TTI_DATA2_MEM_TX_UFC_D(tti->ufc_d); + } + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, data1, + &bar0->tti_data1_mem); + (void)xge_os_pio_mem_read64(hldev->pdev, + hldev->regh0, &bar0->tti_data1_mem); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, data2, + &bar0->tti_data2_mem); + (void)xge_os_pio_mem_read64(hldev->pdev, + hldev->regh0, &bar0->tti_data2_mem); + xge_os_wmb(); + + val64 = XGE_HAL_TTI_CMD_MEM_WE | XGE_HAL_TTI_CMD_MEM_STROBE_NEW_CMD | + XGE_HAL_TTI_CMD_MEM_OFFSET(num); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->tti_command_mem); + + if (!runtime && __hal_device_register_poll(hldev, &bar0->tti_command_mem, + 0, XGE_HAL_TTI_CMD_MEM_STROBE_NEW_CMD, + XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS) != XGE_HAL_OK) { + /* upper layer may require to repeat */ + return XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING; + } + + if (!runtime) { + xge_debug_device(XGE_TRACE, "TTI[%d] configured: tti_data1_mem 0x" + XGE_OS_LLXFMT, num, + (unsigned long long)xge_os_pio_mem_read64(hldev->pdev, + hldev->regh0, &bar0->tti_data1_mem)); + } + + return XGE_HAL_OK; +} + +/* + * __hal_device_tti_configure + * @hldev: HAL device handle. + * + * TTI Initialization. + * Initialize Transmit Traffic Interrupt Scheme. + */ +static xge_hal_status_e +__hal_device_tti_configure(xge_hal_device_t *hldev, int runtime) +{ + int i; + + for (i=0; iconfig.fifo.queue[i].configured) + continue; + + for (j=0; jconfig.fifo.queue[i].tti[j].enabled) + continue; + + /* at least some TTI enabled. Record it. */ + hldev->tti_enabled = 1; + + status = __hal_device_tti_apply(hldev, + &hldev->config.fifo.queue[i].tti[j], + i * XGE_HAL_MAX_FIFO_TTI_NUM + j, runtime); + if (status != XGE_HAL_OK) + return status; + } + } + + /* processing bimodal TTIs */ + for (i=0; ibimodal_tti[i].enabled) + continue; + + /* at least some bimodal TTI enabled. Record it. */ + hldev->tti_enabled = 1; + + status = __hal_device_tti_apply(hldev, &hldev->bimodal_tti[i], + XGE_HAL_MAX_FIFO_TTI_RING_0 + i, runtime); + if (status != XGE_HAL_OK) + return status; + + } + + return XGE_HAL_OK; +} + +/* + * __hal_device_rti_configure + * @hldev: HAL device handle. + * + * RTI Initialization. + * Initialize Receive Traffic Interrupt Scheme. + */ +xge_hal_status_e +__hal_device_rti_configure(xge_hal_device_t *hldev, int runtime) +{ + xge_hal_pci_bar0_t *bar0; + u64 val64, data1 = 0, data2 = 0; + int i; + + if (runtime) { + /* + * we don't want to re-configure RTI in case when + * bimodal interrupts are in use. Instead reconfigure TTI + * with new RTI values. + */ + if (hldev->config.bimodal_interrupts) { + __hal_device_bimodal_configure(hldev); + return __hal_device_tti_configure(hldev, 1); + } + bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->isrbar0; + } else + bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + + for (i=0; iconfig.ring.queue[i].rti; + + if (!hldev->config.ring.queue[i].configured) + continue; + + if (rti->timer_val_us) { + unsigned int rx_interval; + + if (hldev->config.pci_freq_mherz) { + rx_interval = hldev->config.pci_freq_mherz * + rti->timer_val_us / 8; + rx_interval = + __hal_fix_time_ival_herc(hldev, + rx_interval); + } else { + rx_interval = rti->timer_val_us; + } + data1 |=XGE_HAL_RTI_DATA1_MEM_RX_TIMER_VAL(rx_interval); + if (rti->timer_ac_en) { + data1 |= XGE_HAL_RTI_DATA1_MEM_RX_TIMER_AC_EN; + } + data1 |= XGE_HAL_RTI_DATA1_MEM_RX_TIMER_CI_EN; + } + + if (rti->urange_a || + rti->urange_b || + rti->urange_c || + rti->ufc_a || + rti->ufc_b || + rti->ufc_c || + rti->ufc_d) { + data1 |=XGE_HAL_RTI_DATA1_MEM_RX_URNG_A(rti->urange_a) | + XGE_HAL_RTI_DATA1_MEM_RX_URNG_B(rti->urange_b) | + XGE_HAL_RTI_DATA1_MEM_RX_URNG_C(rti->urange_c); + + data2 |= XGE_HAL_RTI_DATA2_MEM_RX_UFC_A(rti->ufc_a) | + XGE_HAL_RTI_DATA2_MEM_RX_UFC_B(rti->ufc_b) | + XGE_HAL_RTI_DATA2_MEM_RX_UFC_C(rti->ufc_c) | + XGE_HAL_RTI_DATA2_MEM_RX_UFC_D(rti->ufc_d); + } + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, data1, + &bar0->rti_data1_mem); + (void)xge_os_pio_mem_read64(hldev->pdev, + hldev->regh0, &bar0->rti_data1_mem); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, data2, + &bar0->rti_data2_mem); + (void)xge_os_pio_mem_read64(hldev->pdev, + hldev->regh0, &bar0->rti_data2_mem); + xge_os_wmb(); + + val64 = XGE_HAL_RTI_CMD_MEM_WE | + XGE_HAL_RTI_CMD_MEM_STROBE_NEW_CMD; + val64 |= XGE_HAL_RTI_CMD_MEM_OFFSET(i); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rti_command_mem); + + if (!runtime && __hal_device_register_poll(hldev, + &bar0->rti_command_mem, 0, + XGE_HAL_RTI_CMD_MEM_STROBE_NEW_CMD, + XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS) != XGE_HAL_OK) { + /* upper layer may require to repeat */ + return XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING; + } + + if (!runtime) { + xge_debug_device(XGE_TRACE, + "RTI[%d] configured: rti_data1_mem 0x"XGE_OS_LLXFMT, + i, + (unsigned long long)xge_os_pio_mem_read64(hldev->pdev, + hldev->regh0, &bar0->rti_data1_mem)); + } + } + + return XGE_HAL_OK; +} + + +/* Constants to be programmed into the Xena's registers to configure + * the XAUI. */ +static u64 default_xena_mdio_cfg[] = { + /* Reset PMA PLL */ + 0xC001010000000000ULL, 0xC0010100000000E0ULL, + 0xC0010100008000E4ULL, + /* Remove Reset from PMA PLL */ + 0xC001010000000000ULL, 0xC0010100000000E0ULL, + 0xC0010100000000E4ULL, + END_SIGN +}; + +static u64 default_herc_mdio_cfg[] = { + END_SIGN +}; + +static u64 default_xena_dtx_cfg[] = { + 0x8000051500000000ULL, 0x80000515000000E0ULL, + 0x80000515D93500E4ULL, 0x8001051500000000ULL, + 0x80010515000000E0ULL, 0x80010515001E00E4ULL, + 0x8002051500000000ULL, 0x80020515000000E0ULL, + 0x80020515F21000E4ULL, + /* Set PADLOOPBACKN */ + 0x8002051500000000ULL, 0x80020515000000E0ULL, + 0x80020515B20000E4ULL, 0x8003051500000000ULL, + 0x80030515000000E0ULL, 0x80030515B20000E4ULL, + 0x8004051500000000ULL, 0x80040515000000E0ULL, + 0x80040515B20000E4ULL, 0x8005051500000000ULL, + 0x80050515000000E0ULL, 0x80050515B20000E4ULL, + SWITCH_SIGN, + /* Remove PADLOOPBACKN */ + 0x8002051500000000ULL, 0x80020515000000E0ULL, + 0x80020515F20000E4ULL, 0x8003051500000000ULL, + 0x80030515000000E0ULL, 0x80030515F20000E4ULL, + 0x8004051500000000ULL, 0x80040515000000E0ULL, + 0x80040515F20000E4ULL, 0x8005051500000000ULL, + 0x80050515000000E0ULL, 0x80050515F20000E4ULL, + END_SIGN +}; + +/* +static u64 default_herc_dtx_cfg[] = { + 0x80000515BA750000ULL, 0x80000515BA7500E0ULL, + 0x80000515BA750004ULL, 0x80000515BA7500E4ULL, + 0x80010515003F0000ULL, 0x80010515003F00E0ULL, + 0x80010515003F0004ULL, 0x80010515003F00E4ULL, + 0x80020515F2100000ULL, 0x80020515F21000E0ULL, + 0x80020515F2100004ULL, 0x80020515F21000E4ULL, + END_SIGN +}; +*/ + +static u64 default_herc_dtx_cfg[] = { + 0x8000051536750000ULL, 0x80000515367500E0ULL, + 0x8000051536750004ULL, 0x80000515367500E4ULL, + + 0x80010515003F0000ULL, 0x80010515003F00E0ULL, + 0x80010515003F0004ULL, 0x80010515003F00E4ULL, + + 0x801205150D440000ULL, 0x801205150D4400E0ULL, + 0x801205150D440004ULL, 0x801205150D4400E4ULL, + + 0x80020515F2100000ULL, 0x80020515F21000E0ULL, + 0x80020515F2100004ULL, 0x80020515F21000E4ULL, + END_SIGN +}; + + +void +__hal_serial_mem_write64(xge_hal_device_t *hldev, u64 value, u64 *reg) +{ + __hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0, + (u32)(value>>32), reg); + xge_os_wmb(); + __hal_pio_mem_write32_lower(hldev->pdev, hldev->regh0, + (u32)value, reg); + xge_os_wmb(); + xge_os_mdelay(1); +} + +u64 +__hal_serial_mem_read64(xge_hal_device_t *hldev, u64 *reg) +{ + u64 val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + reg); + xge_os_mdelay(1); + return val64; +} + +/* + * __hal_device_xaui_configure + * @hldev: HAL device handle. + * + * Configure XAUI Interface of Xena. + * + * To Configure the Xena's XAUI, one has to write a series + * of 64 bit values into two registers in a particular + * sequence. Hence a macro 'SWITCH_SIGN' has been defined + * which will be defined in the array of configuration values + * (default_dtx_cfg & default_mdio_cfg) at appropriate places + * to switch writing from one regsiter to another. We continue + * writing these values until we encounter the 'END_SIGN' macro. + * For example, After making a series of 21 writes into + * dtx_control register the 'SWITCH_SIGN' appears and hence we + * start writing into mdio_control until we encounter END_SIGN. + */ +static void +__hal_device_xaui_configure(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + int mdio_cnt = 0, dtx_cnt = 0; + u64 *default_dtx_cfg = NULL, *default_mdio_cfg = NULL; + + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA) { + default_dtx_cfg = default_xena_dtx_cfg; + default_mdio_cfg = default_xena_mdio_cfg; + } else if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) { + default_dtx_cfg = default_herc_dtx_cfg; + default_mdio_cfg = default_herc_mdio_cfg; + } else { + xge_assert(default_dtx_cfg); + return; + } + + do { + dtx_cfg: + while (default_dtx_cfg[dtx_cnt] != END_SIGN) { + if (default_dtx_cfg[dtx_cnt] == SWITCH_SIGN) { + dtx_cnt++; + goto mdio_cfg; + } + __hal_serial_mem_write64(hldev, default_dtx_cfg[dtx_cnt], + &bar0->dtx_control); + dtx_cnt++; + } + mdio_cfg: + while (default_mdio_cfg[mdio_cnt] != END_SIGN) { + if (default_mdio_cfg[mdio_cnt] == SWITCH_SIGN) { + mdio_cnt++; + goto dtx_cfg; + } + __hal_serial_mem_write64(hldev, default_mdio_cfg[mdio_cnt], + &bar0->mdio_control); + mdio_cnt++; + } + } while ( !((default_dtx_cfg[dtx_cnt] == END_SIGN) && + (default_mdio_cfg[mdio_cnt] == END_SIGN)) ); + + xge_debug_device(XGE_TRACE, "%s", "XAUI interface configured"); +} + +/* + * __hal_device_mac_link_util_set + * @hldev: HAL device handle. + * + * Set sampling rate to calculate link utilization. + */ +static void +__hal_device_mac_link_util_set(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + + val64 = XGE_HAL_MAC_TX_LINK_UTIL_VAL( + hldev->config.mac.tmac_util_period) | + XGE_HAL_MAC_RX_LINK_UTIL_VAL( + hldev->config.mac.rmac_util_period); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->mac_link_util); + xge_debug_device(XGE_TRACE, "%s", + "bandwidth link utilization configured"); +} + +/* + * __hal_device_set_swapper + * @hldev: HAL device handle. + * + * Set the Xframe's byte "swapper" in accordance with + * endianness of the host. + */ +xge_hal_status_e +__hal_device_set_swapper(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + + /* + * from 32bit errarta: + * + * The SWAPPER_CONTROL register determines how the adapter accesses + * host memory as well as how it responds to read and write requests + * from the host system. Writes to this register should be performed + * carefully, since the byte swappers could reverse the order of bytes. + * When configuring this register keep in mind that writes to the PIF + * read and write swappers could reverse the order of the upper and + * lower 32-bit words. This means that the driver may have to write + * to the upper 32 bits of the SWAPPER_CONTROL twice in order to + * configure the entire register. */ + + /* + * The device by default set to a big endian format, so a big endian + * driver need not set anything. + */ + +#if defined(XGE_HAL_CUSTOM_HW_SWAPPER) + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + 0xffffffffffffffffULL, &bar0->swapper_ctrl); + + val64 = XGE_HAL_CUSTOM_HW_SWAPPER; + + xge_os_wmb(); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->swapper_ctrl); + + xge_debug_device(XGE_TRACE, "using custom HW swapper 0x"XGE_OS_LLXFMT, + (unsigned long long)val64); + +#elif !defined(XGE_OS_HOST_BIG_ENDIAN) + + /* + * Initially we enable all bits to make it accessible by the driver, + * then we selectively enable only those bits that we want to set. + * i.e. force swapper to swap for the first time since second write + * will overwrite with the final settings. + * + * Use only for little endian platforms. + */ + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + 0xffffffffffffffffULL, &bar0->swapper_ctrl); + xge_os_wmb(); + val64 = (XGE_HAL_SWAPPER_CTRL_PIF_R_FE | + XGE_HAL_SWAPPER_CTRL_PIF_R_SE | + XGE_HAL_SWAPPER_CTRL_PIF_W_FE | + XGE_HAL_SWAPPER_CTRL_PIF_W_SE | + XGE_HAL_SWAPPER_CTRL_RTH_FE | + XGE_HAL_SWAPPER_CTRL_RTH_SE | + XGE_HAL_SWAPPER_CTRL_TXP_FE | + XGE_HAL_SWAPPER_CTRL_TXP_SE | + XGE_HAL_SWAPPER_CTRL_TXD_R_FE | + XGE_HAL_SWAPPER_CTRL_TXD_R_SE | + XGE_HAL_SWAPPER_CTRL_TXD_W_FE | + XGE_HAL_SWAPPER_CTRL_TXD_W_SE | + XGE_HAL_SWAPPER_CTRL_TXF_R_FE | + XGE_HAL_SWAPPER_CTRL_RXD_R_FE | + XGE_HAL_SWAPPER_CTRL_RXD_R_SE | + XGE_HAL_SWAPPER_CTRL_RXD_W_FE | + XGE_HAL_SWAPPER_CTRL_RXD_W_SE | + XGE_HAL_SWAPPER_CTRL_RXF_W_FE | + XGE_HAL_SWAPPER_CTRL_XMSI_FE | + XGE_HAL_SWAPPER_CTRL_STATS_FE | XGE_HAL_SWAPPER_CTRL_STATS_SE); + + /* + if (hldev->config.intr_mode == XGE_HAL_INTR_MODE_MSIX) { + val64 |= XGE_HAL_SWAPPER_CTRL_XMSI_SE; + } */ + __hal_pio_mem_write32_lower(hldev->pdev, hldev->regh0, (u32)val64, + &bar0->swapper_ctrl); + xge_os_wmb(); + __hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0, (u32)(val64>>32), + &bar0->swapper_ctrl); + xge_os_wmb(); + __hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0, (u32)(val64>>32), + &bar0->swapper_ctrl); + xge_debug_device(XGE_TRACE, "%s", "using little endian set"); +#endif + + /* Verifying if endian settings are accurate by reading a feedback + * register. */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->pif_rd_swapper_fb); + if (val64 != XGE_HAL_IF_RD_SWAPPER_FB) { + xge_debug_device(XGE_ERR, "pif_rd_swapper_fb read "XGE_OS_LLXFMT, + (unsigned long long) val64); + return XGE_HAL_ERR_SWAPPER_CTRL; + } + + xge_debug_device(XGE_TRACE, "%s", "be/le swapper enabled"); + + return XGE_HAL_OK; +} + +/* + * __hal_device_rts_mac_configure - Configure RTS steering based on + * destination mac address. + * @hldev: HAL device handle. + * + */ +xge_hal_status_e +__hal_device_rts_mac_configure(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + + if (!hldev->config.rts_mac_en) { + return XGE_HAL_OK; + } + + /* + * Set the receive traffic steering mode from default(classic) + * to enhanced. + */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->rts_ctrl); + val64 |= XGE_HAL_RTS_CTRL_ENHANCED_MODE; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &bar0->rts_ctrl); + return XGE_HAL_OK; +} + +/* + * __hal_device_rts_port_configure - Configure RTS steering based on + * destination or source port number. + * @hldev: HAL device handle. + * + */ +xge_hal_status_e +__hal_device_rts_port_configure(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + int rnum; + + if (!hldev->config.rts_port_en) { + return XGE_HAL_OK; + } + + /* + * Set the receive traffic steering mode from default(classic) + * to enhanced. + */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->rts_ctrl); + val64 |= XGE_HAL_RTS_CTRL_ENHANCED_MODE; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &bar0->rts_ctrl); + + /* + * Initiate port steering according to per-ring configuration + */ + for (rnum = 0; rnum < XGE_HAL_MAX_RING_NUM; rnum++) { + int pnum; + xge_hal_ring_queue_t *queue = &hldev->config.ring.queue[rnum]; + + if (!queue->configured || queue->rts_port_en) + continue; + + for (pnum = 0; pnum < XGE_HAL_MAX_STEERABLE_PORTS; pnum++) { + xge_hal_rts_port_t *port = &queue->rts_ports[pnum]; + + /* + * Skip and clear empty ports + */ + if (!port->num) { + /* + * Clear CAM memory + */ + xge_os_pio_mem_write64(hldev->pdev, + hldev->regh0, 0ULL, + &bar0->rts_pn_cam_data); + + val64 = BIT(7) | BIT(15); + } else { + /* + * Assign new Port values according + * to configuration + */ + val64 = vBIT(port->num,8,16) | + vBIT(rnum,37,3) | BIT(63); + if (port->src) + val64 = BIT(47); + if (!port->udp) + val64 = BIT(7); + xge_os_pio_mem_write64(hldev->pdev, + hldev->regh0, val64, + &bar0->rts_pn_cam_data); + + val64 = BIT(7) | BIT(15) | vBIT(pnum,24,8); + } + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &bar0->rts_pn_cam_ctrl); + + /* poll until done */ + if (__hal_device_register_poll(hldev, + &bar0->rts_pn_cam_ctrl, 0, + XGE_HAL_RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED, + XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS) != + XGE_HAL_OK) { + /* upper layer may require to repeat */ + return XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING; + } + } + } + return XGE_HAL_OK; +} + +/* + * __hal_device_rts_qos_configure - Configure RTS steering based on + * qos. + * @hldev: HAL device handle. + * + */ +xge_hal_status_e +__hal_device_rts_qos_configure(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + int j, rx_ring_num; + + if (!hldev->config.rts_qos_en) { + return XGE_HAL_OK; + } + + /* First clear the RTS_DS_MEM_DATA */ + val64 = 0; + for (j = 0; j < 64; j++ ) + { + /* First clear the value */ + val64 = XGE_HAL_RTS_DS_MEM_DATA(0); + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rts_ds_mem_data); + + val64 = XGE_HAL_RTS_DS_MEM_CTRL_WE | + XGE_HAL_RTS_DS_MEM_CTRL_STROBE_NEW_CMD | + XGE_HAL_RTS_DS_MEM_CTRL_OFFSET ( j ); + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rts_ds_mem_ctrl); + + + /* poll until done */ + if (__hal_device_register_poll(hldev, + &bar0->rts_ds_mem_ctrl, 0, + XGE_HAL_RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED, + XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS) != XGE_HAL_OK) { + /* upper layer may require to repeat */ + return XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING; + } + + } + + rx_ring_num = 0; + for (j = 0; j < XGE_HAL_MAX_RING_NUM; j++) { + if (hldev->config.ring.queue[j].configured) + rx_ring_num++; + } + + switch (rx_ring_num) { + case 1: + val64 = 0x0; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_0); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_1); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_2); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_3); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_4); + break; + case 2: + val64 = 0x0001000100010001ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_0); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_1); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_2); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_3); + val64 = 0x0001000100000000ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_4); + break; + case 3: + val64 = 0x0001020001020001ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_0); + val64 = 0x0200010200010200ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_1); + val64 = 0x0102000102000102ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_2); + val64 = 0x0001020001020001ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_3); + val64 = 0x0200010200000000ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_4); + break; + case 4: + val64 = 0x0001020300010203ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_0); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_1); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_2); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_3); + val64 = 0x0001020300000000ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_4); + break; + case 5: + val64 = 0x0001020304000102ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_0); + val64 = 0x0304000102030400ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_1); + val64 = 0x0102030400010203ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_2); + val64 = 0x0400010203040001ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_3); + val64 = 0x0203040000000000ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_4); + break; + case 6: + val64 = 0x0001020304050001ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_0); + val64 = 0x0203040500010203ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_1); + val64 = 0x0405000102030405ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_2); + val64 = 0x0001020304050001ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_3); + val64 = 0x0203040500000000ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_4); + break; + case 7: + val64 = 0x0001020304050600ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_0); + val64 = 0x0102030405060001ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_1); + val64 = 0x0203040506000102ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_2); + val64 = 0x0304050600010203ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_3); + val64 = 0x0405060000000000ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_4); + break; + case 8: + val64 = 0x0001020304050607ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_0); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_1); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_2); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_3); + val64 = 0x0001020300000000ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, &bar0->rx_w_round_robin_4); + break; + } + + return XGE_HAL_OK; +} + +/* + * xge__hal_device_rts_mac_enable + * + * @devh: HAL device handle. + * @index: index number where the MAC addr will be stored + * @macaddr: MAC address + * + * - Enable RTS steering for the given MAC address. This function has to be + * called with lock acquired. + * + * NOTE: + * 1. ULD has to call this function with the index value which + * statisfies the following condition: + * ring_num = (index % 8) + * 2.ULD also needs to make sure that the index is not + * occupied by any MAC address. If that index has any MAC address + * it will be overwritten and HAL will not check for it. + * + */ +xge_hal_status_e +xge_hal_device_rts_mac_enable(xge_hal_device_h devh, int index, macaddr_t macaddr) +{ + int max_addr = XGE_HAL_MAX_MAC_ADDRESSES; + xge_hal_status_e status; + + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) + max_addr = XGE_HAL_MAX_MAC_ADDRESSES_HERC; + + if ( index >= max_addr ) + return XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES; + + /* + * Set the MAC address at the given location marked by index. + */ + status = xge_hal_device_macaddr_set(hldev, index, macaddr); + if (status != XGE_HAL_OK) { + xge_debug_device(XGE_ERR, "%s", + "Not able to set the mac addr"); + return status; + } + + return xge_hal_device_rts_section_enable(hldev, index); +} + +/* + * xge__hal_device_rts_mac_disable + * @hldev: HAL device handle. + * @index: index number where to disable the MAC addr + * + * Disable RTS Steering based on the MAC address. + * This function should be called with lock acquired. + * + */ +xge_hal_status_e +xge_hal_device_rts_mac_disable(xge_hal_device_h devh, int index) +{ + xge_hal_status_e status; + u8 macaddr[6] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; + int max_addr = XGE_HAL_MAX_MAC_ADDRESSES; + + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + + xge_debug_ll(XGE_TRACE, "the index value is %d ", index); + + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) + max_addr = XGE_HAL_MAX_MAC_ADDRESSES_HERC; + + if ( index >= max_addr ) + return XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES; + + /* + * Disable MAC address @ given index location + */ + status = xge_hal_device_macaddr_set(hldev, index, macaddr); + if (status != XGE_HAL_OK) { + xge_debug_device(XGE_ERR, "%s", + "Not able to set the mac addr"); + return status; + } + + return XGE_HAL_OK; +} + + +/* + * __hal_device_rth_configure - Configure RTH for the device + * @hldev: HAL device handle. + * + * Using IT (Indirection Table). + */ +xge_hal_status_e +__hal_device_rth_it_configure(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + int rings[XGE_HAL_MAX_RING_NUM]={0}; + int rnum; + int rmax; + int buckets_num; + int bucket; + + if (!hldev->config.rth_en) { + return XGE_HAL_OK; + } + + /* + * Set the receive traffic steering mode from default(classic) + * to enhanced. + */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->rts_ctrl); + val64 |= XGE_HAL_RTS_CTRL_ENHANCED_MODE; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &bar0->rts_ctrl); + + buckets_num = (1 << hldev->config.rth_bucket_size); + + rmax=0; + for (rnum = 0; rnum < XGE_HAL_MAX_RING_NUM; rnum++) { + if (hldev->config.ring.queue[rnum].configured && + hldev->config.ring.queue[rnum].rth_en) + rings[rmax++] = rnum; + } + + rnum = 0; + /* for starters: fill in all the buckets with rings "equally" */ + for (bucket = 0; bucket < buckets_num; bucket++) { + + if (rnum == rmax) + rnum = 0; + + /* write data */ + val64 = XGE_HAL_RTS_RTH_MAP_MEM_DATA_ENTRY_EN | + XGE_HAL_RTS_RTH_MAP_MEM_DATA(rings[rnum]); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rts_rth_map_mem_data); + + /* execute */ + val64 = XGE_HAL_RTS_RTH_MAP_MEM_CTRL_WE | + XGE_HAL_RTS_RTH_MAP_MEM_CTRL_STROBE | + XGE_HAL_RTS_RTH_MAP_MEM_CTRL_OFFSET(bucket); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rts_rth_map_mem_ctrl); + + /* poll until done */ + if (__hal_device_register_poll(hldev, + &bar0->rts_rth_map_mem_ctrl, 0, + XGE_HAL_RTS_RTH_MAP_MEM_CTRL_STROBE, + XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS) != XGE_HAL_OK) { + return XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING; + } + + rnum++; + } + + val64 = XGE_HAL_RTS_RTH_EN; + val64 |= XGE_HAL_RTS_RTH_BUCKET_SIZE(hldev->config.rth_bucket_size); + val64 |= XGE_HAL_RTS_RTH_TCP_IPV4_EN | XGE_HAL_RTS_RTH_UDP_IPV4_EN | XGE_HAL_RTS_RTH_IPV4_EN | + XGE_HAL_RTS_RTH_TCP_IPV6_EN |XGE_HAL_RTS_RTH_UDP_IPV6_EN | XGE_HAL_RTS_RTH_IPV6_EN | + XGE_HAL_RTS_RTH_TCP_IPV6_EX_EN | XGE_HAL_RTS_RTH_UDP_IPV6_EX_EN | XGE_HAL_RTS_RTH_IPV6_EX_EN; + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rts_rth_cfg); + + xge_debug_device(XGE_TRACE, "RTH configured, bucket_size %d", + hldev->config.rth_bucket_size); + + return XGE_HAL_OK; +} + + +/* + * __hal_spdm_entry_add - Add a new entry to the SPDM table. + * + * Add a new entry to the SPDM table + * + * This function add a new entry to the SPDM table. + * + * Note: + * This function should be called with spdm_lock. + * + * See also: xge_hal_spdm_entry_add , xge_hal_spdm_entry_remove. + */ +static xge_hal_status_e +__hal_spdm_entry_add(xge_hal_device_t *hldev, xge_hal_ipaddr_t *src_ip, + xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp, u8 is_tcp, + u8 is_ipv4, u8 tgt_queue, u32 jhash_value, u16 spdm_entry) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + u64 spdm_line_arr[8]; + u8 line_no; + + /* + * Clear the SPDM READY bit + */ + val64 = XGE_HAL_RX_PIC_INT_REG_SPDM_READY; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rxpic_int_reg); + + xge_debug_device(XGE_TRACE, + "L4 SP %x:DP %x: hash %x tgt_queue %d ", + l4_sp, l4_dp, jhash_value, tgt_queue); + + xge_os_memzero(&spdm_line_arr, sizeof(spdm_line_arr)); + + /* + * Construct the SPDM entry. + */ + spdm_line_arr[0] = vBIT(l4_sp,0,16) | + vBIT(l4_dp,16,32) | + vBIT(tgt_queue,53,3) | + vBIT(is_tcp,59,1) | + vBIT(is_ipv4,63,1); + + + if (is_ipv4) { + spdm_line_arr[1] = vBIT(src_ip->ipv4.addr,0,32) | + vBIT(dst_ip->ipv4.addr,32,32); + + } else { + xge_os_memcpy(&spdm_line_arr[1], &src_ip->ipv6.addr[0], 8); + xge_os_memcpy(&spdm_line_arr[2], &src_ip->ipv6.addr[1], 8); + xge_os_memcpy(&spdm_line_arr[3], &dst_ip->ipv6.addr[0], 8); + xge_os_memcpy(&spdm_line_arr[4], &dst_ip->ipv6.addr[1], 8); + } + + spdm_line_arr[7] = vBIT(jhash_value,0,32) | + BIT(63); /* entry enable bit */ + + /* + * Add the entry to the SPDM table + */ + for(line_no = 0; line_no < 8; line_no++) { + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + spdm_line_arr[line_no], + (void *)((char *)hldev->spdm_mem_base + + (spdm_entry * 64) + + (line_no * 8))); + } + + /* + * Wait for the operation to be completed. + */ + if (__hal_device_register_poll(hldev, &bar0->rxpic_int_reg, 1, + XGE_HAL_RX_PIC_INT_REG_SPDM_READY, + XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS) != XGE_HAL_OK) { + return XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING; + } + + /* + * Add this information to a local SPDM table. The purpose of + * maintaining a local SPDM table is to avoid a search in the + * adapter SPDM table for spdm entry lookup which is very costly + * in terms of time. + */ + hldev->spdm_table[spdm_entry]->in_use = 1; + xge_os_memcpy(&hldev->spdm_table[spdm_entry]->src_ip, src_ip, + sizeof(xge_hal_ipaddr_t)); + xge_os_memcpy(&hldev->spdm_table[spdm_entry]->dst_ip, dst_ip, + sizeof(xge_hal_ipaddr_t)); + hldev->spdm_table[spdm_entry]->l4_sp = l4_sp; + hldev->spdm_table[spdm_entry]->l4_dp = l4_dp; + hldev->spdm_table[spdm_entry]->is_tcp = is_tcp; + hldev->spdm_table[spdm_entry]->is_ipv4 = is_ipv4; + hldev->spdm_table[spdm_entry]->tgt_queue = tgt_queue; + hldev->spdm_table[spdm_entry]->jhash_value = jhash_value; + hldev->spdm_table[spdm_entry]->spdm_entry = spdm_entry; + + return XGE_HAL_OK; +} + +/* + * __hal_device_rth_spdm_configure - Configure RTH for the device + * @hldev: HAL device handle. + * + * Using SPDM (Socket-Pair Direct Match). + */ +xge_hal_status_e +__hal_device_rth_spdm_configure(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)hldev->bar0; + u64 val64; + u8 spdm_bar_num; + u32 spdm_bar_offset; + int spdm_table_size; + int i; + + if (!hldev->config.rth_spdm_en) { + return XGE_HAL_OK; + } + + /* + * Retrieve the base address of SPDM Table. + */ + val64 = xge_os_pio_mem_read64(hldev->pdev, + hldev->regh0, &bar0->spdm_bir_offset); + + spdm_bar_num = XGE_HAL_SPDM_PCI_BAR_NUM(val64); + spdm_bar_offset = XGE_HAL_SPDM_PCI_BAR_OFFSET(val64); + + + /* + * spdm_bar_num specifies the PCI bar num register used to + * address the memory space. spdm_bar_offset specifies the offset + * of the SPDM memory with in the bar num memory space. + */ + switch (spdm_bar_num) { + case 0: + { + hldev->spdm_mem_base = (char *)bar0 + + (spdm_bar_offset * 8); + break; + } + case 1: + { + char *bar1 = (char *)hldev->bar1; + hldev->spdm_mem_base = bar1 + (spdm_bar_offset * 8); + break; + } + default: + xge_assert(((spdm_bar_num != 0) && (spdm_bar_num != 1))); + } + + /* + * Retrieve the size of SPDM table(number of entries). + */ + val64 = xge_os_pio_mem_read64(hldev->pdev, + hldev->regh0, &bar0->spdm_structure); + hldev->spdm_max_entries = XGE_HAL_SPDM_MAX_ENTRIES(val64); + + + spdm_table_size = hldev->spdm_max_entries * + sizeof(xge_hal_spdm_entry_t); + if (hldev->spdm_table == NULL) { + void *mem; + + /* + * Allocate memory to hold the copy of SPDM table. + */ + if ((hldev->spdm_table = (xge_hal_spdm_entry_t **) + xge_os_malloc( + hldev->pdev, + (sizeof(xge_hal_spdm_entry_t *) * + hldev->spdm_max_entries))) == NULL) { + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + + if ((mem = xge_os_malloc(hldev->pdev, spdm_table_size)) == NULL) + { + xge_os_free(hldev->pdev, hldev->spdm_table, + (sizeof(xge_hal_spdm_entry_t *) * + hldev->spdm_max_entries)); + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + + xge_os_memzero(mem, spdm_table_size); + for (i = 0; i < hldev->spdm_max_entries; i++) { + hldev->spdm_table[i] = (xge_hal_spdm_entry_t *) + ((char *)mem + + i * sizeof(xge_hal_spdm_entry_t)); + } + xge_os_spin_lock_init(&hldev->spdm_lock, hldev->pdev); + } else { + /* + * We are here because the host driver tries to + * do a soft reset on the device. + * Since the device soft reset clears the SPDM table, copy + * the entries from the local SPDM table to the actual one. + */ + xge_os_spin_lock(&hldev->spdm_lock); + for (i = 0; i < hldev->spdm_max_entries; i++) { + xge_hal_spdm_entry_t *spdm_entry = hldev->spdm_table[i]; + + if (spdm_entry->in_use) { + if (__hal_spdm_entry_add(hldev, + &spdm_entry->src_ip, + &spdm_entry->dst_ip, + spdm_entry->l4_sp, + spdm_entry->l4_dp, + spdm_entry->is_tcp, + spdm_entry->is_ipv4, + spdm_entry->tgt_queue, + spdm_entry->jhash_value, + spdm_entry->spdm_entry) + != XGE_HAL_OK) { + /* Log an warning */ + xge_debug_device(XGE_ERR, + "SPDM table update from local" + " memory failed"); + } + } + } + xge_os_spin_unlock(&hldev->spdm_lock); + } + + /* + * Set the receive traffic steering mode from default(classic) + * to enhanced. + */ + val64 = xge_os_pio_mem_read64(hldev->pdev, + hldev->regh0, &bar0->rts_ctrl); + val64 |= XGE_HAL_RTS_CTRL_ENHANCED_MODE; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &bar0->rts_ctrl); + + /* + * We may not need to configure rts_rth_jhash_cfg register as the + * default values are good enough to calculate the hash. + */ + + /* + * As of now, set all the rth mask registers to zero. TODO. + */ + for(i = 0; i < 5; i++) { + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + 0, &bar0->rts_rth_hash_mask[i]); + } + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + 0, &bar0->rts_rth_hash_mask_5); + + if (hldev->config.rth_spdm_use_l4) { + val64 = XGE_HAL_RTH_STATUS_SPDM_USE_L4; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &bar0->rts_rth_status); + } + + val64 = XGE_HAL_RTS_RTH_EN; + val64 |= XGE_HAL_RTS_RTH_IPV4_EN | XGE_HAL_RTS_RTH_TCP_IPV4_EN; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rts_rth_cfg); + + + return XGE_HAL_OK; +} + +/* + * __hal_device_pci_init + * @hldev: HAL device handle. + * + * Initialize certain PCI/PCI-X configuration registers + * with recommended values. Save config space for future hw resets. + */ +static void +__hal_device_pci_init(xge_hal_device_t *hldev) +{ + int i, pcisize = 0; + u16 cmd = 0; + u8 val; + + /* Store PCI device ID and revision for future references where in we + * decide Xena revision using PCI sub system ID */ + xge_os_pci_read16(hldev->pdev,hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, device_id), + &hldev->device_id); + xge_os_pci_read8(hldev->pdev,hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, revision), + &hldev->revision); + + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) + pcisize = XGE_HAL_PCISIZE_HERC; + else if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA) + pcisize = XGE_HAL_PCISIZE_XENA; + + /* save original PCI config space to restore it on device_terminate() */ + for (i = 0; i < pcisize; i++) { + xge_os_pci_read32(hldev->pdev, hldev->cfgh, i*4, + (u32*)&hldev->pci_config_space_bios + i); + } + + /* Set the PErr Repconse bit and SERR in PCI command register. */ + xge_os_pci_read16(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, command), &cmd); + cmd |= 0x140; + xge_os_pci_write16(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, command), cmd); + + /* Set user spcecified value for the PCI Latency Timer */ + if (hldev->config.latency_timer && + hldev->config.latency_timer != XGE_HAL_USE_BIOS_DEFAULT_LATENCY) { + xge_os_pci_write8(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, + latency_timer), + (u8)hldev->config.latency_timer); + } + /* Read back latency timer to reflect it into user level */ + xge_os_pci_read8(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, latency_timer), &val); + hldev->config.latency_timer = val; + + /* Enable Data Parity Error Recovery in PCI-X command register. */ + xge_os_pci_read16(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, pcix_command), &cmd); + cmd |= 1; + xge_os_pci_write16(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, pcix_command), cmd); + + /* Set MMRB count in PCI-X command register. */ + if (hldev->config.mmrb_count != XGE_HAL_DEFAULT_BIOS_MMRB_COUNT) { + cmd &= 0xFFF3; + cmd |= hldev->config.mmrb_count << 2; + xge_os_pci_write16(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, pcix_command), + cmd); + } + /* Read back MMRB count to reflect it into user level */ + xge_os_pci_read16(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, pcix_command), + &cmd); + cmd &= 0x000C; + hldev->config.mmrb_count = cmd>>2; + + /* Setting Maximum outstanding splits based on system type. */ + if (hldev->config.max_splits_trans != XGE_HAL_USE_BIOS_DEFAULT_SPLITS) { + xge_os_pci_read16(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, pcix_command), + &cmd); + cmd &= 0xFF8F; + cmd |= hldev->config.max_splits_trans << 4; + xge_os_pci_write16(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, pcix_command), + cmd); + } + + /* Read back max split trans to reflect it into user level */ + xge_os_pci_read16(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, pcix_command), &cmd); + cmd &= 0x0070; + hldev->config.max_splits_trans = cmd>>4; + + /* Forcibly disabling relaxed ordering capability of the card. */ + xge_os_pci_read16(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, pcix_command), &cmd); + cmd &= 0xFFFD; + xge_os_pci_write16(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, pcix_command), cmd); + + /* save PCI config space for future resets */ + for (i = 0; i < pcisize; i++) { + xge_os_pci_read32(hldev->pdev, hldev->cfgh, i*4, + (u32*)&hldev->pci_config_space + i); + } + + if (hldev->config.intr_mode == XGE_HAL_INTR_MODE_MSI || + hldev->config.intr_mode == XGE_HAL_INTR_MODE_MSIX) { + /* Upper limit of the MSI number enabled by the system */ + xge_os_pci_read32(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, msi_control), + &hldev->msi_mask); + hldev->msi_mask &= 0x70; + if (!hldev->msi_mask) + return; + hldev->msi_mask >>= 4; + /* + * This number's power of 2 is the number + * of MSIs enabled. + */ + hldev->msi_mask = (0x1 << hldev->msi_mask); + /* + * If 32 MSIs are enabled, then MSI numbers range from 0 - 31. + */ + hldev->msi_mask -= 1; + } +} + +/* + * __hal_device_pci_info_get - Get PCI bus informations such as width, frequency + * and mode. + * @devh: HAL device handle. + * @pci_mode: pointer to a variable of enumerated type + * xge_hal_pci_mode_e{}. + * @bus_frequency: pointer to a variable of enumerated type + * xge_hal_pci_bus_frequency_e{}. + * @bus_width: pointer to a variable of enumerated type + * xge_hal_pci_bus_width_e{}. + * + * Get pci mode, frequency, and PCI bus width. + * + * Returns: one of the xge_hal_status_e{} enumerated types. + * XGE_HAL_OK - for success. + * XGE_HAL_ERR_INVALID_PCI_INFO - for invalid PCI information from the card. + * XGE_HAL_ERR_BAD_DEVICE_ID - for invalid card. + * + * See Also: xge_hal_pci_mode_e, xge_hal_pci_mode_e, xge_hal_pci_width_e. + */ +static xge_hal_status_e +__hal_device_pci_info_get(xge_hal_device_h devh, xge_hal_pci_mode_e *pci_mode, + xge_hal_pci_bus_frequency_e *bus_frequency, + xge_hal_pci_bus_width_e *bus_width) +{ + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + xge_hal_status_e rc_status = XGE_HAL_OK; + xge_hal_card_e card_id = xge_hal_device_check_id (devh); + +#ifdef XGE_HAL_HERC_EMULATION + hldev->config.pci_freq_mherz = + XGE_HAL_PCI_BUS_FREQUENCY_66MHZ; + *bus_frequency = + XGE_HAL_PCI_BUS_FREQUENCY_66MHZ; + *pci_mode = XGE_HAL_PCI_66MHZ_MODE; +#else + if (card_id == XGE_HAL_CARD_HERC) { + xge_hal_pci_bar0_t *bar0 = + (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 pci_info = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->pci_info); + if (XGE_HAL_PCI_32_BIT & pci_info) + *bus_width = XGE_HAL_PCI_BUS_WIDTH_32BIT; + else + *bus_width = XGE_HAL_PCI_BUS_WIDTH_64BIT; + switch((pci_info & XGE_HAL_PCI_INFO)>>60) + { + case XGE_HAL_PCI_33MHZ_MODE: + *bus_frequency = + XGE_HAL_PCI_BUS_FREQUENCY_33MHZ; + *pci_mode = XGE_HAL_PCI_33MHZ_MODE; + break; + case XGE_HAL_PCI_66MHZ_MODE: + *bus_frequency = + XGE_HAL_PCI_BUS_FREQUENCY_66MHZ; + *pci_mode = XGE_HAL_PCI_66MHZ_MODE; + break; + case XGE_HAL_PCIX_M1_66MHZ_MODE: + *bus_frequency = + XGE_HAL_PCI_BUS_FREQUENCY_66MHZ; + *pci_mode = XGE_HAL_PCIX_M1_66MHZ_MODE; + break; + case XGE_HAL_PCIX_M1_100MHZ_MODE: + *bus_frequency = + XGE_HAL_PCI_BUS_FREQUENCY_100MHZ; + *pci_mode = XGE_HAL_PCIX_M1_100MHZ_MODE; + break; + case XGE_HAL_PCIX_M1_133MHZ_MODE: + *bus_frequency = + XGE_HAL_PCI_BUS_FREQUENCY_133MHZ; + *pci_mode = XGE_HAL_PCIX_M1_133MHZ_MODE; + break; + case XGE_HAL_PCIX_M2_66MHZ_MODE: + *bus_frequency = + XGE_HAL_PCI_BUS_FREQUENCY_133MHZ; + *pci_mode = XGE_HAL_PCIX_M2_66MHZ_MODE; + break; + case XGE_HAL_PCIX_M2_100MHZ_MODE: + *bus_frequency = + XGE_HAL_PCI_BUS_FREQUENCY_200MHZ; + *pci_mode = XGE_HAL_PCIX_M2_100MHZ_MODE; + break; + case XGE_HAL_PCIX_M2_133MHZ_MODE: + *bus_frequency = + XGE_HAL_PCI_BUS_FREQUENCY_266MHZ; + *pci_mode = XGE_HAL_PCIX_M2_133MHZ_MODE; + break; + case XGE_HAL_PCIX_M1_RESERVED: + case XGE_HAL_PCIX_M1_66MHZ_NS: + case XGE_HAL_PCIX_M1_100MHZ_NS: + case XGE_HAL_PCIX_M1_133MHZ_NS: + case XGE_HAL_PCIX_M2_RESERVED: + case XGE_HAL_PCIX_533_RESERVED: + default: + rc_status = XGE_HAL_ERR_INVALID_PCI_INFO; + xge_debug_device(XGE_ERR, + "invalid pci info "XGE_OS_LLXFMT, + (unsigned long long)pci_info); + break; + } + if (rc_status != XGE_HAL_ERR_INVALID_PCI_INFO) + xge_debug_device(XGE_TRACE, "PCI info: mode %d width " + "%d frequency %d", *pci_mode, *bus_width, + *bus_frequency); + if (hldev->config.pci_freq_mherz == + XGE_HAL_DEFAULT_USE_HARDCODE) { + hldev->config.pci_freq_mherz = *bus_frequency; + } + } + /* for XENA, we report PCI mode, only. PCI bus frequency, and bus width + * are set to unknown */ + else if (card_id == XGE_HAL_CARD_XENA) { + u32 pcix_status; + u8 dev_num, bus_num; + /* initialize defaults for XENA */ + *bus_frequency = XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN; + *bus_width = XGE_HAL_PCI_BUS_WIDTH_UNKNOWN; + xge_os_pci_read32(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, pcix_status), + &pcix_status); + dev_num = (u8)((pcix_status & 0xF8) >> 3); + bus_num = (u8)((pcix_status & 0xFF00) >> 8); + if (dev_num == 0 && bus_num == 0) + *pci_mode = XGE_HAL_PCI_BASIC_MODE; + else + *pci_mode = XGE_HAL_PCIX_BASIC_MODE; + xge_debug_device(XGE_TRACE, "PCI info: mode %d", *pci_mode); + if (hldev->config.pci_freq_mherz == + XGE_HAL_DEFAULT_USE_HARDCODE) { + /* + * There is no way to detect BUS frequency on Xena, + * so, in case of automatic configuration we hopelessly + * assume 133MHZ. + */ + hldev->config.pci_freq_mherz = + XGE_HAL_PCI_BUS_FREQUENCY_133MHZ; + } + } else if (card_id == XGE_HAL_CARD_TITAN) { + *bus_width = XGE_HAL_PCI_BUS_WIDTH_64BIT; + *bus_frequency = XGE_HAL_PCI_BUS_FREQUENCY_250MHZ; + if (hldev->config.pci_freq_mherz == + XGE_HAL_DEFAULT_USE_HARDCODE) { + hldev->config.pci_freq_mherz = *bus_frequency; + } + } else{ + rc_status = XGE_HAL_ERR_BAD_DEVICE_ID; + xge_debug_device(XGE_ERR, "invalid device id %d", card_id); + } +#endif + + return rc_status; +} + +/* + * __hal_device_handle_link_up_ind + * @hldev: HAL device handle. + * + * Link up indication handler. The function is invoked by HAL when + * Xframe indicates that the link is up for programmable amount of time. + */ +static int +__hal_device_handle_link_up_ind(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + + /* + * If the previous link state is not down, return. + */ + if (hldev->link_state == XGE_HAL_LINK_UP) { +#ifdef XGE_HAL_PROCESS_LINK_INT_IN_ISR + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC){ + val64 = xge_os_pio_mem_read64( + hldev->pdev, hldev->regh0, + &bar0->misc_int_mask); + val64 |= XGE_HAL_MISC_INT_REG_LINK_UP_INT; + val64 &= ~XGE_HAL_MISC_INT_REG_LINK_DOWN_INT; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &bar0->misc_int_mask); + } +#endif + xge_debug_device(XGE_TRACE, + "link up indication while link is up, ignoring.."); + return 0; + } + + /* Now re-enable it as due to noise, hardware turned it off */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->adapter_control); + val64 |= XGE_HAL_ADAPTER_CNTL_EN; + val64 = val64 & (~XGE_HAL_ADAPTER_ECC_EN); /* ECC enable */ + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->adapter_control); + + /* Turn on the Laser */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->adapter_control); + val64 = val64|(XGE_HAL_ADAPTER_EOI_TX_ON | + XGE_HAL_ADAPTER_LED_ON); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->adapter_control); + +#ifdef XGE_HAL_PROCESS_LINK_INT_IN_ISR + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) { + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->adapter_status); + if (val64 & (XGE_HAL_ADAPTER_STATUS_RMAC_REMOTE_FAULT | + XGE_HAL_ADAPTER_STATUS_RMAC_LOCAL_FAULT)) { + xge_debug_device(XGE_TRACE, "%s", + "fail to transition link to up..."); + return 0; + } + else { + /* + * Mask the Link Up interrupt and unmask the Link Down + * interrupt. + */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->misc_int_mask); + val64 |= XGE_HAL_MISC_INT_REG_LINK_UP_INT; + val64 &= ~XGE_HAL_MISC_INT_REG_LINK_DOWN_INT; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->misc_int_mask); + xge_debug_device(XGE_TRACE, "calling link up.."); + hldev->link_state = XGE_HAL_LINK_UP; + + /* notify ULD */ + if (g_xge_hal_driver->uld_callbacks.link_up) { + g_xge_hal_driver->uld_callbacks.link_up( + hldev->upper_layer_info); + } + return 1; + } + } +#endif + xge_os_mdelay(1); + if (__hal_device_register_poll(hldev, &bar0->adapter_status, 0, + (XGE_HAL_ADAPTER_STATUS_RMAC_REMOTE_FAULT | + XGE_HAL_ADAPTER_STATUS_RMAC_LOCAL_FAULT), + XGE_HAL_DEVICE_FAULT_WAIT_MAX_MILLIS) == XGE_HAL_OK) { + + /* notify ULD */ + (void) xge_queue_produce_context(hldev->queueh, + XGE_HAL_EVENT_LINK_IS_UP, + hldev); + /* link is up after been enabled */ + return 1; + } else { + xge_debug_device(XGE_TRACE, "%s", + "fail to transition link to up..."); + return 0; + } +} + +/* + * __hal_device_handle_link_down_ind + * @hldev: HAL device handle. + * + * Link down indication handler. The function is invoked by HAL when + * Xframe indicates that the link is down. + */ +static int +__hal_device_handle_link_down_ind(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + + /* + * If the previous link state is not up, return. + */ + if (hldev->link_state == XGE_HAL_LINK_DOWN) { +#ifdef XGE_HAL_PROCESS_LINK_INT_IN_ISR + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC){ + val64 = xge_os_pio_mem_read64( + hldev->pdev, hldev->regh0, + &bar0->misc_int_mask); + val64 |= XGE_HAL_MISC_INT_REG_LINK_DOWN_INT; + val64 &= ~XGE_HAL_MISC_INT_REG_LINK_UP_INT; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &bar0->misc_int_mask); + } +#endif + xge_debug_device(XGE_TRACE, + "link down indication while link is down, ignoring.."); + return 0; + } + xge_os_mdelay(1); + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->adapter_control); + + /* try to debounce the link only if the adapter is enabled. */ + if (val64 & XGE_HAL_ADAPTER_CNTL_EN) { + if (__hal_device_register_poll(hldev, &bar0->adapter_status, 0, + (XGE_HAL_ADAPTER_STATUS_RMAC_REMOTE_FAULT | + XGE_HAL_ADAPTER_STATUS_RMAC_LOCAL_FAULT), + XGE_HAL_DEVICE_FAULT_WAIT_MAX_MILLIS) == XGE_HAL_OK) { + xge_debug_device(XGE_TRACE, + "link is actually up (possible noisy link?), ignoring."); + return(0); + } + } + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->adapter_control); + /* turn off LED */ + val64 = val64 & (~XGE_HAL_ADAPTER_LED_ON); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->adapter_control); + +#ifdef XGE_HAL_PROCESS_LINK_INT_IN_ISR + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) { + /* + * Mask the Link Down interrupt and unmask the Link up + * interrupt + */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->misc_int_mask); + val64 |= XGE_HAL_MISC_INT_REG_LINK_DOWN_INT; + val64 &= ~XGE_HAL_MISC_INT_REG_LINK_UP_INT; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->misc_int_mask); + + /* link is down */ + xge_debug_device(XGE_TRACE, "calling link down.."); + hldev->link_state = XGE_HAL_LINK_DOWN; + + /* notify ULD */ + if (g_xge_hal_driver->uld_callbacks.link_down) { + g_xge_hal_driver->uld_callbacks.link_down( + hldev->upper_layer_info); + } + return 1; + } +#endif + /* notify ULD */ + (void) xge_queue_produce_context(hldev->queueh, + XGE_HAL_EVENT_LINK_IS_DOWN, + hldev); + /* link is down */ + return 1; +} +/* + * __hal_device_handle_link_state_change + * @hldev: HAL device handle. + * + * Link state change handler. The function is invoked by HAL when + * Xframe indicates link state change condition. The code here makes sure to + * 1) ignore redundant state change indications; + * 2) execute link-up sequence, and handle the failure to bring the link up; + * 3) generate XGE_HAL_LINK_UP/DOWN event for the subsequent handling by + * upper-layer driver (ULD). + */ +static int +__hal_device_handle_link_state_change(xge_hal_device_t *hldev) +{ + u64 hw_status; + int hw_link_state; + int retcode; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + int i = 0; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->adapter_control); + + /* If the adapter is not enabled but the hal thinks we are in the up + * state then transition to the down state. + */ + if ( !(val64 & XGE_HAL_ADAPTER_CNTL_EN) && + (hldev->link_state == XGE_HAL_LINK_UP) ) { + return(__hal_device_handle_link_down_ind(hldev)); + } + + do { + xge_os_mdelay(1); + (void) xge_hal_device_status(hldev, &hw_status); + hw_link_state = (hw_status & + (XGE_HAL_ADAPTER_STATUS_RMAC_REMOTE_FAULT | + XGE_HAL_ADAPTER_STATUS_RMAC_LOCAL_FAULT)) ? + XGE_HAL_LINK_DOWN : XGE_HAL_LINK_UP; + + /* check if the current link state is still considered + * to be changed. This way we will make sure that this is + * not a noise which needs to be filtered out */ + if (hldev->link_state == hw_link_state) + break; + } while (i++ < hldev->config.link_valid_cnt); + + /* If the current link state is same as previous, just return */ + if (hldev->link_state == hw_link_state) + retcode = 0; + /* detected state change */ + else if (hw_link_state == XGE_HAL_LINK_UP) + retcode = __hal_device_handle_link_up_ind(hldev); + else + retcode = __hal_device_handle_link_down_ind(hldev); + return retcode; +} + +/* + * + */ +static void +__hal_device_handle_serr(xge_hal_device_t *hldev, char *reg, u64 value) +{ + hldev->stats.sw_dev_err_stats.serr_cnt++; + if (hldev->config.dump_on_serr) { +#ifdef XGE_HAL_USE_MGMT_AUX + (void) xge_hal_aux_device_dump(hldev); +#endif + } + + (void) xge_queue_produce(hldev->queueh, XGE_HAL_EVENT_SERR, hldev, + 1, sizeof(u64), (void *)&value); + + xge_debug_device(XGE_ERR, "%s: read "XGE_OS_LLXFMT, reg, + (unsigned long long) value); +} + +/* + * + */ +static void +__hal_device_handle_eccerr(xge_hal_device_t *hldev, char *reg, u64 value) +{ + if (hldev->config.dump_on_eccerr) { +#ifdef XGE_HAL_USE_MGMT_AUX + (void) xge_hal_aux_device_dump(hldev); +#endif + } + + /* Herc smart enough to recover on its own! */ + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA) { + (void) xge_queue_produce(hldev->queueh, + XGE_HAL_EVENT_ECCERR, hldev, + 1, sizeof(u64), (void *)&value); + } + + xge_debug_device(XGE_ERR, "%s: read "XGE_OS_LLXFMT, reg, + (unsigned long long) value); +} + +/* + * + */ +static void +__hal_device_handle_parityerr(xge_hal_device_t *hldev, char *reg, u64 value) +{ + if (hldev->config.dump_on_parityerr) { +#ifdef XGE_HAL_USE_MGMT_AUX + (void) xge_hal_aux_device_dump(hldev); +#endif + } + (void) xge_queue_produce_context(hldev->queueh, + XGE_HAL_EVENT_PARITYERR, hldev); + + xge_debug_device(XGE_ERR, "%s: read "XGE_OS_LLXFMT, reg, + (unsigned long long) value); +} + +/* + * + */ +static void +__hal_device_handle_targetabort(xge_hal_device_t *hldev) +{ + (void) xge_queue_produce_context(hldev->queueh, + XGE_HAL_EVENT_TARGETABORT, hldev); +} + + +/* + * __hal_device_hw_initialize + * @hldev: HAL device handle. + * + * Initialize Xframe hardware. + */ +static xge_hal_status_e +__hal_device_hw_initialize(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + xge_hal_status_e status; + u64 val64; + + /* Set proper endian settings and verify the same by reading the PIF + * Feed-back register. */ + status = __hal_device_set_swapper(hldev); + if (status != XGE_HAL_OK) { + return status; + } + + /* update the pci mode, frequency, and width */ + if (__hal_device_pci_info_get(hldev, &hldev->pci_mode, + &hldev->bus_frequency, &hldev->bus_width) != XGE_HAL_OK){ + hldev->pci_mode = XGE_HAL_PCI_INVALID_MODE; + hldev->bus_frequency = XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN; + hldev->bus_width = XGE_HAL_PCI_BUS_WIDTH_UNKNOWN; + /* + * FIXME: this cannot happen. + * But if it happens we cannot continue just like that + */ + xge_debug_device(XGE_ERR, "unable to get pci info"); + } + + if ((hldev->pci_mode == XGE_HAL_PCI_33MHZ_MODE) || + (hldev->pci_mode == XGE_HAL_PCI_66MHZ_MODE) || + (hldev->pci_mode == XGE_HAL_PCI_BASIC_MODE)) { + /* PCI optimization: set TxReqTimeOut + * register (0x800+0x120) to 0x1ff or + * something close to this. + * Note: not to be used for PCI-X! */ + + val64 = XGE_HAL_TXREQTO_VAL(0x1FF); + val64 |= XGE_HAL_TXREQTO_EN; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->txreqtimeout); + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, 0ULL, + &bar0->read_retry_delay); + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, 0ULL, + &bar0->write_retry_delay); + + xge_debug_device(XGE_TRACE, "%s", "optimizing for PCI mode"); + } + + if (hldev->bus_frequency == XGE_HAL_PCI_BUS_FREQUENCY_266MHZ || + hldev->bus_frequency == XGE_HAL_PCI_BUS_FREQUENCY_250MHZ) { + + /* Optimizing for PCI-X 266/250 */ + + val64 = XGE_HAL_TXREQTO_VAL(0x7F); + val64 |= XGE_HAL_TXREQTO_EN; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->txreqtimeout); + + xge_debug_device(XGE_TRACE, "%s", "optimizing for PCI-X 266/250 modes"); + } + + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) { + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, 0x4000000000000ULL, + &bar0->read_retry_delay); + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, 0x4000000000000ULL, + &bar0->write_retry_delay); + } + + /* added this to set the no of bytes used to update lso_bytes_sent + returned TxD0 */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->pic_control_2); + val64 &= ~XGE_HAL_TXD_WRITE_BC(0x2); + val64 |= XGE_HAL_TXD_WRITE_BC(0x4); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->pic_control_2); + /* added this to clear the EOI_RESET field while leaving XGXS_RESET + * in reset, then a 1-second delay */ + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_SW_RESET_XGXS, &bar0->sw_reset); + xge_os_mdelay(1000); + + /* Clear the XGXS_RESET field of the SW_RESET register in order to + * release the XGXS from reset. Its reset value is 0xA5; write 0x00 + * to activate the XGXS. The core requires a minimum 500 us reset.*/ + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, 0, &bar0->sw_reset); + (void) xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->sw_reset); + xge_os_mdelay(1); + + /* read registers in all blocks */ + (void) xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->mac_int_mask); + (void) xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->mc_int_mask); + (void) xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->xgxs_int_mask); + + /* set default MTU and steer based on length*/ + __hal_ring_mtu_set(hldev, hldev->config.mtu+22); // Alway set 22 bytes extra for steering to work + + if (hldev->config.mac.rmac_bcast_en) { + xge_hal_device_bcast_enable(hldev); + } else { + xge_hal_device_bcast_disable(hldev); + } + +#ifndef XGE_HAL_HERC_EMULATION + __hal_device_xaui_configure(hldev); +#endif + __hal_device_mac_link_util_set(hldev); + + __hal_device_mac_link_util_set(hldev); + + /* + * Keep its PCI REQ# line asserted during a write + * transaction up to the end of the transaction + */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->misc_control); + + val64 |= XGE_HAL_MISC_CONTROL_EXT_REQ_EN; + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &bar0->misc_control); + + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) { + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->misc_control); + + val64 |= XGE_HAL_MISC_CONTROL_LINK_FAULT; + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &bar0->misc_control); + } + + /* + * bimodal interrupts is when all Rx traffic interrupts + * will go to TTI, so we need to adjust RTI settings and + * use adaptive TTI timer. We need to make sure RTI is + * properly configured to sane value which will not + * distrupt bimodal behavior. + */ + if (hldev->config.bimodal_interrupts) { + int i; + + /* force polling_cnt to be "0", otherwise + * IRQ workload statistics will be screwed. This could + * be worked out in TXPIC handler later. */ + hldev->config.isr_polling_cnt = 0; + hldev->config.sched_timer_us = 10000; + + /* disable all TTI < 56 */ + for (i=0; iconfig.fifo.queue[i].configured) + continue; + for (j=0; jconfig.fifo.queue[i].tti[j].enabled) + hldev->config.fifo.queue[i].tti[j].enabled = 0; + } + } + + /* now configure bimodal interrupts */ + __hal_device_bimodal_configure(hldev); + } + + status = __hal_device_tti_configure(hldev, 0); + if (status != XGE_HAL_OK) + return status; + + status = __hal_device_rti_configure(hldev, 0); + if (status != XGE_HAL_OK) + return status; + + status = __hal_device_rth_it_configure(hldev); + if (status != XGE_HAL_OK) + return status; + + status = __hal_device_rth_spdm_configure(hldev); + if (status != XGE_HAL_OK) + return status; + + status = __hal_device_rts_mac_configure(hldev); + if (status != XGE_HAL_OK) { + xge_debug_device(XGE_ERR, "__hal_device_rts_mac_configure Failed "); + return status; + } + + status = __hal_device_rts_port_configure(hldev); + if (status != XGE_HAL_OK) { + xge_debug_device(XGE_ERR, "__hal_device_rts_port_configure Failed "); + return status; + } + + status = __hal_device_rts_qos_configure(hldev); + if (status != XGE_HAL_OK) { + xge_debug_device(XGE_ERR, "__hal_device_rts_qos_configure Failed "); + return status; + } + + __hal_device_pause_frames_configure(hldev); + __hal_device_rmac_padding_configure(hldev); + __hal_device_shared_splits_configure(hldev); + + /* make sure all interrupts going to be disabled at the moment */ + __hal_device_intr_mgmt(hldev, XGE_HAL_ALL_INTRS, 0); + + /* SXE-008 Transmit DMA arbitration issue */ + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA && + hldev->revision < 4) { + xge_os_pio_mem_write64(hldev->pdev,hldev->regh0, + XGE_HAL_ADAPTER_PCC_ENABLE_FOUR, + &bar0->pcc_enable); + } + __hal_fifo_hw_initialize(hldev); + __hal_ring_hw_initialize(hldev); + + if (__hal_device_wait_quiescent(hldev, &val64)) { + return XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT; + } + + if (__hal_device_register_poll(hldev, &bar0->adapter_status, 1, + XGE_HAL_ADAPTER_STATUS_RC_PRC_QUIESCENT, + XGE_HAL_DEVICE_QUIESCENT_WAIT_MAX_MILLIS) != XGE_HAL_OK) { + xge_debug_device(XGE_TRACE, "%s", "PRC is not QUIESCENT!"); + return XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT; + } + + xge_debug_device(XGE_TRACE, "device 0x"XGE_OS_LLXFMT" is quiescent", + (unsigned long long)(ulong_t)hldev); + + if (hldev->config.intr_mode == XGE_HAL_INTR_MODE_MSIX || + hldev->config.intr_mode == XGE_HAL_INTR_MODE_MSI) { + /* + * If MSI is enabled, ensure that One Shot for MSI in PCI_CTRL + * is disabled. + */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->pic_control); + val64 &= ~(XGE_HAL_PIC_CNTL_ONE_SHOT_TINT); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->pic_control); + } + + hldev->hw_is_initialized = 1; + hldev->terminating = 0; + return XGE_HAL_OK; +} + +/* + * __hal_device_reset - Reset device only. + * @hldev: HAL device handle. + * + * Reset the device, and subsequently restore + * the previously saved PCI configuration space. + */ +#define XGE_HAL_MAX_PCI_CONFIG_SPACE_REINIT 50 +static xge_hal_status_e +__hal_device_reset(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + int i, j, swap_done, pcisize = 0; + u64 val64, rawval = 0ULL; + + if (hldev->config.intr_mode == XGE_HAL_INTR_MODE_MSIX) { + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) { + if ( hldev->bar2 ) { + u64 *msix_vetor_table = (u64 *)hldev->bar2; + + // 2 64bit words for each entry + for (i = 0; i < XGE_HAL_MAX_MSIX_MESSAGES * 2; + i++) { + hldev->msix_vector_table[i] = + xge_os_pio_mem_read64(hldev->pdev, + hldev->regh2, &msix_vetor_table[i]); + } + } + } + } + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->pif_rd_swapper_fb); + swap_done = (val64 == XGE_HAL_IF_RD_SWAPPER_FB); + + if (swap_done) { + __hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0, + (u32)(XGE_HAL_SW_RESET_ALL>>32), (char *)&bar0->sw_reset); + } else { + u32 val = (u32)(XGE_HAL_SW_RESET_ALL >> 32); +#if defined(XGE_OS_HOST_LITTLE_ENDIAN) || defined(XGE_OS_PIO_LITTLE_ENDIAN) + /* swap it */ + val = (((val & (u32)0x000000ffUL) << 24) | + ((val & (u32)0x0000ff00UL) << 8) | + ((val & (u32)0x00ff0000UL) >> 8) | + ((val & (u32)0xff000000UL) >> 24)); +#endif + xge_os_pio_mem_write32(hldev->pdev, hldev->regh0, val, + &bar0->sw_reset); + } + + pcisize = (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC)? + XGE_HAL_PCISIZE_HERC : XGE_HAL_PCISIZE_XENA; + + xge_os_mdelay(20); /* Wait for 20 ms after reset */ + + { + /* Poll for no more than 1 second */ + for (i = 0; i < XGE_HAL_MAX_PCI_CONFIG_SPACE_REINIT; i++) + { + for (j = 0; j < pcisize; j++) { + xge_os_pci_write32(hldev->pdev, hldev->cfgh, j * 4, + *((u32*)&hldev->pci_config_space + j)); + } + + xge_os_pci_read16(hldev->pdev,hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, device_id), + &hldev->device_id); + + if (xge_hal_device_check_id(hldev) != XGE_HAL_CARD_UNKNOWN) + break; + xge_os_mdelay(20); + } + } + + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_UNKNOWN) + { + xge_debug_device(XGE_ERR, "device reset failed"); + return XGE_HAL_ERR_RESET_FAILED; + } + + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) { + int cnt = 0; + + rawval = XGE_HAL_SW_RESET_RAW_VAL_HERC; + pcisize = XGE_HAL_PCISIZE_HERC; + xge_os_mdelay(1); + do { + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->sw_reset); + if (val64 != rawval) { + break; + } + cnt++; + xge_os_mdelay(1); /* Wait for 1ms before retry */ + } while(cnt < 20); + } else if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA) { + rawval = XGE_HAL_SW_RESET_RAW_VAL_XENA; + pcisize = XGE_HAL_PCISIZE_XENA; + xge_os_mdelay(XGE_HAL_DEVICE_RESET_WAIT_MAX_MILLIS); + } + + /* Restore MSI-X vector table */ + if (hldev->config.intr_mode == XGE_HAL_INTR_MODE_MSIX) { + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) { + if ( hldev->bar2 ) { + /* + * 94: MSIXTable 00000004 ( BIR:4 Offset:0x0 ) + * 98: PBATable 00000404 ( BIR:4 Offset:0x400 ) + */ + u64 *msix_vetor_table = (u64 *)hldev->bar2; + + /* 2 64bit words for each entry */ + for (i = 0; i < XGE_HAL_MAX_MSIX_MESSAGES * 2; + i++) { + xge_os_pio_mem_write64(hldev->pdev, + hldev->regh2, + hldev->msix_vector_table[i], + &msix_vetor_table[i]); + } + } + } + } + + hldev->link_state = XGE_HAL_LINK_DOWN; + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->sw_reset); + + if (val64 != rawval) { + xge_debug_device(XGE_ERR, "device has not been reset " + "got 0x"XGE_OS_LLXFMT", expected 0x"XGE_OS_LLXFMT, + (unsigned long long)val64, (unsigned long long)rawval); + return XGE_HAL_ERR_RESET_FAILED; + } + + hldev->hw_is_initialized = 0; + return XGE_HAL_OK; +} + +/* + * __hal_device_poll - General private routine to poll the device. + * @hldev: HAL device handle. + * + * Returns: one of the xge_hal_status_e{} enumerated types. + * XGE_HAL_OK - for success. + * XGE_HAL_ERR_CRITICAL - when encounters critical error. + */ +static xge_hal_status_e +__hal_device_poll(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *bar0; + u64 err_reg; + + bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + + /* Handling SERR errors by forcing a H/W reset. */ + err_reg = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->serr_source); + if (err_reg & XGE_HAL_SERR_SOURCE_ANY) { + __hal_device_handle_serr(hldev, "serr_source", err_reg); + return XGE_HAL_ERR_CRITICAL; + } + + err_reg = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->misc_int_reg); + + if (err_reg & XGE_HAL_MISC_INT_REG_DP_ERR_INT) { + hldev->stats.sw_dev_err_stats.parity_err_cnt++; + __hal_device_handle_parityerr(hldev, "misc_int_reg", err_reg); + return XGE_HAL_ERR_CRITICAL; + } + +#ifdef XGE_HAL_PROCESS_LINK_INT_IN_ISR + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA) +#endif + { + + /* Handling link status change error Intr */ + err_reg = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->mac_rmac_err_reg); + if (__hal_device_handle_link_state_change(hldev)) + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + err_reg, &bar0->mac_rmac_err_reg); + } + + if (hldev->inject_serr != 0) { + err_reg = hldev->inject_serr; + hldev->inject_serr = 0; + __hal_device_handle_serr(hldev, "inject_serr", err_reg); + return XGE_HAL_ERR_CRITICAL; + } + + if (hldev->inject_ecc != 0) { + err_reg = hldev->inject_ecc; + hldev->inject_ecc = 0; + hldev->stats.sw_dev_err_stats.ecc_err_cnt++; + __hal_device_handle_eccerr(hldev, "inject_ecc", err_reg); + return XGE_HAL_ERR_CRITICAL; + } + + if (hldev->inject_bad_tcode != 0) { + u8 t_code = hldev->inject_bad_tcode; + xge_hal_channel_t channel; + xge_hal_fifo_txd_t txd; + xge_hal_ring_rxd_1_t rxd; + + channel.devh = hldev; + + if (hldev->inject_bad_tcode_for_chan_type == + XGE_HAL_CHANNEL_TYPE_FIFO) { + channel.type = XGE_HAL_CHANNEL_TYPE_FIFO; + + } else { + channel.type = XGE_HAL_CHANNEL_TYPE_RING; + } + + hldev->inject_bad_tcode = 0; + + if (channel.type == XGE_HAL_CHANNEL_TYPE_FIFO) + return xge_hal_device_handle_tcode(&channel, &txd, + t_code); + else + return xge_hal_device_handle_tcode(&channel, &rxd, + t_code); + } + + return XGE_HAL_OK; +} + +/* + * __hal_verify_pcc_idle - Verify All Enbled PCC are IDLE or not + * @hldev: HAL device handle. + * @adp_status: Adapter Status value + * Usage: See xge_hal_device_enable{}. + */ +xge_hal_status_e +__hal_verify_pcc_idle(xge_hal_device_t *hldev, u64 adp_status) +{ + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA && + hldev->revision < 4) { + /* + * For Xena 1,2,3 we enable only 4 PCCs Due to + * SXE-008 (Transmit DMA arbitration issue) + */ + if ((adp_status & XGE_HAL_ADAPTER_STATUS_RMAC_PCC_4_IDLE) + != XGE_HAL_ADAPTER_STATUS_RMAC_PCC_4_IDLE) { + xge_debug_device(XGE_TRACE, "%s", + "PCC is not IDLE after adapter enabled!"); + return XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT; + } + } else { + if ((adp_status & XGE_HAL_ADAPTER_STATUS_RMAC_PCC_IDLE) != + XGE_HAL_ADAPTER_STATUS_RMAC_PCC_IDLE) { + xge_debug_device(XGE_TRACE, "%s", + "PCC is not IDLE after adapter enabled!"); + return XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT; + } + } + return XGE_HAL_OK; +} + +static void +__hal_update_bimodal(xge_hal_device_t *hldev, int ring_no) +{ + int tval, d, iwl_avg, len_avg, bytes_avg, bytes_hist, d_hist; + int iwl_rxcnt, iwl_txcnt, iwl_txavg, len_rxavg, iwl_rxavg, len_txavg; + int iwl_cnt, i; + +#define _HIST_SIZE 50 /* 0.5 sec history */ +#define _HIST_ADJ_TIMER 1 +#define _STEP 2 + + static int bytes_avg_history[_HIST_SIZE] = {0}; + static int d_avg_history[_HIST_SIZE] = {0}; + static int history_idx = 0; + static int pstep = 1; + static int hist_adj_timer = 0; + + /* + * tval - current value of this bimodal timer + */ + tval = hldev->bimodal_tti[ring_no].timer_val_us; + + /* + * d - how many interrupts we were getting since last + * bimodal timer tick. + */ + d = hldev->stats.sw_dev_info_stats.tx_traffic_intr_cnt - + hldev->bimodal_intr_cnt; + + /* advance bimodal interrupt counter */ + hldev->bimodal_intr_cnt = + hldev->stats.sw_dev_info_stats.tx_traffic_intr_cnt; + + /* + * iwl_cnt - how many interrupts we've got since last + * bimodal timer tick. + */ + iwl_rxcnt = (hldev->irq_workload_rxcnt[ring_no] ? + hldev->irq_workload_rxcnt[ring_no] : 1); + iwl_txcnt = (hldev->irq_workload_txcnt[ring_no] ? + hldev->irq_workload_txcnt[ring_no] : 1); + iwl_cnt = iwl_rxcnt + iwl_txcnt; + iwl_cnt = iwl_cnt; /* just to remove the lint warning */ + + /* + * we need to take hldev->config.isr_polling_cnt into account + * but for some reason this line causing GCC to produce wrong + * code on Solaris. As of now, if bimodal_interrupts is configured + * hldev->config.isr_polling_cnt is forced to be "0". + * + * iwl_cnt = iwl_cnt / (hldev->config.isr_polling_cnt + 1); */ + + /* + * iwl_avg - how many RXDs on avarage been processed since + * last bimodal timer tick. This indirectly includes + * CPU utilizations. + */ + iwl_rxavg = hldev->irq_workload_rxd[ring_no] / iwl_rxcnt; + iwl_txavg = hldev->irq_workload_txd[ring_no] / iwl_txcnt; + iwl_avg = iwl_rxavg + iwl_txavg; + iwl_avg = iwl_avg == 0 ? 1 : iwl_avg; + + /* + * len_avg - how many bytes on avarage been processed since + * last bimodal timer tick. i.e. avarage frame size. + */ + len_rxavg = 1 + hldev->irq_workload_rxlen[ring_no] / + (hldev->irq_workload_rxd[ring_no] ? + hldev->irq_workload_rxd[ring_no] : 1); + len_txavg = 1 + hldev->irq_workload_txlen[ring_no] / + (hldev->irq_workload_txd[ring_no] ? + hldev->irq_workload_txd[ring_no] : 1); + len_avg = len_rxavg + len_txavg; + if (len_avg < 60) + len_avg = 60; + + /* align on low boundary */ + if ((tval -_STEP) < hldev->config.bimodal_timer_lo_us) + tval = hldev->config.bimodal_timer_lo_us; + + /* reset faster */ + if (iwl_avg == 1) { + tval = hldev->config.bimodal_timer_lo_us; + /* reset history */ + for (i = 0; i < _HIST_SIZE; i++) + bytes_avg_history[i] = d_avg_history[i] = 0; + history_idx = 0; + pstep = 1; + hist_adj_timer = 0; + } + + /* always try to ajust timer to the best throughput value */ + bytes_avg = iwl_avg * len_avg; + history_idx %= _HIST_SIZE; + bytes_avg_history[history_idx] = bytes_avg; + d_avg_history[history_idx] = d; + history_idx++; + d_hist = bytes_hist = 0; + for (i = 0; i < _HIST_SIZE; i++) { + /* do not re-configure until history is gathered */ + if (!bytes_avg_history[i]) { + tval = hldev->config.bimodal_timer_lo_us; + goto _end; + } + bytes_hist += bytes_avg_history[i]; + d_hist += d_avg_history[i]; + } + bytes_hist /= _HIST_SIZE; + d_hist /= _HIST_SIZE; + +// xge_os_printf("d %d iwl_avg %d len_avg %d:%d:%d tval %d avg %d hist %d pstep %d", +// d, iwl_avg, len_txavg, len_rxavg, len_avg, tval, d*bytes_avg, +// d_hist*bytes_hist, pstep); + + /* make an adaptive step */ + if (d * bytes_avg < d_hist * bytes_hist && hist_adj_timer++ > _HIST_ADJ_TIMER) { + pstep = !pstep; + hist_adj_timer = 0; + } + + if (pstep && + (tval + _STEP) <= hldev->config.bimodal_timer_hi_us) { + tval += _STEP; + hldev->stats.sw_dev_info_stats.bimodal_hi_adjust_cnt++; + } else if ((tval - _STEP) >= hldev->config.bimodal_timer_lo_us) { + tval -= _STEP; + hldev->stats.sw_dev_info_stats.bimodal_lo_adjust_cnt++; + } + + /* enable TTI range A for better latencies */ + hldev->bimodal_urange_a_en = 0; + if (tval <= hldev->config.bimodal_timer_lo_us && iwl_avg > 2) + hldev->bimodal_urange_a_en = 1; + +_end: + /* reset workload statistics counters */ + hldev->irq_workload_rxcnt[ring_no] = 0; + hldev->irq_workload_rxd[ring_no] = 0; + hldev->irq_workload_rxlen[ring_no] = 0; + hldev->irq_workload_txcnt[ring_no] = 0; + hldev->irq_workload_txd[ring_no] = 0; + hldev->irq_workload_txlen[ring_no] = 0; + + /* reconfigure TTI56 + ring_no with new timer value */ + hldev->bimodal_timer_val_us = tval; + (void) __hal_device_rti_configure(hldev, 1); +} + +static void +__hal_update_rxufca(xge_hal_device_t *hldev, int ring_no) +{ + int ufc, ic, i; + + ufc = hldev->config.ring.queue[ring_no].rti.ufc_a; + ic = hldev->stats.sw_dev_info_stats.rx_traffic_intr_cnt; + + /* urange_a adaptive coalescing */ + if (hldev->rxufca_lbolt > hldev->rxufca_lbolt_time) { + if (ic > hldev->rxufca_intr_thres) { + if (ufc < hldev->config.rxufca_hi_lim) { + ufc += 1; + for (i=0; iconfig.ring.queue[i].rti.ufc_a = ufc; + (void) __hal_device_rti_configure(hldev, 1); + hldev->stats.sw_dev_info_stats. + rxufca_hi_adjust_cnt++; + } + hldev->rxufca_intr_thres = ic + + hldev->config.rxufca_intr_thres; /* def: 30 */ + } else { + if (ufc > hldev->config.rxufca_lo_lim) { + ufc -= 1; + for (i=0; iconfig.ring.queue[i].rti.ufc_a = ufc; + (void) __hal_device_rti_configure(hldev, 1); + hldev->stats.sw_dev_info_stats. + rxufca_lo_adjust_cnt++; + } + } + hldev->rxufca_lbolt_time = hldev->rxufca_lbolt + + hldev->config.rxufca_lbolt_period; + } + hldev->rxufca_lbolt++; +} + +/* + * __hal_device_handle_mc - Handle MC interrupt reason + * @hldev: HAL device handle. + * @reason: interrupt reason + */ +xge_hal_status_e +__hal_device_handle_mc(xge_hal_device_t *hldev, u64 reason) +{ + xge_hal_pci_bar0_t *isrbar0 = + (xge_hal_pci_bar0_t *)(void *)hldev->isrbar0; + u64 val64; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->mc_int_status); + if (!(val64 & XGE_HAL_MC_INT_STATUS_MC_INT)) + return XGE_HAL_OK; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->mc_err_reg); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &isrbar0->mc_err_reg); + + if (val64 & XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_L || + val64 & XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_U || + val64 & XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_0 || + val64 & XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_1 || + (xge_hal_device_check_id(hldev) != XGE_HAL_CARD_XENA && + (val64 & XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_L || + val64 & XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_U || + val64 & XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_L || + val64 & XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_U))) { + hldev->stats.sw_dev_err_stats.single_ecc_err_cnt++; + hldev->stats.sw_dev_err_stats.ecc_err_cnt++; + } + + if (val64 & XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_L || + val64 & XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_U || + val64 & XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_0 || + val64 & XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_1 || + (xge_hal_device_check_id(hldev) != XGE_HAL_CARD_XENA && + (val64 & XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_L || + val64 & XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_U || + val64 & XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_L || + val64 & XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_U))) { + hldev->stats.sw_dev_err_stats.double_ecc_err_cnt++; + hldev->stats.sw_dev_err_stats.ecc_err_cnt++; + } + + if (val64 & XGE_HAL_MC_ERR_REG_SM_ERR) { + hldev->stats.sw_dev_err_stats.sm_err_cnt++; + } + + /* those two should result in device reset */ + if (val64 & XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_0 || + val64 & XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_1) { + __hal_device_handle_eccerr(hldev, "mc_err_reg", val64); + return XGE_HAL_ERR_CRITICAL; + } + + return XGE_HAL_OK; +} + +/* + * __hal_device_handle_pic - Handle non-traffic PIC interrupt reason + * @hldev: HAL device handle. + * @reason: interrupt reason + */ +xge_hal_status_e +__hal_device_handle_pic(xge_hal_device_t *hldev, u64 reason) +{ + xge_hal_pci_bar0_t *isrbar0 = + (xge_hal_pci_bar0_t *)(void *)hldev->isrbar0; + u64 val64; + + if (reason & XGE_HAL_PIC_INT_FLSH) { + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->flsh_int_reg); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &isrbar0->flsh_int_reg); + /* FIXME: handle register */ + } + if (reason & XGE_HAL_PIC_INT_MDIO) { + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->mdio_int_reg); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &isrbar0->mdio_int_reg); + /* FIXME: handle register */ + } + if (reason & XGE_HAL_PIC_INT_IIC) { + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->iic_int_reg); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &isrbar0->iic_int_reg); + /* FIXME: handle register */ + } + if (reason & XGE_HAL_PIC_INT_MISC) { + val64 = xge_os_pio_mem_read64(hldev->pdev, + hldev->regh0, &isrbar0->misc_int_reg); +#ifdef XGE_HAL_PROCESS_LINK_INT_IN_ISR + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) { + /* Check for Link interrupts. If both Link Up/Down + * bits are set, clear both and check adapter status + */ + if ((val64 & XGE_HAL_MISC_INT_REG_LINK_UP_INT) && + (val64 & XGE_HAL_MISC_INT_REG_LINK_DOWN_INT)) { + u64 temp64; + + xge_debug_device(XGE_TRACE, + "both link up and link down detected "XGE_OS_LLXFMT, + (unsigned long long)val64); + + temp64 = (XGE_HAL_MISC_INT_REG_LINK_DOWN_INT | + XGE_HAL_MISC_INT_REG_LINK_UP_INT); + xge_os_pio_mem_write64(hldev->pdev, + hldev->regh0, temp64, + &isrbar0->misc_int_reg); + } + else if (val64 & XGE_HAL_MISC_INT_REG_LINK_UP_INT) { + xge_debug_device(XGE_TRACE, + "link up call request, misc_int "XGE_OS_LLXFMT, + (unsigned long long)val64); + __hal_device_handle_link_up_ind(hldev); + } + else if (val64 & XGE_HAL_MISC_INT_REG_LINK_DOWN_INT){ + xge_debug_device(XGE_TRACE, + "link down request, misc_int "XGE_OS_LLXFMT, + (unsigned long long)val64); + __hal_device_handle_link_down_ind(hldev); + } + } else +#endif + { + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &isrbar0->misc_int_reg); + } + } + + return XGE_HAL_OK; +} + +/* + * __hal_device_handle_txpic - Handle TxPIC interrupt reason + * @hldev: HAL device handle. + * @reason: interrupt reason + */ +xge_hal_status_e +__hal_device_handle_txpic(xge_hal_device_t *hldev, u64 reason) +{ + xge_hal_status_e status = XGE_HAL_OK; + xge_hal_pci_bar0_t *isrbar0 = + (xge_hal_pci_bar0_t *)(void *)hldev->isrbar0; + volatile u64 val64; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->pic_int_status); + if ( val64 & (XGE_HAL_PIC_INT_FLSH | + XGE_HAL_PIC_INT_MDIO | + XGE_HAL_PIC_INT_IIC | + XGE_HAL_PIC_INT_MISC) ) { + status = __hal_device_handle_pic(hldev, val64); + xge_os_wmb(); + } + + if (!(val64 & XGE_HAL_PIC_INT_TX)) + return status; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->txpic_int_reg); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &isrbar0->txpic_int_reg); + xge_os_wmb(); + + if (val64 & XGE_HAL_TXPIC_INT_SCHED_INTR) { + int i; + + if (g_xge_hal_driver->uld_callbacks.sched_timer != NULL) + g_xge_hal_driver->uld_callbacks.sched_timer( + hldev, hldev->upper_layer_info); + /* + * This feature implements adaptive receive interrupt + * coalecing. It is disabled by default. To enable it + * set hldev->config.rxufca_lo_lim to be not equal to + * hldev->config.rxufca_hi_lim. + * + * We are using HW timer for this feature, so + * use needs to configure hldev->config.rxufca_lbolt_period + * which is essentially a time slice of timer. + * + * For those who familiar with Linux, lbolt means jiffies + * of this timer. I.e. timer tick. + */ + if (hldev->config.rxufca_lo_lim != + hldev->config.rxufca_hi_lim && + hldev->config.rxufca_lo_lim != 0) { + for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) { + if (!hldev->config.ring.queue[i].configured) + continue; + if (hldev->config.ring.queue[i].rti.urange_a) + __hal_update_rxufca(hldev, i); + } + } + + /* + * This feature implements adaptive TTI timer re-calculation + * based on host utilization, number of interrupt processed, + * number of RXD per tick and avarage length of packets per + * tick. + */ + if (hldev->config.bimodal_interrupts) { + for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) { + if (!hldev->config.ring.queue[i].configured) + continue; + if (hldev->bimodal_tti[i].enabled) + __hal_update_bimodal(hldev, i); + } + } + } + + return XGE_HAL_OK; +} + +/* + * __hal_device_handle_txdma - Handle TxDMA interrupt reason + * @hldev: HAL device handle. + * @reason: interrupt reason + */ +xge_hal_status_e +__hal_device_handle_txdma(xge_hal_device_t *hldev, u64 reason) +{ + xge_hal_pci_bar0_t *isrbar0 = + (xge_hal_pci_bar0_t *)(void *)hldev->isrbar0; + u64 val64, temp64, err; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->txdma_int_status); + if (val64 & XGE_HAL_TXDMA_PFC_INT) { + err = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->pfc_err_reg); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + err, &isrbar0->pfc_err_reg); + hldev->stats.sw_dev_info_stats.pfc_err_cnt++; + temp64 = XGE_HAL_PFC_ECC_DB_ERR|XGE_HAL_PFC_SM_ERR_ALARM + |XGE_HAL_PFC_MISC_0_ERR|XGE_HAL_PFC_MISC_1_ERR + |XGE_HAL_PFC_PCIX_ERR; + if (val64 & temp64) + goto reset; + } + if (val64 & XGE_HAL_TXDMA_TDA_INT) { + err = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->tda_err_reg); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + err, &isrbar0->tda_err_reg); + hldev->stats.sw_dev_info_stats.tda_err_cnt++; + temp64 = XGE_HAL_TDA_Fn_ECC_DB_ERR|XGE_HAL_TDA_SM0_ERR_ALARM + |XGE_HAL_TDA_SM1_ERR_ALARM; + if (val64 & temp64) + goto reset; + } + if (val64 & XGE_HAL_TXDMA_PCC_INT) { + err = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->pcc_err_reg); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + err, &isrbar0->pcc_err_reg); + hldev->stats.sw_dev_info_stats.pcc_err_cnt++; + temp64 = XGE_HAL_PCC_FB_ECC_DB_ERR|XGE_HAL_PCC_TXB_ECC_DB_ERR + |XGE_HAL_PCC_SM_ERR_ALARM|XGE_HAL_PCC_WR_ERR_ALARM + |XGE_HAL_PCC_N_SERR|XGE_HAL_PCC_6_COF_OV_ERR + |XGE_HAL_PCC_7_COF_OV_ERR|XGE_HAL_PCC_6_LSO_OV_ERR + |XGE_HAL_PCC_7_LSO_OV_ERR; + if (val64 & temp64) + goto reset; + } + if (val64 & XGE_HAL_TXDMA_TTI_INT) { + err = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->tti_err_reg); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + err, &isrbar0->tti_err_reg); + hldev->stats.sw_dev_info_stats.tti_err_cnt++; + temp64 = XGE_HAL_TTI_SM_ERR_ALARM; + if (val64 & temp64) + goto reset; + } + if (val64 & XGE_HAL_TXDMA_LSO_INT) { + err = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->lso_err_reg); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + err, &isrbar0->lso_err_reg); + hldev->stats.sw_dev_info_stats.lso_err_cnt++; + temp64 = XGE_HAL_LSO6_ABORT|XGE_HAL_LSO7_ABORT + |XGE_HAL_LSO6_SM_ERR_ALARM|XGE_HAL_LSO7_SM_ERR_ALARM; + if (val64 & temp64) + goto reset; + } + if (val64 & XGE_HAL_TXDMA_TPA_INT) { + err = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->tpa_err_reg); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + err, &isrbar0->tpa_err_reg); + hldev->stats.sw_dev_info_stats.tpa_err_cnt++; + temp64 = XGE_HAL_TPA_SM_ERR_ALARM; + if (val64 & temp64) + goto reset; + } + if (val64 & XGE_HAL_TXDMA_SM_INT) { + err = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->sm_err_reg); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + err, &isrbar0->sm_err_reg); + hldev->stats.sw_dev_info_stats.sm_err_cnt++; + temp64 = XGE_HAL_SM_SM_ERR_ALARM; + if (val64 & temp64) + goto reset; + } + + return XGE_HAL_OK; + +reset : xge_hal_device_reset(hldev); + xge_hal_device_enable(hldev); + xge_hal_device_intr_enable(hldev); + return XGE_HAL_OK; +} + +/* + * __hal_device_handle_txmac - Handle TxMAC interrupt reason + * @hldev: HAL device handle. + * @reason: interrupt reason + */ +xge_hal_status_e +__hal_device_handle_txmac(xge_hal_device_t *hldev, u64 reason) +{ + xge_hal_pci_bar0_t *isrbar0 = + (xge_hal_pci_bar0_t *)(void *)hldev->isrbar0; + u64 val64, temp64; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->mac_int_status); + if (!(val64 & XGE_HAL_MAC_INT_STATUS_TMAC_INT)) + return XGE_HAL_OK; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->mac_tmac_err_reg); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &isrbar0->mac_tmac_err_reg); + hldev->stats.sw_dev_info_stats.mac_tmac_err_cnt++; + temp64 = XGE_HAL_TMAC_TX_BUF_OVRN|XGE_HAL_TMAC_TX_SM_ERR; + if (val64 & temp64) { + xge_hal_device_reset(hldev); + xge_hal_device_enable(hldev); + xge_hal_device_intr_enable(hldev); + } + + return XGE_HAL_OK; +} + +/* + * __hal_device_handle_txxgxs - Handle TxXGXS interrupt reason + * @hldev: HAL device handle. + * @reason: interrupt reason + */ +xge_hal_status_e +__hal_device_handle_txxgxs(xge_hal_device_t *hldev, u64 reason) +{ + xge_hal_pci_bar0_t *isrbar0 = + (xge_hal_pci_bar0_t *)(void *)hldev->isrbar0; + u64 val64, temp64; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->xgxs_int_status); + if (!(val64 & XGE_HAL_XGXS_INT_STATUS_TXGXS)) + return XGE_HAL_OK; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->xgxs_txgxs_err_reg); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &isrbar0->xgxs_txgxs_err_reg); + hldev->stats.sw_dev_info_stats.xgxs_txgxs_err_cnt++; + temp64 = XGE_HAL_TXGXS_ESTORE_UFLOW|XGE_HAL_TXGXS_TX_SM_ERR; + if (val64 & temp64) { + xge_hal_device_reset(hldev); + xge_hal_device_enable(hldev); + xge_hal_device_intr_enable(hldev); + } + + return XGE_HAL_OK; +} + +/* + * __hal_device_handle_rxpic - Handle RxPIC interrupt reason + * @hldev: HAL device handle. + * @reason: interrupt reason + */ +xge_hal_status_e +__hal_device_handle_rxpic(xge_hal_device_t *hldev, u64 reason) +{ + /* FIXME: handle register */ + + return XGE_HAL_OK; +} + +/* + * __hal_device_handle_rxdma - Handle RxDMA interrupt reason + * @hldev: HAL device handle. + * @reason: interrupt reason + */ +xge_hal_status_e +__hal_device_handle_rxdma(xge_hal_device_t *hldev, u64 reason) +{ + xge_hal_pci_bar0_t *isrbar0 = + (xge_hal_pci_bar0_t *)(void *)hldev->isrbar0; + u64 val64, err, temp64; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->rxdma_int_status); + if (val64 & XGE_HAL_RXDMA_RC_INT) { + err = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->rc_err_reg); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + err, &isrbar0->rc_err_reg); + hldev->stats.sw_dev_info_stats.rc_err_cnt++; + temp64 = XGE_HAL_RC_PRCn_ECC_DB_ERR|XGE_HAL_RC_FTC_ECC_DB_ERR + |XGE_HAL_RC_PRCn_SM_ERR_ALARM + |XGE_HAL_RC_FTC_SM_ERR_ALARM; + if (val64 & temp64) + goto reset; + } + if (val64 & XGE_HAL_RXDMA_RPA_INT) { + err = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->rpa_err_reg); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + err, &isrbar0->rpa_err_reg); + hldev->stats.sw_dev_info_stats.rpa_err_cnt++; + temp64 = XGE_HAL_RPA_SM_ERR_ALARM|XGE_HAL_RPA_CREDIT_ERR; + if (val64 & temp64) + goto reset; + } + if (val64 & XGE_HAL_RXDMA_RDA_INT) { + err = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->rda_err_reg); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + err, &isrbar0->rda_err_reg); + hldev->stats.sw_dev_info_stats.rda_err_cnt++; + temp64 = XGE_HAL_RDA_RXDn_ECC_DB_ERR + |XGE_HAL_RDA_FRM_ECC_DB_N_AERR + |XGE_HAL_RDA_SM1_ERR_ALARM|XGE_HAL_RDA_SM0_ERR_ALARM + |XGE_HAL_RDA_RXD_ECC_DB_SERR; + if (val64 & temp64) + goto reset; + } + if (val64 & XGE_HAL_RXDMA_RTI_INT) { + err = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->rti_err_reg); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + err, &isrbar0->rti_err_reg); + hldev->stats.sw_dev_info_stats.rti_err_cnt++; + temp64 = XGE_HAL_RTI_SM_ERR_ALARM; + if (val64 & temp64) + goto reset; + } + + return XGE_HAL_OK; + +reset : xge_hal_device_reset(hldev); + xge_hal_device_enable(hldev); + xge_hal_device_intr_enable(hldev); + return XGE_HAL_OK; +} + +/* + * __hal_device_handle_rxmac - Handle RxMAC interrupt reason + * @hldev: HAL device handle. + * @reason: interrupt reason + */ +xge_hal_status_e +__hal_device_handle_rxmac(xge_hal_device_t *hldev, u64 reason) +{ + xge_hal_pci_bar0_t *isrbar0 = + (xge_hal_pci_bar0_t *)(void *)hldev->isrbar0; + u64 val64, temp64; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->mac_int_status); + if (!(val64 & XGE_HAL_MAC_INT_STATUS_RMAC_INT)) + return XGE_HAL_OK; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->mac_rmac_err_reg); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &isrbar0->mac_rmac_err_reg); + hldev->stats.sw_dev_info_stats.mac_rmac_err_cnt++; + temp64 = XGE_HAL_RMAC_RX_BUFF_OVRN|XGE_HAL_RMAC_RX_SM_ERR; + if (val64 & temp64) { + xge_hal_device_reset(hldev); + xge_hal_device_enable(hldev); + xge_hal_device_intr_enable(hldev); + } + + return XGE_HAL_OK; +} + +/* + * __hal_device_handle_rxxgxs - Handle RxXGXS interrupt reason + * @hldev: HAL device handle. + * @reason: interrupt reason + */ +xge_hal_status_e +__hal_device_handle_rxxgxs(xge_hal_device_t *hldev, u64 reason) +{ + xge_hal_pci_bar0_t *isrbar0 = + (xge_hal_pci_bar0_t *)(void *)hldev->isrbar0; + u64 val64, temp64; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->xgxs_int_status); + if (!(val64 & XGE_HAL_XGXS_INT_STATUS_RXGXS)) + return XGE_HAL_OK; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &isrbar0->xgxs_rxgxs_err_reg); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &isrbar0->xgxs_rxgxs_err_reg); + hldev->stats.sw_dev_info_stats.xgxs_rxgxs_err_cnt++; + temp64 = XGE_HAL_RXGXS_ESTORE_OFLOW|XGE_HAL_RXGXS_RX_SM_ERR; + if (val64 & temp64) { + xge_hal_device_reset(hldev); + xge_hal_device_enable(hldev); + xge_hal_device_intr_enable(hldev); + } + + return XGE_HAL_OK; +} + +/** + * xge_hal_device_enable - Enable device. + * @hldev: HAL device handle. + * + * Enable the specified device: bring up the link/interface. + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT - Failed to restore the device + * to a "quiescent" state. + * + * See also: xge_hal_status_e{}. + * + * Usage: See ex_open{}. + */ +xge_hal_status_e +xge_hal_device_enable(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + u64 adp_status; + int i, j; + + if (!hldev->hw_is_initialized) { + xge_hal_status_e status; + + status = __hal_device_hw_initialize(hldev); + if (status != XGE_HAL_OK) { + return status; + } + } + + /* + * Not needed in most cases, i.e. + * when device_disable() is followed by reset - + * the latter copies back PCI config space, along with + * the bus mastership - see __hal_device_reset(). + * However, there are/may-in-future be other cases, and + * does not hurt. + */ + __hal_device_bus_master_enable(hldev); + + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) { + /* + * Configure the link stability period. + */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->misc_control); + if (hldev->config.link_stability_period != + XGE_HAL_DEFAULT_USE_HARDCODE) { + + val64 |= XGE_HAL_MISC_CONTROL_LINK_STABILITY_PERIOD( + hldev->config.link_stability_period); + } else { + /* + * Use the link stability period 1 ms as default + */ + val64 |= XGE_HAL_MISC_CONTROL_LINK_STABILITY_PERIOD( + XGE_HAL_DEFAULT_LINK_STABILITY_PERIOD); + } + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &bar0->misc_control); + + /* + * Clearing any possible Link up/down interrupts that + * could have popped up just before Enabling the card. + */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->misc_int_reg); + if (val64) { + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &bar0->misc_int_reg); + xge_debug_device(XGE_TRACE, "%s","link state cleared"); + } + } else if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA) { + /* + * Clearing any possible Link state change interrupts that + * could have popped up just before Enabling the card. + */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->mac_rmac_err_reg); + if (val64) { + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &bar0->mac_rmac_err_reg); + xge_debug_device(XGE_TRACE, "%s", "link state cleared"); + } + } + + if (__hal_device_wait_quiescent(hldev, &val64)) { + return XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT; + } + + /* Enabling Laser. */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->adapter_control); + val64 |= XGE_HAL_ADAPTER_EOI_TX_ON; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->adapter_control); + + /* let link establish */ + xge_os_mdelay(1); + + /* set link down untill poll() routine will set it up (maybe) */ + hldev->link_state = XGE_HAL_LINK_DOWN; + + /* If link is UP (adpter is connected) then enable the adapter */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->adapter_status); + if( val64 & (XGE_HAL_ADAPTER_STATUS_RMAC_REMOTE_FAULT | + XGE_HAL_ADAPTER_STATUS_RMAC_LOCAL_FAULT) ) { + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->adapter_control); + val64 = val64 & (~XGE_HAL_ADAPTER_LED_ON); + } else { + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->adapter_control); + val64 = val64 | ( XGE_HAL_ADAPTER_EOI_TX_ON | + XGE_HAL_ADAPTER_LED_ON ); + } + + val64 = val64 | XGE_HAL_ADAPTER_CNTL_EN; /* adapter enable */ + val64 = val64 & (~XGE_HAL_ADAPTER_ECC_EN); /* ECC enable */ + xge_os_pio_mem_write64 (hldev->pdev, hldev->regh0, val64, + &bar0->adapter_control); + + /* We spin here waiting for the Link to come up. + * This is the fix for the Link being unstable after the reset. */ + i = 0; + j = 0; + do + { + adp_status = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->adapter_status); + + /* Read the adapter control register for Adapter_enable bit */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->adapter_control); + if (!(adp_status & (XGE_HAL_ADAPTER_STATUS_RMAC_REMOTE_FAULT | + XGE_HAL_ADAPTER_STATUS_RMAC_LOCAL_FAULT)) && + (val64 & XGE_HAL_ADAPTER_CNTL_EN)) { + j++; + if (j >= hldev->config.link_valid_cnt) { + if (xge_hal_device_status(hldev, &adp_status) == + XGE_HAL_OK) { + if (__hal_verify_pcc_idle(hldev, + adp_status) != XGE_HAL_OK) { + return + XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT; + } + xge_debug_device(XGE_TRACE, + "adp_status: "XGE_OS_LLXFMT + ", link is up on " + "adapter enable!", + (unsigned long long)adp_status); + val64 = xge_os_pio_mem_read64( + hldev->pdev, + hldev->regh0, + &bar0->adapter_control); + val64 = val64| + (XGE_HAL_ADAPTER_EOI_TX_ON | + XGE_HAL_ADAPTER_LED_ON ); + xge_os_pio_mem_write64(hldev->pdev, + hldev->regh0, val64, + &bar0->adapter_control); + xge_os_mdelay(1); + + val64 = xge_os_pio_mem_read64( + hldev->pdev, + hldev->regh0, + &bar0->adapter_control); + break; /* out of for loop */ + } else { + return + XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT; + } + } + } else { + j = 0; /* Reset the count */ + /* Turn on the Laser */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->adapter_control); + val64 = val64 | XGE_HAL_ADAPTER_EOI_TX_ON; + xge_os_pio_mem_write64 (hldev->pdev, hldev->regh0, + val64, &bar0->adapter_control); + + xge_os_mdelay(1); + + /* Now re-enable it as due to noise, hardware + * turned it off */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->adapter_control); + val64 |= XGE_HAL_ADAPTER_CNTL_EN; + val64 = val64 & (~XGE_HAL_ADAPTER_ECC_EN);/*ECC enable*/ + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->adapter_control); + } + xge_os_mdelay(1); /* Sleep for 1 msec */ + i++; + } while (i < hldev->config.link_retry_cnt); + + __hal_device_led_actifity_fix(hldev); + +#ifndef XGE_HAL_PROCESS_LINK_INT_IN_ISR + /* Here we are performing soft reset on XGXS to force link down. + * Since link is already up, we will get link state change + * poll notificatoin after adapter is enabled */ + + __hal_serial_mem_write64(hldev, 0x80010515001E0000ULL, + &bar0->dtx_control); + (void) __hal_serial_mem_read64(hldev, &bar0->dtx_control); + + __hal_serial_mem_write64(hldev, 0x80010515001E00E0ULL, + &bar0->dtx_control); + (void) __hal_serial_mem_read64(hldev, &bar0->dtx_control); + + __hal_serial_mem_write64(hldev, 0x80070515001F00E4ULL, + &bar0->dtx_control); + (void) __hal_serial_mem_read64(hldev, &bar0->dtx_control); + + xge_os_mdelay(100); /* Sleep for 500 msec */ +#else + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA) +#endif + { + /* + * With some switches the link state change interrupt does not + * occur even though the xgxs reset is done as per SPN-006. So, + * poll the adapter status register and check if the link state + * is ok. + */ + adp_status = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->adapter_status); + if (!(adp_status & (XGE_HAL_ADAPTER_STATUS_RMAC_REMOTE_FAULT | + XGE_HAL_ADAPTER_STATUS_RMAC_LOCAL_FAULT))) + { + xge_debug_device(XGE_TRACE, "%s", + "enable device causing link state change ind.."); + (void) __hal_device_handle_link_state_change(hldev); + } + } + + if (hldev->config.stats_refresh_time_sec != + XGE_HAL_STATS_REFRESH_DISABLE) + __hal_stats_enable(&hldev->stats); + + return XGE_HAL_OK; +} + +/** + * xge_hal_device_disable - Disable Xframe adapter. + * @hldev: Device handle. + * + * Disable this device. To gracefully reset the adapter, the host should: + * + * - call xge_hal_device_disable(); + * + * - call xge_hal_device_intr_disable(); + * + * - close all opened channels and clean up outstanding resources; + * + * - do some work (error recovery, change mtu, reset, etc); + * + * - call xge_hal_device_enable(); + * + * - open channels, replenish RxDs, etc. + * + * - call xge_hal_device_intr_enable(). + * + * Note: Disabling the device does _not_ include disabling of interrupts. + * After disabling the device stops receiving new frames but those frames + * that were already in the pipe will keep coming for some few milliseconds. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT - Failed to restore the device to + * a "quiescent" state. + * + * See also: xge_hal_status_e{}. + */ +xge_hal_status_e +xge_hal_device_disable(xge_hal_device_t *hldev) +{ + xge_hal_status_e status = XGE_HAL_OK; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + + xge_debug_device(XGE_TRACE, "%s", "turn off laser, cleanup hardware"); + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->adapter_control); + val64 = val64 & (~XGE_HAL_ADAPTER_CNTL_EN); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->adapter_control); + + if (__hal_device_wait_quiescent(hldev, &val64) != XGE_HAL_OK) { + status = XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT; + } + + if (__hal_device_register_poll(hldev, &bar0->adapter_status, 1, + XGE_HAL_ADAPTER_STATUS_RC_PRC_QUIESCENT, + XGE_HAL_DEVICE_QUIESCENT_WAIT_MAX_MILLIS) != XGE_HAL_OK) { + xge_debug_device(XGE_TRACE, "%s", "PRC is not QUIESCENT!"); + status = XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT; + } + + if (hldev->config.stats_refresh_time_sec != + XGE_HAL_STATS_REFRESH_DISABLE) + __hal_stats_disable(&hldev->stats); +#ifdef XGE_DEBUG_ASSERT + else + xge_assert(!hldev->stats.is_enabled); +#endif + +#ifndef XGE_HAL_DONT_DISABLE_BUS_MASTER_ON_STOP + __hal_device_bus_master_disable(hldev); +#endif + + return status; +} + +/** + * xge_hal_device_reset - Reset device. + * @hldev: HAL device handle. + * + * Soft-reset the device, reset the device stats except reset_cnt. + * + * After reset is done, will try to re-initialize HW. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized. + * XGE_HAL_ERR_RESET_FAILED - Reset failed. + * + * See also: xge_hal_status_e{}. + */ +xge_hal_status_e +xge_hal_device_reset(xge_hal_device_t *hldev) +{ + xge_hal_status_e status; + + /* increment the soft reset counter */ + u32 reset_cnt = hldev->stats.sw_dev_info_stats.soft_reset_cnt; + + xge_debug_device(XGE_TRACE, "%s (%d)", "resetting the device", reset_cnt); + + if (!hldev->is_initialized) + return XGE_HAL_ERR_DEVICE_NOT_INITIALIZED; + + /* actual "soft" reset of the adapter */ + status = __hal_device_reset(hldev); + + /* reset all stats including saved */ + __hal_stats_soft_reset(hldev, 1); + + /* increment reset counter */ + hldev->stats.sw_dev_info_stats.soft_reset_cnt = reset_cnt + 1; + + /* re-initialize rxufca_intr_thres */ + hldev->rxufca_intr_thres = hldev->config.rxufca_intr_thres; + + hldev->reset_needed_after_close = 0; + + return status; +} + +/** + * xge_hal_device_status - Check whether Xframe hardware is ready for + * operation. + * @hldev: HAL device handle. + * @hw_status: Xframe status register. Returned by HAL. + * + * Check whether Xframe hardware is ready for operation. + * The checking includes TDMA, RDMA, PFC, PIC, MC_DRAM, and the rest + * hardware functional blocks. + * + * Returns: XGE_HAL_OK if the device is ready for operation. Otherwise + * returns XGE_HAL_FAIL. Also, fills in adapter status (in @hw_status). + * + * See also: xge_hal_status_e{}. + * Usage: See ex_open{}. + */ +xge_hal_status_e +xge_hal_device_status(xge_hal_device_t *hldev, u64 *hw_status) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 tmp64; + + tmp64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->adapter_status); + + *hw_status = tmp64; + + if (!(tmp64 & XGE_HAL_ADAPTER_STATUS_TDMA_READY)) { + xge_debug_device(XGE_TRACE, "%s", "TDMA is not ready!"); + return XGE_HAL_FAIL; + } + if (!(tmp64 & XGE_HAL_ADAPTER_STATUS_RDMA_READY)) { + xge_debug_device(XGE_TRACE, "%s", "RDMA is not ready!"); + return XGE_HAL_FAIL; + } + if (!(tmp64 & XGE_HAL_ADAPTER_STATUS_PFC_READY)) { + xge_debug_device(XGE_TRACE, "%s", "PFC is not ready!"); + return XGE_HAL_FAIL; + } + if (!(tmp64 & XGE_HAL_ADAPTER_STATUS_TMAC_BUF_EMPTY)) { + xge_debug_device(XGE_TRACE, "%s", "TMAC BUF is not empty!"); + return XGE_HAL_FAIL; + } + if (!(tmp64 & XGE_HAL_ADAPTER_STATUS_PIC_QUIESCENT)) { + xge_debug_device(XGE_TRACE, "%s", "PIC is not QUIESCENT!"); + return XGE_HAL_FAIL; + } + if (!(tmp64 & XGE_HAL_ADAPTER_STATUS_MC_DRAM_READY)) { + xge_debug_device(XGE_TRACE, "%s", "MC_DRAM is not ready!"); + return XGE_HAL_FAIL; + } + if (!(tmp64 & XGE_HAL_ADAPTER_STATUS_MC_QUEUES_READY)) { + xge_debug_device(XGE_TRACE, "%s", "MC_QUEUES is not ready!"); + return XGE_HAL_FAIL; + } + if (!(tmp64 & XGE_HAL_ADAPTER_STATUS_M_PLL_LOCK)) { + xge_debug_device(XGE_TRACE, "%s", "M_PLL is not locked!"); + return XGE_HAL_FAIL; + } +#ifndef XGE_HAL_HERC_EMULATION + /* + * Andrew: in PCI 33 mode, the P_PLL is not used, and therefore, + * the the P_PLL_LOCK bit in the adapter_status register will + * not be asserted. + */ + if (!(tmp64 & XGE_HAL_ADAPTER_STATUS_P_PLL_LOCK) && + xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC && + hldev->pci_mode != XGE_HAL_PCI_33MHZ_MODE) { + xge_debug_device(XGE_TRACE, "%s", "P_PLL is not locked!"); + return XGE_HAL_FAIL; + } +#endif + + return XGE_HAL_OK; +} + +void +__hal_device_msi_intr_endis(xge_hal_device_t *hldev, int flag) +{ + u16 msi_control_reg; + + xge_os_pci_read16(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, + msi_control), &msi_control_reg); + + if (flag) + msi_control_reg |= 0x1; + else + msi_control_reg &= ~0x1; + + xge_os_pci_write16(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, + msi_control), msi_control_reg); +} + +void +__hal_device_msix_intr_endis(xge_hal_device_t *hldev, + xge_hal_channel_t *channel, int flag) +{ + u64 val64; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)hldev->bar0; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->xmsi_mask_reg); + + if (flag) + val64 &= ~(1LL << ( 63 - channel->msix_idx )); + else + val64 |= (1LL << ( 63 - channel->msix_idx )); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->xmsi_mask_reg); +} + +/** + * xge_hal_device_intr_enable - Enable Xframe interrupts. + * @hldev: HAL device handle. + * @op: One of the xge_hal_device_intr_e enumerated values specifying + * the type(s) of interrupts to enable. + * + * Enable Xframe interrupts. The function is to be executed the last in + * Xframe initialization sequence. + * + * See also: xge_hal_device_intr_disable() + */ +void +xge_hal_device_intr_enable(xge_hal_device_t *hldev) +{ + xge_list_t *item; + u64 val64; + + /* PRC initialization and configuration */ + xge_list_for_each(item, &hldev->ring_channels) { + xge_hal_channel_h channel; + channel = xge_container_of(item, xge_hal_channel_t, item); + __hal_ring_prc_enable(channel); + } + + /* enable traffic only interrupts */ + if (hldev->config.intr_mode != XGE_HAL_INTR_MODE_IRQLINE) { + /* + * make sure all interrupts going to be disabled if MSI + * is enabled. + */ + __hal_device_intr_mgmt(hldev, XGE_HAL_ALL_INTRS, 0); + } else { + /* + * Enable the Tx traffic interrupts only if the TTI feature is + * enabled. + */ + val64 = 0; + if (hldev->tti_enabled) + val64 = XGE_HAL_TX_TRAFFIC_INTR; + + if (!hldev->config.bimodal_interrupts) + val64 |= XGE_HAL_RX_TRAFFIC_INTR; + + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA) + val64 |= XGE_HAL_RX_TRAFFIC_INTR; + + val64 |=XGE_HAL_TX_PIC_INTR | + XGE_HAL_MC_INTR | + XGE_HAL_TX_DMA_INTR | + (hldev->config.sched_timer_us != + XGE_HAL_SCHED_TIMER_DISABLED ? XGE_HAL_SCHED_INTR : 0); + __hal_device_intr_mgmt(hldev, val64, 1); + } + + /* + * Enable MSI-X interrupts + */ + if (hldev->config.intr_mode == XGE_HAL_INTR_MODE_MSIX) { + + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) { + /* + * To enable MSI-X, MSI also needs to be enabled, + * due to a bug in the herc NIC. + */ + __hal_device_msi_intr_endis(hldev, 1); + } + + + /* Enable the MSI-X interrupt for each configured channel */ + xge_list_for_each(item, &hldev->fifo_channels) { + xge_hal_channel_t *channel; + + channel = xge_container_of(item, + xge_hal_channel_t, item); + + /* 0 vector is reserved for alarms */ + if (!channel->msix_idx) + continue; + + __hal_device_msix_intr_endis(hldev, channel, 1); + } + + xge_list_for_each(item, &hldev->ring_channels) { + xge_hal_channel_t *channel; + + channel = xge_container_of(item, + xge_hal_channel_t, item); + + /* 0 vector is reserved for alarms */ + if (!channel->msix_idx) + continue; + + __hal_device_msix_intr_endis(hldev, channel, 1); + } + } + + xge_debug_device(XGE_TRACE, "%s", "interrupts are enabled"); +} + + +/** + * xge_hal_device_intr_disable - Disable Xframe interrupts. + * @hldev: HAL device handle. + * @op: One of the xge_hal_device_intr_e enumerated values specifying + * the type(s) of interrupts to disable. + * + * Disable Xframe interrupts. + * + * See also: xge_hal_device_intr_enable() + */ +void +xge_hal_device_intr_disable(xge_hal_device_t *hldev) +{ + xge_list_t *item; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + + if (hldev->config.intr_mode == XGE_HAL_INTR_MODE_MSIX) { + + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) { + /* + * To disable MSI-X, MSI also needs to be disabled, + * due to a bug in the herc NIC. + */ + __hal_device_msi_intr_endis(hldev, 0); + } + + /* Disable the MSI-X interrupt for each configured channel */ + xge_list_for_each(item, &hldev->fifo_channels) { + xge_hal_channel_t *channel; + + channel = xge_container_of(item, + xge_hal_channel_t, item); + + /* 0 vector is reserved for alarms */ + if (!channel->msix_idx) + continue; + + __hal_device_msix_intr_endis(hldev, channel, 0); + + } + + xge_os_pio_mem_write64(hldev->pdev, + hldev->regh0, 0xFFFFFFFFFFFFFFFFULL, + &bar0->tx_traffic_mask); + + xge_list_for_each(item, &hldev->ring_channels) { + xge_hal_channel_t *channel; + + channel = xge_container_of(item, + xge_hal_channel_t, item); + + /* 0 vector is reserved for alarms */ + if (!channel->msix_idx) + continue; + + __hal_device_msix_intr_endis(hldev, channel, 0); + } + + xge_os_pio_mem_write64(hldev->pdev, + hldev->regh0, 0xFFFFFFFFFFFFFFFFULL, + &bar0->rx_traffic_mask); + } + + /* + * Disable traffic only interrupts. + * Tx traffic interrupts are used only if the TTI feature is + * enabled. + */ + val64 = 0; + if (hldev->tti_enabled) + val64 = XGE_HAL_TX_TRAFFIC_INTR; + + val64 |= XGE_HAL_RX_TRAFFIC_INTR | + XGE_HAL_TX_PIC_INTR | + XGE_HAL_MC_INTR | + (hldev->config.sched_timer_us != XGE_HAL_SCHED_TIMER_DISABLED ? + XGE_HAL_SCHED_INTR : 0); + __hal_device_intr_mgmt(hldev, val64, 0); + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + 0xFFFFFFFFFFFFFFFFULL, + &bar0->general_int_mask); + + + /* disable all configured PRCs */ + xge_list_for_each(item, &hldev->ring_channels) { + xge_hal_channel_h channel; + channel = xge_container_of(item, xge_hal_channel_t, item); + __hal_ring_prc_disable(channel); + } + + xge_debug_device(XGE_TRACE, "%s", "interrupts are disabled"); +} + + +/** + * xge_hal_device_mcast_enable - Enable Xframe multicast addresses. + * @hldev: HAL device handle. + * + * Enable Xframe multicast addresses. + * Returns: XGE_HAL_OK on success. + * XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING - Failed to enable mcast + * feature within the time(timeout). + * + * See also: xge_hal_device_mcast_disable(), xge_hal_status_e{}. + */ +xge_hal_status_e +xge_hal_device_mcast_enable(xge_hal_device_t *hldev) +{ + u64 val64; + xge_hal_pci_bar0_t *bar0; + int mc_offset = XGE_HAL_MAC_MC_ALL_MC_ADDR_OFFSET; + + if (hldev == NULL) + return XGE_HAL_ERR_INVALID_DEVICE; + + if (hldev->mcast_refcnt) + return XGE_HAL_OK; + + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) + mc_offset = XGE_HAL_MAC_MC_ALL_MC_ADDR_OFFSET_HERC; + + hldev->mcast_refcnt = 1; + + bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + + /* Enable all Multicast addresses */ + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_RMAC_ADDR_DATA0_MEM_ADDR(0x010203040506ULL), + &bar0->rmac_addr_data0_mem); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_RMAC_ADDR_DATA1_MEM_MASK(0xfeffffffffffULL), + &bar0->rmac_addr_data1_mem); + val64 = XGE_HAL_RMAC_ADDR_CMD_MEM_WE | + XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | + XGE_HAL_RMAC_ADDR_CMD_MEM_OFFSET(mc_offset); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rmac_addr_cmd_mem); + + if (__hal_device_register_poll(hldev, + &bar0->rmac_addr_cmd_mem, 0, + XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, + XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS) != XGE_HAL_OK) { + /* upper layer may require to repeat */ + return XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING; + } + + return XGE_HAL_OK; +} + +/** + * xge_hal_device_mcast_disable - Disable Xframe multicast addresses. + * @hldev: HAL device handle. + * + * Disable Xframe multicast addresses. + * Returns: XGE_HAL_OK - success. + * XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING - Failed to disable mcast + * feature within the time(timeout). + * + * See also: xge_hal_device_mcast_enable(), xge_hal_status_e{}. + */ +xge_hal_status_e +xge_hal_device_mcast_disable(xge_hal_device_t *hldev) +{ + u64 val64; + xge_hal_pci_bar0_t *bar0; + int mc_offset = XGE_HAL_MAC_MC_ALL_MC_ADDR_OFFSET; + + if (hldev == NULL) + return XGE_HAL_ERR_INVALID_DEVICE; + + if (hldev->mcast_refcnt == 0) + return XGE_HAL_OK; + + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) + mc_offset = XGE_HAL_MAC_MC_ALL_MC_ADDR_OFFSET_HERC; + + hldev->mcast_refcnt = 0; + + bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + + /* Disable all Multicast addresses */ + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_RMAC_ADDR_DATA0_MEM_ADDR(0xffffffffffffULL), + &bar0->rmac_addr_data0_mem); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_RMAC_ADDR_DATA1_MEM_MASK(0), + &bar0->rmac_addr_data1_mem); + + val64 = XGE_HAL_RMAC_ADDR_CMD_MEM_WE | + XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | + XGE_HAL_RMAC_ADDR_CMD_MEM_OFFSET(mc_offset); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rmac_addr_cmd_mem); + + if (__hal_device_register_poll(hldev, + &bar0->rmac_addr_cmd_mem, 0, + XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, + XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS) != XGE_HAL_OK) { + /* upper layer may require to repeat */ + return XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING; + } + + return XGE_HAL_OK; +} + +/** + * xge_hal_device_promisc_enable - Enable promiscuous mode. + * @hldev: HAL device handle. + * + * Enable promiscuous mode of Xframe operation. + * + * See also: xge_hal_device_promisc_disable(). + */ +void +xge_hal_device_promisc_enable(xge_hal_device_t *hldev) +{ + u64 val64; + xge_hal_pci_bar0_t *bar0; + + xge_assert(hldev); + + bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + + if (!hldev->is_promisc) { + /* Put the NIC into promiscuous mode */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->mac_cfg); + val64 |= XGE_HAL_MAC_CFG_RMAC_PROM_ENABLE; + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_RMAC_CFG_KEY(0x4C0D), + &bar0->rmac_cfg_key); + + __hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0, + (u32)(val64 >> 32), + &bar0->mac_cfg); + + hldev->is_promisc = 1; + xge_debug_device(XGE_TRACE, + "mac_cfg 0x"XGE_OS_LLXFMT": promisc enabled", + (unsigned long long)val64); + } +} + +/** + * xge_hal_device_promisc_disable - Disable promiscuous mode. + * @hldev: HAL device handle. + * + * Disable promiscuous mode of Xframe operation. + * + * See also: xge_hal_device_promisc_enable(). + */ +void +xge_hal_device_promisc_disable(xge_hal_device_t *hldev) +{ + u64 val64; + xge_hal_pci_bar0_t *bar0; + + xge_assert(hldev); + + bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + + if (hldev->is_promisc) { + /* Remove the NIC from promiscuous mode */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->mac_cfg); + val64 &= ~XGE_HAL_MAC_CFG_RMAC_PROM_ENABLE; + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_RMAC_CFG_KEY(0x4C0D), + &bar0->rmac_cfg_key); + + __hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0, + (u32)(val64 >> 32), + &bar0->mac_cfg); + + hldev->is_promisc = 0; + xge_debug_device(XGE_TRACE, + "mac_cfg 0x"XGE_OS_LLXFMT": promisc disabled", + (unsigned long long)val64); + } +} + +/** + * xge_hal_device_macaddr_get - Get MAC addresses. + * @hldev: HAL device handle. + * @index: MAC address index, in the range from 0 to + * XGE_HAL_MAX_MAC_ADDRESSES. + * @macaddr: MAC address. Returned by HAL. + * + * Retrieve one of the stored MAC addresses by reading non-volatile + * memory on the chip. + * + * Up to %XGE_HAL_MAX_MAC_ADDRESSES addresses is supported. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING - Failed to retrieve the mac + * address within the time(timeout). + * XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES - Invalid MAC address index. + * + * See also: xge_hal_device_macaddr_set(), xge_hal_status_e{}. + */ +xge_hal_status_e +xge_hal_device_macaddr_get(xge_hal_device_t *hldev, int index, + macaddr_t *macaddr) +{ + xge_hal_pci_bar0_t *bar0 = + (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + int i; + + if (hldev == NULL) { + return XGE_HAL_ERR_INVALID_DEVICE; + } + + if ( index >= XGE_HAL_MAX_MAC_ADDRESSES ) { + return XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES; + } + +#ifdef XGE_HAL_HERC_EMULATION + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,0x0000010000000000, + &bar0->rmac_addr_data0_mem); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,0x0000000000000000, + &bar0->rmac_addr_data1_mem); + val64 = XGE_HAL_RMAC_ADDR_CMD_MEM_RD | + XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | + XGE_HAL_RMAC_ADDR_CMD_MEM_OFFSET((index)); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rmac_addr_cmd_mem); + + /* poll until done */ + __hal_device_register_poll(hldev, + &bar0->rmac_addr_cmd_mem, 0, + XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD, + XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS); + +#endif + + val64 = ( XGE_HAL_RMAC_ADDR_CMD_MEM_RD | + XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | + XGE_HAL_RMAC_ADDR_CMD_MEM_OFFSET((index)) ); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rmac_addr_cmd_mem); + + if (__hal_device_register_poll(hldev, &bar0->rmac_addr_cmd_mem, 0, + XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, + XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS) != XGE_HAL_OK) { + /* upper layer may require to repeat */ + return XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING; + } + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->rmac_addr_data0_mem); + for (i=0; i < XGE_HAL_ETH_ALEN; i++) { + (*macaddr)[i] = (u8)(val64 >> ((64 - 8) - (i * 8))); + } + +#ifdef XGE_HAL_HERC_EMULATION + for (i=0; i < XGE_HAL_ETH_ALEN; i++) { + (*macaddr)[i] = (u8)0; + } + (*macaddr)[1] = (u8)1; + +#endif + + return XGE_HAL_OK; +} + +/** + * xge_hal_device_macaddr_set - Set MAC address. + * @hldev: HAL device handle. + * @index: MAC address index, in the range from 0 to + * XGE_HAL_MAX_MAC_ADDRESSES. + * @macaddr: New MAC address to configure. + * + * Configure one of the available MAC address "slots". + * + * Up to %XGE_HAL_MAX_MAC_ADDRESSES addresses is supported. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING - Failed to set the new mac + * address within the time(timeout). + * XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES - Invalid MAC address index. + * + * See also: xge_hal_device_macaddr_get(), xge_hal_status_e{}. + */ +xge_hal_status_e +xge_hal_device_macaddr_set(xge_hal_device_t *hldev, int index, + macaddr_t macaddr) +{ + xge_hal_pci_bar0_t *bar0 = + (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64, temp64; + int i; + + if ( index >= XGE_HAL_MAX_MAC_ADDRESSES ) + return XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES; + + temp64 = 0; + for (i=0; i < XGE_HAL_ETH_ALEN; i++) { + temp64 |= macaddr[i]; + temp64 <<= 8; + } + temp64 >>= 8; + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_RMAC_ADDR_DATA0_MEM_ADDR(temp64), + &bar0->rmac_addr_data0_mem); + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_RMAC_ADDR_DATA1_MEM_MASK(0ULL), + &bar0->rmac_addr_data1_mem); + + val64 = ( XGE_HAL_RMAC_ADDR_CMD_MEM_WE | + XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | + XGE_HAL_RMAC_ADDR_CMD_MEM_OFFSET((index)) ); + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rmac_addr_cmd_mem); + + if (__hal_device_register_poll(hldev, &bar0->rmac_addr_cmd_mem, 0, + XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, + XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS) != XGE_HAL_OK) { + /* upper layer may require to repeat */ + return XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING; + } + + return XGE_HAL_OK; +} + +/** + * xge_hal_device_macaddr_clear - Set MAC address. + * @hldev: HAL device handle. + * @index: MAC address index, in the range from 0 to + * XGE_HAL_MAX_MAC_ADDRESSES. + * + * Clear one of the available MAC address "slots". + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING - Failed to set the new mac + * address within the time(timeout). + * XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES - Invalid MAC address index. + * + * See also: xge_hal_device_macaddr_set(), xge_hal_status_e{}. + */ +xge_hal_status_e +xge_hal_device_macaddr_clear(xge_hal_device_t *hldev, int index) +{ + xge_hal_status_e status; + u8 macaddr[6] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; + + status = xge_hal_device_macaddr_set(hldev, index, macaddr); + if (status != XGE_HAL_OK) { + xge_debug_device(XGE_ERR, "%s", + "Not able to set the mac addr"); + return status; + } + + return XGE_HAL_OK; +} + +/** + * xge_hal_device_macaddr_find - Finds index in the rmac table. + * @hldev: HAL device handle. + * @wanted: Wanted MAC address. + * + * See also: xge_hal_device_macaddr_set(). + */ +int +xge_hal_device_macaddr_find(xge_hal_device_t *hldev, macaddr_t wanted) +{ + int i; + + if (hldev == NULL) { + return XGE_HAL_ERR_INVALID_DEVICE; + } + + for (i=1; iconfig.mtu != new_mtu) { + if (hldev->reset_needed_after_close || + !hldev->mtu_first_time_set) { + status = xge_hal_device_reset(hldev); + if (status != XGE_HAL_OK) { + xge_debug_device(XGE_TRACE, "%s", + "fatal: can not reset the device"); + return status; + } + } + /* store the new MTU in device, reset will use it */ + hldev->config.mtu = new_mtu; + xge_debug_device(XGE_TRACE, "new MTU %d applied", + new_mtu); + } + + if (!hldev->mtu_first_time_set) + hldev->mtu_first_time_set = 1; + + return XGE_HAL_OK; +} + +/** + * xge_hal_device_initialize - Initialize Xframe device. + * @hldev: HAL device handle. + * @attr: pointer to xge_hal_device_attr_t structure + * @device_config: Configuration to be _applied_ to the device, + * For the Xframe configuration "knobs" please + * refer to xge_hal_device_config_t and Xframe + * User Guide. + * + * Initialize Xframe device. Note that all the arguments of this public API + * are 'IN', including @hldev. Upper-layer driver (ULD) cooperates with + * OS to find new Xframe device, locate its PCI and memory spaces. + * + * When done, the ULD allocates sizeof(xge_hal_device_t) bytes for HAL + * to enable the latter to perform Xframe hardware initialization. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_DRIVER_NOT_INITIALIZED - Driver is not initialized. + * XGE_HAL_ERR_BAD_DEVICE_CONFIG - Device configuration params are not + * valid. + * XGE_HAL_ERR_OUT_OF_MEMORY - Memory allocation failed. + * XGE_HAL_ERR_BAD_SUBSYSTEM_ID - Device subsystem id is invalid. + * XGE_HAL_ERR_INVALID_MAC_ADDRESS - Device mac address in not valid. + * XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING - Failed to retrieve the mac + * address within the time(timeout) or TTI/RTI initialization failed. + * XGE_HAL_ERR_SWAPPER_CTRL - Failed to configure swapper control. + * XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT -Device is not queiscent. + * + * See also: xge_hal_device_terminate(), xge_hal_status_e{} + * xge_hal_device_attr_t{}. + */ +xge_hal_status_e +xge_hal_device_initialize(xge_hal_device_t *hldev, xge_hal_device_attr_t *attr, + xge_hal_device_config_t *device_config) +{ + int i; + xge_hal_status_e status; + xge_hal_channel_t *channel; + u16 subsys_device; + u16 subsys_vendor; + int total_dram_size, ring_auto_dram_cfg, left_dram_size; + int total_dram_size_max = 0; + + xge_debug_device(XGE_TRACE, "device 0x"XGE_OS_LLXFMT" is initializing", + (unsigned long long)(ulong_t)hldev); + + /* sanity check */ + if (g_xge_hal_driver == NULL || + !g_xge_hal_driver->is_initialized) { + return XGE_HAL_ERR_DRIVER_NOT_INITIALIZED; + } + + xge_os_memzero(hldev, sizeof(xge_hal_device_t)); + + /* + * validate a common part of Xframe-I/II configuration + * (and run check_card() later, once PCI inited - see below) + */ + status = __hal_device_config_check_common(device_config); + if (status != XGE_HAL_OK) + return status; + + /* apply config */ + xge_os_memcpy(&hldev->config, device_config, + sizeof(xge_hal_device_config_t)); + + /* save original attr */ + xge_os_memcpy(&hldev->orig_attr, attr, + sizeof(xge_hal_device_attr_t)); + + /* initialize rxufca_intr_thres */ + hldev->rxufca_intr_thres = hldev->config.rxufca_intr_thres; + + hldev->regh0 = attr->regh0; + hldev->regh1 = attr->regh1; + hldev->regh2 = attr->regh2; + hldev->isrbar0 = hldev->bar0 = attr->bar0; + hldev->bar1 = attr->bar1; + hldev->bar2 = attr->bar2; + hldev->pdev = attr->pdev; + hldev->irqh = attr->irqh; + hldev->cfgh = attr->cfgh; + + /* set initial bimodal timer for bimodal adaptive schema */ + hldev->bimodal_timer_val_us = hldev->config.bimodal_timer_lo_us; + + hldev->queueh = xge_queue_create(hldev->pdev, hldev->irqh, + g_xge_hal_driver->config.queue_size_initial, + g_xge_hal_driver->config.queue_size_max, + __hal_device_event_queued, hldev); + if (hldev->queueh == NULL) + return XGE_HAL_ERR_OUT_OF_MEMORY; + + hldev->magic = XGE_HAL_MAGIC; + + xge_assert(hldev->regh0); + xge_assert(hldev->regh1); + xge_assert(hldev->bar0); + xge_assert(hldev->bar1); + xge_assert(hldev->pdev); + xge_assert(hldev->irqh); + xge_assert(hldev->cfgh); + + /* initialize some PCI/PCI-X fields of this PCI device. */ + __hal_device_pci_init(hldev); + + /* + * initlialize lists to properly handling a potential + * terminate request + */ + xge_list_init(&hldev->free_channels); + xge_list_init(&hldev->fifo_channels); + xge_list_init(&hldev->ring_channels); + + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA) { + /* fixups for xena */ + hldev->config.rth_en = 0; + hldev->config.rth_spdm_en = 0; + hldev->config.rts_mac_en = 0; + total_dram_size_max = XGE_HAL_MAX_RING_QUEUE_SIZE_XENA; + + status = __hal_device_config_check_xena(device_config); + if (status != XGE_HAL_OK) { + xge_hal_device_terminate(hldev); + return status; + } + if (hldev->config.bimodal_interrupts == 1) { + xge_hal_device_terminate(hldev); + return XGE_HAL_BADCFG_BIMODAL_XENA_NOT_ALLOWED; + } else if (hldev->config.bimodal_interrupts == + XGE_HAL_DEFAULT_USE_HARDCODE) + hldev->config.bimodal_interrupts = 0; + } else if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) { + /* fixups for herc */ + total_dram_size_max = XGE_HAL_MAX_RING_QUEUE_SIZE_HERC; + status = __hal_device_config_check_herc(device_config); + if (status != XGE_HAL_OK) { + xge_hal_device_terminate(hldev); + return status; + } + if (hldev->config.bimodal_interrupts == + XGE_HAL_DEFAULT_USE_HARDCODE) + hldev->config.bimodal_interrupts = 1; + } else { + xge_debug_device(XGE_ERR, + "detected unknown device_id 0x%x", hldev->device_id); + xge_hal_device_terminate(hldev); + return XGE_HAL_ERR_BAD_DEVICE_ID; + } + +#ifdef XGEHAL_RNIC + + if(__hal_blockpool_create(hldev,&hldev->block_pool, + XGE_HAL_BLOCKPOOL_SIZE) != XGE_HAL_OK) { + xge_debug_device(XGE_ERR, + "block pool: __hal_blockpool_create failed"); + xge_hal_device_terminate(hldev); + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + + if(__hal_regpool_create(hldev,&hldev->reg_pool, + XGE_HAL_REGPOOL_SIZE) != XGE_HAL_OK) { + xge_debug_device(XGE_ERR, + "reg pool: __hal_regpool_create failed"); + xge_hal_device_terminate(hldev); + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + + for(i = 0; i < XGE_HAL_MAX_VIRTUAL_PATHS; i++) { + if(__hal_vp_initialize(hldev, i, &device_config->vp_config[i]) + != XGE_HAL_OK) { + xge_debug_device(XGE_ERR, + "virtual Paths: __hal_vp_initialize failed"); + xge_hal_device_terminate(hldev); + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + } + +#endif + + /* allocate and initialize FIFO types of channels according to + * configuration */ + for (i = 0; i < XGE_HAL_MAX_FIFO_NUM; i++) { + if (!device_config->fifo.queue[i].configured) + continue; + + channel = __hal_channel_allocate(hldev, i, +#ifdef XGEHAL_RNIC + 0, +#endif + XGE_HAL_CHANNEL_TYPE_FIFO); + if (channel == NULL) { + xge_debug_device(XGE_ERR, + "fifo: __hal_channel_allocate failed"); + xge_hal_device_terminate(hldev); + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + /* add new channel to the device */ + xge_list_insert(&channel->item, &hldev->free_channels); + } + + /* + * automatic DRAM adjustment + */ + total_dram_size = 0; + ring_auto_dram_cfg = 0; + for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) { + if (!device_config->ring.queue[i].configured) + continue; + if (device_config->ring.queue[i].dram_size_mb == + XGE_HAL_DEFAULT_USE_HARDCODE) { + ring_auto_dram_cfg++; + continue; + } + total_dram_size += device_config->ring.queue[i].dram_size_mb; + } + left_dram_size = total_dram_size_max - total_dram_size; + if (left_dram_size < 0 || + (ring_auto_dram_cfg && left_dram_size / ring_auto_dram_cfg == 0)) { + xge_debug_device(XGE_ERR, + "ring config: exceeded DRAM size %d MB", + total_dram_size_max); + xge_hal_device_terminate(hldev); + return XGE_HAL_BADCFG_RING_QUEUE_SIZE; + } + + /* + * allocate and initialize RING types of channels according to + * configuration + */ + for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) { + if (!device_config->ring.queue[i].configured) + continue; + + if (device_config->ring.queue[i].dram_size_mb == + XGE_HAL_DEFAULT_USE_HARDCODE) { + hldev->config.ring.queue[i].dram_size_mb = + device_config->ring.queue[i].dram_size_mb = + left_dram_size / ring_auto_dram_cfg; + } + + channel = __hal_channel_allocate(hldev, i, +#ifdef XGEHAL_RNIC + 0, +#endif + XGE_HAL_CHANNEL_TYPE_RING); + if (channel == NULL) { + xge_debug_device(XGE_ERR, + "ring: __hal_channel_allocate failed"); + xge_hal_device_terminate(hldev); + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + /* add new channel to the device */ + xge_list_insert(&channel->item, &hldev->free_channels); + } + + /* get subsystem IDs */ + xge_os_pci_read16(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, subsystem_id), + &subsys_device); + xge_os_pci_read16(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, subsystem_vendor_id), + &subsys_vendor); + xge_debug_device(XGE_TRACE, + "subsystem_id %04x:%04x", + subsys_vendor, subsys_device); + + /* reset device initially */ + (void) __hal_device_reset(hldev); + + /* set host endian before, to assure proper action */ + status = __hal_device_set_swapper(hldev); + if (status != XGE_HAL_OK) { + xge_debug_device(XGE_ERR, + "__hal_device_set_swapper failed"); + xge_hal_device_terminate(hldev); + (void) __hal_device_reset(hldev); + return status; + } + +#ifndef XGE_HAL_HERC_EMULATION + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA) + __hal_device_xena_fix_mac(hldev); +#endif + + /* MAC address initialization. + * For now only one mac address will be read and used. */ + status = xge_hal_device_macaddr_get(hldev, 0, &hldev->macaddr[0]); + if (status != XGE_HAL_OK) { + xge_debug_device(XGE_ERR, + "xge_hal_device_macaddr_get failed"); + xge_hal_device_terminate(hldev); + return status; + } + + if (hldev->macaddr[0][0] == 0xFF && + hldev->macaddr[0][1] == 0xFF && + hldev->macaddr[0][2] == 0xFF && + hldev->macaddr[0][3] == 0xFF && + hldev->macaddr[0][4] == 0xFF && + hldev->macaddr[0][5] == 0xFF) { + xge_debug_device(XGE_ERR, + "xge_hal_device_macaddr_get returns all FFs"); + xge_hal_device_terminate(hldev); + return XGE_HAL_ERR_INVALID_MAC_ADDRESS; + } + + xge_debug_device(XGE_TRACE, + "default macaddr: 0x%02x-%02x-%02x-%02x-%02x-%02x", + hldev->macaddr[0][0], hldev->macaddr[0][1], + hldev->macaddr[0][2], hldev->macaddr[0][3], + hldev->macaddr[0][4], hldev->macaddr[0][5]); + + status = __hal_stats_initialize(&hldev->stats, hldev); + if (status != XGE_HAL_OK) { + xge_debug_device(XGE_ERR, + "__hal_stats_initialize failed"); + xge_hal_device_terminate(hldev); + return status; + } + + status = __hal_device_hw_initialize(hldev); + if (status != XGE_HAL_OK) { + xge_debug_device(XGE_ERR, + "__hal_device_hw_initialize failed"); + xge_hal_device_terminate(hldev); + return status; + } + hldev->dump_buf=(char*)xge_os_malloc(hldev->pdev, XGE_HAL_DUMP_BUF_SIZE); + if (hldev->dump_buf == NULL) { + xge_debug_device(XGE_ERR, + "__hal_device_hw_initialize failed"); + xge_hal_device_terminate(hldev); + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + + + /* Xena-only: need to serialize fifo posts across all device fifos */ +#if defined(XGE_HAL_TX_MULTI_POST) + xge_os_spin_lock_init(&hldev->xena_post_lock, hldev->pdev); +#elif defined(XGE_HAL_TX_MULTI_POST_IRQ) + xge_os_spin_lock_init_irq(&hldev->xena_post_lock, hldev->irqh); +#endif + /* Getting VPD data */ + __hal_device_get_vpd_data(hldev); + + hldev->is_initialized = 1; + + return XGE_HAL_OK; +} + +/** + * xge_hal_device_terminating - Mark the device as 'terminating'. + * @devh: HAL device handle. + * + * Mark the device as 'terminating', going to terminate. Can be used + * to serialize termination with other running processes/contexts. + * + * See also: xge_hal_device_terminate(). + */ +void +xge_hal_device_terminating(xge_hal_device_h devh) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + hldev->terminating = 1; +} + +/** + * xge_hal_device_terminate - Terminate Xframe device. + * @hldev: HAL device handle. + * + * Terminate HAL device. + * + * See also: xge_hal_device_initialize(). + */ +void +xge_hal_device_terminate(xge_hal_device_t *hldev) +{ +#ifdef XGEHAL_RNIC + int i; +#endif + xge_assert(g_xge_hal_driver != NULL); + xge_assert(hldev != NULL); + xge_assert(hldev->magic == XGE_HAL_MAGIC); + + xge_queue_flush(hldev->queueh); + + hldev->terminating = 1; + hldev->is_initialized = 0; + hldev->in_poll = 0; + hldev->magic = XGE_HAL_DEAD; + +#if defined(XGE_HAL_TX_MULTI_POST) + xge_os_spin_lock_destroy(&hldev->xena_post_lock, hldev->pdev); +#elif defined(XGE_HAL_TX_MULTI_POST_IRQ) + xge_os_spin_lock_destroy_irq(&hldev->xena_post_lock, hldev->pdev); +#endif + + xge_debug_device(XGE_TRACE, "device "XGE_OS_LLXFMT" is terminating", + (unsigned long long)(ulong_t)hldev); + + xge_assert(xge_list_is_empty(&hldev->fifo_channels)); + xge_assert(xge_list_is_empty(&hldev->ring_channels)); + + if (hldev->stats.is_initialized) { + __hal_stats_terminate(&hldev->stats); + } + + /* close if open and free all channels */ + while (!xge_list_is_empty(&hldev->free_channels)) { + xge_hal_channel_t *channel = (xge_hal_channel_t*) + hldev->free_channels.next; + + xge_assert(!channel->is_open); + xge_list_remove(&channel->item); + __hal_channel_free(channel); + } + + if (hldev->queueh) { + xge_queue_destroy(hldev->queueh); + } + + if (hldev->spdm_table) { + xge_os_free(hldev->pdev, + hldev->spdm_table[0], + (sizeof(xge_hal_spdm_entry_t) * + hldev->spdm_max_entries)); + xge_os_free(hldev->pdev, + hldev->spdm_table, + (sizeof(xge_hal_spdm_entry_t *) * + hldev->spdm_max_entries)); + xge_os_spin_lock_destroy(&hldev->spdm_lock, hldev->pdev); + hldev->spdm_table = NULL; + } + + if (hldev->dump_buf) { + xge_os_free(hldev->pdev, hldev->dump_buf, + XGE_HAL_DUMP_BUF_SIZE); + hldev->dump_buf = NULL; + } + + if (hldev->device_id != 0) { + int j, pcisize; + + pcisize = (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC)? + XGE_HAL_PCISIZE_HERC : XGE_HAL_PCISIZE_XENA; + for (j = 0; j < pcisize; j++) { + xge_os_pci_write32(hldev->pdev, hldev->cfgh, j * 4, + *((u32*)&hldev->pci_config_space_bios + j)); + } + } +#ifdef XGEHAL_RNIC + + for(i = 0; i < XGE_HAL_MAX_VIRTUAL_PATHS; i++) { + __hal_vp_terminate(hldev, i); + } + + __hal_blockpool_destroy(&hldev->block_pool); + + __hal_regpool_destroy(&hldev->reg_pool); +#endif + +} +/** + * __hal_device_get_vpd_data - Getting vpd_data. + * + * @hldev: HAL device handle. + * + * Getting product name and serial number from vpd capabilites structure + * + */ +void +__hal_device_get_vpd_data(xge_hal_device_t *hldev) +{ + u8 * vpd_data; + u8 data; + int index = 0, count, fail = 0; + u8 vpd_addr = XGE_HAL_CARD_XENA_VPD_ADDR; + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) + vpd_addr = XGE_HAL_CARD_HERC_VPD_ADDR; + + xge_os_strcpy((char *) hldev->vpd_data.product_name, + "10 Gigabit Ethernet Adapter"); + xge_os_strcpy((char *) hldev->vpd_data.serial_num, "not available"); + + vpd_data = ( u8*) xge_os_malloc(hldev->pdev, XGE_HAL_VPD_BUFFER_SIZE); + if ( vpd_data == 0 ) + return; + + for (index = 0; index < XGE_HAL_VPD_BUFFER_SIZE; index +=4 ) { + xge_os_pci_write8(hldev->pdev, hldev->cfgh, (vpd_addr + 2), (u8)index); + xge_os_pci_read8(hldev->pdev, hldev->cfgh,(vpd_addr + 2), &data); + xge_os_pci_write8(hldev->pdev, hldev->cfgh, (vpd_addr + 3), 0); + for (count = 0; count < 5; count++ ) { + xge_os_mdelay(2); + xge_os_pci_read8(hldev->pdev, hldev->cfgh,(vpd_addr + 3), &data); + if (data == XGE_HAL_VPD_READ_COMPLETE) + break; + } + + if (count >= 5) { + xge_os_printf("ERR, Reading VPD data failed"); + fail = 1; + break; + } + + xge_os_pci_read32(hldev->pdev, hldev->cfgh,(vpd_addr + 4), + (u32 *)&vpd_data[index]); + } + + if(!fail) { + + /* read serial number of adapter */ + for (count = 0; count < XGE_HAL_VPD_BUFFER_SIZE; count++) { + if ((vpd_data[count] == 'S') && + (vpd_data[count + 1] == 'N') && + (vpd_data[count + 2] < XGE_HAL_VPD_LENGTH)) { + memset(hldev->vpd_data.serial_num, 0, XGE_HAL_VPD_LENGTH); + memcpy(hldev->vpd_data.serial_num, &vpd_data[count + 3], + vpd_data[count + 2]); + break; + } + } + + if (vpd_data[1] < XGE_HAL_VPD_LENGTH) { + memset(hldev->vpd_data.product_name, 0, vpd_data[1]); + memcpy(hldev->vpd_data.product_name, &vpd_data[3], vpd_data[1]); + } + + } + + xge_os_free(hldev->pdev, vpd_data, XGE_HAL_VPD_BUFFER_SIZE); +} + + +/** + * xge_hal_device_handle_tcode - Handle transfer code. + * @channelh: Channel handle. + * @dtrh: Descriptor handle. + * @t_code: One of the enumerated (and documented in the Xframe user guide) + * "transfer codes". + * + * Handle descriptor's transfer code. The latter comes with each completed + * descriptor, see xge_hal_fifo_dtr_next_completed() and + * xge_hal_ring_dtr_next_completed(). + * Transfer codes are enumerated in xgehal-fifo.h and xgehal-ring.h. + * + * Returns: one of the xge_hal_status_e{} enumerated types. + * XGE_HAL_OK - for success. + * XGE_HAL_ERR_CRITICAL - when encounters critical error. + */ +xge_hal_status_e +xge_hal_device_handle_tcode (xge_hal_channel_h channelh, + xge_hal_dtr_h dtrh, u8 t_code) +{ + xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; + xge_hal_device_t *hldev = (xge_hal_device_t *)channel->devh; + + if (t_code > 15) { + xge_os_printf("invalid t_code %d", t_code); + return XGE_HAL_OK; + } + + if (channel->type == XGE_HAL_CHANNEL_TYPE_FIFO) { + hldev->stats.sw_dev_err_stats.txd_t_code_err_cnt[t_code]++; + +#if defined(XGE_HAL_DEBUG_BAD_TCODE) + xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)dtrh; + xge_os_printf(""XGE_OS_LLXFMT":"XGE_OS_LLXFMT":" + XGE_OS_LLXFMT":"XGE_OS_LLXFMT, + txdp->control_1, txdp->control_2, txdp->buffer_pointer, + txdp->host_control); +#endif + + /* handle link "down" immediately without going through + * xge_hal_device_poll() routine. */ + if (t_code == XGE_HAL_TXD_T_CODE_LOSS_OF_LINK) { + /* link is down */ + if (hldev->link_state != XGE_HAL_LINK_DOWN) { + xge_hal_pci_bar0_t *bar0 = + (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + + hldev->link_state = XGE_HAL_LINK_DOWN; + + val64 = xge_os_pio_mem_read64(hldev->pdev, + hldev->regh0, &bar0->adapter_control); + + /* turn off LED */ + val64 = val64 & (~XGE_HAL_ADAPTER_LED_ON); + xge_os_pio_mem_write64(hldev->pdev, + hldev->regh0, val64, + &bar0->adapter_control); + + g_xge_hal_driver->uld_callbacks.link_down( + hldev->upper_layer_info); + } + } else if (t_code == XGE_HAL_TXD_T_CODE_ABORT_BUFFER || + t_code == XGE_HAL_TXD_T_CODE_ABORT_DTOR) { + __hal_device_handle_targetabort(hldev); + return XGE_HAL_ERR_CRITICAL; + } + return XGE_HAL_ERR_PKT_DROP; + } else if (channel->type == XGE_HAL_CHANNEL_TYPE_RING) { + hldev->stats.sw_dev_err_stats.rxd_t_code_err_cnt[t_code]++; + +#if defined(XGE_HAL_DEBUG_BAD_TCODE) + xge_hal_ring_rxd_1_t *rxdp = (xge_hal_ring_rxd_1_t *)dtrh; + xge_os_printf(""XGE_OS_LLXFMT":"XGE_OS_LLXFMT":"XGE_OS_LLXFMT + ":"XGE_OS_LLXFMT, rxdp->control_1, + rxdp->control_2, rxdp->buffer0_ptr, + rxdp->host_control); +#endif + if (t_code == XGE_HAL_RXD_T_CODE_BAD_ECC) { + hldev->stats.sw_dev_err_stats.ecc_err_cnt++; + __hal_device_handle_eccerr(hldev, "rxd_t_code", + (u64)t_code); + return XGE_HAL_ERR_CRITICAL; + } else if (t_code == XGE_HAL_RXD_T_CODE_PARITY || + t_code == XGE_HAL_RXD_T_CODE_PARITY_ABORT) { + hldev->stats.sw_dev_err_stats.parity_err_cnt++; + __hal_device_handle_parityerr(hldev, "rxd_t_code", + (u64)t_code); + return XGE_HAL_ERR_CRITICAL; + /* do not drop if detected unknown IPv6 extension */ + } else if (t_code != XGE_HAL_RXD_T_CODE_UNKNOWN_PROTO) { + return XGE_HAL_ERR_PKT_DROP; + } + } + return XGE_HAL_OK; +} + +/** + * xge_hal_device_link_state - Get link state. + * @devh: HAL device handle. + * @ls: Link state, see xge_hal_device_link_state_e{}. + * + * Get link state. + * Returns: XGE_HAL_OK. + * See also: xge_hal_device_link_state_e{}. + */ +xge_hal_status_e xge_hal_device_link_state(xge_hal_device_h devh, + xge_hal_device_link_state_e *ls) +{ + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + + xge_assert(ls != NULL); + *ls = hldev->link_state; + return XGE_HAL_OK; +} + +/** + * xge_hal_device_sched_timer - Configure scheduled device interrupt. + * @devh: HAL device handle. + * @interval_us: Time interval, in miscoseconds. + * Unlike transmit and receive interrupts, + * the scheduled interrupt is generated independently of + * traffic, but purely based on time. + * @one_shot: 1 - generate scheduled interrupt only once. + * 0 - generate scheduled interrupt periodically at the specified + * @interval_us interval. + * + * (Re-)configure scheduled interrupt. Can be called at runtime to change + * the setting, generate one-shot interrupts based on the resource and/or + * traffic conditions, other purposes. + * See also: xge_hal_device_config_t{}. + */ +void xge_hal_device_sched_timer(xge_hal_device_h devh, int interval_us, + int one_shot) +{ + u64 val64; + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + xge_hal_pci_bar0_t *bar0 = + (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + unsigned int interval = hldev->config.pci_freq_mherz * interval_us; + + interval = __hal_fix_time_ival_herc(hldev, interval); + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->scheduled_int_ctrl); + if (interval) { + val64 &= XGE_HAL_SCHED_INT_PERIOD_MASK; + val64 |= XGE_HAL_SCHED_INT_PERIOD(interval); + if (one_shot) { + val64 |= XGE_HAL_SCHED_INT_CTRL_ONE_SHOT; + } + val64 |= XGE_HAL_SCHED_INT_CTRL_TIMER_EN; + } else { + val64 &= ~XGE_HAL_SCHED_INT_CTRL_TIMER_EN; + } + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &bar0->scheduled_int_ctrl); + + xge_debug_device(XGE_TRACE, "sched_timer 0x"XGE_OS_LLXFMT": %s", + (unsigned long long)val64, + interval ? "enabled" : "disabled"); +} + +/** + * xge_hal_device_check_id - Verify device ID. + * @devh: HAL device handle. + * + * Verify device ID. + * Returns: one of the xge_hal_card_e{} enumerated types. + * See also: xge_hal_card_e{}. + */ +xge_hal_card_e +xge_hal_device_check_id(xge_hal_device_h devh) +{ + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + switch (hldev->device_id) { + case XGE_PCI_DEVICE_ID_XENA_1: + case XGE_PCI_DEVICE_ID_XENA_2: + return XGE_HAL_CARD_XENA; + case XGE_PCI_DEVICE_ID_HERC_1: + case XGE_PCI_DEVICE_ID_HERC_2: + return XGE_HAL_CARD_HERC; + case XGE_PCI_DEVICE_ID_TITAN_1: + case XGE_PCI_DEVICE_ID_TITAN_2: + return XGE_HAL_CARD_TITAN; + default: + return XGE_HAL_CARD_UNKNOWN; + } +} + +/** + * xge_hal_device_pci_info_get - Get PCI bus informations such as width, + * frequency, and mode from previously stored values. + * @devh: HAL device handle. + * @pci_mode: pointer to a variable of enumerated type + * xge_hal_pci_mode_e{}. + * @bus_frequency: pointer to a variable of enumerated type + * xge_hal_pci_bus_frequency_e{}. + * @bus_width: pointer to a variable of enumerated type + * xge_hal_pci_bus_width_e{}. + * + * Get pci mode, frequency, and PCI bus width. + * Returns: one of the xge_hal_status_e{} enumerated types. + * XGE_HAL_OK - for success. + * XGE_HAL_ERR_INVALID_DEVICE - for invalid device handle. + * See Also: xge_hal_pci_mode_e, xge_hal_pci_mode_e, xge_hal_pci_width_e. + */ +xge_hal_status_e +xge_hal_device_pci_info_get(xge_hal_device_h devh, xge_hal_pci_mode_e *pci_mode, + xge_hal_pci_bus_frequency_e *bus_frequency, + xge_hal_pci_bus_width_e *bus_width) +{ + xge_hal_status_e rc_status; + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + + if (!hldev || !hldev->is_initialized || hldev->magic != XGE_HAL_MAGIC) { + rc_status = XGE_HAL_ERR_INVALID_DEVICE; + xge_debug_device(XGE_ERR, + "xge_hal_device_pci_info_get error, rc %d for device %p", + rc_status, hldev); + + return rc_status; + } + + *pci_mode = hldev->pci_mode; + *bus_frequency = hldev->bus_frequency; + *bus_width = hldev->bus_width; + rc_status = XGE_HAL_OK; + return rc_status; +} + +/** + * xge_hal_reinitialize_hw + * @hldev: private member of the device structure. + * + * This function will soft reset the NIC and re-initalize all the + * I/O registers to the values they had after it's inital initialization + * through the probe function. + */ +int xge_hal_reinitialize_hw(xge_hal_device_t * hldev) +{ + (void) xge_hal_device_reset(hldev); + if (__hal_device_hw_initialize(hldev) != XGE_HAL_OK) { + xge_hal_device_terminate(hldev); + (void) __hal_device_reset(hldev); + return 1; + } + return 0; +} + + +/* + * __hal_read_spdm_entry_line + * @hldev: pointer to xge_hal_device_t structure + * @spdm_line: spdm line in the spdm entry to be read. + * @spdm_entry: spdm entry of the spdm_line in the SPDM table. + * @spdm_line_val: Contains the value stored in the spdm line. + * + * SPDM table contains upto a maximum of 256 spdm entries. + * Each spdm entry contains 8 lines and each line stores 8 bytes. + * This function reads the spdm line(addressed by @spdm_line) + * of the spdm entry(addressed by @spdm_entry) in + * the SPDM table. + */ +xge_hal_status_e +__hal_read_spdm_entry_line(xge_hal_device_t *hldev, u8 spdm_line, + u16 spdm_entry, u64 *spdm_line_val) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + + val64 = XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_STROBE | + XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_LINE_SEL(spdm_line) | + XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_OFFSET(spdm_entry); + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rts_rth_spdm_mem_ctrl); + + /* poll until done */ + if (__hal_device_register_poll(hldev, + &bar0->rts_rth_spdm_mem_ctrl, 0, + XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_STROBE, + XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS) != XGE_HAL_OK) { + + return XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING; + } + + *spdm_line_val = xge_os_pio_mem_read64(hldev->pdev, + hldev->regh0, &bar0->rts_rth_spdm_mem_data); + return XGE_HAL_OK; +} + + +/* + * __hal_get_free_spdm_entry + * @hldev: pointer to xge_hal_device_t structure + * @spdm_entry: Contains an index to the unused spdm entry in the SPDM table. + * + * This function returns an index of unused spdm entry in the SPDM + * table. + */ +static xge_hal_status_e +__hal_get_free_spdm_entry(xge_hal_device_t *hldev, u16 *spdm_entry) +{ + xge_hal_status_e status; + u64 spdm_line_val=0; + + /* + * Search in the local SPDM table for a free slot. + */ + *spdm_entry = 0; + for(; *spdm_entry < hldev->spdm_max_entries; (*spdm_entry)++) { + if (hldev->spdm_table[*spdm_entry]->in_use) { + break; + } + } + + if (*spdm_entry >= hldev->spdm_max_entries) { + return XGE_HAL_ERR_SPDM_TABLE_FULL; + } + + /* + * Make sure that the corresponding spdm entry in the SPDM + * table is free. + * Seventh line of the spdm entry contains information about + * whether the entry is free or not. + */ + if ((status = __hal_read_spdm_entry_line(hldev, 7, *spdm_entry, + &spdm_line_val)) != XGE_HAL_OK) { + return status; + } + + /* BIT(63) in spdm_line 7 corresponds to entry_enable bit */ + if ((spdm_line_val & BIT(63))) { + /* + * Log a warning + */ + xge_debug_device(XGE_ERR, "Local SPDM table is not " + "consistent with the actual one for the spdm " + "entry %d", *spdm_entry); + return XGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT; + } + + return XGE_HAL_OK; +} + + +/* + * __hal_calc_jhash - Calculate Jenkins hash. + * @msg: Jenkins hash algorithm key. + * @length: Length of the key. + * @golden_ratio: Jenkins hash golden ratio. + * @init_value: Jenkins hash initial value. + * + * This function implements the Jenkins based algorithm used for the + * calculation of the RTH hash. + * Returns: Jenkins hash value. + * + */ +static u32 +__hal_calc_jhash(u8 *msg, u32 length, u32 golden_ratio, u32 init_value) +{ + + register u32 a,b,c,len; + + /* + * Set up the internal state + */ + len = length; + a = b = golden_ratio; /* the golden ratio; an arbitrary value */ + c = init_value; /* the previous hash value */ + + /* handle most of the key */ + while (len >= 12) + { + a += (msg[0] + ((u32)msg[1]<<8) + ((u32)msg[2]<<16) + + ((u32)msg[3]<<24)); + b += (msg[4] + ((u32)msg[5]<<8) + ((u32)msg[6]<<16) + + ((u32)msg[7]<<24)); + c += (msg[8] + ((u32)msg[9]<<8) + ((u32)msg[10]<<16) + + ((u32)msg[11]<<24)); + mix(a,b,c); + msg += 12; len -= 12; + } + + /* handle the last 11 bytes */ + c += length; + switch(len) /* all the case statements fall through */ + { + case 11: c+= ((u32)msg[10]<<24); + break; + case 10: c+= ((u32)msg[9]<<16); + break; + case 9 : c+= ((u32)msg[8]<<8); + break; + /* the first byte of c is reserved for the length */ + case 8 : b+= ((u32)msg[7]<<24); + break; + case 7 : b+= ((u32)msg[6]<<16); + break; + case 6 : b+= ((u32)msg[5]<<8); + break; + case 5 : b+= msg[4]; + break; + case 4 : a+= ((u32)msg[3]<<24); + break; + case 3 : a+= ((u32)msg[2]<<16); + break; + case 2 : a+= ((u32)msg[1]<<8); + break; + case 1 : a+= msg[0]; + break; + /* case 0: nothing left to add */ + } + + mix(a,b,c); + + /* report the result */ + return c; +} + + +/** + * xge_hal_spdm_entry_add - Add a new entry to the SPDM table. + * @devh: HAL device handle. + * @src_ip: Source ip address(IPv4/IPv6). + * @dst_ip: Destination ip address(IPv4/IPv6). + * @l4_sp: L4 source port. + * @l4_dp: L4 destination port. + * @is_tcp: Set to 1, if the protocol is TCP. + * 0, if the protocol is UDP. + * @is_ipv4: Set to 1, if the protocol is IPv4. + * 0, if the protocol is IPv6. + * @tgt_queue: Target queue to route the receive packet. + * + * This function add a new entry to the SPDM table. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_SPDM_NOT_ENABLED - SPDM support is not enabled. + * XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING - Failed to add a new entry with in + * the time(timeout). + * XGE_HAL_ERR_SPDM_TABLE_FULL - SPDM table is full. + * XGE_HAL_ERR_SPDM_INVALID_ENTRY - Invalid SPDM entry. + * + * See also: xge_hal_spdm_entry_remove{}. + */ +xge_hal_status_e +xge_hal_spdm_entry_add(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip, + xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp, + u8 is_tcp, u8 is_ipv4, u8 tgt_queue) +{ + + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u32 jhash_value; + u32 jhash_init_val; + u32 jhash_golden_ratio; + u64 val64; + int off; + u16 spdm_entry; + u8 msg[XGE_HAL_JHASH_MSG_LEN]; + int ipaddr_len; + xge_hal_status_e status; + + + if (!hldev->config.rth_spdm_en) { + return XGE_HAL_ERR_SPDM_NOT_ENABLED; + } + + if ((tgt_queue < XGE_HAL_MIN_RING_NUM) || + (tgt_queue > XGE_HAL_MAX_RING_NUM)) { + return XGE_HAL_ERR_SPDM_INVALID_ENTRY; + } + + + /* + * Calculate the jenkins hash. + */ + /* + * Create the Jenkins hash algorithm key. + * key = {L3SA, L3DA, L4SP, L4DP}, if SPDM is configured to + * use L4 information. Otherwize key = {L3SA, L3DA}. + */ + + if (is_ipv4) { + ipaddr_len = 4; // In bytes + } else { + ipaddr_len = 16; + } + + /* + * Jenkins hash algorithm expects the key in the big endian + * format. Since key is the byte array, memcpy won't work in the + * case of little endian. So, the current code extracts each + * byte starting from MSB and store it in the key. + */ + if (is_ipv4) { + for (off = 0; off < ipaddr_len; off++) { + u32 mask = vBIT32(0xff,(off*8),8); + int shift = 32-(off+1)*8; + msg[off] = (u8)((src_ip->ipv4.addr & mask) >> shift); + msg[off+ipaddr_len] = + (u8)((dst_ip->ipv4.addr & mask) >> shift); + } + } else { + for (off = 0; off < ipaddr_len; off++) { + int loc = off % 8; + u64 mask = vBIT(0xff,(loc*8),8); + int shift = 64-(loc+1)*8; + + msg[off] = (u8)((src_ip->ipv6.addr[off/8] & mask) + >> shift); + msg[off+ipaddr_len] = (u8)((dst_ip->ipv6.addr[off/8] + & mask) >> shift); + } + } + + off = (2*ipaddr_len); + + if (hldev->config.rth_spdm_use_l4) { + msg[off] = (u8)((l4_sp & 0xff00) >> 8); + msg[off + 1] = (u8)(l4_sp & 0xff); + msg[off + 2] = (u8)((l4_dp & 0xff00) >> 8); + msg[off + 3] = (u8)(l4_dp & 0xff); + off += 4; + } + + /* + * Calculate jenkins hash for this configuration + */ + val64 = xge_os_pio_mem_read64(hldev->pdev, + hldev->regh0, + &bar0->rts_rth_jhash_cfg); + jhash_golden_ratio = (u32)(val64 >> 32); + jhash_init_val = (u32)(val64 & 0xffffffff); + + jhash_value = __hal_calc_jhash(msg, off, + jhash_golden_ratio, + jhash_init_val); + + xge_os_spin_lock(&hldev->spdm_lock); + + /* + * Locate a free slot in the SPDM table. To avoid a seach in the + * actual SPDM table, which is very expensive in terms of time, + * we are maintaining a local copy of the table and the search for + * the free entry is performed in the local table. + */ + if ((status = __hal_get_free_spdm_entry(hldev,&spdm_entry)) + != XGE_HAL_OK) { + xge_os_spin_unlock(&hldev->spdm_lock); + return status; + } + + /* + * Add this entry to the SPDM table + */ + status = __hal_spdm_entry_add(hldev, src_ip, dst_ip, l4_sp, l4_dp, + is_tcp, is_ipv4, tgt_queue, + jhash_value, /* calculated jhash */ + spdm_entry); + + xge_os_spin_unlock(&hldev->spdm_lock); + + return status; +} + +/** + * xge_hal_spdm_entry_remove - Remove an entry from the SPDM table. + * @devh: HAL device handle. + * @src_ip: Source ip address(IPv4/IPv6). + * @dst_ip: Destination ip address(IPv4/IPv6). + * @l4_sp: L4 source port. + * @l4_dp: L4 destination port. + * @is_tcp: Set to 1, if the protocol is TCP. + * 0, if the protocol os UDP. + * @is_ipv4: Set to 1, if the protocol is IPv4. + * 0, if the protocol is IPv6. + * + * This function remove an entry from the SPDM table. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_SPDM_NOT_ENABLED - SPDM support is not enabled. + * XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING - Failed to remove an entry with in + * the time(timeout). + * XGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND - Unable to locate the entry in the SPDM + * table. + * + * See also: xge_hal_spdm_entry_add{}. + */ +xge_hal_status_e +xge_hal_spdm_entry_remove(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip, + xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp, + u8 is_tcp, u8 is_ipv4) +{ + + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + u16 spdm_entry; + xge_hal_status_e status; + u64 spdm_line_arr[8]; + u8 line_no; + u8 spdm_is_tcp; + u8 spdm_is_ipv4; + u16 spdm_l4_sp; + u16 spdm_l4_dp; + + if (!hldev->config.rth_spdm_en) { + return XGE_HAL_ERR_SPDM_NOT_ENABLED; + } + + xge_os_spin_lock(&hldev->spdm_lock); + + /* + * Poll the rxpic_int_reg register until spdm ready bit is set or + * timeout happens. + */ + if (__hal_device_register_poll(hldev, &bar0->rxpic_int_reg, 1, + XGE_HAL_RX_PIC_INT_REG_SPDM_READY, + XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS) != XGE_HAL_OK) { + + /* upper layer may require to repeat */ + xge_os_spin_unlock(&hldev->spdm_lock); + return XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING; + } + + /* + * Clear the SPDM READY bit. + */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->rxpic_int_reg); + val64 &= ~XGE_HAL_RX_PIC_INT_REG_SPDM_READY; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rxpic_int_reg); + + /* + * Search in the local SPDM table to get the index of the + * corresponding entry in the SPDM table. + */ + spdm_entry = 0; + for (;spdm_entry < hldev->spdm_max_entries; spdm_entry++) { + if ((!hldev->spdm_table[spdm_entry]->in_use) || + (hldev->spdm_table[spdm_entry]->is_tcp != is_tcp) || + (hldev->spdm_table[spdm_entry]->l4_sp != l4_sp) || + (hldev->spdm_table[spdm_entry]->l4_dp != l4_dp) || + (hldev->spdm_table[spdm_entry]->is_ipv4 != is_ipv4)) { + continue; + } + + /* + * Compare the src/dst IP addresses of source and target + */ + if (is_ipv4) { + if ((hldev->spdm_table[spdm_entry]->src_ip.ipv4.addr + != src_ip->ipv4.addr) || + (hldev->spdm_table[spdm_entry]->dst_ip.ipv4.addr + != dst_ip->ipv4.addr)) { + continue; + } + } else { + if ((hldev->spdm_table[spdm_entry]->src_ip.ipv6.addr[0] + != src_ip->ipv6.addr[0]) || + (hldev->spdm_table[spdm_entry]->src_ip.ipv6.addr[1] + != src_ip->ipv6.addr[1]) || + (hldev->spdm_table[spdm_entry]->dst_ip.ipv6.addr[0] + != dst_ip->ipv6.addr[0]) || + (hldev->spdm_table[spdm_entry]->dst_ip.ipv6.addr[1] + != dst_ip->ipv6.addr[1])) { + continue; + } + } + break; + } + + if (spdm_entry >= hldev->spdm_max_entries) { + xge_os_spin_unlock(&hldev->spdm_lock); + return XGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND; + } + + /* + * Retrieve the corresponding entry from the SPDM table and + * make sure that the data is consistent. + */ + for(line_no = 0; line_no < 8; line_no++) { + + /* + * SPDM line 2,3,4 are valid only for IPv6 entry. + * SPDM line 5 & 6 are reserved. We don't have to + * read these entries in the above cases. + */ + if (((is_ipv4) && + ((line_no == 2)||(line_no == 3)||(line_no == 4))) || + (line_no == 5) || + (line_no == 6)) { + continue; + } + + if ((status = __hal_read_spdm_entry_line( + hldev, + line_no, + spdm_entry, + &spdm_line_arr[line_no])) + != XGE_HAL_OK) { + xge_os_spin_unlock(&hldev->spdm_lock); + return status; + } + } + + /* + * Seventh line of the spdm entry contains the entry_enable + * bit. Make sure that the entry_enable bit of this spdm entry + * is set. + * To remove an entry from the SPDM table, reset this + * bit. + */ + if (!(spdm_line_arr[7] & BIT(63))) { + /* + * Log a warning + */ + xge_debug_device(XGE_ERR, "Local SPDM table is not " + "consistent with the actual one for the spdm " + "entry %d ", spdm_entry); + goto err_exit; + } + + /* + * Retreive the L4 SP/DP, src/dst ip addresses from the SPDM + * table and do a comparision. + */ + spdm_is_tcp = (u8)((spdm_line_arr[0] & BIT(59)) >> 4); + spdm_is_ipv4 = (u8)(spdm_line_arr[0] & BIT(63)); + spdm_l4_sp = (u16)(spdm_line_arr[0] >> 48); + spdm_l4_dp = (u16)((spdm_line_arr[0] >> 32) & 0xffff); + + + if ((spdm_is_tcp != is_tcp) || + (spdm_is_ipv4 != is_ipv4) || + (spdm_l4_sp != l4_sp) || + (spdm_l4_dp != l4_dp)) { + /* + * Log a warning + */ + xge_debug_device(XGE_ERR, "Local SPDM table is not " + "consistent with the actual one for the spdm " + "entry %d ", spdm_entry); + goto err_exit; + } + + if (is_ipv4) { + /* Upper 32 bits of spdm_line(64 bit) contains the + * src IPv4 address. Lower 32 bits of spdm_line + * contains the destination IPv4 address. + */ + u32 temp_src_ip = (u32)(spdm_line_arr[1] >> 32); + u32 temp_dst_ip = (u32)(spdm_line_arr[1] & 0xffffffff); + + if ((temp_src_ip != src_ip->ipv4.addr) || + (temp_dst_ip != dst_ip->ipv4.addr)) { + xge_debug_device(XGE_ERR, "Local SPDM table is not " + "consistent with the actual one for the spdm " + "entry %d ", spdm_entry); + goto err_exit; + } + + } else { + /* + * SPDM line 1 & 2 contains the src IPv6 address. + * SPDM line 3 & 4 contains the dst IPv6 address. + */ + if ((spdm_line_arr[1] != src_ip->ipv6.addr[0]) || + (spdm_line_arr[2] != src_ip->ipv6.addr[1]) || + (spdm_line_arr[3] != dst_ip->ipv6.addr[0]) || + (spdm_line_arr[4] != dst_ip->ipv6.addr[1])) { + + /* + * Log a warning + */ + xge_debug_device(XGE_ERR, "Local SPDM table is not " + "consistent with the actual one for the spdm " + "entry %d ", spdm_entry); + goto err_exit; + } + } + + /* + * Reset the entry_enable bit to zero + */ + spdm_line_arr[7] &= ~BIT(63); + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + spdm_line_arr[7], + (void *)((char *)hldev->spdm_mem_base + + (spdm_entry * 64) + (7 * 8))); + + /* + * Wait for the operation to be completed. + */ + if (__hal_device_register_poll(hldev, + &bar0->rxpic_int_reg, 1, + XGE_HAL_RX_PIC_INT_REG_SPDM_READY, + XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS) != XGE_HAL_OK) { + xge_os_spin_unlock(&hldev->spdm_lock); + return XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING; + } + + /* + * Make the corresponding spdm entry in the local SPDM table + * available for future use. + */ + hldev->spdm_table[spdm_entry]->in_use = 0; + xge_os_spin_unlock(&hldev->spdm_lock); + + return XGE_HAL_OK; + +err_exit: + xge_os_spin_unlock(&hldev->spdm_lock); + return XGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT; +} + +/* + * __hal_device_rti_set + * @ring: The post_qid of the ring. + * @channel: HAL channel of the ring. + * + * This function stores the RTI value associated for the MSI and + * also unmasks this particular RTI in the rti_mask register. + */ +static void __hal_device_rti_set(int ring_qid, xge_hal_channel_t *channel) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)channel->devh; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)hldev->bar0; + u64 val64; + + if (hldev->config.intr_mode == XGE_HAL_INTR_MODE_MSI || + hldev->config.intr_mode == XGE_HAL_INTR_MODE_MSIX) + channel->rti = (u8)ring_qid; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->rx_traffic_mask); + val64 &= ~BIT(ring_qid); + xge_os_pio_mem_write64(hldev->pdev, + hldev->regh0, val64, + &bar0->rx_traffic_mask); +} + +/* + * __hal_device_tti_set + * @ring: The post_qid of the FIFO. + * @channel: HAL channel the FIFO. + * + * This function stores the TTI value associated for the MSI and + * also unmasks this particular TTI in the tti_mask register. + */ +static void __hal_device_tti_set(int fifo_qid, xge_hal_channel_t *channel) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)channel->devh; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)hldev->bar0; + u64 val64; + + if (hldev->config.intr_mode == XGE_HAL_INTR_MODE_MSI || + hldev->config.intr_mode == XGE_HAL_INTR_MODE_MSIX) + channel->tti = (u8)fifo_qid; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->tx_traffic_mask); + val64 &= ~BIT(fifo_qid); + xge_os_pio_mem_write64(hldev->pdev, + hldev->regh0, val64, + &bar0->tx_traffic_mask); +} + +/** + * xge_hal_channel_msi_set - Associate a RTI with a ring or TTI with a + * FIFO for a given MSI. + * @channelh: HAL channel handle. + * @msi: MSI Number associated with the channel. + * @msi_msg: The MSI message associated with the MSI number above. + * + * This API will associate a given channel (either Ring or FIFO) with the + * given MSI number. It will alo program the Tx_Mat/Rx_Mat tables in the + * hardware to indicate this association to the hardware. + */ +xge_hal_status_e +xge_hal_channel_msi_set(xge_hal_channel_h channelh, int msi, u32 msi_msg) +{ + xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; + xge_hal_device_t *hldev = (xge_hal_device_t*)channel->devh; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)hldev->bar0; + u64 val64; + + channel->msi_msg = msi_msg; + if (channel->type == XGE_HAL_CHANNEL_TYPE_RING) { + int ring = channel->post_qid; + xge_debug_osdep(XGE_TRACE, "MSI Data: 0x%4x, Ring: %d," + " MSI: %d", channel->msi_msg, ring, msi); + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->rx_mat); + val64 |= XGE_HAL_SET_RX_MAT(ring, msi); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rx_mat); + __hal_device_rti_set(ring, channel); + } else { + int fifo = channel->post_qid; + xge_debug_osdep(XGE_TRACE, "MSI Data: 0x%4x, Fifo: %d," + " MSI: %d", channel->msi_msg, fifo, msi); + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->tx_mat[0]); + val64 |= XGE_HAL_SET_TX_MAT(fifo, msi); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->tx_mat[0]); + __hal_device_tti_set(fifo, channel); + } + + return XGE_HAL_OK; +} + +/** + * xge_hal_mask_msix - Begin IRQ processing. + * @hldev: HAL device handle. + * @msi_id: MSI ID + * + * The function masks the msix interrupt for the given msi_id + * + * Note: + * + * Returns: 0, + * Otherwise, XGE_HAL_ERR_WRONG_IRQ if the msix index is out of range + * status. + * See also: + */ +xge_hal_status_e +xge_hal_mask_msix(xge_hal_device_h devh, int msi_id) +{ + xge_hal_status_e status = XGE_HAL_OK; + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + u32 *bar2 = (u32 *)hldev->bar2; + u32 val32; + + xge_assert(msi_id < XGE_HAL_MAX_MSIX_MESSAGES); + + val32 = xge_os_pio_mem_read32(hldev->pdev, hldev->regh2, &bar2[msi_id*4+3]); + val32 |= 1; + xge_os_pio_mem_write32(hldev->pdev, hldev->regh2, val32, &bar2[msi_id*4+3]); + return status; +} + +/** + * xge_hal_mask_msix - Begin IRQ processing. + * @hldev: HAL device handle. + * @msi_id: MSI ID + * + * The function masks the msix interrupt for the given msi_id + * + * Note: + * + * Returns: 0, + * Otherwise, XGE_HAL_ERR_WRONG_IRQ if the msix index is out of range + * status. + * See also: + */ +xge_hal_status_e +xge_hal_unmask_msix(xge_hal_device_h devh, int msi_id) +{ + xge_hal_status_e status = XGE_HAL_OK; + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + u32 *bar2 = (u32 *)hldev->bar2; + u32 val32; + + xge_assert(msi_id < XGE_HAL_MAX_MSIX_MESSAGES); + + val32 = xge_os_pio_mem_read32(hldev->pdev, hldev->regh2, &bar2[msi_id*4+3]); + val32 &= ~1; + xge_os_pio_mem_write32(hldev->pdev, hldev->regh2, val32, &bar2[msi_id*4+3]); + return status; +} + +/* + * __hal_set_msix_vals + * @devh: HAL device handle. + * @msix_value: 32bit MSI-X value transferred across PCI to @msix_address. + * Filled in by this function. + * @msix_address: 32bit MSI-X DMA address. + * Filled in by this function. + * @msix_idx: index that corresponds to the (@msix_value, @msix_address) + * entry in the table of MSI-X (value, address) pairs. + * + * This function will program the hardware associating the given + * address/value cobination to the specified msi number. + */ +static void __hal_set_msix_vals (xge_hal_device_h devh, + u32 *msix_value, + u64 *msix_addr, + int msix_idx) +{ + int cnt = 0; + + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)hldev->bar0; + u64 val64; + + val64 = XGE_HAL_XMSI_NO(msix_idx) | XGE_HAL_XMSI_STROBE; + __hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0, + (u32)(val64 >> 32), &bar0->xmsi_access); + __hal_pio_mem_write32_lower(hldev->pdev, hldev->regh0, + (u32)(val64), &bar0->xmsi_access); + do { + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->xmsi_access); + if (val64 & XGE_HAL_XMSI_STROBE) + break; + cnt++; + xge_os_mdelay(20); + } while(cnt < 5); + *msix_value = (u32)(xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->xmsi_data)); + *msix_addr = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->xmsi_address); +} + +/** + * xge_hal_channel_msix_set - Associate MSI-X with a channel. + * @channelh: HAL channel handle. + * @msix_idx: index that corresponds to a particular (@msix_value, + * @msix_address) entry in the MSI-X table. + * + * This API associates a given channel (either Ring or FIFO) with the + * given MSI-X number. It programs the Xframe's Tx_Mat/Rx_Mat tables + * to indicate this association. + */ +xge_hal_status_e +xge_hal_channel_msix_set(xge_hal_channel_h channelh, int msix_idx) +{ + xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; + xge_hal_device_t *hldev = (xge_hal_device_t*)channel->devh; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)hldev->bar0; + u64 val64; + + if (channel->type == XGE_HAL_CHANNEL_TYPE_RING) { + /* Currently Ring and RTI is one on one. */ + int ring = channel->post_qid; + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->rx_mat); + val64 |= XGE_HAL_SET_RX_MAT(ring, msix_idx); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rx_mat); + __hal_device_rti_set(ring, channel); + hldev->config.fifo.queue[channel->post_qid].intr_vector = + msix_idx; + } else if (channel->type == XGE_HAL_CHANNEL_TYPE_FIFO) { + int fifo = channel->post_qid; + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->tx_mat[0]); + val64 |= XGE_HAL_SET_TX_MAT(fifo, msix_idx); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->tx_mat[0]); + __hal_device_tti_set(fifo, channel); + hldev->config.ring.queue[channel->post_qid].intr_vector = + msix_idx; + } + channel->msix_idx = msix_idx; + __hal_set_msix_vals(hldev, &channel->msix_data, + &channel->msix_address, + channel->msix_idx); + + return XGE_HAL_OK; +} + +#if defined(XGE_HAL_CONFIG_LRO) +/** + * xge_hal_lro_terminate - Terminate lro resources. + * @lro_scale: Amount of lro memory. + * @hldev: Hal device structure. + * + */ +void +xge_hal_lro_terminate(u32 lro_scale, + xge_hal_device_t *hldev) +{ +} + +/** + * xge_hal_lro_init - Initiate lro resources. + * @lro_scale: Amount of lro memory. + * @hldev: Hal device structure. + * Note: For time being I am using only one LRO per device. Later on size + * will be increased. + */ + +xge_hal_status_e +xge_hal_lro_init(u32 lro_scale, + xge_hal_device_t *hldev) +{ + int i; + + if (hldev->config.lro_sg_size == XGE_HAL_DEFAULT_USE_HARDCODE) + hldev->config.lro_sg_size = XGE_HAL_LRO_DEFAULT_SG_SIZE; + + if (hldev->config.lro_frm_len == XGE_HAL_DEFAULT_USE_HARDCODE) + hldev->config.lro_frm_len = XGE_HAL_LRO_DEFAULT_FRM_LEN; + + for (i=0; i < XGE_HAL_MAX_RING_NUM; i++) + { + xge_os_memzero(hldev->lro_desc[i].lro_pool, + sizeof(lro_t) * XGE_HAL_LRO_MAX_BUCKETS); + + hldev->lro_desc[i].lro_next_idx = 0; + hldev->lro_desc[i].lro_recent = NULL; + } + + return XGE_HAL_OK; +} +#endif + + +/** + * xge_hal_device_poll - HAL device "polling" entry point. + * @devh: HAL device. + * + * HAL "polling" entry point. Note that this is part of HAL public API. + * Upper-Layer driver _must_ periodically poll HAL via + * xge_hal_device_poll(). + * + * HAL uses caller's execution context to serially process accumulated + * slow-path events, such as link state changes and hardware error + * indications. + * + * The rate of polling could be somewhere between 500us to 10ms, + * depending on requirements (e.g., the requirement to support fail-over + * could mean that 500us or even 100us polling interval need to be used). + * + * The need and motivation for external polling includes + * + * - remove the error-checking "burden" from the HAL interrupt handler + * (see xge_hal_device_handle_irq()); + * + * - remove the potential source of portability issues by _not_ + * implementing separate polling thread within HAL itself. + * + * See also: xge_hal_event_e{}, xge_hal_driver_config_t{}. + * Usage: See ex_slow_path{}. + */ +void +xge_hal_device_poll(xge_hal_device_h devh) +{ + unsigned char item_buf[sizeof(xge_queue_item_t) + + XGE_DEFAULT_EVENT_MAX_DATA_SIZE]; + xge_queue_item_t *item = (xge_queue_item_t *)(void *)item_buf; + xge_queue_status_e qstatus; + xge_hal_status_e hstatus; + int i = 0; + int queue_has_critical_event = 0; + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + + xge_os_memzero(item_buf, (sizeof(xge_queue_item_t) + + XGE_DEFAULT_EVENT_MAX_DATA_SIZE)); + +_again: + if (!hldev->is_initialized || + hldev->terminating || + hldev->magic != XGE_HAL_MAGIC) + return; + + if(hldev->stats.sw_dev_err_stats.xpak_counter.tick_period < 72000) + { + /* + * Wait for an Hour + */ + hldev->stats.sw_dev_err_stats.xpak_counter.tick_period++; + } else { + /* + * Logging Error messages in the excess temperature, + * Bias current, laser ouput for three cycle + */ + __hal_updt_stats_xpak(hldev); + hldev->stats.sw_dev_err_stats.xpak_counter.tick_period = 0; + } + + if (!queue_has_critical_event) + queue_has_critical_event = + __queue_get_reset_critical(hldev->queueh); + + hldev->in_poll = 1; + while (i++ < XGE_HAL_DRIVER_QUEUE_CONSUME_MAX || queue_has_critical_event) { + + qstatus = xge_queue_consume(hldev->queueh, + XGE_DEFAULT_EVENT_MAX_DATA_SIZE, + item); + if (qstatus == XGE_QUEUE_IS_EMPTY) + break; + + xge_debug_queue(XGE_TRACE, + "queueh 0x"XGE_OS_LLXFMT" consumed event: %d ctxt 0x" + XGE_OS_LLXFMT, (u64)(ulong_t)hldev->queueh, item->event_type, + (u64)(ulong_t)item->context); + + if (!hldev->is_initialized || + hldev->magic != XGE_HAL_MAGIC) { + hldev->in_poll = 0; + return; + } + + switch (item->event_type) { + case XGE_HAL_EVENT_LINK_IS_UP: { + if (!queue_has_critical_event && + g_xge_hal_driver->uld_callbacks.link_up) { + g_xge_hal_driver->uld_callbacks.link_up( + hldev->upper_layer_info); + hldev->link_state = XGE_HAL_LINK_UP; + } + } break; + case XGE_HAL_EVENT_LINK_IS_DOWN: { + if (!queue_has_critical_event && + g_xge_hal_driver->uld_callbacks.link_down) { + g_xge_hal_driver->uld_callbacks.link_down( + hldev->upper_layer_info); + hldev->link_state = XGE_HAL_LINK_DOWN; + } + } break; + case XGE_HAL_EVENT_SERR: + case XGE_HAL_EVENT_ECCERR: + case XGE_HAL_EVENT_PARITYERR: + case XGE_HAL_EVENT_TARGETABORT: + case XGE_HAL_EVENT_SLOT_FREEZE: { + void *item_data = xge_queue_item_data(item); + xge_hal_event_e event_type = item->event_type; + u64 val64 = *((u64*)item_data); + + if (event_type != XGE_HAL_EVENT_SLOT_FREEZE) + if (xge_hal_device_is_slot_freeze(hldev)) + event_type = XGE_HAL_EVENT_SLOT_FREEZE; + if (g_xge_hal_driver->uld_callbacks.crit_err) { + g_xge_hal_driver->uld_callbacks.crit_err( + hldev->upper_layer_info, + event_type, + val64); + /* handle one critical event per poll cycle */ + hldev->in_poll = 0; + return; + } + } break; + default: { + xge_debug_queue(XGE_TRACE, + "got non-HAL event %d", + item->event_type); + } break; + } + + /* broadcast this event */ + if (g_xge_hal_driver->uld_callbacks.event) + g_xge_hal_driver->uld_callbacks.event(item); + } + + if (g_xge_hal_driver->uld_callbacks.before_device_poll) { + if (g_xge_hal_driver->uld_callbacks.before_device_poll( + hldev) != 0) { + hldev->in_poll = 0; + return; + } + } + + hstatus = __hal_device_poll(hldev); + if (g_xge_hal_driver->uld_callbacks.after_device_poll) + g_xge_hal_driver->uld_callbacks.after_device_poll(hldev); + + /* + * handle critical error right away: + * - walk the device queue again + * - drop non-critical events, if any + * - look for the 1st critical + */ + if (hstatus == XGE_HAL_ERR_CRITICAL) { + queue_has_critical_event = 1; + goto _again; + } + + hldev->in_poll = 0; +} + +/** + * xge_hal_rts_rth_init - Set enhanced mode for RTS hashing. + * @hldev: HAL device handle. + * + * This function is used to set the adapter to enhanced mode. + * + * See also: xge_hal_rts_rth_clr(), xge_hal_rts_rth_set(). + */ +void +xge_hal_rts_rth_init(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + + /* + * Set the receive traffic steering mode from default(classic) + * to enhanced. + */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->rts_ctrl); + val64 |= XGE_HAL_RTS_CTRL_ENHANCED_MODE; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &bar0->rts_ctrl); +} + +/** + * xge_hal_rts_rth_clr - Clear RTS hashing. + * @hldev: HAL device handle. + * + * This function is used to clear all RTS hashing related stuff. + * It brings the adapter out from enhanced mode to classic mode. + * It also clears RTS_RTH_CFG register i.e clears hash type, function etc. + * + * See also: xge_hal_rts_rth_set(), xge_hal_rts_rth_itable_set(). + */ +void +xge_hal_rts_rth_clr(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + + /* + * Set the receive traffic steering mode from default(classic) + * to enhanced. + */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->rts_ctrl); + val64 &= ~XGE_HAL_RTS_CTRL_ENHANCED_MODE; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &bar0->rts_ctrl); + val64 = 0; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rts_rth_cfg); +} + +/** + * xge_hal_rts_rth_set - Set/configure RTS hashing. + * @hldev: HAL device handle. + * @def_q: default queue + * @hash_type: hash type i.e TcpIpV4, TcpIpV6 etc. + * @bucket_size: no of least significant bits to be used for hashing. + * + * Used to set/configure all RTS hashing related stuff. + * - set the steering mode to enhanced. + * - set hash function i.e algo selection. + * - set the default queue. + * + * See also: xge_hal_rts_rth_clr(), xge_hal_rts_rth_itable_set(). + */ +void +xge_hal_rts_rth_set(xge_hal_device_t *hldev, u8 def_q, u64 hash_type, + u16 bucket_size) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + + val64 = XGE_HAL_RTS_DEFAULT_Q(def_q); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rts_default_q); + + val64 = hash_type; + val64 |= XGE_HAL_RTS_RTH_EN; + val64 |= XGE_HAL_RTS_RTH_BUCKET_SIZE(bucket_size); + val64 |= XGE_HAL_RTS_RTH_ALG_SEL_MS; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rts_rth_cfg); +} + +/** + * xge_hal_rts_rth_start - Start RTS hashing. + * @hldev: HAL device handle. + * + * Used to Start RTS hashing . + * + * See also: xge_hal_rts_rth_clr(), xge_hal_rts_rth_itable_set(), xge_hal_rts_rth_start. + */ +void +xge_hal_rts_rth_start(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->rts_rth_cfg); + val64 |= XGE_HAL_RTS_RTH_EN; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rts_rth_cfg); +} + +/** + * xge_hal_rts_rth_stop - Stop the RTS hashing. + * @hldev: HAL device handle. + * + * Used to Staop RTS hashing . + * + * See also: xge_hal_rts_rth_clr(), xge_hal_rts_rth_itable_set(), xge_hal_rts_rth_start. + */ +void +xge_hal_rts_rth_stop(xge_hal_device_t *hldev) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->rts_rth_cfg); + val64 &= ~XGE_HAL_RTS_RTH_EN; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rts_rth_cfg); +} + +/** + * xge_hal_rts_rth_itable_set - Set/configure indirection table (IT). + * @hldev: HAL device handle. + * @itable: Pointer to the indirection table + * @itable_size: no of least significant bits to be used for hashing + * + * Used to set/configure indirection table. + * It enables the required no of entries in the IT. + * It adds entries to the IT. + * + * See also: xge_hal_rts_rth_clr(), xge_hal_rts_rth_set(). + */ +xge_hal_status_e +xge_hal_rts_rth_itable_set(xge_hal_device_t *hldev, u8 *itable, u32 itable_size) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + u32 idx; + + for (idx = 0; idx < itable_size; idx++) { + val64 = XGE_HAL_RTS_RTH_MAP_MEM_DATA_ENTRY_EN | + XGE_HAL_RTS_RTH_MAP_MEM_DATA(itable[idx]); + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rts_rth_map_mem_data); + + /* execute */ + val64 = (XGE_HAL_RTS_RTH_MAP_MEM_CTRL_WE | + XGE_HAL_RTS_RTH_MAP_MEM_CTRL_STROBE | + XGE_HAL_RTS_RTH_MAP_MEM_CTRL_OFFSET(idx)); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rts_rth_map_mem_ctrl); + + /* poll until done */ + if (__hal_device_register_poll(hldev, + &bar0->rts_rth_map_mem_ctrl, 0, + XGE_HAL_RTS_RTH_MAP_MEM_CTRL_STROBE, + XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS) != XGE_HAL_OK) { + /* upper layer may require to repeat */ + return XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING; + } + } + + return XGE_HAL_OK; +} + + +/** + * xge_hal_device_rts_rth_key_set - Configure 40byte secret for hash calc. + * + * @hldev: HAL device handle. + * @KeySize: Number of 64-bit words + * @Key: upto 40-byte array of 8-bit values + * This function configures the 40-byte secret which is used for hash + * calculation. + * + * See also: xge_hal_rts_rth_clr(), xge_hal_rts_rth_set(). + */ +void +xge_hal_device_rts_rth_key_set(xge_hal_device_t *hldev, u8 KeySize, u8 *Key) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *) hldev->bar0; + u64 val64; + u32 entry, nreg, i; + + entry = 0; + nreg = 0; + + while( KeySize ) { + val64 = 0; + for ( i = 0; i < 8 ; i++) { + /* Prepare 64-bit word for 'nreg' containing 8 keys. */ + if (i) + val64 <<= 8; + val64 |= Key[entry++]; + } + + KeySize--; + + /* temp64 = XGE_HAL_RTH_HASH_MASK_n(val64, (n<<3), (n<<3)+7);*/ + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rts_rth_hash_mask[nreg++]); + } + + while( nreg < 5 ) { + /* Clear the rest if key is less than 40 bytes */ + val64 = 0; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rts_rth_hash_mask[nreg++]); + } +} + + +/** + * xge_hal_device_is_closed - Device is closed + * + * @devh: HAL device handle. + */ +int +xge_hal_device_is_closed(xge_hal_device_h devh) +{ + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + + if (xge_list_is_empty(&hldev->fifo_channels) && + xge_list_is_empty(&hldev->ring_channels)) + return 1; + + return 0; +} + +xge_hal_status_e +xge_hal_device_rts_section_enable(xge_hal_device_h devh, int index) +{ + u64 val64; + int section; + int max_addr = XGE_HAL_MAX_MAC_ADDRESSES; + + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) + max_addr = XGE_HAL_MAX_MAC_ADDRESSES_HERC; + + if ( index >= max_addr ) + return XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES; + + /* + * Calculate the section value + */ + section = index / 32; + + xge_debug_device(XGE_TRACE, "the Section value is %d ", section); + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->rts_mac_cfg); + switch(section) + { + case 0: + val64 |= XGE_HAL_RTS_MAC_SECT0_EN; + break; + case 1: + val64 |= XGE_HAL_RTS_MAC_SECT1_EN; + break; + case 2: + val64 |= XGE_HAL_RTS_MAC_SECT2_EN; + break; + case 3: + val64 |= XGE_HAL_RTS_MAC_SECT3_EN; + break; + case 4: + val64 |= XGE_HAL_RTS_MAC_SECT4_EN; + break; + case 5: + val64 |= XGE_HAL_RTS_MAC_SECT5_EN; + break; + case 6: + val64 |= XGE_HAL_RTS_MAC_SECT6_EN; + break; + case 7: + val64 |= XGE_HAL_RTS_MAC_SECT7_EN; + break; + default: + xge_debug_device(XGE_ERR, "Invalid Section value %d " + , section); + } + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &bar0->rts_mac_cfg); + return XGE_HAL_OK; +} + + diff --git a/sys/dev/nxge/xgehal/xgehal-driver.c b/sys/dev/nxge/xgehal/xgehal-driver.c new file mode 100644 index 0000000..c8d1989 --- /dev/null +++ b/sys/dev/nxge/xgehal/xgehal-driver.c @@ -0,0 +1,300 @@ +/*- + * Copyright (c) 2002-2007 Neterion, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * FileName : xgehal-driver.c + * + * Description: HAL driver object functionality + * + * Created: 10 May 2004 + */ + +#include +#include + +static xge_hal_driver_t g_driver; +xge_hal_driver_t *g_xge_hal_driver = NULL; +char *g_xge_hal_log = NULL; + +#ifdef XGE_OS_MEMORY_CHECK +xge_os_malloc_t g_malloc_arr[XGE_OS_MALLOC_CNT_MAX]; +int g_malloc_cnt = 0; +#endif + +/* + * Runtime tracing support + */ +static unsigned long g_module_mask_default = 0; +unsigned long *g_module_mask = &g_module_mask_default; +static int g_level_default = 0; +int *g_level = &g_level_default; + +#ifdef XGE_TRACE_INTO_CIRCULAR_ARR +static xge_os_tracebuf_t g_tracebuf; +char *dmesg, *dmesg_start; + +/** + * xge_hal_driver_tracebuf_dump - Dump the trace buffer. + * + * Dump the trace buffer contents. + */ +void +xge_hal_driver_tracebuf_dump(void) +{ + int i; + int off = 0; + + if (g_xge_os_tracebuf == NULL) { + return; + } + + xge_os_printf("################ Trace dump Begin ###############"); + if (g_xge_os_tracebuf->wrapped_once) { + for (i = 0; i < g_xge_os_tracebuf->size - + g_xge_os_tracebuf->offset; i += off) { + if (*(dmesg_start + i)) + xge_os_printf(dmesg_start + i); + off = xge_os_strlen(dmesg_start + i) + 1; + } + } + for (i = 0; i < g_xge_os_tracebuf->offset; i += off) { + if (*(dmesg + i)) + xge_os_printf(dmesg + i); + off = xge_os_strlen(dmesg + i) + 1; + } + xge_os_printf("################ Trace dump End ###############"); +} + +xge_hal_status_e +xge_hal_driver_tracebuf_read(int bufsize, char *retbuf, int *retsize) +{ + int i; + int off = 0, retbuf_off = 0; + + *retsize = 0; + *retbuf = 0; + + if (g_xge_os_tracebuf == NULL) { + return XGE_HAL_FAIL; + } + + if (g_xge_os_tracebuf->wrapped_once) { + for (i = 0; i < g_xge_os_tracebuf->size - + g_xge_os_tracebuf->offset; i += off) { + if (*(dmesg_start + i)) { + xge_os_sprintf(retbuf + retbuf_off, "%s\n", dmesg_start + i); + retbuf_off += xge_os_strlen(dmesg_start + i) + 1; + if (retbuf_off > bufsize) + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + off = xge_os_strlen(dmesg_start + i) + 1; + } + } + for (i = 0; i < g_xge_os_tracebuf->offset; i += off) { + if (*(dmesg + i)) { + xge_os_sprintf(retbuf + retbuf_off, "%s\n", dmesg + i); + retbuf_off += xge_os_strlen(dmesg + i) + 1; + if (retbuf_off > bufsize) + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + off = xge_os_strlen(dmesg + i) + 1; + } + + *retsize = retbuf_off; + *(retbuf + retbuf_off + 1) = 0; + + return XGE_HAL_OK; +} +#endif +xge_os_tracebuf_t *g_xge_os_tracebuf = NULL; + +#ifdef XGE_HAL_DEBUG_BAR0_OFFSET +void +xge_hal_driver_bar0_offset_check(void) +{ + xge_assert(xge_offsetof(xge_hal_pci_bar0_t, adapter_status) == + 0x108); + xge_assert(xge_offsetof(xge_hal_pci_bar0_t, tx_traffic_int) == + 0x08E0); + xge_assert(xge_offsetof(xge_hal_pci_bar0_t, dtx_control) == + 0x09E8); + xge_assert(xge_offsetof(xge_hal_pci_bar0_t, tx_fifo_partition_0) == + 0x1108); + xge_assert(xge_offsetof(xge_hal_pci_bar0_t, pcc_enable) == + 0x1170); + xge_assert(xge_offsetof(xge_hal_pci_bar0_t, prc_rxd0_n[0]) == + 0x1930); + xge_assert(xge_offsetof(xge_hal_pci_bar0_t, rti_command_mem) == + 0x19B8); + xge_assert(xge_offsetof(xge_hal_pci_bar0_t, mac_cfg) == + 0x2100); + xge_assert(xge_offsetof(xge_hal_pci_bar0_t, rmac_addr_cmd_mem) == + 0x2128); + xge_assert(xge_offsetof(xge_hal_pci_bar0_t, mac_link_util) == + 0x2170); + xge_assert(xge_offsetof(xge_hal_pci_bar0_t, mc_pause_thresh_q0q3) == + 0x2918); + xge_assert(xge_offsetof(xge_hal_pci_bar0_t, pcc_err_reg) == + 0x1040); + xge_assert(xge_offsetof(xge_hal_pci_bar0_t, rxdma_int_status) == + 0x1800); + xge_assert(xge_offsetof(xge_hal_pci_bar0_t, mac_tmac_err_reg) == + 0x2010); + xge_assert(xge_offsetof(xge_hal_pci_bar0_t, mc_err_reg) == + 0x2810); + xge_assert(xge_offsetof(xge_hal_pci_bar0_t, xgxs_int_status) == + 0x3000); +} +#endif + +/** + * xge_hal_driver_initialize - Initialize HAL. + * @config: HAL configuration, see xge_hal_driver_config_t{}. + * @uld_callbacks: Upper-layer driver callbacks, e.g. link-up. + * + * HAL initialization entry point. Not to confuse with device initialization + * (note that HAL "contains" zero or more Xframe devices). + * + * Returns: XGE_HAL_OK - success; + * XGE_HAL_ERR_BAD_DRIVER_CONFIG - Driver configuration params invalid. + * + * See also: xge_hal_device_initialize(), xge_hal_status_e{}, + * xge_hal_uld_cbs_t{}. + */ +xge_hal_status_e +xge_hal_driver_initialize(xge_hal_driver_config_t *config, + xge_hal_uld_cbs_t *uld_callbacks) +{ + xge_hal_status_e status; + + g_xge_hal_driver = &g_driver; + + xge_hal_driver_debug_module_mask_set(XGE_DEBUG_MODULE_MASK_DEF); + xge_hal_driver_debug_level_set(XGE_DEBUG_LEVEL_DEF); + +#ifdef XGE_HAL_DEBUG_BAR0_OFFSET + xge_hal_driver_bar0_offset_check(); +#endif + +#ifdef XGE_TRACE_INTO_CIRCULAR_ARR + if (config->tracebuf_size == 0) + /* + * Trace buffer implementation is not lock protected. + * The only harm to expect is memcpy() to go beyond of + * allowed boundaries. To make it safe (driver-wise), + * we pre-allocate needed number of extra bytes. + */ + config->tracebuf_size = XGE_HAL_DEF_CIRCULAR_ARR + + XGE_OS_TRACE_MSGBUF_MAX; +#endif + + status = __hal_driver_config_check(config); + if (status != XGE_HAL_OK) + return status; + + xge_os_memzero(g_xge_hal_driver, sizeof(xge_hal_driver_t)); + + /* apply config */ + xge_os_memcpy(&g_xge_hal_driver->config, config, + sizeof(xge_hal_driver_config_t)); + + /* apply ULD callbacks */ + xge_os_memcpy(&g_xge_hal_driver->uld_callbacks, uld_callbacks, + sizeof(xge_hal_uld_cbs_t)); + + g_xge_hal_driver->is_initialized = 1; + +#ifdef XGE_TRACE_INTO_CIRCULAR_ARR + g_tracebuf.size = config->tracebuf_size; + g_tracebuf.data = (char *)xge_os_malloc(NULL, g_tracebuf.size); + if (g_tracebuf.data == NULL) { + xge_os_printf("cannot allocate trace buffer!"); + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + /* timestamps disabled by default */ + g_tracebuf.timestamp = config->tracebuf_timestamp_en; + if (g_tracebuf.timestamp) { + xge_os_timestamp(g_tracebuf.msg); + g_tracebuf.msgbuf_max = XGE_OS_TRACE_MSGBUF_MAX - + xge_os_strlen(g_tracebuf.msg); + } else + g_tracebuf.msgbuf_max = XGE_OS_TRACE_MSGBUF_MAX; + g_tracebuf.offset = 0; + *g_tracebuf.msg = 0; + xge_os_memzero(g_tracebuf.data, g_tracebuf.size); + g_xge_os_tracebuf = &g_tracebuf; + dmesg = g_tracebuf.data; + *dmesg = 0; +#endif + return XGE_HAL_OK; +} + +/** + * xge_hal_driver_terminate - Terminate HAL. + * + * HAL termination entry point. + * + * See also: xge_hal_device_terminate(). + */ +void +xge_hal_driver_terminate(void) +{ + g_xge_hal_driver->is_initialized = 0; + +#ifdef XGE_TRACE_INTO_CIRCULAR_ARR + if (g_tracebuf.size) { + xge_os_free(NULL, g_tracebuf.data, g_tracebuf.size); + } +#endif + + g_xge_hal_driver = NULL; + +#ifdef XGE_OS_MEMORY_CHECK + { + int i, leaks=0; + xge_os_printf("OSPAL: max g_malloc_cnt %d", g_malloc_cnt); + for (i=0; i +#endif + +__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_fifo_txdl_priv_t* +__hal_fifo_txdl_priv(xge_hal_dtr_h dtrh) +{ + xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t*)dtrh; + xge_hal_fifo_txdl_priv_t *txdl_priv; + + xge_assert(txdp); + txdl_priv = (xge_hal_fifo_txdl_priv_t *) + (ulong_t)txdp->host_control; + + xge_assert(txdl_priv); + xge_assert(txdl_priv->dma_object); + xge_assert(txdl_priv->dma_addr); + + xge_assert(txdl_priv->dma_object->handle == txdl_priv->dma_handle); + + return txdl_priv; +} + +__HAL_STATIC_FIFO __HAL_INLINE_FIFO void +__hal_fifo_dtr_post_single(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, + u64 ctrl_1) +{ + xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh; + xge_hal_fifo_hw_pair_t *hw_pair = fifo->hw_pair; + xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)dtrh; + xge_hal_fifo_txdl_priv_t *txdl_priv; + u64 ctrl; + + txdp->control_1 |= XGE_HAL_TXD_LIST_OWN_XENA; + +#ifdef XGE_DEBUG_ASSERT + /* make sure Xena overwrites the (illegal) t_code value on completion */ + XGE_HAL_SET_TXD_T_CODE(txdp->control_1, XGE_HAL_TXD_T_CODE_UNUSED_5); +#endif + + txdl_priv = __hal_fifo_txdl_priv(dtrh); + +#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_DTR_STREAMING) + /* sync the TxDL to device */ + xge_os_dma_sync(fifo->channel.pdev, + txdl_priv->dma_handle, + txdl_priv->dma_addr, + txdl_priv->dma_offset, + txdl_priv->frags << 5 /* sizeof(xge_hal_fifo_txd_t) */, + XGE_OS_DMA_DIR_TODEVICE); +#endif + /* write the pointer first */ + xge_os_pio_mem_write64(fifo->channel.pdev, + fifo->channel.regh1, + txdl_priv->dma_addr, + &hw_pair->txdl_pointer); + + /* spec: 0x00 = 1 TxD in the list */ + ctrl = XGE_HAL_TX_FIFO_LAST_TXD_NUM(txdl_priv->frags - 1); + ctrl |= ctrl_1; + ctrl |= fifo->no_snoop_bits; + + if (txdp->control_1 & XGE_HAL_TXD_LSO_COF_CTRL(XGE_HAL_TXD_TCP_LSO)) { + ctrl |= XGE_HAL_TX_FIFO_SPECIAL_FUNC; + } + + /* + * according to the XENA spec: + * + * It is important to note that pointers and list control words are + * always written in pairs: in the first write, the host must write a + * pointer, and in the second write, it must write the list control + * word. Any other access will result in an error. Also, all 16 bytes + * of the pointer/control structure must be written, including any + * reserved bytes. + */ + xge_os_wmb(); + + /* + * we want touch work_arr in order with ownership bit set to HW + */ + __hal_channel_dtr_post(channelh, dtrh); + + xge_os_pio_mem_write64(fifo->channel.pdev, fifo->channel.regh1, + ctrl, &hw_pair->list_control); + + xge_debug_fifo(XGE_TRACE, "posted txdl 0x"XGE_OS_LLXFMT" ctrl 0x"XGE_OS_LLXFMT" " + "into 0x"XGE_OS_LLXFMT"", (unsigned long long)txdl_priv->dma_addr, + (unsigned long long)ctrl, + (unsigned long long)(ulong_t)&hw_pair->txdl_pointer); + +#ifdef XGE_HAL_FIFO_DUMP_TXD + xge_os_printf(""XGE_OS_LLXFMT":"XGE_OS_LLXFMT":"XGE_OS_LLXFMT":" + XGE_OS_LLXFMT" dma "XGE_OS_LLXFMT, + txdp->control_1, txdp->control_2, txdp->buffer_pointer, + txdp->host_control, txdl_priv->dma_addr); +#endif + + fifo->channel.stats.total_posts++; + fifo->channel.usage_cnt++; + if (fifo->channel.stats.usage_max < fifo->channel.usage_cnt) + fifo->channel.stats.usage_max = fifo->channel.usage_cnt; +} + +__HAL_STATIC_FIFO __HAL_INLINE_FIFO void +__hal_fifo_txdl_free_many(xge_hal_channel_h channelh, + xge_hal_fifo_txd_t *txdp, int list_size, int frags) +{ + xge_hal_fifo_txdl_priv_t *current_txdl_priv; + xge_hal_fifo_txdl_priv_t *next_txdl_priv; + int invalid_frags = frags % list_size; + if (invalid_frags){ + xge_debug_fifo(XGE_ERR, + "freeing corrupt dtrh %p, fragments %d list size %d", + txdp, frags, list_size); + xge_assert(invalid_frags == 0); + } + while(txdp){ + xge_debug_fifo(XGE_TRACE, + "freeing linked dtrh %p, fragments %d list size %d", + txdp, frags, list_size); + current_txdl_priv = __hal_fifo_txdl_priv(txdp); +#if defined(XGE_DEBUG_ASSERT) && defined(XGE_OS_MEMORY_CHECK) + current_txdl_priv->allocated = 0; +#endif + __hal_channel_dtr_free(channelh, txdp); + next_txdl_priv = current_txdl_priv->next_txdl_priv; + xge_assert(frags); + frags -= list_size; + if (next_txdl_priv) { + current_txdl_priv->next_txdl_priv = NULL; + txdp = next_txdl_priv->first_txdp; + } + else { + xge_debug_fifo(XGE_TRACE, + "freed linked dtrh fragments %d list size %d", + frags, list_size); + break; + } + } + xge_assert(frags == 0) +} + +__HAL_STATIC_FIFO __HAL_INLINE_FIFO void +__hal_fifo_txdl_restore_many(xge_hal_channel_h channelh, + xge_hal_fifo_txd_t *txdp, int txdl_count) +{ + xge_hal_fifo_txdl_priv_t *current_txdl_priv; + xge_hal_fifo_txdl_priv_t *next_txdl_priv; + int i = txdl_count; + + xge_assert(((xge_hal_channel_t *)channelh)->reserve_length + + txdl_count <= ((xge_hal_channel_t *)channelh)->reserve_initial); + + current_txdl_priv = __hal_fifo_txdl_priv(txdp); + do{ + xge_assert(i); +#if defined(XGE_DEBUG_ASSERT) && defined(XGE_OS_MEMORY_CHECK) + current_txdl_priv->allocated = 0; +#endif + next_txdl_priv = current_txdl_priv->next_txdl_priv; + txdp = current_txdl_priv->first_txdp; + current_txdl_priv->next_txdl_priv = NULL; + __hal_channel_dtr_restore(channelh, (xge_hal_dtr_h )txdp, --i); + xge_debug_fifo(XGE_TRACE, + "dtrh %p restored at offset %d", txdp, i); + current_txdl_priv = next_txdl_priv; + } while(current_txdl_priv); + __hal_channel_dtr_restore(channelh, NULL, txdl_count); +} +/** + * xge_hal_fifo_dtr_private - Retrieve per-descriptor private data. + * @channelh: Channel handle. + * @dtrh: Descriptor handle. + * + * Retrieve per-descriptor private data. + * Note that ULD requests per-descriptor space via + * xge_hal_channel_open(). + * + * Returns: private ULD data associated with the descriptor. + * Usage: See ex_xmit{} and ex_tx_compl{}. + */ +__HAL_STATIC_FIFO __HAL_INLINE_FIFO void* +xge_hal_fifo_dtr_private(xge_hal_dtr_h dtrh) +{ + xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)dtrh; + + return ((char *)(ulong_t)txdp->host_control) + + sizeof(xge_hal_fifo_txdl_priv_t); +} + +/** + * xge_hal_fifo_dtr_buffer_cnt - Get number of buffers carried by the + * descriptor. + * @dtrh: Descriptor handle. + * + * Returns: Number of buffers stored in the given descriptor. Can be used + * _after_ the descriptor is set up for posting (see + * xge_hal_fifo_dtr_post()) and _before_ it is deallocated (see + * xge_hal_fifo_dtr_free()). + * + */ +__HAL_STATIC_FIFO __HAL_INLINE_FIFO int +xge_hal_fifo_dtr_buffer_cnt(xge_hal_dtr_h dtrh) +{ + xge_hal_fifo_txdl_priv_t *txdl_priv; + + txdl_priv = __hal_fifo_txdl_priv(dtrh); + + return txdl_priv->frags; +} +/** + * xge_hal_fifo_dtr_reserve_many- Reserve fifo descriptors which span more + * than single txdl. + * @channelh: Channel handle. + * @dtrh: Reserved descriptor. On success HAL fills this "out" parameter + * with a valid handle. + * @frags: minimum number of fragments to be reserved. + * + * Reserve TxDL(s) (that is, fifo descriptor) + * for the subsequent filling-in by upper layerdriver (ULD)) + * and posting on the corresponding channel (@channelh) + * via xge_hal_fifo_dtr_post(). + * + * Returns: XGE_HAL_OK - success; + * XGE_HAL_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available + * + * See also: xge_hal_fifo_dtr_reserve_sp(), xge_hal_fifo_dtr_free(), + * xge_hal_ring_dtr_reserve(), xge_hal_status_e{}. + * Usage: See ex_xmit{}. + */ +__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e +xge_hal_fifo_dtr_reserve_many(xge_hal_channel_h channelh, + xge_hal_dtr_h *dtrh, const int frags) +{ + xge_hal_status_e status = XGE_HAL_OK; + int alloc_frags = 0, dang_frags = 0; + xge_hal_fifo_txd_t *curr_txdp = NULL; + xge_hal_fifo_txd_t *next_txdp; + xge_hal_fifo_txdl_priv_t *next_txdl_priv, *curr_txdl_priv = NULL; + xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh; + int max_frags = fifo->config->max_frags; + xge_hal_dtr_h dang_dtrh = NULL; +#if defined(XGE_HAL_TX_MULTI_RESERVE_IRQ) + unsigned long flags=0; +#endif + xge_debug_fifo(XGE_TRACE, "dtr_reserve_many called for frags %d", + frags); + xge_assert(frags < (fifo->txdl_per_memblock * max_frags)); +#if defined(XGE_HAL_TX_MULTI_RESERVE) + xge_os_spin_lock(&fifo->channel.reserve_lock); +#elif defined(XGE_HAL_TX_MULTI_RESERVE_IRQ) + xge_os_spin_lock_irq(&fifo->channel.reserve_lock, flags); +#endif + while(alloc_frags < frags) { + status = __hal_channel_dtr_alloc(channelh, + (xge_hal_dtr_h *)(void*)&next_txdp); + if (status != XGE_HAL_OK){ + xge_debug_fifo(XGE_ERR, + "failed to allocate linked fragments rc %d", + status); + xge_assert(status == XGE_HAL_INF_OUT_OF_DESCRIPTORS); + if (*dtrh) { + xge_assert(alloc_frags/max_frags); + __hal_fifo_txdl_restore_many(channelh, + (xge_hal_fifo_txd_t *) *dtrh, alloc_frags/max_frags); + } + if (dang_dtrh) { + xge_assert(dang_frags/max_frags); + __hal_fifo_txdl_restore_many(channelh, + (xge_hal_fifo_txd_t *) dang_dtrh, dang_frags/max_frags); + } + break; + } + xge_debug_fifo(XGE_TRACE, "allocated linked dtrh %p" + " for frags %d", next_txdp, frags); + next_txdl_priv = __hal_fifo_txdl_priv(next_txdp); + xge_assert(next_txdl_priv); + xge_assert(next_txdl_priv->first_txdp == next_txdp); + next_txdl_priv->dang_txdl = NULL; + next_txdl_priv->dang_frags = 0; + next_txdl_priv->next_txdl_priv = NULL; +#if defined(XGE_OS_MEMORY_CHECK) + next_txdl_priv->allocated = 1; +#endif + if (!curr_txdp || !curr_txdl_priv) { + curr_txdp = next_txdp; + curr_txdl_priv = next_txdl_priv; + *dtrh = (xge_hal_dtr_h)next_txdp; + alloc_frags = max_frags; + continue; + } + if (curr_txdl_priv->memblock == + next_txdl_priv->memblock) { + xge_debug_fifo(XGE_TRACE, + "linking dtrh %p, with %p", + *dtrh, next_txdp); + xge_assert (next_txdp == + curr_txdp + max_frags); + alloc_frags += max_frags; + curr_txdl_priv->next_txdl_priv = next_txdl_priv; + } + else { + xge_assert(*dtrh); + xge_assert(dang_dtrh == NULL); + dang_dtrh = *dtrh; + dang_frags = alloc_frags; + xge_debug_fifo(XGE_TRACE, + "dangling dtrh %p, linked with dtrh %p", + *dtrh, next_txdp); + next_txdl_priv->dang_txdl = (xge_hal_fifo_txd_t *) *dtrh; + next_txdl_priv->dang_frags = alloc_frags; + alloc_frags = max_frags; + *dtrh = next_txdp; + } + curr_txdp = next_txdp; + curr_txdl_priv = next_txdl_priv; + } + +#if defined(XGE_HAL_TX_MULTI_RESERVE) + xge_os_spin_unlock(&fifo->channel.reserve_lock); +#elif defined(XGE_HAL_TX_MULTI_RESERVE_IRQ) + xge_os_spin_unlock_irq(&fifo->channel.reserve_lock, flags); +#endif + + if (status == XGE_HAL_OK) { + xge_hal_fifo_txdl_priv_t * txdl_priv; + xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)*dtrh; + xge_hal_stats_channel_info_t *statsp = &fifo->channel.stats; + txdl_priv = __hal_fifo_txdl_priv(txdp); + /* reset the TxDL's private */ + txdl_priv->align_dma_offset = 0; + txdl_priv->align_vaddr_start = txdl_priv->align_vaddr; + txdl_priv->align_used_frags = 0; + txdl_priv->frags = 0; + txdl_priv->bytes_sent = 0; + txdl_priv->alloc_frags = alloc_frags; + /* reset TxD0 */ + txdp->control_1 = txdp->control_2 = 0; + +#if defined(XGE_OS_MEMORY_CHECK) + txdl_priv->allocated = 1; +#endif + /* update statistics */ + statsp->total_posts_dtrs_many++; + statsp->total_posts_frags_many += txdl_priv->alloc_frags; + if (txdl_priv->dang_frags){ + statsp->total_posts_dang_dtrs++; + statsp->total_posts_dang_frags += txdl_priv->dang_frags; + } + } + + return status; +} + +/** + * xge_hal_fifo_dtr_reserve - Reserve fifo descriptor. + * @channelh: Channel handle. + * @dtrh: Reserved descriptor. On success HAL fills this "out" parameter + * with a valid handle. + * + * Reserve a single TxDL (that is, fifo descriptor) + * for the subsequent filling-in by upper layerdriver (ULD)) + * and posting on the corresponding channel (@channelh) + * via xge_hal_fifo_dtr_post(). + * + * Note: it is the responsibility of ULD to reserve multiple descriptors + * for lengthy (e.g., LSO) transmit operation. A single fifo descriptor + * carries up to configured number (fifo.max_frags) of contiguous buffers. + * + * Returns: XGE_HAL_OK - success; + * XGE_HAL_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available + * + * See also: xge_hal_fifo_dtr_reserve_sp(), xge_hal_fifo_dtr_free(), + * xge_hal_ring_dtr_reserve(), xge_hal_status_e{}. + * Usage: See ex_xmit{}. + */ +__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e +xge_hal_fifo_dtr_reserve(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh) +{ + xge_hal_status_e status; +#if defined(XGE_HAL_TX_MULTI_RESERVE_IRQ) + unsigned long flags=0; +#endif + +#if defined(XGE_HAL_TX_MULTI_RESERVE) + xge_os_spin_lock(&((xge_hal_channel_t*)channelh)->reserve_lock); +#elif defined(XGE_HAL_TX_MULTI_RESERVE_IRQ) + xge_os_spin_lock_irq(&((xge_hal_channel_t*)channelh)->reserve_lock, + flags); +#endif + + status = __hal_channel_dtr_alloc(channelh, dtrh); + +#if defined(XGE_HAL_TX_MULTI_RESERVE) + xge_os_spin_unlock(&((xge_hal_channel_t*)channelh)->reserve_lock); +#elif defined(XGE_HAL_TX_MULTI_RESERVE_IRQ) + xge_os_spin_unlock_irq(&((xge_hal_channel_t*)channelh)->reserve_lock, + flags); +#endif + + if (status == XGE_HAL_OK) { + xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)*dtrh; + xge_hal_fifo_txdl_priv_t *txdl_priv; + + txdl_priv = __hal_fifo_txdl_priv(txdp); + + /* reset the TxDL's private */ + txdl_priv->align_dma_offset = 0; + txdl_priv->align_vaddr_start = txdl_priv->align_vaddr; + txdl_priv->align_used_frags = 0; + txdl_priv->frags = 0; + txdl_priv->alloc_frags = + ((xge_hal_fifo_t *)channelh)->config->max_frags; + txdl_priv->dang_txdl = NULL; + txdl_priv->dang_frags = 0; + txdl_priv->next_txdl_priv = NULL; + txdl_priv->bytes_sent = 0; + + /* reset TxD0 */ + txdp->control_1 = txdp->control_2 = 0; + +#if defined(XGE_OS_MEMORY_CHECK) + txdl_priv->allocated = 1; +#endif + } + + return status; +} + +/** + * xge_hal_fifo_dtr_reserve_sp - Reserve fifo descriptor and store it in + * the ULD-provided "scratch" memory. + * @channelh: Channel handle. + * @dtr_sp_size: Size of the %dtr_sp "scratch pad" that HAL can use for TxDL. + * @dtr_sp: "Scratch pad" supplied by upper-layer driver (ULD). + * + * Reserve TxDL and fill-in ULD supplied "scratch pad". The difference + * between this API and xge_hal_fifo_dtr_reserve() is (possibly) - + * performance. + * + * If upper-layer uses ULP-defined commands, and if those commands have enough + * space for HAL/Xframe descriptors - tnan it is better (read: faster) to fit + * all the per-command information into one command, which is typically + * one contiguous block. + * + * Note: Unlike xge_hal_fifo_dtr_reserve(), this function can be used to + * allocate a single descriptor for transmit operation. + * + * See also: xge_hal_fifo_dtr_reserve(), xge_hal_fifo_dtr_free(), + * xge_hal_ring_dtr_reserve(), xge_hal_status_e{}. + */ +__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e +xge_hal_fifo_dtr_reserve_sp(xge_hal_channel_h channelh, int dtr_sp_size, + xge_hal_dtr_h dtr_sp) +{ + /* FIXME: implement */ + return XGE_HAL_OK; +} + +/** + * xge_hal_fifo_dtr_post - Post descriptor on the fifo channel. + * @channelh: Channel handle. + * @dtrh: Descriptor obtained via xge_hal_fifo_dtr_reserve() or + * xge_hal_fifo_dtr_reserve_sp() + * @frags: Number of contiguous buffers that are part of a single + * transmit operation. + * + * Post descriptor on the 'fifo' type channel for transmission. + * Prior to posting the descriptor should be filled in accordance with + * Host/Xframe interface specification for a given service (LL, etc.). + * + * See also: xge_hal_fifo_dtr_post_many(), xge_hal_ring_dtr_post(). + * Usage: See ex_xmit{}. + */ +__HAL_STATIC_FIFO __HAL_INLINE_FIFO void +xge_hal_fifo_dtr_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh) +{ + xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh; + xge_hal_fifo_txdl_priv_t *txdl_priv; + xge_hal_fifo_txd_t *txdp_last; + xge_hal_fifo_txd_t *txdp_first; +#if defined(XGE_HAL_TX_MULTI_POST_IRQ) + unsigned long flags = 0; +#endif + + txdl_priv = __hal_fifo_txdl_priv(dtrh); + + txdp_first = (xge_hal_fifo_txd_t *)dtrh; + txdp_first->control_1 |= XGE_HAL_TXD_GATHER_CODE_FIRST; + txdp_first->control_2 |= fifo->interrupt_type; + + txdp_last = (xge_hal_fifo_txd_t *)dtrh + (txdl_priv->frags - 1); + txdp_last->control_1 |= XGE_HAL_TXD_GATHER_CODE_LAST; + +#if defined(XGE_HAL_TX_MULTI_POST) + xge_os_spin_lock(fifo->post_lock_ptr); +#elif defined(XGE_HAL_TX_MULTI_POST_IRQ) + xge_os_spin_lock_irq(fifo->post_lock_ptr, flags); +#endif + + __hal_fifo_dtr_post_single(channelh, dtrh, + (u64)(XGE_HAL_TX_FIFO_FIRST_LIST | XGE_HAL_TX_FIFO_LAST_LIST)); + +#if defined(XGE_HAL_TX_MULTI_POST) + xge_os_spin_unlock(fifo->post_lock_ptr); +#elif defined(XGE_HAL_TX_MULTI_POST_IRQ) + xge_os_spin_unlock_irq(fifo->post_lock_ptr, flags); +#endif +} + +/** + * xge_hal_fifo_dtr_post_many - Post multiple descriptors on fifo + * channel. + * @channelh: Channel to post descriptor. + * @num: Number of descriptors (i.e., fifo TxDLs) in the %dtrs[]. + * @dtrs: Descriptors obtained via xge_hal_fifo_dtr_reserve(). + * @frags_arr: Number of fragments carried @dtrs descriptors. + * Note that frag_arr[i] corresponds to descriptor dtrs[i]. + * + * Post multi-descriptor on the fifo channel. The operation is atomic: + * all descriptrs are posted on the channel "back-to-back' without + * letting other posts (possibly driven by multiple transmitting threads) + * to interleave. + * + * See also: xge_hal_fifo_dtr_post(), xge_hal_ring_dtr_post(). + */ +__HAL_STATIC_FIFO __HAL_INLINE_FIFO void +xge_hal_fifo_dtr_post_many(xge_hal_channel_h channelh, int num, + xge_hal_dtr_h dtrs[]) +{ + int i; + xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh; + xge_hal_fifo_txd_t *txdp_last; + xge_hal_fifo_txd_t *txdp_first; + xge_hal_fifo_txdl_priv_t *txdl_priv_last; +#if defined(XGE_HAL_TX_MULTI_POST_IRQ) + unsigned long flags = 0; +#endif + + xge_assert(num > 1); + + txdp_first = (xge_hal_fifo_txd_t *)dtrs[0]; + txdp_first->control_1 |= XGE_HAL_TXD_GATHER_CODE_FIRST; + txdp_first->control_2 |= fifo->interrupt_type; + + txdl_priv_last = __hal_fifo_txdl_priv(dtrs[num-1]); + txdp_last = (xge_hal_fifo_txd_t *)dtrs[num-1] + + (txdl_priv_last->frags - 1); + txdp_last->control_1 |= XGE_HAL_TXD_GATHER_CODE_LAST; + +#if defined(XGE_HAL_TX_MULTI_POST) + xge_os_spin_lock(&((xge_hal_channel_t*)channelh)->post_lock); +#elif defined(XGE_HAL_TX_MULTI_POST_IRQ) + xge_os_spin_lock_irq(&((xge_hal_channel_t*)channelh)->post_lock, + flags); +#endif + + for (i=0; ipost_lock); +#elif defined(XGE_HAL_TX_MULTI_POST_IRQ) + xge_os_spin_unlock_irq(&((xge_hal_channel_t*)channelh)->post_lock, + flags); +#endif + + fifo->channel.stats.total_posts_many++; +} + +/** + * xge_hal_fifo_dtr_next_completed - Retrieve next completed descriptor. + * @channelh: Channel handle. + * @dtrh: Descriptor handle. Returned by HAL. + * @t_code: Transfer code, as per Xframe User Guide, + * Transmit Descriptor Format. + * Returned by HAL. + * + * Retrieve the _next_ completed descriptor. + * HAL uses channel callback (*xge_hal_channel_callback_f) to notifiy + * upper-layer driver (ULD) of new completed descriptors. After that + * the ULD can use xge_hal_fifo_dtr_next_completed to retrieve the rest + * completions (the very first completion is passed by HAL via + * xge_hal_channel_callback_f). + * + * Implementation-wise, the upper-layer driver is free to call + * xge_hal_fifo_dtr_next_completed either immediately from inside the + * channel callback, or in a deferred fashion and separate (from HAL) + * context. + * + * Non-zero @t_code means failure to process the descriptor. + * The failure could happen, for instance, when the link is + * down, in which case Xframe completes the descriptor because it + * is not able to send the data out. + * + * For details please refer to Xframe User Guide. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors + * are currently available for processing. + * + * See also: xge_hal_channel_callback_f{}, + * xge_hal_ring_dtr_next_completed(). + * Usage: See ex_tx_compl{}. + */ +__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e +xge_hal_fifo_dtr_next_completed(xge_hal_channel_h channelh, + xge_hal_dtr_h *dtrh, u8 *t_code) +{ + xge_hal_fifo_txd_t *txdp; + xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh; +#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_DTR_STREAMING) + xge_hal_fifo_txdl_priv_t *txdl_priv; +#endif + + __hal_channel_dtr_try_complete(channelh, dtrh); + txdp = (xge_hal_fifo_txd_t *)*dtrh; + if (txdp == NULL) { + return XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS; + } + +#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_DTR_STREAMING) + txdl_priv = __hal_fifo_txdl_priv(txdp); + + /* sync TxDL to read the ownership + * + * Note: 16bytes means Control_1 & Control_2 */ + xge_os_dma_sync(fifo->channel.pdev, + txdl_priv->dma_handle, + txdl_priv->dma_addr, + txdl_priv->dma_offset, + 16, + XGE_OS_DMA_DIR_FROMDEVICE); +#endif + + /* check whether host owns it */ + if ( !(txdp->control_1 & XGE_HAL_TXD_LIST_OWN_XENA) ) { + + xge_assert(txdp->host_control!=0); + + __hal_channel_dtr_complete(channelh); + + *t_code = (u8)XGE_HAL_GET_TXD_T_CODE(txdp->control_1); + + /* see XGE_HAL_SET_TXD_T_CODE() above.. */ + xge_assert(*t_code != XGE_HAL_TXD_T_CODE_UNUSED_5); + + if (fifo->channel.usage_cnt > 0) + fifo->channel.usage_cnt--; + + return XGE_HAL_OK; + } + + /* no more completions */ + *dtrh = 0; + return XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS; +} + +/** + * xge_hal_fifo_dtr_free - Free descriptor. + * @channelh: Channel handle. + * @dtr: Descriptor handle. + * + * Free the reserved descriptor. This operation is "symmetrical" to + * xge_hal_fifo_dtr_reserve or xge_hal_fifo_dtr_reserve_sp. + * The "free-ing" completes the descriptor's lifecycle. + * + * After free-ing (see xge_hal_fifo_dtr_free()) the descriptor again can + * be: + * + * - reserved (xge_hal_fifo_dtr_reserve); + * + * - posted (xge_hal_fifo_dtr_post); + * + * - completed (xge_hal_fifo_dtr_next_completed); + * + * - and recycled again (xge_hal_fifo_dtr_free). + * + * For alternative state transitions and more details please refer to + * the design doc. + * + * See also: xge_hal_ring_dtr_free(), xge_hal_fifo_dtr_reserve(). + * Usage: See ex_tx_compl{}. + */ +__HAL_STATIC_FIFO __HAL_INLINE_FIFO void +xge_hal_fifo_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtr) +{ +#if defined(XGE_HAL_TX_MULTI_FREE_IRQ) + unsigned long flags = 0; +#endif + xge_hal_fifo_txdl_priv_t *txdl_priv = __hal_fifo_txdl_priv( + (xge_hal_fifo_txd_t *)dtr); + int max_frags = ((xge_hal_fifo_t *)channelh)->config->max_frags; +#if defined(XGE_HAL_TX_MULTI_FREE) + xge_os_spin_lock(&((xge_hal_channel_t*)channelh)->free_lock); +#elif defined(XGE_HAL_TX_MULTI_FREE_IRQ) + xge_os_spin_lock_irq(&((xge_hal_channel_t*)channelh)->free_lock, + flags); +#endif + + if (txdl_priv->alloc_frags > max_frags) { + xge_hal_fifo_txd_t *dang_txdp = (xge_hal_fifo_txd_t *) + txdl_priv->dang_txdl; + int dang_frags = txdl_priv->dang_frags; + int alloc_frags = txdl_priv->alloc_frags; + txdl_priv->dang_txdl = NULL; + txdl_priv->dang_frags = 0; + txdl_priv->alloc_frags = 0; + /* dtrh must have a linked list of dtrh */ + xge_assert(txdl_priv->next_txdl_priv); + + /* free any dangling dtrh first */ + if (dang_txdp) { + xge_debug_fifo(XGE_TRACE, + "freeing dangled dtrh %p for %d fragments", + dang_txdp, dang_frags); + __hal_fifo_txdl_free_many(channelh, dang_txdp, + max_frags, dang_frags); + } + + /* now free the reserved dtrh list */ + xge_debug_fifo(XGE_TRACE, + "freeing dtrh %p list of %d fragments", dtr, + alloc_frags); + __hal_fifo_txdl_free_many(channelh, + (xge_hal_fifo_txd_t *)dtr, max_frags, + alloc_frags); + } + else + __hal_channel_dtr_free(channelh, dtr); + + ((xge_hal_channel_t *)channelh)->poll_bytes += txdl_priv->bytes_sent; + +#if defined(XGE_DEBUG_ASSERT) && defined(XGE_OS_MEMORY_CHECK) + __hal_fifo_txdl_priv(dtr)->allocated = 0; +#endif + +#if defined(XGE_HAL_TX_MULTI_FREE) + xge_os_spin_unlock(&((xge_hal_channel_t*)channelh)->free_lock); +#elif defined(XGE_HAL_TX_MULTI_FREE_IRQ) + xge_os_spin_unlock_irq(&((xge_hal_channel_t*)channelh)->free_lock, + flags); +#endif +} + + +/** + * xge_hal_fifo_dtr_buffer_set_aligned - Align transmit buffer and fill + * in fifo descriptor. + * @channelh: Channel handle. + * @dtrh: Descriptor handle. + * @frag_idx: Index of the data buffer in the caller's scatter-gather listá + * (of buffers). + * @vaddr: Virtual address of the data buffer. + * @dma_pointer: DMA address of the data buffer referenced by @frag_idx. + * @size: Size of the data buffer (in bytes). + * @misaligned_size: Size (in bytes) of the misaligned portion of the + * data buffer. Calculated by the caller, based on the platform/OS/other + * specific criteria, which is outside of HAL's domain. See notes below. + * + * This API is part of the transmit descriptor preparation for posting + * (via xge_hal_fifo_dtr_post()). The related "preparation" APIs include + * xge_hal_fifo_dtr_mss_set() and xge_hal_fifo_dtr_cksum_set_bits(). + * All three APIs fill in the fields of the fifo descriptor, + * in accordance with the Xframe specification. + * On the PCI-X based systems aligning transmit data typically provides better + * transmit performance. The typical alignment granularity: L2 cacheline size. + * However, HAL does not make assumptions in terms of the alignment granularity; + * this is specified via additional @misaligned_size parameter described above. + * Prior to calling xge_hal_fifo_dtr_buffer_set_aligned(), + * ULD is supposed to check alignment of a given fragment/buffer. For this HAL + * provides a separate xge_hal_check_alignment() API sufficient to cover + * most (but not all) possible alignment criteria. + * If the buffer appears to be aligned, the ULD calls + * xge_hal_fifo_dtr_buffer_set(). + * Otherwise, ULD calls xge_hal_fifo_dtr_buffer_set_aligned(). + * + * Note; This API is a "superset" of xge_hal_fifo_dtr_buffer_set(). In + * addition to filling in the specified descriptor it aligns transmit data on + * the specified boundary. + * Note: Decision on whether to align or not to align a given contiguous + * transmit buffer is outside of HAL's domain. To this end ULD can use any + * programmable criteria, which can help to 1) boost transmit performance, + * and/or 2) provide a workaround for PCI bridge bugs, if any. + * + * See also: xge_hal_fifo_dtr_buffer_set(), + * xge_hal_check_alignment(). + * + * See also: xge_hal_fifo_dtr_reserve(), xge_hal_fifo_dtr_post(), + * xge_hal_fifo_dtr_mss_set(), xge_hal_fifo_dtr_cksum_set_bits() + */ +__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e +xge_hal_fifo_dtr_buffer_set_aligned(xge_hal_channel_h channelh, + xge_hal_dtr_h dtrh, int frag_idx, void *vaddr, + dma_addr_t dma_pointer, int size, int misaligned_size) +{ + xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh; + xge_hal_fifo_txdl_priv_t *txdl_priv; + xge_hal_fifo_txd_t *txdp; + int remaining_size; + ptrdiff_t prev_boff; + + txdl_priv = __hal_fifo_txdl_priv(dtrh); + txdp = (xge_hal_fifo_txd_t *)dtrh + txdl_priv->frags; + + if (frag_idx != 0) { + txdp->control_1 = txdp->control_2 = 0; + } + + /* On some systems buffer size could be zero. + * It is the responsibility of ULD and *not HAL* to + * detect it and skip it. */ + xge_assert(size > 0); + xge_assert(frag_idx < txdl_priv->alloc_frags); + xge_assert(misaligned_size != 0 && + misaligned_size <= fifo->config->alignment_size); + + remaining_size = size - misaligned_size; + xge_assert(remaining_size >= 0); + + xge_os_memcpy((char*)txdl_priv->align_vaddr_start, + vaddr, misaligned_size); + + if (txdl_priv->align_used_frags >= fifo->config->max_aligned_frags) { + return XGE_HAL_ERR_OUT_ALIGNED_FRAGS; + } + + /* setup new buffer */ + prev_boff = txdl_priv->align_vaddr_start - txdl_priv->align_vaddr; + txdp->buffer_pointer = (u64)txdl_priv->align_dma_addr + prev_boff; + txdp->control_1 |= XGE_HAL_TXD_BUFFER0_SIZE(misaligned_size); + txdl_priv->bytes_sent += misaligned_size; + fifo->channel.stats.total_buffers++; + txdl_priv->frags++; + txdl_priv->align_used_frags++; + txdl_priv->align_vaddr_start += fifo->config->alignment_size; + txdl_priv->align_dma_offset = 0; + +#if defined(XGE_OS_DMA_REQUIRES_SYNC) + /* sync new buffer */ + xge_os_dma_sync(fifo->channel.pdev, + txdl_priv->align_dma_handle, + txdp->buffer_pointer, + 0, + misaligned_size, + XGE_OS_DMA_DIR_TODEVICE); +#endif + + if (remaining_size) { + xge_assert(frag_idx < txdl_priv->alloc_frags); + txdp++; + txdp->buffer_pointer = (u64)dma_pointer + + misaligned_size; + txdp->control_1 = + XGE_HAL_TXD_BUFFER0_SIZE(remaining_size); + txdl_priv->bytes_sent += remaining_size; + txdp->control_2 = 0; + fifo->channel.stats.total_buffers++; + txdl_priv->frags++; + } + + return XGE_HAL_OK; +} + +/** + * xge_hal_fifo_dtr_buffer_append - Append the contents of virtually + * contiguous data buffer to a single physically contiguous buffer. + * @channelh: Channel handle. + * @dtrh: Descriptor handle. + * @vaddr: Virtual address of the data buffer. + * @size: Size of the data buffer (in bytes). + * + * This API is part of the transmit descriptor preparation for posting + * (via xge_hal_fifo_dtr_post()). + * The main difference of this API wrt to the APIs + * xge_hal_fifo_dtr_buffer_set_aligned() is that this API appends the + * contents of virtually contiguous data buffers received from + * upper layer into a single physically contiguous data buffer and the + * device will do a DMA from this buffer. + * + * See Also: xge_hal_fifo_dtr_buffer_finalize(), xge_hal_fifo_dtr_buffer_set(), + * xge_hal_fifo_dtr_buffer_set_aligned(). + */ +__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e +xge_hal_fifo_dtr_buffer_append(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, + void *vaddr, int size) +{ + xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh; + xge_hal_fifo_txdl_priv_t *txdl_priv; + ptrdiff_t used; + + xge_assert(size > 0); + + txdl_priv = __hal_fifo_txdl_priv(dtrh); + + used = txdl_priv->align_vaddr_start - txdl_priv->align_vaddr; + used += txdl_priv->align_dma_offset; + if (used + (unsigned int)size > (unsigned int)fifo->align_size) + return XGE_HAL_ERR_OUT_ALIGNED_FRAGS; + + xge_os_memcpy((char*)txdl_priv->align_vaddr_start + + txdl_priv->align_dma_offset, vaddr, size); + + fifo->channel.stats.copied_frags++; + + txdl_priv->align_dma_offset += size; + return XGE_HAL_OK; +} + +/** + * xge_hal_fifo_dtr_buffer_finalize - Prepares a descriptor that contains the + * single physically contiguous buffer. + * + * @channelh: Channel handle. + * @dtrh: Descriptor handle. + * @frag_idx: Index of the data buffer in the Txdl list. + * + * This API in conjuction with xge_hal_fifo_dtr_buffer_append() prepares + * a descriptor that consists of a single physically contiguous buffer + * which inturn contains the contents of one or more virtually contiguous + * buffers received from the upper layer. + * + * See Also: xge_hal_fifo_dtr_buffer_append(). +*/ +__HAL_STATIC_FIFO __HAL_INLINE_FIFO void +xge_hal_fifo_dtr_buffer_finalize(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, + int frag_idx) +{ + xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh; + xge_hal_fifo_txdl_priv_t *txdl_priv; + xge_hal_fifo_txd_t *txdp; + ptrdiff_t prev_boff; + + xge_assert(frag_idx < fifo->config->max_frags); + + txdl_priv = __hal_fifo_txdl_priv(dtrh); + txdp = (xge_hal_fifo_txd_t *)dtrh + txdl_priv->frags; + + if (frag_idx != 0) { + txdp->control_1 = txdp->control_2 = 0; + } + + prev_boff = txdl_priv->align_vaddr_start - txdl_priv->align_vaddr; + txdp->buffer_pointer = (u64)txdl_priv->align_dma_addr + prev_boff; + txdp->control_1 |= + XGE_HAL_TXD_BUFFER0_SIZE(txdl_priv->align_dma_offset); + txdl_priv->bytes_sent += (unsigned int)txdl_priv->align_dma_offset; + fifo->channel.stats.total_buffers++; + fifo->channel.stats.copied_buffers++; + txdl_priv->frags++; + txdl_priv->align_used_frags++; + +#if defined(XGE_OS_DMA_REQUIRES_SYNC) + /* sync pre-mapped buffer */ + xge_os_dma_sync(fifo->channel.pdev, + txdl_priv->align_dma_handle, + txdp->buffer_pointer, + 0, + txdl_priv->align_dma_offset, + XGE_OS_DMA_DIR_TODEVICE); +#endif + + /* increment vaddr_start for the next buffer_append() iteration */ + txdl_priv->align_vaddr_start += txdl_priv->align_dma_offset; + txdl_priv->align_dma_offset = 0; +} + +/** + * xge_hal_fifo_dtr_buffer_set - Set transmit buffer pointer in the + * descriptor. + * @channelh: Channel handle. + * @dtrh: Descriptor handle. + * @frag_idx: Index of the data buffer in the caller's scatter-gather listá + * (of buffers). + * @dma_pointer: DMA address of the data buffer referenced by @frag_idx. + * @size: Size of the data buffer (in bytes). + * + * This API is part of the preparation of the transmit descriptor for posting + * (via xge_hal_fifo_dtr_post()). The related "preparation" APIs include + * xge_hal_fifo_dtr_mss_set() and xge_hal_fifo_dtr_cksum_set_bits(). + * All three APIs fill in the fields of the fifo descriptor, + * in accordance with the Xframe specification. + * + * See also: xge_hal_fifo_dtr_buffer_set_aligned(), + * xge_hal_check_alignment(). + * + * See also: xge_hal_fifo_dtr_reserve(), xge_hal_fifo_dtr_post(), + * xge_hal_fifo_dtr_mss_set(), xge_hal_fifo_dtr_cksum_set_bits() + * Prepare transmit descriptor for transmission (via + * xge_hal_fifo_dtr_post()). + * See also: xge_hal_fifo_dtr_vlan_set(). + * Note: Compare with xge_hal_fifo_dtr_buffer_set_aligned(). + * + * Usage: See ex_xmit{}. + */ +__HAL_STATIC_FIFO __HAL_INLINE_FIFO void +xge_hal_fifo_dtr_buffer_set(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, + int frag_idx, dma_addr_t dma_pointer, int size) +{ + xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh; + xge_hal_fifo_txdl_priv_t *txdl_priv; + xge_hal_fifo_txd_t *txdp; + + txdl_priv = __hal_fifo_txdl_priv(dtrh); + txdp = (xge_hal_fifo_txd_t *)dtrh + txdl_priv->frags; + + if (frag_idx != 0) { + txdp->control_1 = txdp->control_2 = 0; + } + + /* Note: + * it is the responsibility of upper layers and not HAL + * detect it and skip zero-size fragment + */ + xge_assert(size > 0); + xge_assert(frag_idx < txdl_priv->alloc_frags); + + txdp->buffer_pointer = (u64)dma_pointer; + txdp->control_1 |= XGE_HAL_TXD_BUFFER0_SIZE(size); + txdl_priv->bytes_sent += size; + fifo->channel.stats.total_buffers++; + txdl_priv->frags++; +} + +/** + * xge_hal_fifo_dtr_mss_set - Set MSS. + * @dtrh: Descriptor handle. + * @mss: MSS size for _this_ TCP connection. Passed by TCP stack down to the + * ULD, which in turn inserts the MSS into the @dtrh. + * + * This API is part of the preparation of the transmit descriptor for posting + * (via xge_hal_fifo_dtr_post()). The related "preparation" APIs include + * xge_hal_fifo_dtr_buffer_set(), xge_hal_fifo_dtr_buffer_set_aligned(), + * and xge_hal_fifo_dtr_cksum_set_bits(). + * All these APIs fill in the fields of the fifo descriptor, + * in accordance with the Xframe specification. + * + * See also: xge_hal_fifo_dtr_reserve(), + * xge_hal_fifo_dtr_post(), xge_hal_fifo_dtr_vlan_set(). + * Usage: See ex_xmit{}. + */ +__HAL_STATIC_FIFO __HAL_INLINE_FIFO void +xge_hal_fifo_dtr_mss_set(xge_hal_dtr_h dtrh, int mss) +{ + xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)dtrh; + + txdp->control_1 |= XGE_HAL_TXD_LSO_COF_CTRL(XGE_HAL_TXD_TCP_LSO); + txdp->control_1 |= XGE_HAL_TXD_TCP_LSO_MSS(mss); +} + +/** + * xge_hal_fifo_dtr_cksum_set_bits - Offload checksum. + * @dtrh: Descriptor handle. + * @cksum_bits: Specifies which checksums are to be offloaded: IPv4, + * and/or TCP and/or UDP. + * + * Ask Xframe to calculate IPv4 & transport checksums for _this_ transmit + * descriptor. + * This API is part of the preparation of the transmit descriptor for posting + * (via xge_hal_fifo_dtr_post()). The related "preparation" APIs include + * xge_hal_fifo_dtr_mss_set(), xge_hal_fifo_dtr_buffer_set_aligned(), + * and xge_hal_fifo_dtr_buffer_set(). + * All these APIs fill in the fields of the fifo descriptor, + * in accordance with the Xframe specification. + * + * See also: xge_hal_fifo_dtr_reserve(), + * xge_hal_fifo_dtr_post(), XGE_HAL_TXD_TX_CKO_IPV4_EN, + * XGE_HAL_TXD_TX_CKO_TCP_EN. + * Usage: See ex_xmit{}. + */ +__HAL_STATIC_FIFO __HAL_INLINE_FIFO void +xge_hal_fifo_dtr_cksum_set_bits(xge_hal_dtr_h dtrh, u64 cksum_bits) +{ + xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)dtrh; + + txdp->control_2 |= cksum_bits; +} + + +/** + * xge_hal_fifo_dtr_vlan_set - Set VLAN tag. + * @dtrh: Descriptor handle. + * @vlan_tag: 16bit VLAN tag. + * + * Insert VLAN tag into specified transmit descriptor. + * The actual insertion of the tag into outgoing frame is done by the hardware. + * See also: xge_hal_fifo_dtr_buffer_set(), xge_hal_fifo_dtr_mss_set(). + */ +__HAL_STATIC_FIFO __HAL_INLINE_FIFO void +xge_hal_fifo_dtr_vlan_set(xge_hal_dtr_h dtrh, u16 vlan_tag) +{ + xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)dtrh; + + txdp->control_2 |= XGE_HAL_TXD_VLAN_ENABLE; + txdp->control_2 |= XGE_HAL_TXD_VLAN_TAG(vlan_tag); +} + +/** + * xge_hal_fifo_is_next_dtr_completed - Checks if the next dtr is completed + * @channelh: Channel handle. + */ +__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e +xge_hal_fifo_is_next_dtr_completed(xge_hal_channel_h channelh) +{ + xge_hal_fifo_txd_t *txdp; + xge_hal_dtr_h dtrh; + + __hal_channel_dtr_try_complete(channelh, &dtrh); + txdp = (xge_hal_fifo_txd_t *)dtrh; + if (txdp == NULL) { + return XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS; + } + + /* check whether host owns it */ + if ( !(txdp->control_1 & XGE_HAL_TXD_LIST_OWN_XENA) ) { + xge_assert(txdp->host_control!=0); + return XGE_HAL_OK; + } + + /* no more completions */ + return XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS; +} diff --git a/sys/dev/nxge/xgehal/xgehal-fifo.c b/sys/dev/nxge/xgehal/xgehal-fifo.c new file mode 100644 index 0000000..de6befd --- /dev/null +++ b/sys/dev/nxge/xgehal/xgehal-fifo.c @@ -0,0 +1,568 @@ +/*- + * Copyright (c) 2002-2007 Neterion, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * FileName : xgehal-fifo.c + * + * Description: fifo object implementation + * + * Created: 10 May 2004 + */ + +#include +#include + +static xge_hal_status_e +__hal_fifo_mempool_item_alloc(xge_hal_mempool_h mempoolh, + void *memblock, + int memblock_index, + xge_hal_mempool_dma_t *dma_object, + void *item, + int index, + int is_last, + void *userdata) +{ + int memblock_item_idx; + xge_hal_fifo_txdl_priv_t *txdl_priv; + xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)item; + xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)userdata; + + xge_assert(item); + txdl_priv = (xge_hal_fifo_txdl_priv_t *) \ + __hal_mempool_item_priv((xge_hal_mempool_t *) mempoolh, + memblock_index, + item, + &memblock_item_idx); + xge_assert(txdl_priv); + + /* pre-format HAL's TxDL's private */ + txdl_priv->dma_offset = (char*)item - (char*)memblock; + txdl_priv->dma_addr = dma_object->addr + txdl_priv->dma_offset; + txdl_priv->dma_handle = dma_object->handle; + txdl_priv->memblock = memblock; + txdl_priv->first_txdp = (xge_hal_fifo_txd_t *)item; + txdl_priv->next_txdl_priv = NULL; + txdl_priv->dang_txdl = NULL; + txdl_priv->dang_frags = 0; + txdl_priv->alloc_frags = 0; + +#ifdef XGE_DEBUG_ASSERT + txdl_priv->dma_object = dma_object; +#endif + txdp->host_control = (u64)(ulong_t)txdl_priv; + +#ifdef XGE_HAL_ALIGN_XMIT + txdl_priv->align_vaddr = NULL; + txdl_priv->align_dma_addr = (dma_addr_t)0; + +#ifndef XGE_HAL_ALIGN_XMIT_ALLOC_RT + { + xge_hal_status_e status; + if (fifo->config->alignment_size) { + status =__hal_fifo_dtr_align_alloc_map(fifo, txdp); + if (status != XGE_HAL_OK) { + xge_debug_mm(XGE_ERR, + "align buffer[%d] %d bytes, status %d", + index, + fifo->align_size, + status); + return status; + } + } + } +#endif +#endif + + if (fifo->channel.dtr_init) { + fifo->channel.dtr_init(fifo, (xge_hal_dtr_h)txdp, index, + fifo->channel.userdata, XGE_HAL_CHANNEL_OC_NORMAL); + } + + return XGE_HAL_OK; +} + + +static xge_hal_status_e +__hal_fifo_mempool_item_free(xge_hal_mempool_h mempoolh, + void *memblock, + int memblock_index, + xge_hal_mempool_dma_t *dma_object, + void *item, + int index, + int is_last, + void *userdata) +{ + int memblock_item_idx; + xge_hal_fifo_txdl_priv_t *txdl_priv; +#ifdef XGE_HAL_ALIGN_XMIT + xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)userdata; +#endif + + xge_assert(item); + + txdl_priv = (xge_hal_fifo_txdl_priv_t *) \ + __hal_mempool_item_priv((xge_hal_mempool_t *) mempoolh, + memblock_index, + item, + &memblock_item_idx); + xge_assert(txdl_priv); + +#ifdef XGE_HAL_ALIGN_XMIT + if (fifo->config->alignment_size) { + if (txdl_priv->align_dma_addr != 0) { + xge_os_dma_unmap(fifo->channel.pdev, + txdl_priv->align_dma_handle, + txdl_priv->align_dma_addr, + fifo->align_size, + XGE_OS_DMA_DIR_TODEVICE); + + txdl_priv->align_dma_addr = 0; + } + + if (txdl_priv->align_vaddr != NULL) { + xge_os_dma_free(fifo->channel.pdev, + txdl_priv->align_vaddr, + fifo->align_size, + &txdl_priv->align_dma_acch, + &txdl_priv->align_dma_handle); + + txdl_priv->align_vaddr = NULL; + } + } +#endif + + return XGE_HAL_OK; +} + +xge_hal_status_e +__hal_fifo_open(xge_hal_channel_h channelh, xge_hal_channel_attr_t *attr) +{ + xge_hal_device_t *hldev; + xge_hal_status_e status; + xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh; + xge_hal_fifo_queue_t *queue; + int i, txdl_size, max_arr_index, mid_point; + xge_hal_dtr_h dtrh; + + hldev = (xge_hal_device_t *)fifo->channel.devh; + fifo->config = &hldev->config.fifo; + queue = &fifo->config->queue[attr->post_qid]; + +#if defined(XGE_HAL_TX_MULTI_RESERVE) + xge_os_spin_lock_init(&fifo->channel.reserve_lock, hldev->pdev); +#elif defined(XGE_HAL_TX_MULTI_RESERVE_IRQ) + xge_os_spin_lock_init_irq(&fifo->channel.reserve_lock, hldev->irqh); +#endif +#if defined(XGE_HAL_TX_MULTI_POST) + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA) { + fifo->post_lock_ptr = &hldev->xena_post_lock; + } else { + xge_os_spin_lock_init(&fifo->channel.post_lock, hldev->pdev); + fifo->post_lock_ptr = &fifo->channel.post_lock; + } +#elif defined(XGE_HAL_TX_MULTI_POST_IRQ) + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA) { + fifo->post_lock_ptr = &hldev->xena_post_lock; + } else { + xge_os_spin_lock_init_irq(&fifo->channel.post_lock, + hldev->irqh); + fifo->post_lock_ptr = &fifo->channel.post_lock; + } +#endif + + fifo->align_size = + fifo->config->alignment_size * fifo->config->max_aligned_frags; + + /* Initializing the BAR1 address as the start of + * the FIFO queue pointer and as a location of FIFO control + * word. */ + fifo->hw_pair = + (xge_hal_fifo_hw_pair_t *) (void *)(hldev->bar1 + + (attr->post_qid * XGE_HAL_FIFO_HW_PAIR_OFFSET)); + + /* apply "interrupts per txdl" attribute */ + fifo->interrupt_type = XGE_HAL_TXD_INT_TYPE_UTILZ; + if (queue->intr) { + fifo->interrupt_type = XGE_HAL_TXD_INT_TYPE_PER_LIST; + } + fifo->no_snoop_bits = + (int)(XGE_HAL_TX_FIFO_NO_SNOOP(queue->no_snoop_bits)); + + /* + * FIFO memory management strategy: + * + * TxDL splitted into three independent parts: + * - set of TxD's + * - TxD HAL private part + * - upper layer private part + * + * Adaptative memory allocation used. i.e. Memory allocated on + * demand with the size which will fit into one memory block. + * One memory block may contain more than one TxDL. In simple case + * memory block size can be equal to CPU page size. On more + * sophisticated OS's memory block can be contigious across + * several pages. + * + * During "reserve" operations more memory can be allocated on demand + * for example due to FIFO full condition. + * + * Pool of memory memblocks never shrinks except __hal_fifo_close + * routine which will essentially stop channel and free the resources. + */ + + /* TxDL common private size == TxDL private + ULD private */ + fifo->priv_size = sizeof(xge_hal_fifo_txdl_priv_t) + + attr->per_dtr_space; + fifo->priv_size = ((fifo->priv_size + __xge_os_cacheline_size -1) / + __xge_os_cacheline_size) * + __xge_os_cacheline_size; + + /* recompute txdl size to be cacheline aligned */ + fifo->txdl_size = fifo->config->max_frags * sizeof(xge_hal_fifo_txd_t); + txdl_size = ((fifo->txdl_size + __xge_os_cacheline_size - 1) / + __xge_os_cacheline_size) * __xge_os_cacheline_size; + + if (fifo->txdl_size != txdl_size) + xge_debug_fifo(XGE_ERR, "cacheline > 128 ( ?? ): %d, %d, %d, %d", + fifo->config->max_frags, fifo->txdl_size, txdl_size, + __xge_os_cacheline_size); + + fifo->txdl_size = txdl_size; + + /* since dtr_init() callback will be called from item_alloc(), + * the same way channels userdata might be used prior to + * channel_initialize() */ + fifo->channel.dtr_init = attr->dtr_init; + fifo->channel.userdata = attr->userdata; + fifo->txdl_per_memblock = fifo->config->memblock_size / + fifo->txdl_size; + + fifo->mempool = __hal_mempool_create(hldev->pdev, + fifo->config->memblock_size, + fifo->txdl_size, + fifo->priv_size, + queue->initial, + queue->max, + __hal_fifo_mempool_item_alloc, + __hal_fifo_mempool_item_free, + fifo); + if (fifo->mempool == NULL) { + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + + status = __hal_channel_initialize(channelh, attr, + (void **) __hal_mempool_items_arr(fifo->mempool), + queue->initial, queue->max, + fifo->config->reserve_threshold); + if (status != XGE_HAL_OK) { + __hal_fifo_close(channelh); + return status; + } + xge_debug_fifo(XGE_TRACE, + "DTR reserve_length:%d reserve_top:%d\n" + "max_frags:%d reserve_threshold:%d\n" + "memblock_size:%d alignment_size:%d max_aligned_frags:%d", + fifo->channel.reserve_length, fifo->channel.reserve_top, + fifo->config->max_frags, fifo->config->reserve_threshold, + fifo->config->memblock_size, fifo->config->alignment_size, + fifo->config->max_aligned_frags); + +#ifdef XGE_DEBUG_ASSERT + for ( i = 0; i < fifo->channel.reserve_length; i++) { + xge_debug_fifo(XGE_TRACE, "DTR before reversing index:%d" + " handle:%p", i, fifo->channel.reserve_arr[i]); + } +#endif + + xge_assert(fifo->channel.reserve_length); + /* reverse the FIFO dtr array */ + max_arr_index = fifo->channel.reserve_length - 1; + max_arr_index -=fifo->channel.reserve_top; + xge_assert(max_arr_index); + mid_point = (fifo->channel.reserve_length - fifo->channel.reserve_top)/2; + for (i = 0; i < mid_point; i++) { + dtrh = fifo->channel.reserve_arr[i]; + fifo->channel.reserve_arr[i] = + fifo->channel.reserve_arr[max_arr_index - i]; + fifo->channel.reserve_arr[max_arr_index - i] = dtrh; + } + +#ifdef XGE_DEBUG_ASSERT + for ( i = 0; i < fifo->channel.reserve_length; i++) { + xge_debug_fifo(XGE_TRACE, "DTR after reversing index:%d" + " handle:%p", i, fifo->channel.reserve_arr[i]); + } +#endif + + return XGE_HAL_OK; +} + +void +__hal_fifo_close(xge_hal_channel_h channelh) +{ + xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh; + xge_hal_device_t *hldev = (xge_hal_device_t *)fifo->channel.devh; + + if (fifo->mempool) { + __hal_mempool_destroy(fifo->mempool); + } + + __hal_channel_terminate(channelh); + +#if defined(XGE_HAL_TX_MULTI_RESERVE) + xge_os_spin_lock_destroy(&fifo->channel.reserve_lock, hldev->pdev); +#elif defined(XGE_HAL_TX_MULTI_RESERVE_IRQ) + xge_os_spin_lock_destroy_irq(&fifo->channel.reserve_lock, hldev->pdev); +#endif + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) { +#if defined(XGE_HAL_TX_MULTI_POST) + xge_os_spin_lock_destroy(&fifo->channel.post_lock, hldev->pdev); +#elif defined(XGE_HAL_TX_MULTI_POST_IRQ) + xge_os_spin_lock_destroy_irq(&fifo->channel.post_lock, + hldev->pdev); +#endif + } +} + +void +__hal_fifo_hw_initialize(xge_hal_device_h devh) +{ + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64* tx_fifo_partitions[4]; + u64* tx_fifo_wrr[5]; + u64 tx_fifo_wrr_value[5]; + u64 val64, part0; + int i; + + /* Tx DMA Initialization */ + + tx_fifo_partitions[0] = &bar0->tx_fifo_partition_0; + tx_fifo_partitions[1] = &bar0->tx_fifo_partition_1; + tx_fifo_partitions[2] = &bar0->tx_fifo_partition_2; + tx_fifo_partitions[3] = &bar0->tx_fifo_partition_3; + + tx_fifo_wrr[0] = &bar0->tx_w_round_robin_0; + tx_fifo_wrr[1] = &bar0->tx_w_round_robin_1; + tx_fifo_wrr[2] = &bar0->tx_w_round_robin_2; + tx_fifo_wrr[3] = &bar0->tx_w_round_robin_3; + tx_fifo_wrr[4] = &bar0->tx_w_round_robin_4; + + tx_fifo_wrr_value[0] = XGE_HAL_FIFO_WRR_0; + tx_fifo_wrr_value[1] = XGE_HAL_FIFO_WRR_1; + tx_fifo_wrr_value[2] = XGE_HAL_FIFO_WRR_2; + tx_fifo_wrr_value[3] = XGE_HAL_FIFO_WRR_3; + tx_fifo_wrr_value[4] = XGE_HAL_FIFO_WRR_4; + + /* Note: WRR calendar must be configured before the transmit + * FIFOs are enabled! page 6-77 user guide */ + + if (!hldev->config.rts_qos_en) { + /* all zeroes for Round-Robin */ + for (i = 0; i < XGE_HAL_FIFO_MAX_WRR; i++) { + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, 0, + tx_fifo_wrr[i]); + } + + /* reset all of them but '0' */ + for (i=1; i < XGE_HAL_FIFO_MAX_PARTITION; i++) { + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, 0ULL, + tx_fifo_partitions[i]); + } + } else { /* Change the default settings */ + + for (i = 0; i < XGE_HAL_FIFO_MAX_WRR; i++) { + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + tx_fifo_wrr_value[i], tx_fifo_wrr[i]); + } + } + + /* configure only configured FIFOs */ + val64 = 0; part0 = 0; + for (i = 0; i < XGE_HAL_MAX_FIFO_NUM; i++) { + int reg_half = i % 2; + int reg_num = i / 2; + + if (hldev->config.fifo.queue[i].configured) { + int priority = hldev->config.fifo.queue[i].priority; + val64 |= + vBIT((hldev->config.fifo.queue[i].max-1), + (((reg_half) * 32) + 19), + 13) | vBIT(priority, (((reg_half)*32) + 5), 3); + } + + /* NOTE: do write operation for each second u64 half + * or force for first one if configured number + * is even */ + if (reg_half) { + if (reg_num == 0) { + /* skip partition '0', must write it once at + * the end */ + part0 = val64; + } else { + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, tx_fifo_partitions[reg_num]); + xge_debug_fifo(XGE_TRACE, + "fifo partition_%d at: " + "0x"XGE_OS_LLXFMT" is: 0x"XGE_OS_LLXFMT, + reg_num, (unsigned long long)(ulong_t) + tx_fifo_partitions[reg_num], + (unsigned long long)val64); + } + val64 = 0; + } + } + + part0 |= BIT(0); /* to enable the FIFO partition. */ + __hal_pio_mem_write32_lower(hldev->pdev, hldev->regh0, (u32)part0, + tx_fifo_partitions[0]); + xge_os_wmb(); + __hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0, (u32)(part0>>32), + tx_fifo_partitions[0]); + xge_debug_fifo(XGE_TRACE, "fifo partition_0 at: " + "0x"XGE_OS_LLXFMT" is: 0x"XGE_OS_LLXFMT, + (unsigned long long)(ulong_t) + tx_fifo_partitions[0], + (unsigned long long) part0); + + /* + * Initialization of Tx_PA_CONFIG register to ignore packet + * integrity checking. + */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->tx_pa_cfg); + val64 |= XGE_HAL_TX_PA_CFG_IGNORE_FRM_ERR | + XGE_HAL_TX_PA_CFG_IGNORE_SNAP_OUI | + XGE_HAL_TX_PA_CFG_IGNORE_LLC_CTRL | + XGE_HAL_TX_PA_CFG_IGNORE_L2_ERR; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->tx_pa_cfg); + + /* + * Assign MSI-X vectors + */ + for (i = 0; i < XGE_HAL_MAX_FIFO_NUM; i++) { + xge_list_t *item; + xge_hal_channel_t *channel = NULL; + + if (!hldev->config.fifo.queue[i].configured || + !hldev->config.fifo.queue[i].intr_vector || + !hldev->config.intr_mode != XGE_HAL_INTR_MODE_MSIX) + continue; + + /* find channel */ + xge_list_for_each(item, &hldev->free_channels) { + xge_hal_channel_t *tmp; + tmp = xge_container_of(item, xge_hal_channel_t, + item); + if (tmp->type == XGE_HAL_CHANNEL_TYPE_FIFO && + tmp->post_qid == i) { + channel = tmp; + break; + } + } + + if (channel) { + xge_hal_channel_msix_set(channel, + hldev->config.fifo.queue[i].intr_vector); + } + } + + xge_debug_fifo(XGE_TRACE, "%s", "fifo channels initialized"); +} + +#ifdef XGE_HAL_ALIGN_XMIT +void +__hal_fifo_dtr_align_free_unmap(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh) +{ + xge_hal_fifo_txdl_priv_t *txdl_priv; + xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)dtrh; + xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh; + + txdl_priv = __hal_fifo_txdl_priv(txdp); + + if (txdl_priv->align_dma_addr != 0) { + xge_os_dma_unmap(fifo->channel.pdev, + txdl_priv->align_dma_handle, + txdl_priv->align_dma_addr, + fifo->align_size, + XGE_OS_DMA_DIR_TODEVICE); + + txdl_priv->align_dma_addr = 0; + } + + if (txdl_priv->align_vaddr != NULL) { + xge_os_dma_free(fifo->channel.pdev, + txdl_priv->align_vaddr, + fifo->align_size, + &txdl_priv->align_dma_acch, + &txdl_priv->align_dma_handle); + + + txdl_priv->align_vaddr = NULL; + } + } + +xge_hal_status_e +__hal_fifo_dtr_align_alloc_map(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh) +{ + xge_hal_fifo_txdl_priv_t *txdl_priv; + xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)dtrh; + xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh; + + xge_assert(txdp); + + txdl_priv = __hal_fifo_txdl_priv(txdp); + + /* allocate alignment DMA-buffer */ + txdl_priv->align_vaddr = xge_os_dma_malloc(fifo->channel.pdev, + fifo->align_size, + XGE_OS_DMA_CACHELINE_ALIGNED | + XGE_OS_DMA_STREAMING, + &txdl_priv->align_dma_handle, + &txdl_priv->align_dma_acch); + if (txdl_priv->align_vaddr == NULL) { + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + + /* map it */ + txdl_priv->align_dma_addr = xge_os_dma_map(fifo->channel.pdev, + txdl_priv->align_dma_handle, txdl_priv->align_vaddr, + fifo->align_size, + XGE_OS_DMA_DIR_TODEVICE, XGE_OS_DMA_STREAMING); + + if (txdl_priv->align_dma_addr == XGE_OS_INVALID_DMA_ADDR) { + __hal_fifo_dtr_align_free_unmap(channelh, dtrh); + return XGE_HAL_ERR_OUT_OF_MAPPING; + } + + return XGE_HAL_OK; +} +#endif + + diff --git a/sys/dev/nxge/xgehal/xgehal-mgmt.c b/sys/dev/nxge/xgehal/xgehal-mgmt.c new file mode 100644 index 0000000..3e30e25 --- /dev/null +++ b/sys/dev/nxge/xgehal/xgehal-mgmt.c @@ -0,0 +1,1772 @@ +/*- + * Copyright (c) 2002-2007 Neterion, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * FileName : xgehal-mgmt.c + * + * Description: Xframe-family management facility implementation + * + * Created: 1 September 2004 + */ + +#include +#include +#include + +/** + * xge_hal_mgmt_about - Retrieve about info. + * @devh: HAL device handle. + * @about_info: Filled in by HAL. See xge_hal_mgmt_about_info_t{}. + * @size: Size of the @about_info buffer. HAL will return error if the + * size is smaller than sizeof(xge_hal_mgmt_about_info_t). + * + * Retrieve information such as PCI device and vendor IDs, board + * revision number, HAL version number, etc. + * + * Returns: XGE_HAL_OK - success; + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. + * XGE_HAL_FAIL - Failed to retrieve the information. + * + * See also: xge_hal_mgmt_about_info_t{}. + */ +xge_hal_status_e +xge_hal_mgmt_about(xge_hal_device_h devh, xge_hal_mgmt_about_info_t *about_info, + int size) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + + if ((hldev == NULL) || (hldev->magic != XGE_HAL_MAGIC)) { + return XGE_HAL_ERR_INVALID_DEVICE; + } + + if (size != sizeof(xge_hal_mgmt_about_info_t)) { + return XGE_HAL_ERR_VERSION_CONFLICT; + } + + xge_os_pci_read16(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, vendor_id), + &about_info->vendor); + + xge_os_pci_read16(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, device_id), + &about_info->device); + + xge_os_pci_read16(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, subsystem_vendor_id), + &about_info->subsys_vendor); + + xge_os_pci_read16(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, subsystem_id), + &about_info->subsys_device); + + xge_os_pci_read8(hldev->pdev, hldev->cfgh, + xge_offsetof(xge_hal_pci_config_le_t, revision), + &about_info->board_rev); + + xge_os_strcpy(about_info->vendor_name, XGE_DRIVER_VENDOR); + xge_os_strcpy(about_info->chip_name, XGE_CHIP_FAMILY); + xge_os_strcpy(about_info->media, XGE_SUPPORTED_MEDIA_0); + + xge_os_strcpy(about_info->hal_major, XGE_HAL_VERSION_MAJOR); + xge_os_strcpy(about_info->hal_minor, XGE_HAL_VERSION_MINOR); + xge_os_strcpy(about_info->hal_fix, XGE_HAL_VERSION_FIX); + xge_os_strcpy(about_info->hal_build, XGE_HAL_VERSION_BUILD); + + xge_os_strcpy(about_info->ll_major, XGELL_VERSION_MAJOR); + xge_os_strcpy(about_info->ll_minor, XGELL_VERSION_MINOR); + xge_os_strcpy(about_info->ll_fix, XGELL_VERSION_FIX); + xge_os_strcpy(about_info->ll_build, XGELL_VERSION_BUILD); + + about_info->transponder_temperature = + xge_hal_read_xfp_current_temp(devh); + + return XGE_HAL_OK; +} + +/** + * xge_hal_mgmt_reg_read - Read Xframe register. + * @devh: HAL device handle. + * @bar_id: 0 - for BAR0, 1- for BAR1. + * @offset: Register offset in the Base Address Register (BAR) space. + * @value: Register value. Returned by HAL. + * Read Xframe register. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not + * valid. + * XGE_HAL_ERR_INVALID_BAR_ID - BAR id is not valid. + * + * See also: xge_hal_aux_bar0_read(), xge_hal_aux_bar1_read(). + */ +xge_hal_status_e +xge_hal_mgmt_reg_read(xge_hal_device_h devh, int bar_id, unsigned int offset, + u64 *value) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + + if ((hldev == NULL) || (hldev->magic != XGE_HAL_MAGIC)) { + return XGE_HAL_ERR_INVALID_DEVICE; + } + + if (bar_id == 0) { + if (offset > sizeof(xge_hal_pci_bar0_t)-8) { + return XGE_HAL_ERR_INVALID_OFFSET; + } + *value = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + (void *)(hldev->bar0 + offset)); + } else if (bar_id == 1 && + (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA || + xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC)) { + int i; + for (i=0; ipdev, hldev->regh1, + (void *)(hldev->bar1 + offset)); + } else if (bar_id == 1) { + /* FIXME: check TITAN BAR1 offsets */ + } else { + return XGE_HAL_ERR_INVALID_BAR_ID; + } + + return XGE_HAL_OK; +} + +/** + * xge_hal_mgmt_reg_write - Write Xframe register. + * @devh: HAL device handle. + * @bar_id: 0 - for BAR0, 1- for BAR1. + * @offset: Register offset in the Base Address Register (BAR) space. + * @value: Register value. + * + * Write Xframe register. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not + * valid. + * XGE_HAL_ERR_INVALID_BAR_ID - BAR id is not valid. + * + * See also: xge_hal_aux_bar0_write(). + */ +xge_hal_status_e +xge_hal_mgmt_reg_write(xge_hal_device_h devh, int bar_id, unsigned int offset, + u64 value) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + + if ((hldev == NULL) || (hldev->magic != XGE_HAL_MAGIC)) { + return XGE_HAL_ERR_INVALID_DEVICE; + } + + if (bar_id == 0) { + if (offset > sizeof(xge_hal_pci_bar0_t)-8) { + return XGE_HAL_ERR_INVALID_OFFSET; + } + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, value, + (void *)(hldev->bar0 + offset)); + } else if (bar_id == 1 && + (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA || + xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC)) { + int i; + for (i=0; ipdev, hldev->regh1, value, + (void *)(hldev->bar1 + offset)); + } else if (bar_id == 1) { + /* FIXME: check TITAN BAR1 offsets */ + } else { + return XGE_HAL_ERR_INVALID_BAR_ID; + } + + return XGE_HAL_OK; +} + +/** + * xge_hal_mgmt_hw_stats - Get Xframe hardware statistics. + * @devh: HAL device handle. + * @hw_stats: Hardware statistics. Returned by HAL. + * See xge_hal_stats_hw_info_t{}. + * @size: Size of the @hw_stats buffer. HAL will return an error + * if the size is smaller than sizeof(xge_hal_stats_hw_info_t). + * Get Xframe hardware statistics. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. + * + * See also: xge_hal_mgmt_sw_stats(). + */ +xge_hal_status_e +xge_hal_mgmt_hw_stats(xge_hal_device_h devh, xge_hal_mgmt_hw_stats_t *hw_stats, + int size) +{ + xge_hal_status_e status; + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + xge_hal_stats_hw_info_t *hw_info; + + xge_assert(xge_hal_device_check_id(hldev) != XGE_HAL_CARD_TITAN); + + if ((hldev == NULL) || (hldev->magic != XGE_HAL_MAGIC)) { + return XGE_HAL_ERR_INVALID_DEVICE; + } + + if (size != sizeof(xge_hal_stats_hw_info_t)) { + return XGE_HAL_ERR_VERSION_CONFLICT; + } + + if ((status = xge_hal_stats_hw (devh, &hw_info)) != XGE_HAL_OK) { + return status; + } + + xge_os_memcpy(hw_stats, hw_info, sizeof(xge_hal_stats_hw_info_t)); + + return XGE_HAL_OK; +} + +/** + * xge_hal_mgmt_hw_stats_off - TBD. + * @devh: HAL device handle. + * @off: TBD + * @size: TBD + * @out: TBD + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. + * + * See also: xge_hal_mgmt_sw_stats(). + */ +xge_hal_status_e +xge_hal_mgmt_hw_stats_off(xge_hal_device_h devh, int off, int size, char *out) +{ + xge_hal_status_e status; + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + xge_hal_stats_hw_info_t *hw_info; + + xge_assert(xge_hal_device_check_id(hldev) != XGE_HAL_CARD_TITAN); + + if ((hldev == NULL) || (hldev->magic != XGE_HAL_MAGIC)) { + return XGE_HAL_ERR_INVALID_DEVICE; + } + + if (off > sizeof(xge_hal_stats_hw_info_t)-4 || + size > 8) { + return XGE_HAL_ERR_INVALID_OFFSET; + } + + if ((status = xge_hal_stats_hw (devh, &hw_info)) != XGE_HAL_OK) { + return status; + } + + xge_os_memcpy(out, (char*)hw_info + off, size); + + return XGE_HAL_OK; +} + +/** + * xge_hal_mgmt_pcim_stats - Get Titan hardware statistics. + * @devh: HAL device handle. + * @pcim_stats: PCIM statistics. Returned by HAL. + * See xge_hal_stats_hw_info_t{}. + * @size: Size of the @hw_stats buffer. HAL will return an error + * if the size is smaller than sizeof(xge_hal_stats_hw_info_t). + * Get Xframe hardware statistics. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. + * + * See also: xge_hal_mgmt_sw_stats(). + */ +xge_hal_status_e +xge_hal_mgmt_pcim_stats(xge_hal_device_h devh, + xge_hal_mgmt_pcim_stats_t *pcim_stats, int size) +{ + xge_hal_status_e status; + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + xge_hal_stats_pcim_info_t *pcim_info; + + xge_assert(xge_hal_device_check_id(hldev) == XGE_HAL_CARD_TITAN); + + if ((hldev == NULL) || (hldev->magic != XGE_HAL_MAGIC)) { + return XGE_HAL_ERR_INVALID_DEVICE; + } + + if (size != sizeof(xge_hal_stats_pcim_info_t)) { + return XGE_HAL_ERR_VERSION_CONFLICT; + } + + if ((status = xge_hal_stats_pcim (devh, &pcim_info)) != XGE_HAL_OK) { + return status; + } + + xge_os_memcpy(pcim_stats, pcim_info, + sizeof(xge_hal_stats_pcim_info_t)); + + return XGE_HAL_OK; +} + +/** + * xge_hal_mgmt_pcim_stats_off - TBD. + * @devh: HAL device handle. + * @off: TBD + * @size: TBD + * @out: TBD + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. + * + * See also: xge_hal_mgmt_sw_stats(). + */ +xge_hal_status_e +xge_hal_mgmt_pcim_stats_off(xge_hal_device_h devh, int off, int size, + char *out) +{ + xge_hal_status_e status; + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + xge_hal_stats_pcim_info_t *pcim_info; + + xge_assert(xge_hal_device_check_id(hldev) == XGE_HAL_CARD_TITAN); + + if ((hldev == NULL) || (hldev->magic != XGE_HAL_MAGIC)) { + return XGE_HAL_ERR_INVALID_DEVICE; + } + + if (off > sizeof(xge_hal_stats_pcim_info_t)-8 || + size > 8) { + return XGE_HAL_ERR_INVALID_OFFSET; + } + + if ((status = xge_hal_stats_pcim (devh, &pcim_info)) != XGE_HAL_OK) { + return status; + } + + xge_os_memcpy(out, (char*)pcim_info + off, size); + + return XGE_HAL_OK; +} + +/** + * xge_hal_mgmt_sw_stats - Get per-device software statistics. + * @devh: HAL device handle. + * @sw_stats: Hardware statistics. Returned by HAL. + * See xge_hal_stats_sw_err_t{}. + * @size: Size of the @sw_stats buffer. HAL will return an error + * if the size is smaller than sizeof(xge_hal_stats_sw_err_t). + * Get device software statistics, including ECC and Parity error + * counters, etc. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. + * + * See also: xge_hal_stats_sw_err_t{}, xge_hal_mgmt_hw_stats(). + */ +xge_hal_status_e +xge_hal_mgmt_sw_stats(xge_hal_device_h devh, xge_hal_mgmt_sw_stats_t *sw_stats, + int size) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + + if ((hldev == NULL) || (hldev->magic != XGE_HAL_MAGIC)) { + return XGE_HAL_ERR_INVALID_DEVICE; + } + + if (size != sizeof(xge_hal_stats_sw_err_t)) { + return XGE_HAL_ERR_VERSION_CONFLICT; + } + + if (!hldev->stats.is_initialized || + !hldev->stats.is_enabled) { + return XGE_HAL_INF_STATS_IS_NOT_READY; + } + + /* Updating xpak stats value */ + __hal_updt_stats_xpak(hldev); + + xge_os_memcpy(sw_stats, &hldev->stats.sw_dev_err_stats, + sizeof(xge_hal_stats_sw_err_t)); + + return XGE_HAL_OK; +} + +/** + * xge_hal_mgmt_device_stats - Get HAL device statistics. + * @devh: HAL device handle. + * @device_stats: HAL device "soft" statistics. Maintained by HAL itself. + * (as opposed to xge_hal_mgmt_hw_stats() - those are + * maintained by the Xframe hardware). + * Returned by HAL. + * See xge_hal_stats_device_info_t{}. + * @size: Size of the @device_stats buffer. HAL will return an error + * if the size is smaller than sizeof(xge_hal_stats_device_info_t). + * + * Get HAL (layer) statistic counters. + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. + * XGE_HAL_INF_STATS_IS_NOT_READY - Statistics information is not + * currently available. + * + */ +xge_hal_status_e +xge_hal_mgmt_device_stats(xge_hal_device_h devh, + xge_hal_mgmt_device_stats_t *device_stats, int size) +{ + xge_hal_status_e status; + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + xge_hal_stats_device_info_t *device_info; + + if ((hldev == NULL) || (hldev->magic != XGE_HAL_MAGIC)) { + return XGE_HAL_ERR_INVALID_DEVICE; + } + + if (size != sizeof(xge_hal_stats_device_info_t)) { + return XGE_HAL_ERR_VERSION_CONFLICT; + } + + if ((status = xge_hal_stats_device (devh, &device_info)) != + XGE_HAL_OK) { + return status; + } + + xge_os_memcpy(device_stats, device_info, + sizeof(xge_hal_stats_device_info_t)); + + return XGE_HAL_OK; +} + +/* + * __hal_update_ring_bump - Update the ring bump counter for the + * particular channel. + * @hldev: HAL device handle. + * @queue: the queue who's data is to be collected. + * @chinfo: pointer to the statistics structure of the given channel. + * Usage: See xge_hal_aux_stats_hal_read{} + */ + +static void +__hal_update_ring_bump(xge_hal_device_t *hldev, int queue, + xge_hal_stats_channel_info_t *chinfo) +{ + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)hldev->bar0; + u64 rbc = 0; + int reg = (queue / 4); + void * addr; + + addr = (reg == 1)? (&bar0->ring_bump_counter2) : + (&bar0->ring_bump_counter1); + rbc = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, addr); + chinfo->ring_bump_cnt = XGE_HAL_RING_BUMP_CNT(queue, rbc); +} + +/** + * xge_hal_mgmt_channel_stats - Get HAL channel statistics. + * @channelh: HAL channel handle. + * @channel_stats: HAL channel statistics. Maintained by HAL itself + * (as opposed to xge_hal_mgmt_hw_stats() - those are + * maintained by the Xframe hardware). + * Returned by HAL. + * See xge_hal_stats_channel_info_t{}. + * @size: Size of the @channel_stats buffer. HAL will return an error + * if the size is smaller than sizeof(xge_hal_mgmt_channel_stats_t). + * + * Get HAL per-channel statistic counters. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. + * XGE_HAL_INF_STATS_IS_NOT_READY - Statistics information is not + * currently available. + * + */ +xge_hal_status_e +xge_hal_mgmt_channel_stats(xge_hal_channel_h channelh, + xge_hal_mgmt_channel_stats_t *channel_stats, int size) +{ + xge_hal_status_e status; + xge_hal_stats_channel_info_t *channel_info; + xge_hal_channel_t *channel = (xge_hal_channel_t* ) channelh; + + if (size != sizeof(xge_hal_stats_channel_info_t)) { + return XGE_HAL_ERR_VERSION_CONFLICT; + } + + if ((status = xge_hal_stats_channel (channelh, &channel_info)) != + XGE_HAL_OK) { + return status; + } + + if (xge_hal_device_check_id(channel->devh) == XGE_HAL_CARD_HERC) { + __hal_update_ring_bump( (xge_hal_device_t *) channel->devh, channel->post_qid, channel_info); + } + + xge_os_memcpy(channel_stats, channel_info, + sizeof(xge_hal_stats_channel_info_t)); + + return XGE_HAL_OK; +} + +/** + * xge_hal_mgmt_pcireg_read - Read PCI configuration at a specified + * offset. + * @devh: HAL device handle. + * @offset: Offset in the 256 byte PCI configuration space. + * @value_bits: 8, 16, or 32 (bits) to read. + * @value: Value returned by HAL. + * + * Read PCI configuration, given device and offset in the PCI space. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not + * valid. + * XGE_HAL_ERR_INVALID_VALUE_BIT_SIZE - Invalid bits size. Valid + * values(8/16/32). + * + */ +xge_hal_status_e +xge_hal_mgmt_pcireg_read(xge_hal_device_h devh, unsigned int offset, + int value_bits, u32 *value) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + + if ((hldev == NULL) || (hldev->magic != XGE_HAL_MAGIC)) { + return XGE_HAL_ERR_INVALID_DEVICE; + } + + if (offset > sizeof(xge_hal_pci_config_t)-value_bits/8) { + return XGE_HAL_ERR_INVALID_OFFSET; + } + + if (value_bits == 8) { + xge_os_pci_read8(hldev->pdev, hldev->cfgh, offset, (u8*)value); + } else if (value_bits == 16) { + xge_os_pci_read16(hldev->pdev, hldev->cfgh, offset, + (u16*)value); + } else if (value_bits == 32) { + xge_os_pci_read32(hldev->pdev, hldev->cfgh, offset, value); + } else { + return XGE_HAL_ERR_INVALID_VALUE_BIT_SIZE; + } + + return XGE_HAL_OK; +} + +/** + * xge_hal_mgmt_device_config - Retrieve device configuration. + * @devh: HAL device handle. + * @dev_config: Device configuration, see xge_hal_device_config_t{}. + * @size: Size of the @dev_config buffer. HAL will return an error + * if the size is smaller than sizeof(xge_hal_mgmt_device_config_t). + * + * Get device configuration. Permits to retrieve at run-time configuration + * values that were used to initialize and configure the device. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. + * + * See also: xge_hal_device_config_t{}, xge_hal_mgmt_driver_config(). + */ +xge_hal_status_e +xge_hal_mgmt_device_config(xge_hal_device_h devh, + xge_hal_mgmt_device_config_t *dev_config, int size) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + + if ((hldev == NULL) || (hldev->magic != XGE_HAL_MAGIC)) { + return XGE_HAL_ERR_INVALID_DEVICE; + } + + if (size != sizeof(xge_hal_mgmt_device_config_t)) { + return XGE_HAL_ERR_VERSION_CONFLICT; + } + + xge_os_memcpy(dev_config, &hldev->config, + sizeof(xge_hal_device_config_t)); + + return XGE_HAL_OK; +} + +/** + * xge_hal_mgmt_driver_config - Retrieve driver configuration. + * @drv_config: Device configuration, see xge_hal_driver_config_t{}. + * @size: Size of the @dev_config buffer. HAL will return an error + * if the size is smaller than sizeof(xge_hal_mgmt_driver_config_t). + * + * Get driver configuration. Permits to retrieve at run-time configuration + * values that were used to configure the device at load-time. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_DRIVER_NOT_INITIALIZED - HAL is not initialized. + * XGE_HAL_ERR_VERSION_CONFLICT - Version is not maching. + * + * See also: xge_hal_driver_config_t{}, xge_hal_mgmt_device_config(). + */ +xge_hal_status_e +xge_hal_mgmt_driver_config(xge_hal_mgmt_driver_config_t *drv_config, int size) +{ + + if (g_xge_hal_driver == NULL) { + return XGE_HAL_ERR_DRIVER_NOT_INITIALIZED; + } + + if (size != sizeof(xge_hal_mgmt_driver_config_t)) { + return XGE_HAL_ERR_VERSION_CONFLICT; + } + + xge_os_memcpy(drv_config, &g_xge_hal_driver->config, + sizeof(xge_hal_mgmt_driver_config_t)); + + return XGE_HAL_OK; +} + +/** + * xge_hal_mgmt_pci_config - Retrieve PCI configuration. + * @devh: HAL device handle. + * @pci_config: 256 byte long buffer for PCI configuration space. + * @size: Size of the @ buffer. HAL will return an error + * if the size is smaller than sizeof(xge_hal_mgmt_pci_config_t). + * + * Get PCI configuration. Permits to retrieve at run-time configuration + * values that were used to configure the device at load-time. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. + * + */ +xge_hal_status_e +xge_hal_mgmt_pci_config(xge_hal_device_h devh, + xge_hal_mgmt_pci_config_t *pci_config, int size) +{ + int i; + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + + if ((hldev == NULL) || (hldev->magic != XGE_HAL_MAGIC)) { + return XGE_HAL_ERR_INVALID_DEVICE; + } + + if (size != sizeof(xge_hal_mgmt_pci_config_t)) { + return XGE_HAL_ERR_VERSION_CONFLICT; + } + + /* refresh PCI config space */ + for (i = 0; i < 0x68/4+1; i++) { + xge_os_pci_read32(hldev->pdev, hldev->cfgh, i*4, + (u32*)&hldev->pci_config_space + i); + } + + xge_os_memcpy(pci_config, &hldev->pci_config_space, + sizeof(xge_hal_mgmt_pci_config_t)); + + return XGE_HAL_OK; +} + +#ifdef XGE_TRACE_INTO_CIRCULAR_ARR +/** + * xge_hal_mgmt_trace_read - Read trace buffer contents. + * @buffer: Buffer to store the trace buffer contents. + * @buf_size: Size of the buffer. + * @offset: Offset in the internal trace buffer to read data. + * @read_length: Size of the valid data in the buffer. + * + * Read HAL trace buffer contents starting from the offset + * upto the size of the buffer or till EOF is reached. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_EOF_TRACE_BUF - No more data in the trace buffer. + * + */ +xge_hal_status_e +xge_hal_mgmt_trace_read (char *buffer, + unsigned buf_size, + unsigned *offset, + unsigned *read_length) +{ + int data_offset; + int start_offset; + + if ((g_xge_os_tracebuf == NULL) || + (g_xge_os_tracebuf->offset == g_xge_os_tracebuf->size - 2)) { + return XGE_HAL_EOF_TRACE_BUF; + } + + data_offset = g_xge_os_tracebuf->offset + 1; + + if (*offset >= (unsigned)xge_os_strlen(g_xge_os_tracebuf->data + + data_offset)) { + + return XGE_HAL_EOF_TRACE_BUF; + } + + xge_os_memzero(buffer, buf_size); + + start_offset = data_offset + *offset; + *read_length = xge_os_strlen(g_xge_os_tracebuf->data + + start_offset); + + if (*read_length >= buf_size) { + *read_length = buf_size - 1; + } + + xge_os_memcpy(buffer, g_xge_os_tracebuf->data + start_offset, + *read_length); + + *offset += *read_length; + (*read_length) ++; + + return XGE_HAL_OK; +} + +#endif + +/** + * xge_hal_restore_link_led - Restore link LED to its original state. + * @devh: HAL device handle. + */ +void +xge_hal_restore_link_led(xge_hal_device_h devh) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)hldev->bar0; + u64 val64; + + /* + * If the current link state is UP, switch on LED else make it + * off. + */ + + /* + * For Xena 3 and lower revision cards, adapter control needs to be + * used for making LED ON/OFF. + */ + if ((xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA) && + (xge_hal_device_rev(hldev) <= 3)) { + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->adapter_control); + if (hldev->link_state == XGE_HAL_LINK_UP) { + val64 |= XGE_HAL_ADAPTER_LED_ON; + } else { + val64 &= ~XGE_HAL_ADAPTER_LED_ON; + } + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->adapter_control); + return; + } + + /* + * Use beacon control register to control the LED. + * LED link output corresponds to bit 8 of the beacon control + * register. Note that, in the case of Xena, beacon control register + * represents the gpio control register. In the case of Herc, LED + * handling is done by beacon control register as opposed to gpio + * control register in Xena. Beacon control is used only to toggle + * and the value written into it does not depend on the link state. + * It is upto the ULD to toggle the LED even number of times which + * brings the LED to it's original state. + */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->beacon_control); + val64 |= 0x0000800000000000ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &bar0->beacon_control); +} + +/** + * xge_hal_flick_link_led - Flick (blink) link LED. + * @devh: HAL device handle. + * + * Depending on the card revision flicker the link LED by using the + * beacon control or the adapter_control register. + */ +void +xge_hal_flick_link_led(xge_hal_device_h devh) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)hldev->bar0; + u64 val64 = 0; + + /* + * For Xena 3 and lower revision cards, adapter control needs to be + * used for making LED ON/OFF. + */ + if ((xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA) && + (xge_hal_device_rev(hldev) <= 3)) { + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->adapter_control); + val64 ^= XGE_HAL_ADAPTER_LED_ON; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->adapter_control); + return; + } + + /* + * Use beacon control register to control the Link LED. + * Note that, in the case of Xena, beacon control register represents + * the gpio control register. In the case of Herc, LED handling is + * done by beacon control register as opposed to gpio control register + * in Xena. + */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->beacon_control); + val64 ^= XGE_HAL_GPIO_CTRL_GPIO_0; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->beacon_control); +} + +/** + * xge_hal_read_eeprom - Read 4 bytes of data from user given offset. + * @devh: HAL device handle. + * @off: offset at which the data must be written + * @data: output parameter where the data is stored. + * + * Read 4 bytes of data from the user given offset and return the + * read data. + * Note: will allow to read only part of the EEPROM visible through the + * I2C bus. + * Returns: -1 on failure, 0 on success. + */ +xge_hal_status_e +xge_hal_read_eeprom(xge_hal_device_h devh, int off, u32* data) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + xge_hal_status_e ret = XGE_HAL_FAIL; + u32 exit_cnt = 0; + u64 val64; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)hldev->bar0; + + val64 = XGE_HAL_I2C_CONTROL_DEV_ID(XGE_DEV_ID) | + XGE_HAL_I2C_CONTROL_ADDR(off) | + XGE_HAL_I2C_CONTROL_BYTE_CNT(0x3) | + XGE_HAL_I2C_CONTROL_READ | XGE_HAL_I2C_CONTROL_CNTL_START; + + __hal_serial_mem_write64(hldev, val64, &bar0->i2c_control); + + while (exit_cnt < 5) { + val64 = __hal_serial_mem_read64(hldev, &bar0->i2c_control); + if (XGE_HAL_I2C_CONTROL_CNTL_END(val64)) { + *data = XGE_HAL_I2C_CONTROL_GET_DATA(val64); + ret = XGE_HAL_OK; + break; + } + exit_cnt++; + } + + return ret; +} + +/* + * xge_hal_write_eeprom - actually writes the relevant part of the data + value. + * @devh: HAL device handle. + * @off: offset at which the data must be written + * @data : The data that is to be written + * @cnt : Number of bytes of the data that are actually to be written into + * the Eeprom. (max of 3) + * + * Actually writes the relevant part of the data value into the Eeprom + * through the I2C bus. + * Return value: + * 0 on success, -1 on failure. + */ + +xge_hal_status_e +xge_hal_write_eeprom(xge_hal_device_h devh, int off, u32 data, int cnt) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + xge_hal_status_e ret = XGE_HAL_FAIL; + u32 exit_cnt = 0; + u64 val64; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)hldev->bar0; + + val64 = XGE_HAL_I2C_CONTROL_DEV_ID(XGE_DEV_ID) | + XGE_HAL_I2C_CONTROL_ADDR(off) | + XGE_HAL_I2C_CONTROL_BYTE_CNT(cnt) | + XGE_HAL_I2C_CONTROL_SET_DATA(data) | + XGE_HAL_I2C_CONTROL_CNTL_START; + __hal_serial_mem_write64(hldev, val64, &bar0->i2c_control); + + while (exit_cnt < 5) { + val64 = __hal_serial_mem_read64(hldev, &bar0->i2c_control); + if (XGE_HAL_I2C_CONTROL_CNTL_END(val64)) { + if (!(val64 & XGE_HAL_I2C_CONTROL_NACK)) + ret = XGE_HAL_OK; + break; + } + exit_cnt++; + } + + return ret; +} + +/* + * xge_hal_register_test - reads and writes into all clock domains. + * @hldev : private member of the device structure. + * xge_nic structure. + * @data : variable that returns the result of each of the test conducted b + * by the driver. + * + * Read and write into all clock domains. The NIC has 3 clock domains, + * see that registers in all the three regions are accessible. + * Return value: + * 0 on success. + */ +xge_hal_status_e +xge_hal_register_test(xge_hal_device_h devh, u64 *data) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)hldev->bar0; + u64 val64 = 0; + int fail = 0; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->pif_rd_swapper_fb); + if (val64 != 0x123456789abcdefULL) { + fail = 1; + xge_debug_osdep(XGE_TRACE, "Read Test level 1 fails"); + } + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->rmac_pause_cfg); + if (val64 != 0xc000ffff00000000ULL) { + fail = 1; + xge_debug_osdep(XGE_TRACE, "Read Test level 2 fails"); + } + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->rx_queue_cfg); + if (val64 != 0x0808080808080808ULL) { + fail = 1; + xge_debug_osdep(XGE_TRACE, "Read Test level 3 fails"); + } + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->xgxs_efifo_cfg); + if (val64 != 0x000000001923141EULL) { + fail = 1; + xge_debug_osdep(XGE_TRACE, "Read Test level 4 fails"); + } + + val64 = 0x5A5A5A5A5A5A5A5AULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->xmsi_data); + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->xmsi_data); + if (val64 != 0x5A5A5A5A5A5A5A5AULL) { + fail = 1; + xge_debug_osdep(XGE_ERR, "Write Test level 1 fails"); + } + + val64 = 0xA5A5A5A5A5A5A5A5ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->xmsi_data); + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->xmsi_data); + if (val64 != 0xA5A5A5A5A5A5A5A5ULL) { + fail = 1; + xge_debug_osdep(XGE_ERR, "Write Test level 2 fails"); + } + + *data = fail; + return XGE_HAL_OK; +} + +/* + * xge_hal_rldram_test - offline test for access to the RldRam chip on + the NIC + * @devh: HAL device handle. + * @data: variable that returns the result of each of the test + * conducted by the driver. + * + * This is one of the offline test that tests the read and write + * access to the RldRam chip on the NIC. + * Return value: + * 0 on success. + */ +xge_hal_status_e +xge_hal_rldram_test(xge_hal_device_h devh, u64 *data) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)hldev->bar0; + u64 val64; + int cnt, iteration = 0, test_pass = 0; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->adapter_control); + val64 &= ~XGE_HAL_ADAPTER_ECC_EN; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->adapter_control); + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->mc_rldram_test_ctrl); + val64 |= XGE_HAL_MC_RLDRAM_TEST_MODE; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->mc_rldram_test_ctrl); + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->mc_rldram_mrs); + val64 |= XGE_HAL_MC_RLDRAM_QUEUE_SIZE_ENABLE; + __hal_serial_mem_write64(hldev, val64, &bar0->i2c_control); + + val64 |= XGE_HAL_MC_RLDRAM_MRS_ENABLE; + __hal_serial_mem_write64(hldev, val64, &bar0->i2c_control); + + while (iteration < 2) { + val64 = 0x55555555aaaa0000ULL; + if (iteration == 1) { + val64 ^= 0xFFFFFFFFFFFF0000ULL; + } + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->mc_rldram_test_d0); + + val64 = 0xaaaa5a5555550000ULL; + if (iteration == 1) { + val64 ^= 0xFFFFFFFFFFFF0000ULL; + } + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->mc_rldram_test_d1); + + val64 = 0x55aaaaaaaa5a0000ULL; + if (iteration == 1) { + val64 ^= 0xFFFFFFFFFFFF0000ULL; + } + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->mc_rldram_test_d2); + + val64 = (u64) (0x0000003fffff0000ULL); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->mc_rldram_test_add); + + + val64 = XGE_HAL_MC_RLDRAM_TEST_MODE; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->mc_rldram_test_ctrl); + + val64 |= + XGE_HAL_MC_RLDRAM_TEST_MODE | XGE_HAL_MC_RLDRAM_TEST_WRITE | + XGE_HAL_MC_RLDRAM_TEST_GO; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->mc_rldram_test_ctrl); + + for (cnt = 0; cnt < 5; cnt++) { + val64 = xge_os_pio_mem_read64(hldev->pdev, + hldev->regh0, &bar0->mc_rldram_test_ctrl); + if (val64 & XGE_HAL_MC_RLDRAM_TEST_DONE) + break; + xge_os_mdelay(200); + } + + if (cnt == 5) + break; + + val64 = XGE_HAL_MC_RLDRAM_TEST_MODE; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->mc_rldram_test_ctrl); + + val64 |= XGE_HAL_MC_RLDRAM_TEST_MODE | + XGE_HAL_MC_RLDRAM_TEST_GO; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->mc_rldram_test_ctrl); + + for (cnt = 0; cnt < 5; cnt++) { + val64 = xge_os_pio_mem_read64(hldev->pdev, + hldev->regh0, &bar0->mc_rldram_test_ctrl); + if (val64 & XGE_HAL_MC_RLDRAM_TEST_DONE) + break; + xge_os_mdelay(500); + } + + if (cnt == 5) + break; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->mc_rldram_test_ctrl); + if (val64 & XGE_HAL_MC_RLDRAM_TEST_PASS) + test_pass = 1; + + iteration++; + } + + if (!test_pass) + *data = 1; + else + *data = 0; + + return XGE_HAL_OK; +} + +/* + * xge_hal_pma_loopback - Enable or disable PMA loopback + * @devh: HAL device handle. + * @enable:Boolean set to 1 to enable and 0 to disable. + * + * Enable or disable PMA loopback. + * Return value: + * 0 on success. + */ +xge_hal_status_e +xge_hal_pma_loopback( xge_hal_device_h devh, int enable ) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)hldev->bar0; + u64 val64; + u16 data; + + /* + * This code if for MAC loopbak + * Should be enabled through another parameter + */ +#if 0 + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->mac_cfg); + if ( enable ) + { + val64 |= ( XGE_HAL_MAC_CFG_TMAC_LOOPBACK | XGE_HAL_MAC_CFG_RMAC_PROM_ENABLE ); + } + __hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0, + (u32)(val64 >> 32), (char*)&bar0->mac_cfg); + xge_os_mdelay(1); +#endif + + val64 = XGE_HAL_MDIO_CONTROL_MMD_INDX_ADDR(0) | + XGE_HAL_MDIO_CONTROL_MMD_DEV_ADDR(1) | + XGE_HAL_MDIO_CONTROL_MMD_PRT_ADDR(0) | + XGE_HAL_MDIO_CONTROL_MMD_CTRL(0) | + XGE_HAL_MDIO_CONTROL_MMD_OP(XGE_HAL_MDIO_OP_ADDRESS); + __hal_serial_mem_write64(hldev, val64, &bar0->mdio_control); + + val64 |= XGE_HAL_MDIO_CONTROL_MMD_CTRL(XGE_HAL_MDIO_CTRL_START); + __hal_serial_mem_write64(hldev, val64, &bar0->mdio_control); + + val64 = XGE_HAL_MDIO_CONTROL_MMD_INDX_ADDR(0) | + XGE_HAL_MDIO_CONTROL_MMD_DEV_ADDR(1) | + XGE_HAL_MDIO_CONTROL_MMD_PRT_ADDR(0) | + XGE_HAL_MDIO_CONTROL_MMD_CTRL(0) | + XGE_HAL_MDIO_CONTROL_MMD_OP(XGE_HAL_MDIO_OP_READ); + __hal_serial_mem_write64(hldev, val64, &bar0->mdio_control); + + val64 |= XGE_HAL_MDIO_CONTROL_MMD_CTRL(XGE_HAL_MDIO_CTRL_START); + __hal_serial_mem_write64(hldev, val64, &bar0->mdio_control); + + val64 = __hal_serial_mem_read64(hldev, &bar0->mdio_control); + + data = (u16)XGE_HAL_MDIO_CONTROL_MMD_DATA_GET(val64); + +#define _HAL_LOOPBK_PMA 1 + + if( enable ) + data |= 1; + else + data &= 0xfe; + + val64 = XGE_HAL_MDIO_CONTROL_MMD_INDX_ADDR(0) | + XGE_HAL_MDIO_CONTROL_MMD_DEV_ADDR(1) | + XGE_HAL_MDIO_CONTROL_MMD_PRT_ADDR(0) | + XGE_HAL_MDIO_CONTROL_MMD_CTRL(0) | + XGE_HAL_MDIO_CONTROL_MMD_OP(XGE_HAL_MDIO_OP_ADDRESS); + __hal_serial_mem_write64(hldev, val64, &bar0->mdio_control); + + val64 |= XGE_HAL_MDIO_CONTROL_MMD_CTRL(XGE_HAL_MDIO_CTRL_START); + __hal_serial_mem_write64(hldev, val64, &bar0->mdio_control); + + val64 = XGE_HAL_MDIO_CONTROL_MMD_INDX_ADDR(0) | + XGE_HAL_MDIO_CONTROL_MMD_DEV_ADDR(1) | + XGE_HAL_MDIO_CONTROL_MMD_PRT_ADDR(0) | + XGE_HAL_MDIO_CONTROL_MMD_DATA(data) | + XGE_HAL_MDIO_CONTROL_MMD_CTRL(0x0) | + XGE_HAL_MDIO_CONTROL_MMD_OP(XGE_HAL_MDIO_OP_WRITE); + __hal_serial_mem_write64(hldev, val64, &bar0->mdio_control); + + val64 |= XGE_HAL_MDIO_CONTROL_MMD_CTRL(XGE_HAL_MDIO_CTRL_START); + __hal_serial_mem_write64(hldev, val64, &bar0->mdio_control); + + val64 = XGE_HAL_MDIO_CONTROL_MMD_INDX_ADDR(0) | + XGE_HAL_MDIO_CONTROL_MMD_DEV_ADDR(1) | + XGE_HAL_MDIO_CONTROL_MMD_PRT_ADDR(0) | + XGE_HAL_MDIO_CONTROL_MMD_CTRL(0x0) | + XGE_HAL_MDIO_CONTROL_MMD_OP(XGE_HAL_MDIO_OP_READ); + __hal_serial_mem_write64(hldev, val64, &bar0->mdio_control); + + val64 |= XGE_HAL_MDIO_CONTROL_MMD_CTRL(XGE_HAL_MDIO_CTRL_START); + __hal_serial_mem_write64(hldev, val64, &bar0->mdio_control); + + return XGE_HAL_OK; +} + +u16 +xge_hal_mdio_read( xge_hal_device_h devh, u32 mmd_type, u64 addr ) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)hldev->bar0; + u64 val64 = 0x0; + u16 rval16 = 0x0; + u8 i = 0; + + /* address transaction */ + val64 = XGE_HAL_MDIO_CONTROL_MMD_INDX_ADDR(addr) | + XGE_HAL_MDIO_CONTROL_MMD_DEV_ADDR(mmd_type) | + XGE_HAL_MDIO_CONTROL_MMD_PRT_ADDR(0) | + XGE_HAL_MDIO_CONTROL_MMD_OP(XGE_HAL_MDIO_OP_ADDRESS); + __hal_serial_mem_write64(hldev, val64, &bar0->mdio_control); + + val64 |= XGE_HAL_MDIO_CONTROL_MMD_CTRL(XGE_HAL_MDIO_CTRL_START); + __hal_serial_mem_write64(hldev, val64, &bar0->mdio_control); + do + { + val64 = __hal_serial_mem_read64(hldev, &bar0->mdio_control); + if (i++ > 10) + { + break; + } + }while((val64 & XGE_HAL_MDIO_CONTROL_MMD_CTRL(0xF)) != XGE_HAL_MDIO_CONTROL_MMD_CTRL(1)); + + /* Data transaction */ + val64 = XGE_HAL_MDIO_CONTROL_MMD_INDX_ADDR(addr) | + XGE_HAL_MDIO_CONTROL_MMD_DEV_ADDR(mmd_type) | + XGE_HAL_MDIO_CONTROL_MMD_PRT_ADDR(0) | + XGE_HAL_MDIO_CONTROL_MMD_OP(XGE_HAL_MDIO_OP_READ); + __hal_serial_mem_write64(hldev, val64, &bar0->mdio_control); + + val64 |= XGE_HAL_MDIO_CONTROL_MMD_CTRL(XGE_HAL_MDIO_CTRL_START); + __hal_serial_mem_write64(hldev, val64, &bar0->mdio_control); + + i = 0; + + do + { + val64 = __hal_serial_mem_read64(hldev, &bar0->mdio_control); + if (i++ > 10) + { + break; + } + }while((val64 & XGE_HAL_MDIO_CONTROL_MMD_CTRL(0xF)) != XGE_HAL_MDIO_CONTROL_MMD_CTRL(1)); + + rval16 = (u16)XGE_HAL_MDIO_CONTROL_MMD_DATA_GET(val64); + + return rval16; +} + +xge_hal_status_e +xge_hal_mdio_write( xge_hal_device_h devh, u32 mmd_type, u64 addr, u32 value ) +{ + u64 val64 = 0x0; + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)hldev->bar0; + u8 i = 0; + /* address transaction */ + + val64 = XGE_HAL_MDIO_CONTROL_MMD_INDX_ADDR(addr) | + XGE_HAL_MDIO_CONTROL_MMD_DEV_ADDR(mmd_type) | + XGE_HAL_MDIO_CONTROL_MMD_PRT_ADDR(0) | + XGE_HAL_MDIO_CONTROL_MMD_OP(XGE_HAL_MDIO_OP_ADDRESS); + __hal_serial_mem_write64(hldev, val64, &bar0->mdio_control); + + val64 |= XGE_HAL_MDIO_CONTROL_MMD_CTRL(XGE_HAL_MDIO_CTRL_START); + __hal_serial_mem_write64(hldev, val64, &bar0->mdio_control); + + do + { + val64 = __hal_serial_mem_read64(hldev, &bar0->mdio_control); + if (i++ > 10) + { + break; + } + } while((val64 & XGE_HAL_MDIO_CONTROL_MMD_CTRL(0xF)) != + XGE_HAL_MDIO_CONTROL_MMD_CTRL(1)); + + /* Data transaction */ + + val64 = 0x0; + + val64 = XGE_HAL_MDIO_CONTROL_MMD_INDX_ADDR(addr) | + XGE_HAL_MDIO_CONTROL_MMD_DEV_ADDR(mmd_type) | + XGE_HAL_MDIO_CONTROL_MMD_PRT_ADDR(0) | + XGE_HAL_MDIO_CONTROL_MMD_DATA(value) | + XGE_HAL_MDIO_CONTROL_MMD_OP(XGE_HAL_MDIO_OP_WRITE); + __hal_serial_mem_write64(hldev, val64, &bar0->mdio_control); + + val64 |= XGE_HAL_MDIO_CONTROL_MMD_CTRL(XGE_HAL_MDIO_CTRL_START); + __hal_serial_mem_write64(hldev, val64, &bar0->mdio_control); + + i = 0; + + do + { + val64 = __hal_serial_mem_read64(hldev, &bar0->mdio_control); + if (i++ > 10) + { + break; + } + }while((val64 & XGE_HAL_MDIO_CONTROL_MMD_CTRL(0xF)) != XGE_HAL_MDIO_CONTROL_MMD_CTRL(1)); + + return XGE_HAL_OK; +} + +/* + * xge_hal_eeprom_test - to verify that EEprom in the xena can be + programmed. + * @devh: HAL device handle. + * @data:variable that returns the result of each of the test conducted by + * the driver. + * + * Verify that EEPROM in the xena can be programmed using I2C_CONTROL + * register. + * Return value: + * 0 on success. + */ +xge_hal_status_e +xge_hal_eeprom_test(xge_hal_device_h devh, u64 *data) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + int fail = 0; + u32 ret_data = 0; + + /* Test Write Error at offset 0 */ + if (!xge_hal_write_eeprom(hldev, 0, 0, 3)) + fail = 1; + + /* Test Write at offset 4f0 */ + if (xge_hal_write_eeprom(hldev, 0x4F0, 0x01234567, 3)) + fail = 1; + if (xge_hal_read_eeprom(hldev, 0x4F0, &ret_data)) + fail = 1; + + if (ret_data != 0x01234567) + fail = 1; + + /* Reset the EEPROM data go FFFF */ + (void) xge_hal_write_eeprom(hldev, 0x4F0, 0xFFFFFFFF, 3); + + /* Test Write Request Error at offset 0x7c */ + if (!xge_hal_write_eeprom(hldev, 0x07C, 0, 3)) + fail = 1; + + /* Test Write Request at offset 0x7fc */ + if (xge_hal_write_eeprom(hldev, 0x7FC, 0x01234567, 3)) + fail = 1; + if (xge_hal_read_eeprom(hldev, 0x7FC, &ret_data)) + fail = 1; + + if (ret_data != 0x01234567) + fail = 1; + + /* Reset the EEPROM data go FFFF */ + (void) xge_hal_write_eeprom(hldev, 0x7FC, 0xFFFFFFFF, 3); + + /* Test Write Error at offset 0x80 */ + if (!xge_hal_write_eeprom(hldev, 0x080, 0, 3)) + fail = 1; + + /* Test Write Error at offset 0xfc */ + if (!xge_hal_write_eeprom(hldev, 0x0FC, 0, 3)) + fail = 1; + + /* Test Write Error at offset 0x100 */ + if (!xge_hal_write_eeprom(hldev, 0x100, 0, 3)) + fail = 1; + + /* Test Write Error at offset 4ec */ + if (!xge_hal_write_eeprom(hldev, 0x4EC, 0, 3)) + fail = 1; + + *data = fail; + return XGE_HAL_OK; +} + +/* + * xge_hal_bist_test - invokes the MemBist test of the card . + * @devh: HAL device handle. + * xge_nic structure. + * @data:variable that returns the result of each of the test conducted by + * the driver. + * + * This invokes the MemBist test of the card. We give around + * 2 secs time for the Test to complete. If it's still not complete + * within this peiod, we consider that the test failed. + * Return value: + * 0 on success and -1 on failure. + */ +xge_hal_status_e +xge_hal_bist_test(xge_hal_device_h devh, u64 *data) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + u8 bist = 0; + int cnt = 0; + xge_hal_status_e ret = XGE_HAL_FAIL; + + xge_os_pci_read8(hldev->pdev, hldev->cfgh, 0x0f, &bist); + bist |= 0x40; + xge_os_pci_write8(hldev->pdev, hldev->cfgh, 0x0f, bist); + + while (cnt < 20) { + xge_os_pci_read8(hldev->pdev, hldev->cfgh, 0x0f, &bist); + if (!(bist & 0x40)) { + *data = (bist & 0x0f); + ret = XGE_HAL_OK; + break; + } + xge_os_mdelay(100); + cnt++; + } + + return ret; +} + +/* + * xge_hal_link_test - verifies the link state of the nic + * @devh: HAL device handle. + * @data: variable that returns the result of each of the test conducted by + * the driver. + * + * Verify the link state of the NIC and updates the input + * argument 'data' appropriately. + * Return value: + * 0 on success. + */ +xge_hal_status_e +xge_hal_link_test(xge_hal_device_h devh, u64 *data) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)hldev->bar0; + u64 val64; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->adapter_status); + if (val64 & XGE_HAL_ADAPTER_STATUS_RMAC_LOCAL_FAULT) + *data = 1; + + return XGE_HAL_OK; +} + + +/** + * xge_hal_getpause_data -Pause frame frame generation and reception. + * @devh: HAL device handle. + * @tx : A field to return the pause generation capability of the NIC. + * @rx : A field to return the pause reception capability of the NIC. + * + * Returns the Pause frame generation and reception capability of the NIC. + * Return value: + * void + */ +void xge_hal_getpause_data(xge_hal_device_h devh, int *tx, int *rx) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)hldev->bar0; + u64 val64; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->rmac_pause_cfg); + if (val64 & XGE_HAL_RMAC_PAUSE_GEN_EN) + *tx = 1; + if (val64 & XGE_HAL_RMAC_PAUSE_RCV_EN) + *rx = 1; +} + +/** + * xge_hal_setpause_data - set/reset pause frame generation. + * @devh: HAL device handle. + * @tx: A field that indicates the pause generation capability to be + * set on the NIC. + * @rx: A field that indicates the pause reception capability to be + * set on the NIC. + * + * It can be used to set or reset Pause frame generation or reception + * support of the NIC. + * Return value: + * int, returns 0 on Success + */ + +int xge_hal_setpause_data(xge_hal_device_h devh, int tx, int rx) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)hldev->bar0; + u64 val64; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->rmac_pause_cfg); + if (tx) + val64 |= XGE_HAL_RMAC_PAUSE_GEN_EN; + else + val64 &= ~XGE_HAL_RMAC_PAUSE_GEN_EN; + if (rx) + val64 |= XGE_HAL_RMAC_PAUSE_RCV_EN; + else + val64 &= ~XGE_HAL_RMAC_PAUSE_RCV_EN; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &bar0->rmac_pause_cfg); + return 0; +} + +/** + * xge_hal_read_xfp_current_temp - + * @hldev: HAL device handle. + * + * This routine only gets the temperature for XFP modules. Also, updating of the + * NVRAM can sometimes fail and so the reading we might get may not be uptodate. + */ +u32 xge_hal_read_xfp_current_temp(xge_hal_device_h hldev) +{ + u16 val_1, val_2, i = 0; + u32 actual; + + /* First update the NVRAM table of XFP. */ + + (void) xge_hal_mdio_write(hldev, XGE_HAL_MDIO_MMD_PMA_DEV_ADDR, 0x8000, 0x3); + + + /* Now wait for the transfer to complete */ + do + { + xge_os_mdelay( 50 ); // wait 50 milliseonds + + val_1 = xge_hal_mdio_read(hldev, XGE_HAL_MDIO_MMD_PMA_DEV_ADDR, 0x8000); + + if ( i++ > 10 ) + { + // waited 500 ms which should be plenty of time. + break; + } + }while (( val_1 & 0x000C ) != 0x0004); + + /* Now NVRAM table of XFP should be updated, so read the temp */ + val_1 = (u8) xge_hal_mdio_read(hldev, XGE_HAL_MDIO_MMD_PMA_DEV_ADDR, 0x8067); + val_2 = (u8) xge_hal_mdio_read(hldev, XGE_HAL_MDIO_MMD_PMA_DEV_ADDR, 0x8068); + + actual = ((val_1 << 8) | val_2); + + if (actual >= 32768) + actual = actual- 65536; + actual = actual/256; + + return actual; +} + +/** + * __hal_chk_xpak_counter - check the Xpak error count and log the msg. + * @hldev: pointer to xge_hal_device_t structure + * @type: xpak stats error type + * @value: xpak stats value + * + * It is used to log the error message based on the xpak stats value + * Return value: + * None + */ + +void __hal_chk_xpak_counter(xge_hal_device_t *hldev, int type, u32 value) +{ + /* + * If the value is high for three consecutive cylce, + * log a error message + */ + if(value == 3) + { + switch(type) + { + case 1: + hldev->stats.sw_dev_err_stats.xpak_counter. + excess_temp = 0; + + /* + * Notify the ULD on Excess Xpak temperature alarm msg + */ + if (g_xge_hal_driver->uld_callbacks.xpak_alarm_log) { + g_xge_hal_driver->uld_callbacks.xpak_alarm_log( + hldev->upper_layer_info, + XGE_HAL_XPAK_ALARM_EXCESS_TEMP); + } + break; + case 2: + hldev->stats.sw_dev_err_stats.xpak_counter. + excess_bias_current = 0; + + /* + * Notify the ULD on Excess xpak bias current alarm msg + */ + if (g_xge_hal_driver->uld_callbacks.xpak_alarm_log) { + g_xge_hal_driver->uld_callbacks.xpak_alarm_log( + hldev->upper_layer_info, + XGE_HAL_XPAK_ALARM_EXCESS_BIAS_CURRENT); + } + break; + case 3: + hldev->stats.sw_dev_err_stats.xpak_counter. + excess_laser_output = 0; + + /* + * Notify the ULD on Excess Xpak Laser o/p power + * alarm msg + */ + if (g_xge_hal_driver->uld_callbacks.xpak_alarm_log) { + g_xge_hal_driver->uld_callbacks.xpak_alarm_log( + hldev->upper_layer_info, + XGE_HAL_XPAK_ALARM_EXCESS_LASER_OUTPUT); + } + break; + default: + xge_debug_osdep(XGE_TRACE, "Incorrect XPAK Alarm " + "type "); + } + } + +} + +/** + * __hal_updt_stats_xpak - update the Xpak error count. + * @hldev: pointer to xge_hal_device_t structure + * + * It is used to update the xpak stats value + * Return value: + * None + */ +void __hal_updt_stats_xpak(xge_hal_device_t *hldev) +{ + u16 val_1; + u64 addr; + + /* Check the communication with the MDIO slave */ + addr = 0x0000; + val_1 = 0x0; + val_1 = xge_hal_mdio_read(hldev, XGE_HAL_MDIO_MMD_PMA_DEV_ADDR, addr); + if((val_1 == 0xFFFF) || (val_1 == 0x0000)) + { + xge_debug_osdep(XGE_TRACE, "ERR: MDIO slave access failed - " + "Returned %x", val_1); + return; + } + + /* Check for the expected value of 2040 at PMA address 0x0000 */ + if(val_1 != 0x2040) + { + xge_debug_osdep(XGE_TRACE, "Incorrect value at PMA address 0x0000 - "); + xge_debug_osdep(XGE_TRACE, "Returned: %llx- Expected: 0x2040", + (unsigned long long)(unsigned long)val_1); + return; + } + + /* Loading the DOM register to MDIO register */ + addr = 0xA100; + (void) xge_hal_mdio_write(hldev, XGE_HAL_MDIO_MMD_PMA_DEV_ADDR, addr, 0x0); + val_1 = xge_hal_mdio_read(hldev, XGE_HAL_MDIO_MMD_PMA_DEV_ADDR, addr); + + /* + * Reading the Alarm flags + */ + addr = 0xA070; + val_1 = 0x0; + val_1 = xge_hal_mdio_read(hldev, XGE_HAL_MDIO_MMD_PMA_DEV_ADDR, addr); + if(CHECKBIT(val_1, 0x7)) + { + hldev->stats.sw_dev_err_stats.stats_xpak. + alarm_transceiver_temp_high++; + hldev->stats.sw_dev_err_stats.xpak_counter.excess_temp++; + __hal_chk_xpak_counter(hldev, 0x1, + hldev->stats.sw_dev_err_stats.xpak_counter.excess_temp); + } else { + hldev->stats.sw_dev_err_stats.xpak_counter.excess_temp = 0; + } + if(CHECKBIT(val_1, 0x6)) + hldev->stats.sw_dev_err_stats.stats_xpak. + alarm_transceiver_temp_low++; + + if(CHECKBIT(val_1, 0x3)) + { + hldev->stats.sw_dev_err_stats.stats_xpak. + alarm_laser_bias_current_high++; + hldev->stats.sw_dev_err_stats.xpak_counter. + excess_bias_current++; + __hal_chk_xpak_counter(hldev, 0x2, + hldev->stats.sw_dev_err_stats.xpak_counter. + excess_bias_current); + } else { + hldev->stats.sw_dev_err_stats.xpak_counter. + excess_bias_current = 0; + } + if(CHECKBIT(val_1, 0x2)) + hldev->stats.sw_dev_err_stats.stats_xpak. + alarm_laser_bias_current_low++; + + if(CHECKBIT(val_1, 0x1)) + { + hldev->stats.sw_dev_err_stats.stats_xpak. + alarm_laser_output_power_high++; + hldev->stats.sw_dev_err_stats.xpak_counter. + excess_laser_output++; + __hal_chk_xpak_counter(hldev, 0x3, + hldev->stats.sw_dev_err_stats.xpak_counter. + excess_laser_output); + } else { + hldev->stats.sw_dev_err_stats.xpak_counter. + excess_laser_output = 0; + } + if(CHECKBIT(val_1, 0x0)) + hldev->stats.sw_dev_err_stats.stats_xpak. + alarm_laser_output_power_low++; + + /* + * Reading the warning flags + */ + addr = 0xA074; + val_1 = 0x0; + val_1 = xge_hal_mdio_read(hldev, XGE_HAL_MDIO_MMD_PMA_DEV_ADDR, addr); + if(CHECKBIT(val_1, 0x7)) + hldev->stats.sw_dev_err_stats.stats_xpak. + warn_transceiver_temp_high++; + if(CHECKBIT(val_1, 0x6)) + hldev->stats.sw_dev_err_stats.stats_xpak. + warn_transceiver_temp_low++; + if(CHECKBIT(val_1, 0x3)) + hldev->stats.sw_dev_err_stats.stats_xpak. + warn_laser_bias_current_high++; + if(CHECKBIT(val_1, 0x2)) + hldev->stats.sw_dev_err_stats.stats_xpak. + warn_laser_bias_current_low++; + if(CHECKBIT(val_1, 0x1)) + hldev->stats.sw_dev_err_stats.stats_xpak. + warn_laser_output_power_high++; + if(CHECKBIT(val_1, 0x0)) + hldev->stats.sw_dev_err_stats.stats_xpak. + warn_laser_output_power_low++; +} diff --git a/sys/dev/nxge/xgehal/xgehal-mgmtaux.c b/sys/dev/nxge/xgehal/xgehal-mgmtaux.c new file mode 100644 index 0000000..e2f0046 --- /dev/null +++ b/sys/dev/nxge/xgehal/xgehal-mgmtaux.c @@ -0,0 +1,1731 @@ +/*- + * Copyright (c) 2002-2007 Neterion, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * FileName : xgehal-mgmtaux.c + * + * Description: Xframe-family management auxiliary API implementation + * + * Created: 1 September 2004 + */ + +#include +#include +#include + +#ifdef XGE_OS_HAS_SNPRINTF +#define __hal_aux_snprintf(retbuf, bufsize, fmt, key, value, retsize) \ + if (bufsize <= 0) return XGE_HAL_ERR_OUT_OF_SPACE; \ + retsize = xge_os_snprintf(retbuf, bufsize, fmt, key, \ + XGE_HAL_AUX_SEPA, value); \ + if (retsize < 0 || retsize >= bufsize) return XGE_HAL_ERR_OUT_OF_SPACE; +#else +#define __hal_aux_snprintf(retbuf, bufsize, fmt, key, value, retsize) \ + if (bufsize <= 0) return XGE_HAL_ERR_OUT_OF_SPACE; \ + retsize = xge_os_sprintf(retbuf, fmt, key, XGE_HAL_AUX_SEPA, value); \ + xge_assert(retsize < bufsize); \ + if (retsize < 0 || retsize >= bufsize) \ + return XGE_HAL_ERR_OUT_OF_SPACE; +#endif + +#define __HAL_AUX_ENTRY_DECLARE(size, buf) \ + int entrysize = 0, leftsize = size; \ + char *ptr = buf; + +#define __HAL_AUX_ENTRY(key, value, fmt) \ + ptr += entrysize; leftsize -= entrysize; \ + __hal_aux_snprintf(ptr, leftsize, "%s%c"fmt"\n", key, value, entrysize) + +#define __HAL_AUX_ENTRY_END(bufsize, retsize) \ + leftsize -= entrysize; \ + *retsize = bufsize - leftsize; + +#define __hal_aux_pci_link_info(name, index, var) { \ + __HAL_AUX_ENTRY(name, \ + (unsigned long long)pcim.link_info[index].var, "%llu") \ + } + +#define __hal_aux_pci_aggr_info(name, index, var) { \ + __HAL_AUX_ENTRY(name, \ + (unsigned long long)pcim.aggr_info[index].var, "%llu") \ + } + +/** + * xge_hal_aux_bar0_read - Read and format Xframe BAR0 register. + * @devh: HAL device handle. + * @offset: Register offset in the BAR0 space. + * @bufsize: Buffer size. + * @retbuf: Buffer pointer. + * @retsize: Size of the result. Cannot be greater than @bufsize. + * + * Read Xframe register from BAR0 space. The result is formatted as an ascii string. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_OUT_OF_SPACE - Buffer size is very small. + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not + * valid. + * XGE_HAL_ERR_INVALID_BAR_ID - BAR id is not valid. + * + * See also: xge_hal_mgmt_reg_read(). + */ +xge_hal_status_e xge_hal_aux_bar0_read(xge_hal_device_h devh, + unsigned int offset, int bufsize, char *retbuf, + int *retsize) +{ + xge_hal_status_e status; + u64 retval; + + status = xge_hal_mgmt_reg_read(devh, 0, offset, &retval); + if (status != XGE_HAL_OK) { + return status; + } + + if (bufsize < XGE_OS_SPRINTF_STRLEN) { + return XGE_HAL_ERR_OUT_OF_SPACE; + } + + *retsize = xge_os_sprintf(retbuf, "0x%04X%c0x%08X%08X\n", offset, + XGE_HAL_AUX_SEPA, (u32)(retval>>32), (u32)retval); + + return XGE_HAL_OK; +} + +/** + * xge_hal_aux_bar1_read - Read and format Xframe BAR1 register. + * @devh: HAL device handle. + * @offset: Register offset in the BAR1 space. + * @bufsize: Buffer size. + * @retbuf: Buffer pointer. + * @retsize: Size of the result. Cannot be greater than @bufsize. + * + * Read Xframe register from BAR1 space. The result is formatted as ascii string. + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_OUT_OF_SPACE - Buffer size is very small. + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not + * valid. + * XGE_HAL_ERR_INVALID_BAR_ID - BAR id is not valid. + * + * See also: xge_hal_mgmt_reg_read(). + */ +xge_hal_status_e xge_hal_aux_bar1_read(xge_hal_device_h devh, + unsigned int offset, int bufsize, char *retbuf, + int *retsize) +{ + xge_hal_status_e status; + u64 retval; + + status = xge_hal_mgmt_reg_read(devh, 1, offset, &retval); + if (status != XGE_HAL_OK) { + return status; + } + + if (bufsize < XGE_OS_SPRINTF_STRLEN) { + return XGE_HAL_ERR_OUT_OF_SPACE; + } + + *retsize = xge_os_sprintf(retbuf, "0x%04X%c0x%08X%08X\n", + offset, + XGE_HAL_AUX_SEPA, (u32)(retval>>32), (u32)retval); + + return XGE_HAL_OK; +} + +/** + * xge_hal_aux_bar0_write - Write BAR0 register. + * @devh: HAL device handle. + * @offset: Register offset in the BAR0 space. + * @value: Regsister value (to write). + * + * Write BAR0 register. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not + * valid. + * XGE_HAL_ERR_INVALID_BAR_ID - BAR id is not valid. + * + * See also: xge_hal_mgmt_reg_write(). + */ +xge_hal_status_e xge_hal_aux_bar0_write(xge_hal_device_h devh, + unsigned int offset, u64 value) +{ + xge_hal_status_e status; + + status = xge_hal_mgmt_reg_write(devh, 0, offset, value); + if (status != XGE_HAL_OK) { + return status; + } + + return XGE_HAL_OK; +} + +/** + * xge_hal_aux_about_read - Retrieve and format about info. + * @devh: HAL device handle. + * @bufsize: Buffer size. + * @retbuf: Buffer pointer. + * @retsize: Size of the result. Cannot be greater than @bufsize. + * + * Retrieve about info (using xge_hal_mgmt_about()) and sprintf it + * into the provided @retbuf. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. + * XGE_HAL_FAIL - Failed to retrieve the information. + * + * See also: xge_hal_mgmt_about(), xge_hal_aux_device_dump(). + */ +xge_hal_status_e xge_hal_aux_about_read(xge_hal_device_h devh, int bufsize, + char *retbuf, int *retsize) +{ + xge_hal_status_e status; + xge_hal_mgmt_about_info_t about_info; + __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf); + + status = xge_hal_mgmt_about(devh, &about_info, + sizeof(xge_hal_mgmt_about_info_t)); + if (status != XGE_HAL_OK) { + return status; + } + + __HAL_AUX_ENTRY("vendor", about_info.vendor, "0x%x"); + __HAL_AUX_ENTRY("device", about_info.device, "0x%x"); + __HAL_AUX_ENTRY("subsys_vendor", about_info.subsys_vendor, "0x%x"); + __HAL_AUX_ENTRY("subsys_device", about_info.subsys_device, "0x%x"); + __HAL_AUX_ENTRY("board_rev", about_info.board_rev, "0x%x"); + __HAL_AUX_ENTRY("vendor_name", about_info.vendor_name, "%s"); + __HAL_AUX_ENTRY("chip_name", about_info.chip_name, "%s"); + __HAL_AUX_ENTRY("media", about_info.media, "%s"); + __HAL_AUX_ENTRY("hal_major", about_info.hal_major, "%s"); + __HAL_AUX_ENTRY("hal_minor", about_info.hal_minor, "%s"); + __HAL_AUX_ENTRY("hal_fix", about_info.hal_fix, "%s"); + __HAL_AUX_ENTRY("hal_build", about_info.hal_build, "%s"); + __HAL_AUX_ENTRY("ll_major", about_info.ll_major, "%s"); + __HAL_AUX_ENTRY("ll_minor", about_info.ll_minor, "%s"); + __HAL_AUX_ENTRY("ll_fix", about_info.ll_fix, "%s"); + __HAL_AUX_ENTRY("ll_build", about_info.ll_build, "%s"); + + __HAL_AUX_ENTRY("transponder_temperature", + about_info.transponder_temperature, "%d C"); + + __HAL_AUX_ENTRY_END(bufsize, retsize); + + return XGE_HAL_OK; +} + +/** + * xge_hal_aux_stats_tmac_read - Read TMAC hardware statistics. + * @devh: HAL device handle. + * @bufsize: Buffer size. + * @retbuf: Buffer pointer. + * @retsize: Size of the result. Cannot be greater than @bufsize. + * + * Read TMAC hardware statistics. This is a subset of stats counters + * from xge_hal_stats_hw_info_t{}. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. + * + * See also: xge_hal_mgmt_hw_stats{}, xge_hal_stats_hw_info_t{}, + * xge_hal_aux_stats_pci_read(), + * xge_hal_aux_device_dump(). + */ +xge_hal_status_e xge_hal_aux_stats_tmac_read(xge_hal_device_h devh, int bufsize, + char *retbuf, int *retsize) +{ + xge_hal_status_e status; + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + + __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf); + + if (xge_hal_device_check_id(hldev) != XGE_HAL_CARD_TITAN) { + xge_hal_mgmt_hw_stats_t hw; + + status = xge_hal_mgmt_hw_stats(devh, &hw, + sizeof(xge_hal_mgmt_hw_stats_t)); + if (status != XGE_HAL_OK) { + return status; + } + + __HAL_AUX_ENTRY("tmac_data_octets", hw.tmac_data_octets, "%u"); + __HAL_AUX_ENTRY("tmac_frms", hw.tmac_frms, "%u"); + __HAL_AUX_ENTRY("tmac_drop_frms", (unsigned long long) + hw.tmac_drop_frms, "%llu"); + __HAL_AUX_ENTRY("tmac_bcst_frms", hw.tmac_bcst_frms, "%u"); + __HAL_AUX_ENTRY("tmac_mcst_frms", hw.tmac_mcst_frms, "%u"); + __HAL_AUX_ENTRY("tmac_pause_ctrl_frms", (unsigned long long) + hw.tmac_pause_ctrl_frms, "%llu"); + __HAL_AUX_ENTRY("tmac_ucst_frms", hw.tmac_ucst_frms, "%u"); + __HAL_AUX_ENTRY("tmac_ttl_octets", hw.tmac_ttl_octets, "%u"); + __HAL_AUX_ENTRY("tmac_any_err_frms", hw.tmac_any_err_frms, "%u"); + __HAL_AUX_ENTRY("tmac_nucst_frms", hw.tmac_nucst_frms, "%u"); + __HAL_AUX_ENTRY("tmac_ttl_less_fb_octets", (unsigned long long) + hw.tmac_ttl_less_fb_octets, "%llu"); + __HAL_AUX_ENTRY("tmac_vld_ip_octets", (unsigned long long) + hw.tmac_vld_ip_octets, "%llu"); + __HAL_AUX_ENTRY("tmac_drop_ip", hw.tmac_drop_ip, "%u"); + __HAL_AUX_ENTRY("tmac_vld_ip", hw.tmac_vld_ip, "%u"); + __HAL_AUX_ENTRY("tmac_rst_tcp", hw.tmac_rst_tcp, "%u"); + __HAL_AUX_ENTRY("tmac_icmp", hw.tmac_icmp, "%u"); + __HAL_AUX_ENTRY("tmac_tcp", (unsigned long long) + hw.tmac_tcp, "%llu"); + __HAL_AUX_ENTRY("reserved_0", hw.reserved_0, "%u"); + __HAL_AUX_ENTRY("tmac_udp", hw.tmac_udp, "%u"); + } else { + int i; + xge_hal_mgmt_pcim_stats_t pcim; + status = xge_hal_mgmt_pcim_stats(devh, &pcim, + sizeof(xge_hal_mgmt_pcim_stats_t)); + if (status != XGE_HAL_OK) { + return status; + } + + for (i = 0; i < XGE_HAL_MAC_LINKS; i++) { + __hal_aux_pci_link_info("tx_frms", i, + tx_frms); + __hal_aux_pci_link_info("tx_ttl_eth_octets", + i, tx_ttl_eth_octets ); + __hal_aux_pci_link_info("tx_data_octets", i, + tx_data_octets); + __hal_aux_pci_link_info("tx_mcst_frms", i, + tx_mcst_frms); + __hal_aux_pci_link_info("tx_bcst_frms", i, + tx_bcst_frms); + __hal_aux_pci_link_info("tx_ucst_frms", i, + tx_ucst_frms); + __hal_aux_pci_link_info("tx_tagged_frms", i, + tx_tagged_frms); + __hal_aux_pci_link_info("tx_vld_ip", i, + tx_vld_ip); + __hal_aux_pci_link_info("tx_vld_ip_octets", i, + tx_vld_ip_octets); + __hal_aux_pci_link_info("tx_icmp", i, + tx_icmp); + __hal_aux_pci_link_info("tx_tcp", i, + tx_tcp); + __hal_aux_pci_link_info("tx_rst_tcp", i, + tx_rst_tcp); + __hal_aux_pci_link_info("tx_udp", i, + tx_udp); + __hal_aux_pci_link_info("tx_unknown_protocol", i, + tx_unknown_protocol); + __hal_aux_pci_link_info("tx_parse_error", i, + tx_parse_error); + __hal_aux_pci_link_info("tx_pause_ctrl_frms", i, + tx_pause_ctrl_frms); + __hal_aux_pci_link_info("tx_lacpdu_frms", i, + tx_lacpdu_frms); + __hal_aux_pci_link_info("tx_marker_pdu_frms", i, + tx_marker_pdu_frms); + __hal_aux_pci_link_info("tx_marker_resp_pdu_frms", i, + tx_marker_resp_pdu_frms); + __hal_aux_pci_link_info("tx_drop_ip", i, + tx_drop_ip); + __hal_aux_pci_link_info("tx_xgmii_char1_match", i, + tx_xgmii_char1_match); + __hal_aux_pci_link_info("tx_xgmii_char2_match", i, + tx_xgmii_char2_match); + __hal_aux_pci_link_info("tx_xgmii_column1_match", i, + tx_xgmii_column1_match); + __hal_aux_pci_link_info("tx_xgmii_column2_match", i, + tx_xgmii_column2_match); + __hal_aux_pci_link_info("tx_drop_frms", i, + tx_drop_frms); + __hal_aux_pci_link_info("tx_any_err_frms", i, + tx_any_err_frms); + } + + for (i = 0; i < XGE_HAL_MAC_AGGREGATORS; i++) { + __hal_aux_pci_aggr_info("tx_frms", i, tx_frms); + __hal_aux_pci_aggr_info("tx_mcst_frms", i, + tx_mcst_frms); + __hal_aux_pci_aggr_info("tx_bcst_frms", i, + tx_bcst_frms); + __hal_aux_pci_aggr_info("tx_discarded_frms", i, + tx_discarded_frms); + __hal_aux_pci_aggr_info("tx_errored_frms", i, + tx_errored_frms); + } + } + + __HAL_AUX_ENTRY_END(bufsize, retsize); + + return XGE_HAL_OK; +} + +/** + * xge_hal_aux_stats_rmac_read - Read RMAC hardware statistics. + * @devh: HAL device handle. + * @bufsize: Buffer size. + * @retbuf: Buffer pointer. + * @retsize: Size of the result. Cannot be greater than @bufsize. + * + * Read RMAC hardware statistics. This is a subset of stats counters + * from xge_hal_stats_hw_info_t{}. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. + * + * See also: xge_hal_mgmt_hw_stats{}, xge_hal_stats_hw_info_t{}, + * xge_hal_aux_stats_pci_read(), xge_hal_aux_stats_tmac_read(), + * xge_hal_aux_device_dump(). + */ +xge_hal_status_e xge_hal_aux_stats_rmac_read(xge_hal_device_h devh, int bufsize, + char *retbuf, int *retsize) +{ + xge_hal_status_e status; + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + + __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf); + + if (xge_hal_device_check_id(hldev) != XGE_HAL_CARD_TITAN) { + xge_hal_mgmt_hw_stats_t hw; + + status = xge_hal_mgmt_hw_stats(devh, &hw, + sizeof(xge_hal_mgmt_hw_stats_t)); + if (status != XGE_HAL_OK) { + return status; + } + + __HAL_AUX_ENTRY("rmac_data_octets", hw.rmac_data_octets, "%u"); + __HAL_AUX_ENTRY("rmac_vld_frms", hw.rmac_vld_frms, "%u"); + __HAL_AUX_ENTRY("rmac_fcs_err_frms", (unsigned long long) + hw.rmac_fcs_err_frms, "%llu"); + __HAL_AUX_ENTRY("mac_drop_frms", (unsigned long long) + hw.rmac_drop_frms, "%llu"); + __HAL_AUX_ENTRY("rmac_vld_bcst_frms", hw.rmac_vld_bcst_frms, + "%u"); + __HAL_AUX_ENTRY("rmac_vld_mcst_frms", hw.rmac_vld_mcst_frms, + "%u"); + __HAL_AUX_ENTRY("rmac_out_rng_len_err_frms", + hw.rmac_out_rng_len_err_frms, "%u"); + __HAL_AUX_ENTRY("rmac_in_rng_len_err_frms", + hw.rmac_in_rng_len_err_frms, "%u"); + __HAL_AUX_ENTRY("rmac_long_frms", (unsigned long long) + hw.rmac_long_frms, "%llu"); + __HAL_AUX_ENTRY("rmac_pause_ctrl_frms", (unsigned long long) + hw.rmac_pause_ctrl_frms, "%llu"); + __HAL_AUX_ENTRY("rmac_unsup_ctrl_frms", (unsigned long long) + hw.rmac_unsup_ctrl_frms, "%llu"); + __HAL_AUX_ENTRY("rmac_accepted_ucst_frms", + hw.rmac_accepted_ucst_frms, "%u"); + __HAL_AUX_ENTRY("rmac_ttl_octets", hw.rmac_ttl_octets, "%u"); + __HAL_AUX_ENTRY("rmac_discarded_frms", hw.rmac_discarded_frms, + "%u"); + __HAL_AUX_ENTRY("rmac_accepted_nucst_frms", + hw.rmac_accepted_nucst_frms, "%u"); + __HAL_AUX_ENTRY("reserved_1", hw.reserved_1, "%u"); + __HAL_AUX_ENTRY("rmac_drop_events", hw.rmac_drop_events, "%u"); + __HAL_AUX_ENTRY("rmac_ttl_less_fb_octets", (unsigned long long) + hw.rmac_ttl_less_fb_octets, "%llu"); + __HAL_AUX_ENTRY("rmac_ttl_frms", (unsigned long long) + hw.rmac_ttl_frms, "%llu"); + __HAL_AUX_ENTRY("reserved_2", (unsigned long long) + hw.reserved_2, "%llu"); + __HAL_AUX_ENTRY("rmac_usized_frms", hw.rmac_usized_frms, "%u"); + __HAL_AUX_ENTRY("reserved_3", hw.reserved_3, "%u"); + __HAL_AUX_ENTRY("rmac_frag_frms", hw.rmac_frag_frms, "%u"); + __HAL_AUX_ENTRY("rmac_osized_frms", hw.rmac_osized_frms, "%u"); + __HAL_AUX_ENTRY("reserved_4", hw.reserved_4, "%u"); + __HAL_AUX_ENTRY("rmac_jabber_frms", hw.rmac_jabber_frms, "%u"); + __HAL_AUX_ENTRY("rmac_ttl_64_frms", (unsigned long long) + hw.rmac_ttl_64_frms, "%llu"); + __HAL_AUX_ENTRY("rmac_ttl_65_127_frms", (unsigned long long) + hw.rmac_ttl_65_127_frms, "%llu"); + __HAL_AUX_ENTRY("reserved_5", (unsigned long long) + hw.reserved_5, "%llu"); + __HAL_AUX_ENTRY("rmac_ttl_128_255_frms", (unsigned long long) + hw.rmac_ttl_128_255_frms, "%llu"); + __HAL_AUX_ENTRY("rmac_ttl_256_511_frms", (unsigned long long) + hw.rmac_ttl_256_511_frms, "%llu"); + __HAL_AUX_ENTRY("reserved_6", (unsigned long long) + hw.reserved_6, "%llu"); + __HAL_AUX_ENTRY("rmac_ttl_512_1023_frms", (unsigned long long) + hw.rmac_ttl_512_1023_frms, "%llu"); + __HAL_AUX_ENTRY("rmac_ttl_1024_1518_frms", (unsigned long long) + hw.rmac_ttl_1024_1518_frms, "%llu"); + __HAL_AUX_ENTRY("rmac_ip", hw.rmac_ip, "%u"); + __HAL_AUX_ENTRY("reserved_7", hw.reserved_7, "%u"); + __HAL_AUX_ENTRY("rmac_ip_octets", (unsigned long long) + hw.rmac_ip_octets, "%llu"); + __HAL_AUX_ENTRY("rmac_drop_ip", hw.rmac_drop_ip, "%u"); + __HAL_AUX_ENTRY("rmac_hdr_err_ip", hw.rmac_hdr_err_ip, "%u"); + __HAL_AUX_ENTRY("reserved_8", hw.reserved_8, "%u"); + __HAL_AUX_ENTRY("rmac_icmp", hw.rmac_icmp, "%u"); + __HAL_AUX_ENTRY("rmac_tcp", (unsigned long long) + hw.rmac_tcp, "%llu"); + __HAL_AUX_ENTRY("rmac_err_drp_udp", hw.rmac_err_drp_udp, "%u"); + __HAL_AUX_ENTRY("rmac_udp", hw.rmac_udp, "%u"); + __HAL_AUX_ENTRY("rmac_xgmii_err_sym", (unsigned long long) + hw.rmac_xgmii_err_sym, "%llu"); + __HAL_AUX_ENTRY("rmac_frms_q0", (unsigned long long) + hw.rmac_frms_q0, "%llu"); + __HAL_AUX_ENTRY("rmac_frms_q1", (unsigned long long) + hw.rmac_frms_q1, "%llu"); + __HAL_AUX_ENTRY("rmac_frms_q2", (unsigned long long) + hw.rmac_frms_q2, "%llu"); + __HAL_AUX_ENTRY("rmac_frms_q3", (unsigned long long) + hw.rmac_frms_q3, "%llu"); + __HAL_AUX_ENTRY("rmac_frms_q4", (unsigned long long) + hw.rmac_frms_q4, "%llu"); + __HAL_AUX_ENTRY("rmac_frms_q5", (unsigned long long) + hw.rmac_frms_q5, "%llu"); + __HAL_AUX_ENTRY("rmac_frms_q6", (unsigned long long) + hw.rmac_frms_q6, "%llu"); + __HAL_AUX_ENTRY("rmac_frms_q7", (unsigned long long) + hw.rmac_frms_q7, "%llu"); + __HAL_AUX_ENTRY("rmac_full_q3", hw.rmac_full_q3, "%d"); + __HAL_AUX_ENTRY("rmac_full_q2", hw.rmac_full_q2, "%d"); + __HAL_AUX_ENTRY("rmac_full_q1", hw.rmac_full_q1, "%d"); + __HAL_AUX_ENTRY("rmac_full_q0", hw.rmac_full_q0, "%d"); + __HAL_AUX_ENTRY("rmac_full_q7", hw.rmac_full_q7, "%d"); + __HAL_AUX_ENTRY("rmac_full_q6", hw.rmac_full_q6, "%d"); + __HAL_AUX_ENTRY("rmac_full_q5", hw.rmac_full_q5, "%d"); + __HAL_AUX_ENTRY("rmac_full_q4", hw.rmac_full_q4, "%d"); + __HAL_AUX_ENTRY("reserved_9", hw.reserved_9, "%u"); + __HAL_AUX_ENTRY("rmac_pause_cnt", hw.rmac_pause_cnt, "%u"); + __HAL_AUX_ENTRY("rmac_xgmii_data_err_cnt", (unsigned long long) + hw.rmac_xgmii_data_err_cnt, "%llu"); + __HAL_AUX_ENTRY("rmac_xgmii_ctrl_err_cnt", (unsigned long long) + hw.rmac_xgmii_ctrl_err_cnt, "%llu"); + __HAL_AUX_ENTRY("rmac_err_tcp", hw.rmac_err_tcp, "%u"); + __HAL_AUX_ENTRY("rmac_accepted_ip", hw.rmac_accepted_ip, "%u"); + } else { + int i; + xge_hal_mgmt_pcim_stats_t pcim; + status = xge_hal_mgmt_pcim_stats(devh, &pcim, + sizeof(xge_hal_mgmt_pcim_stats_t)); + if (status != XGE_HAL_OK) { + return status; + } + for (i = 0; i < XGE_HAL_MAC_LINKS; i++) { + __hal_aux_pci_link_info("rx_ttl_frms", i, + rx_ttl_frms); + __hal_aux_pci_link_info("rx_vld_frms", i, + rx_vld_frms); + __hal_aux_pci_link_info("rx_offld_frms", i, + rx_offld_frms); + __hal_aux_pci_link_info("rx_ttl_eth_octets", i, + rx_ttl_eth_octets); + __hal_aux_pci_link_info("rx_data_octets", i, + rx_data_octets); + __hal_aux_pci_link_info("rx_offld_octets", i, + rx_offld_octets); + __hal_aux_pci_link_info("rx_vld_mcst_frms", i, + rx_vld_mcst_frms); + __hal_aux_pci_link_info("rx_vld_bcst_frms", i, + rx_vld_bcst_frms); + __hal_aux_pci_link_info("rx_accepted_ucst_frms", i, + rx_accepted_ucst_frms); + __hal_aux_pci_link_info("rx_accepted_nucst_frms", i, + rx_accepted_nucst_frms); + __hal_aux_pci_link_info("rx_tagged_frms", i, + rx_tagged_frms); + __hal_aux_pci_link_info("rx_long_frms", i, + rx_long_frms); + __hal_aux_pci_link_info("rx_usized_frms", i, + rx_usized_frms); + __hal_aux_pci_link_info("rx_osized_frms", i, + rx_osized_frms); + __hal_aux_pci_link_info("rx_frag_frms", i, + rx_frag_frms); + __hal_aux_pci_link_info("rx_jabber_frms", i, + rx_jabber_frms); + __hal_aux_pci_link_info("rx_ttl_64_frms", i, + rx_ttl_64_frms); + __hal_aux_pci_link_info("rx_ttl_65_127_frms", i, + rx_ttl_65_127_frms); + __hal_aux_pci_link_info("rx_ttl_128_255_frms", i, + rx_ttl_128_255_frms); + __hal_aux_pci_link_info("rx_ttl_256_511_frms", i, + rx_ttl_256_511_frms); + __hal_aux_pci_link_info("rx_ttl_512_1023_frms", i, + rx_ttl_512_1023_frms); + __hal_aux_pci_link_info("rx_ttl_1024_1518_frms", i, + rx_ttl_1024_1518_frms); + __hal_aux_pci_link_info("rx_ttl_1519_4095_frms", i, + rx_ttl_1519_4095_frms); + __hal_aux_pci_link_info("rx_ttl_40956_8191_frms", i, + rx_ttl_40956_8191_frms); + __hal_aux_pci_link_info("rx_ttl_8192_max_frms", i, + rx_ttl_8192_max_frms); + __hal_aux_pci_link_info("rx_ttl_gt_max_frms", i, + rx_ttl_gt_max_frms); + __hal_aux_pci_link_info("rx_ip", i, + rx_ip); + __hal_aux_pci_link_info("rx_ip_octets", i, + rx_ip_octets); + + __hal_aux_pci_link_info("rx_hdr_err_ip", i, + rx_hdr_err_ip); + + __hal_aux_pci_link_info("rx_icmp", i, + rx_icmp); + __hal_aux_pci_link_info("rx_tcp", i, + rx_tcp); + __hal_aux_pci_link_info("rx_udp", i, + rx_udp); + __hal_aux_pci_link_info("rx_err_tcp", i, + rx_err_tcp); + __hal_aux_pci_link_info("rx_pause_cnt", i, + rx_pause_cnt); + __hal_aux_pci_link_info("rx_pause_ctrl_frms", i, + rx_pause_ctrl_frms); + __hal_aux_pci_link_info("rx_unsup_ctrl_frms", i, + rx_pause_cnt); + __hal_aux_pci_link_info("rx_in_rng_len_err_frms", i, + rx_in_rng_len_err_frms); + __hal_aux_pci_link_info("rx_out_rng_len_err_frms", i, + rx_out_rng_len_err_frms); + __hal_aux_pci_link_info("rx_drop_frms", i, + rx_drop_frms); + __hal_aux_pci_link_info("rx_discarded_frms", i, + rx_discarded_frms); + __hal_aux_pci_link_info("rx_drop_ip", i, + rx_drop_ip); + __hal_aux_pci_link_info("rx_err_drp_udp", i, + rx_err_drp_udp); + __hal_aux_pci_link_info("rx_lacpdu_frms", i, + rx_lacpdu_frms); + __hal_aux_pci_link_info("rx_marker_pdu_frms", i, + rx_marker_pdu_frms); + __hal_aux_pci_link_info("rx_marker_resp_pdu_frms", i, + rx_marker_resp_pdu_frms); + __hal_aux_pci_link_info("rx_unknown_pdu_frms", i, + rx_unknown_pdu_frms); + __hal_aux_pci_link_info("rx_illegal_pdu_frms", i, + rx_illegal_pdu_frms); + __hal_aux_pci_link_info("rx_fcs_discard", i, + rx_fcs_discard); + __hal_aux_pci_link_info("rx_len_discard", i, + rx_len_discard); + __hal_aux_pci_link_info("rx_pf_discard", i, + rx_pf_discard); + __hal_aux_pci_link_info("rx_trash_discard", i, + rx_trash_discard); + __hal_aux_pci_link_info("rx_rts_discard", i, + rx_trash_discard); + __hal_aux_pci_link_info("rx_wol_discard", i, + rx_wol_discard); + __hal_aux_pci_link_info("rx_red_discard", i, + rx_red_discard); + __hal_aux_pci_link_info("rx_ingm_full_discard", i, + rx_ingm_full_discard); + __hal_aux_pci_link_info("rx_xgmii_data_err_cnt", i, + rx_xgmii_data_err_cnt); + __hal_aux_pci_link_info("rx_xgmii_ctrl_err_cnt", i, + rx_xgmii_ctrl_err_cnt); + __hal_aux_pci_link_info("rx_xgmii_err_sym", i, + rx_xgmii_err_sym); + __hal_aux_pci_link_info("rx_xgmii_char1_match", i, + rx_xgmii_char1_match); + __hal_aux_pci_link_info("rx_xgmii_char2_match", i, + rx_xgmii_char2_match); + __hal_aux_pci_link_info("rx_xgmii_column1_match", i, + rx_xgmii_column1_match); + __hal_aux_pci_link_info("rx_xgmii_column2_match", i, + rx_xgmii_column2_match); + __hal_aux_pci_link_info("rx_local_fault", i, + rx_local_fault); + __hal_aux_pci_link_info("rx_remote_fault", i, + rx_remote_fault); + __hal_aux_pci_link_info("rx_queue_full", i, + rx_queue_full); + } + for (i = 0; i < XGE_HAL_MAC_AGGREGATORS; i++) { + __hal_aux_pci_aggr_info("rx_frms", i, rx_frms); + __hal_aux_pci_link_info("rx_data_octets", i, + rx_data_octets); + __hal_aux_pci_aggr_info("rx_mcst_frms", i, + rx_mcst_frms); + __hal_aux_pci_aggr_info("rx_bcst_frms", i, + rx_bcst_frms); + __hal_aux_pci_aggr_info("rx_discarded_frms", i, + rx_discarded_frms); + __hal_aux_pci_aggr_info("rx_errored_frms", i, + rx_errored_frms); + __hal_aux_pci_aggr_info("rx_unknown_protocol_frms", i, + rx_unknown_protocol_frms); + } + + } + __HAL_AUX_ENTRY_END(bufsize, retsize); + + return XGE_HAL_OK; +} + +/** + * xge_hal_aux_stats_herc_enchanced - Get Hercules hardware statistics. + * @devh: HAL device handle. + * @bufsize: Buffer size. + * @retbuf: Buffer pointer. + * @retsize: Size of the result. Cannot be greater than @bufsize. + * + * Read Hercules device hardware statistics. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. + * + * See also: xge_hal_mgmt_hw_stats{}, xge_hal_stats_hw_info_t{}, + * xge_hal_aux_stats_tmac_read(), xge_hal_aux_stats_rmac_read(), + * xge_hal_aux_device_dump(). +*/ +xge_hal_status_e xge_hal_aux_stats_herc_enchanced(xge_hal_device_h devh, + int bufsize, char *retbuf, int *retsize) +{ + xge_hal_status_e status; + xge_hal_mgmt_hw_stats_t hw; + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + + __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf); + + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_TITAN) { + + __HAL_AUX_ENTRY_END(bufsize, retsize); + + return XGE_HAL_OK; + } + + + status = xge_hal_mgmt_hw_stats(devh, &hw, + sizeof(xge_hal_mgmt_hw_stats_t)); + if (status != XGE_HAL_OK) { + return status; + } + __HAL_AUX_ENTRY("tmac_frms_oflow", hw.tmac_frms_oflow, "%u"); + __HAL_AUX_ENTRY("tmac_data_octets_oflow", hw.tmac_data_octets_oflow, + "%u"); + __HAL_AUX_ENTRY("tmac_mcst_frms_oflow", hw.tmac_mcst_frms_oflow, "%u"); + __HAL_AUX_ENTRY("tmac_bcst_frms_oflow", hw.tmac_bcst_frms_oflow, "%u"); + __HAL_AUX_ENTRY("tmac_ttl_octets_oflow", hw.tmac_ttl_octets_oflow, + "%u"); + __HAL_AUX_ENTRY("tmac_ucst_frms_oflow", hw.tmac_ucst_frms_oflow, "%u"); + __HAL_AUX_ENTRY("tmac_nucst_frms_oflow", hw.tmac_nucst_frms_oflow, + "%u"); + __HAL_AUX_ENTRY("tmac_any_err_frms_oflow", hw.tmac_any_err_frms_oflow, + "%u"); + __HAL_AUX_ENTRY("tmac_vlan_frms", (unsigned long long)hw.tmac_vlan_frms, + "%llu"); + __HAL_AUX_ENTRY("tmac_vld_ip_oflow", hw.tmac_vld_ip_oflow, "%u"); + __HAL_AUX_ENTRY("tmac_drop_ip_oflow", hw.tmac_drop_ip_oflow, "%u"); + __HAL_AUX_ENTRY("tmac_icmp_oflow", hw.tmac_icmp_oflow, "%u"); + __HAL_AUX_ENTRY("tmac_rst_tcp_oflow", hw.tmac_rst_tcp_oflow, "%u"); + __HAL_AUX_ENTRY("tmac_udp_oflow", hw.tmac_udp_oflow, "%u"); + __HAL_AUX_ENTRY("tpa_unknown_protocol", hw.tpa_unknown_protocol, "%u"); + __HAL_AUX_ENTRY("tpa_parse_failure", hw.tpa_parse_failure, "%u"); + __HAL_AUX_ENTRY("rmac_vld_frms_oflow", hw.rmac_vld_frms_oflow, "%u"); + __HAL_AUX_ENTRY("rmac_data_octets_oflow", hw.rmac_data_octets_oflow, + "%u"); + __HAL_AUX_ENTRY("rmac_vld_mcst_frms_oflow", hw.rmac_vld_mcst_frms_oflow, + "%u"); + __HAL_AUX_ENTRY("rmac_vld_bcst_frms_oflow", hw.rmac_vld_bcst_frms_oflow, + "%u"); + __HAL_AUX_ENTRY("rmac_ttl_octets_oflow", hw.rmac_ttl_octets_oflow, + "%u"); + __HAL_AUX_ENTRY("rmac_accepted_ucst_frms_oflow", + hw.rmac_accepted_ucst_frms_oflow, "%u"); + __HAL_AUX_ENTRY("rmac_accepted_nucst_frms_oflow", + hw.rmac_accepted_nucst_frms_oflow, "%u"); + __HAL_AUX_ENTRY("rmac_discarded_frms_oflow", + hw.rmac_discarded_frms_oflow, "%u"); + __HAL_AUX_ENTRY("rmac_drop_events_oflow", hw.rmac_drop_events_oflow, + "%u"); + __HAL_AUX_ENTRY("rmac_usized_frms_oflow", hw.rmac_usized_frms_oflow, + "%u"); + __HAL_AUX_ENTRY("rmac_osized_frms_oflow", hw.rmac_osized_frms_oflow, + "%u"); + __HAL_AUX_ENTRY("rmac_frag_frms_oflow", hw.rmac_frag_frms_oflow, "%u"); + __HAL_AUX_ENTRY("rmac_jabber_frms_oflow", hw.rmac_jabber_frms_oflow, + "%u"); + __HAL_AUX_ENTRY("rmac_ip_oflow", hw.rmac_ip_oflow, "%u"); + __HAL_AUX_ENTRY("rmac_drop_ip_oflow", hw.rmac_drop_ip_oflow, "%u"); + __HAL_AUX_ENTRY("rmac_icmp_oflow", hw.rmac_icmp_oflow, "%u"); + __HAL_AUX_ENTRY("rmac_udp_oflow", hw.rmac_udp_oflow, "%u"); + __HAL_AUX_ENTRY("rmac_err_drp_udp_oflow", hw.rmac_err_drp_udp_oflow, + "%u"); + __HAL_AUX_ENTRY("rmac_pause_cnt_oflow", hw.rmac_pause_cnt_oflow, "%u"); + __HAL_AUX_ENTRY("rmac_ttl_1519_4095_frms", + (unsigned long long)hw.rmac_ttl_1519_4095_frms, "%llu"); + __HAL_AUX_ENTRY("rmac_ttl_4096_8191_frms", + (unsigned long long)hw.rmac_ttl_4096_8191_frms, "%llu"); + __HAL_AUX_ENTRY("rmac_ttl_8192_max_frms", + (unsigned long long)hw.rmac_ttl_8192_max_frms, "%llu"); + __HAL_AUX_ENTRY("rmac_ttl_gt_max_frms", + (unsigned long long)hw.rmac_ttl_gt_max_frms, "%llu"); + __HAL_AUX_ENTRY("rmac_osized_alt_frms", + (unsigned long long)hw.rmac_osized_alt_frms, "%llu"); + __HAL_AUX_ENTRY("rmac_jabber_alt_frms", + (unsigned long long)hw.rmac_jabber_alt_frms, "%llu"); + __HAL_AUX_ENTRY("rmac_gt_max_alt_frms", + (unsigned long long)hw.rmac_gt_max_alt_frms, "%llu"); + __HAL_AUX_ENTRY("rmac_vlan_frms", + (unsigned long long)hw.rmac_vlan_frms, "%llu"); + __HAL_AUX_ENTRY("rmac_fcs_discard", hw.rmac_fcs_discard, "%u"); + __HAL_AUX_ENTRY("rmac_len_discard", hw.rmac_len_discard, "%u"); + __HAL_AUX_ENTRY("rmac_da_discard", hw.rmac_da_discard, "%u"); + __HAL_AUX_ENTRY("rmac_pf_discard", hw.rmac_pf_discard, "%u"); + __HAL_AUX_ENTRY("rmac_rts_discard", hw.rmac_rts_discard, "%u"); + __HAL_AUX_ENTRY("rmac_red_discard", hw.rmac_red_discard, "%u"); + __HAL_AUX_ENTRY("rmac_ingm_full_discard", hw.rmac_ingm_full_discard, + "%u"); + __HAL_AUX_ENTRY("rmac_accepted_ip_oflow", hw.rmac_accepted_ip_oflow, + "%u"); + __HAL_AUX_ENTRY("link_fault_cnt", hw.link_fault_cnt, "%u"); + + __HAL_AUX_ENTRY_END(bufsize, retsize); + + return XGE_HAL_OK; +} + +/** + * xge_hal_aux_stats_rmac_read - Read PCI hardware statistics. + * @devh: HAL device handle. + * @bufsize: Buffer size. + * @retbuf: Buffer pointer. + * @retsize: Size of the result. Cannot be greater than @bufsize. + * + * Read PCI statistics counters, including number of PCI read and + * write transactions, PCI retries, discards, etc. + * This is a subset of stats counters from xge_hal_stats_hw_info_t{}. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. + * + * See also: xge_hal_mgmt_hw_stats{}, xge_hal_stats_hw_info_t{}, + * xge_hal_aux_stats_tmac_read(), xge_hal_aux_stats_rmac_read(), + * xge_hal_aux_device_dump(). + */ +xge_hal_status_e xge_hal_aux_stats_pci_read(xge_hal_device_h devh, int bufsize, + char *retbuf, int *retsize) +{ + xge_hal_status_e status; + xge_hal_mgmt_hw_stats_t hw; + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + + __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf); + + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_TITAN) { + + __HAL_AUX_ENTRY_END(bufsize, retsize); + + return XGE_HAL_OK; + } + + + status = xge_hal_mgmt_hw_stats(devh, &hw, + sizeof(xge_hal_mgmt_hw_stats_t)); + if (status != XGE_HAL_OK) { + return status; + } + + __HAL_AUX_ENTRY("new_rd_req_cnt", hw.new_rd_req_cnt, "%u"); + __HAL_AUX_ENTRY("rd_req_cnt", hw.rd_req_cnt, "%u"); + __HAL_AUX_ENTRY("rd_rtry_cnt", hw.rd_rtry_cnt, "%u"); + __HAL_AUX_ENTRY("new_rd_req_rtry_cnt", hw.new_rd_req_rtry_cnt, "%u"); + __HAL_AUX_ENTRY("wr_req_cnt", hw.wr_req_cnt, "%u"); + __HAL_AUX_ENTRY("wr_rtry_rd_ack_cnt", hw.wr_rtry_rd_ack_cnt, "%u"); + __HAL_AUX_ENTRY("new_wr_req_rtry_cnt", hw.new_wr_req_rtry_cnt, "%u"); + __HAL_AUX_ENTRY("new_wr_req_cnt", hw.new_wr_req_cnt, "%u"); + __HAL_AUX_ENTRY("wr_disc_cnt", hw.wr_disc_cnt, "%u"); + __HAL_AUX_ENTRY("wr_rtry_cnt", hw.wr_rtry_cnt, "%u"); + __HAL_AUX_ENTRY("txp_wr_cnt", hw.txp_wr_cnt, "%u"); + __HAL_AUX_ENTRY("rd_rtry_wr_ack_cnt", hw.rd_rtry_wr_ack_cnt, "%u"); + __HAL_AUX_ENTRY("txd_wr_cnt", hw.txd_wr_cnt, "%u"); + __HAL_AUX_ENTRY("txd_rd_cnt", hw.txd_rd_cnt, "%u"); + __HAL_AUX_ENTRY("rxd_wr_cnt", hw.rxd_wr_cnt, "%u"); + __HAL_AUX_ENTRY("rxd_rd_cnt", hw.rxd_rd_cnt, "%u"); + __HAL_AUX_ENTRY("rxf_wr_cnt", hw.rxf_wr_cnt, "%u"); + __HAL_AUX_ENTRY("txf_rd_cnt", hw.txf_rd_cnt, "%u"); + + __HAL_AUX_ENTRY_END(bufsize, retsize); + + return XGE_HAL_OK; +} + +/** + * xge_hal_aux_stats_hal_read - Read HAL (layer) statistics. + * @devh: HAL device handle. + * @bufsize: Buffer size. + * @retbuf: Buffer pointer. + * @retsize: Size of the result. Cannot be greater than @bufsize. + * + * Read HAL statistics. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. + * XGE_HAL_INF_STATS_IS_NOT_READY - Statistics information is not + * currently available. + * + * See also: xge_hal_aux_device_dump(). + */ +xge_hal_status_e xge_hal_aux_stats_hal_read(xge_hal_device_h devh, + int bufsize, char *retbuf, int *retsize) +{ + xge_list_t *item; + xge_hal_channel_t *channel; + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + xge_hal_status_e status; + xge_hal_mgmt_device_stats_t devstat; + xge_hal_mgmt_channel_stats_t chstat; + __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf); + + status = xge_hal_mgmt_device_stats(hldev, &devstat, + sizeof(xge_hal_mgmt_device_stats_t)); + if (status != XGE_HAL_OK) { + return status; + } + + if (!hldev->config.bimodal_interrupts) { + __HAL_AUX_ENTRY("rx_traffic_intr_cnt", + devstat.rx_traffic_intr_cnt, "%u"); + } + __HAL_AUX_ENTRY("tx_traffic_intr_cnt", devstat.tx_traffic_intr_cnt, "%u"); + __HAL_AUX_ENTRY("txpic_intr_cnt", devstat.txpic_intr_cnt, "%u"); + __HAL_AUX_ENTRY("txdma_intr_cnt", devstat.txdma_intr_cnt, "%u"); + __HAL_AUX_ENTRY("txmac_intr_cnt", devstat.txmac_intr_cnt, "%u"); + __HAL_AUX_ENTRY("txxgxs_intr_cnt", devstat.txxgxs_intr_cnt, "%u"); + __HAL_AUX_ENTRY("rxpic_intr_cnt", devstat.rxpic_intr_cnt, "%u"); + __HAL_AUX_ENTRY("rxdma_intr_cnt", devstat.rxdma_intr_cnt, "%u"); + __HAL_AUX_ENTRY("rxmac_intr_cnt", devstat.rxmac_intr_cnt, "%u"); + __HAL_AUX_ENTRY("rxxgxs_intr_cnt", devstat.rxxgxs_intr_cnt, "%u"); + __HAL_AUX_ENTRY("mc_intr_cnt", devstat.mc_intr_cnt, "%u"); + __HAL_AUX_ENTRY("not_xge_intr_cnt", devstat.not_xge_intr_cnt, "%u"); + __HAL_AUX_ENTRY("not_traffic_intr_cnt", + devstat.not_traffic_intr_cnt, "%u"); + __HAL_AUX_ENTRY("traffic_intr_cnt", devstat.traffic_intr_cnt, "%u"); + __HAL_AUX_ENTRY("total_intr_cnt", devstat.total_intr_cnt, "%u"); + __HAL_AUX_ENTRY("soft_reset_cnt", devstat.soft_reset_cnt, "%u"); + + if (hldev->config.rxufca_hi_lim != hldev->config.rxufca_lo_lim && + hldev->config.rxufca_lo_lim != 0) { + __HAL_AUX_ENTRY("rxufca_lo_adjust_cnt", + devstat.rxufca_lo_adjust_cnt, "%u"); + __HAL_AUX_ENTRY("rxufca_hi_adjust_cnt", + devstat.rxufca_hi_adjust_cnt, "%u"); + } + + if (hldev->config.bimodal_interrupts) { + __HAL_AUX_ENTRY("bimodal_lo_adjust_cnt", + devstat.bimodal_lo_adjust_cnt, "%u"); + __HAL_AUX_ENTRY("bimodal_hi_adjust_cnt", + devstat.bimodal_hi_adjust_cnt, "%u"); + } + +#if defined(XGE_HAL_CONFIG_LRO) + __HAL_AUX_ENTRY("tot_frms_lroised", + devstat.tot_frms_lroised, "%u"); + __HAL_AUX_ENTRY("tot_lro_sessions", + devstat.tot_lro_sessions, "%u"); + __HAL_AUX_ENTRY("lro_frm_len_exceed_cnt", + devstat.lro_frm_len_exceed_cnt, "%u"); + __HAL_AUX_ENTRY("lro_sg_exceed_cnt", + devstat.lro_sg_exceed_cnt, "%u"); + __HAL_AUX_ENTRY("lro_out_of_seq_pkt_cnt", + devstat.lro_out_of_seq_pkt_cnt, "%u"); + __HAL_AUX_ENTRY("lro_dup_pkt_cnt", + devstat.lro_dup_pkt_cnt, "%u"); +#endif + + /* for each opened rx channel */ + xge_list_for_each(item, &hldev->ring_channels) { + char key[XGE_OS_SPRINTF_STRLEN]; + channel = xge_container_of(item, xge_hal_channel_t, item); + + status = xge_hal_mgmt_channel_stats(channel, &chstat, + sizeof(xge_hal_mgmt_channel_stats_t)); + if (status != XGE_HAL_OK) { + return status; + } + + (void) xge_os_sprintf(key, "ring%d_", channel->post_qid); + + xge_os_strcpy(key+6, "full_cnt"); + __HAL_AUX_ENTRY(key, chstat.full_cnt, "%u"); + xge_os_strcpy(key+6, "usage_max"); + __HAL_AUX_ENTRY(key, chstat.usage_max, "%u"); + xge_os_strcpy(key+6, "usage_cnt"); + __HAL_AUX_ENTRY(key, channel->usage_cnt, "%u"); + xge_os_strcpy(key+6, "reserve_free_swaps_cnt"); + __HAL_AUX_ENTRY(key, chstat.reserve_free_swaps_cnt, "%u"); + if (!hldev->config.bimodal_interrupts) { + xge_os_strcpy(key+6, "avg_compl_per_intr_cnt"); + __HAL_AUX_ENTRY(key, chstat.avg_compl_per_intr_cnt, "%u"); + } + xge_os_strcpy(key+6, "total_compl_cnt"); + __HAL_AUX_ENTRY(key, chstat.total_compl_cnt, "%u"); + xge_os_strcpy(key+6, "bump_cnt"); + __HAL_AUX_ENTRY(key, chstat.ring_bump_cnt, "%u"); + } + + /* for each opened tx channel */ + xge_list_for_each(item, &hldev->fifo_channels) { + char key[XGE_OS_SPRINTF_STRLEN]; + channel = xge_container_of(item, xge_hal_channel_t, item); + + status = xge_hal_mgmt_channel_stats(channel, &chstat, + sizeof(xge_hal_mgmt_channel_stats_t)); + if (status != XGE_HAL_OK) { + return status; + } + + (void) xge_os_sprintf(key, "fifo%d_", channel->post_qid); + + xge_os_strcpy(key+6, "full_cnt"); + __HAL_AUX_ENTRY(key, chstat.full_cnt, "%u"); + xge_os_strcpy(key+6, "usage_max"); + __HAL_AUX_ENTRY(key, chstat.usage_max, "%u"); + xge_os_strcpy(key+6, "usage_cnt"); + __HAL_AUX_ENTRY(key, channel->usage_cnt, "%u"); + xge_os_strcpy(key+6, "reserve_free_swaps_cnt"); + __HAL_AUX_ENTRY(key, chstat.reserve_free_swaps_cnt, "%u"); + xge_os_strcpy(key+6, "avg_compl_per_intr_cnt"); + __HAL_AUX_ENTRY(key, chstat.avg_compl_per_intr_cnt, "%u"); + xge_os_strcpy(key+6, "total_compl_cnt"); + __HAL_AUX_ENTRY(key, chstat.total_compl_cnt, "%u"); + xge_os_strcpy(key+6, "total_posts"); + __HAL_AUX_ENTRY(key, chstat.total_posts, "%u"); + xge_os_strcpy(key+6, "total_posts_many"); + __HAL_AUX_ENTRY(key, chstat.total_posts_many, "%u"); + xge_os_strcpy(key+6, "copied_frags"); + __HAL_AUX_ENTRY(key, chstat.copied_frags, "%u"); + xge_os_strcpy(key+6, "copied_buffers"); + __HAL_AUX_ENTRY(key, chstat.copied_buffers, "%u"); + xge_os_strcpy(key+6, "total_buffers"); + __HAL_AUX_ENTRY(key, chstat.total_buffers, "%u"); + xge_os_strcpy(key+6, "avg_buffers_per_post"); + __HAL_AUX_ENTRY(key, chstat.avg_buffers_per_post, "%u"); + xge_os_strcpy(key+6, "avg_buffer_size"); + __HAL_AUX_ENTRY(key, chstat.avg_buffer_size, "%u"); + xge_os_strcpy(key+6, "avg_post_size"); + __HAL_AUX_ENTRY(key, chstat.avg_post_size, "%u"); + xge_os_strcpy(key+6, "total_posts_dtrs_many"); + __HAL_AUX_ENTRY(key, chstat.total_posts_dtrs_many, "%u"); + xge_os_strcpy(key+6, "total_posts_frags_many"); + __HAL_AUX_ENTRY(key, chstat.total_posts_frags_many, "%u"); + xge_os_strcpy(key+6, "total_posts_dang_dtrs"); + __HAL_AUX_ENTRY(key, chstat.total_posts_dang_dtrs, "%u"); + xge_os_strcpy(key+6, "total_posts_dang_frags"); + __HAL_AUX_ENTRY(key, chstat.total_posts_dang_frags, "%u"); + } + + __HAL_AUX_ENTRY_END(bufsize, retsize); + + return XGE_HAL_OK; +} + + + +/** + * xge_hal_aux_stats_sw_dev_read - Read software device statistics. + * @devh: HAL device handle. + * @bufsize: Buffer size. + * @retbuf: Buffer pointer. + * @retsize: Size of the result. Cannot be greater than @bufsize. + * + * Read software-maintained device statistics. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. + * XGE_HAL_INF_STATS_IS_NOT_READY - Statistics information is not + * currently available. + * + * See also: xge_hal_aux_device_dump(). + */ +xge_hal_status_e xge_hal_aux_stats_sw_dev_read(xge_hal_device_h devh, + int bufsize, char *retbuf, int *retsize) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + xge_hal_status_e status; + xge_hal_mgmt_sw_stats_t sw_dev_err_stats; + int t_code; + char buf[XGE_OS_SPRINTF_STRLEN]; + + __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf); + + status = xge_hal_mgmt_sw_stats(hldev, &sw_dev_err_stats, + sizeof(xge_hal_mgmt_sw_stats_t)); + if (status != XGE_HAL_OK) { + return status; + } + + __HAL_AUX_ENTRY("sm_err_cnt",sw_dev_err_stats.sm_err_cnt, "%u"); + __HAL_AUX_ENTRY("single_ecc_err_cnt",sw_dev_err_stats.single_ecc_err_cnt, "%u"); + __HAL_AUX_ENTRY("double_ecc_err_cnt",sw_dev_err_stats.double_ecc_err_cnt, "%u"); + __HAL_AUX_ENTRY("ecc_err_cnt", sw_dev_err_stats.ecc_err_cnt, "%u"); + __HAL_AUX_ENTRY("parity_err_cnt",sw_dev_err_stats.parity_err_cnt, "%u"); + __HAL_AUX_ENTRY("serr_cnt",sw_dev_err_stats.serr_cnt, "%u"); + + for (t_code = 1; t_code < 16; t_code++) { + int t_code_cnt = sw_dev_err_stats.rxd_t_code_err_cnt[t_code]; + if (t_code_cnt) { + (void) xge_os_sprintf(buf, "rxd_t_code_%d", t_code); + __HAL_AUX_ENTRY(buf, t_code_cnt, "%u"); + } + t_code_cnt = sw_dev_err_stats.txd_t_code_err_cnt[t_code]; + if (t_code_cnt) { + (void) xge_os_sprintf(buf, "txd_t_code_%d", t_code); + __HAL_AUX_ENTRY(buf, t_code_cnt, "%u"); + } + } + __HAL_AUX_ENTRY("alarm_transceiver_temp_high",sw_dev_err_stats. + stats_xpak.alarm_transceiver_temp_high, "%u"); + __HAL_AUX_ENTRY("alarm_transceiver_temp_low",sw_dev_err_stats. + stats_xpak.alarm_transceiver_temp_low, "%u"); + __HAL_AUX_ENTRY("alarm_laser_bias_current_high",sw_dev_err_stats. + stats_xpak.alarm_laser_bias_current_high, "%u"); + __HAL_AUX_ENTRY("alarm_laser_bias_current_low",sw_dev_err_stats. + stats_xpak.alarm_laser_bias_current_low, "%u"); + __HAL_AUX_ENTRY("alarm_laser_output_power_high",sw_dev_err_stats. + stats_xpak.alarm_laser_output_power_high, "%u"); + __HAL_AUX_ENTRY("alarm_laser_output_power_low",sw_dev_err_stats. + stats_xpak.alarm_laser_output_power_low, "%u"); + __HAL_AUX_ENTRY("warn_transceiver_temp_high",sw_dev_err_stats. + stats_xpak.warn_transceiver_temp_high, "%u"); + __HAL_AUX_ENTRY("warn_transceiver_temp_low",sw_dev_err_stats. + stats_xpak.warn_transceiver_temp_low, "%u"); + __HAL_AUX_ENTRY("warn_laser_bias_current_high",sw_dev_err_stats. + stats_xpak.warn_laser_bias_current_high, "%u"); + __HAL_AUX_ENTRY("warn_laser_bias_current_low",sw_dev_err_stats. + stats_xpak.warn_laser_bias_current_low, "%u"); + __HAL_AUX_ENTRY("warn_laser_output_power_high",sw_dev_err_stats. + stats_xpak.warn_laser_output_power_high, "%u"); + __HAL_AUX_ENTRY("warn_laser_output_power_low",sw_dev_err_stats. + stats_xpak.warn_laser_output_power_low, "%u"); + + __HAL_AUX_ENTRY_END(bufsize, retsize); + + return XGE_HAL_OK; +} + +/** + * xge_hal_aux_pci_config_read - Retrieve and format PCI Configuration + * info. + * @devh: HAL device handle. + * @bufsize: Buffer size. + * @retbuf: Buffer pointer. + * @retsize: Size of the result. Cannot be greater than @bufsize. + * + * Retrieve about info (using xge_hal_mgmt_pci_config()) and sprintf it + * into the provided @retbuf. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. + * + * See also: xge_hal_mgmt_pci_config(), xge_hal_aux_device_dump(). + */ +xge_hal_status_e xge_hal_aux_pci_config_read(xge_hal_device_h devh, int bufsize, + char *retbuf, int *retsize) +{ + xge_hal_status_e status; + xge_hal_mgmt_pci_config_t pci_config; + __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf); + + status = xge_hal_mgmt_pci_config(devh, &pci_config, + sizeof(xge_hal_mgmt_pci_config_t)); + if (status != XGE_HAL_OK) { + return status; + } + + __HAL_AUX_ENTRY("vendor_id", pci_config.vendor_id, "0x%04X"); + __HAL_AUX_ENTRY("device_id", pci_config.device_id, "0x%04X"); + __HAL_AUX_ENTRY("command", pci_config.command, "0x%04X"); + __HAL_AUX_ENTRY("status", pci_config.status, "0x%04X"); + __HAL_AUX_ENTRY("revision", pci_config.revision, "0x%02X"); + __HAL_AUX_ENTRY("pciClass1", pci_config.pciClass[0], "0x%02X"); + __HAL_AUX_ENTRY("pciClass2", pci_config.pciClass[1], "0x%02X"); + __HAL_AUX_ENTRY("pciClass3", pci_config.pciClass[2], "0x%02X"); + __HAL_AUX_ENTRY("cache_line_size", + pci_config.cache_line_size, "0x%02X"); + __HAL_AUX_ENTRY("latency_timer", pci_config.latency_timer, "0x%02X"); + __HAL_AUX_ENTRY("header_type", pci_config.header_type, "0x%02X"); + __HAL_AUX_ENTRY("bist", pci_config.bist, "0x%02X"); + __HAL_AUX_ENTRY("base_addr0_lo", pci_config.base_addr0_lo, "0x%08X"); + __HAL_AUX_ENTRY("base_addr0_hi", pci_config.base_addr0_hi, "0x%08X"); + __HAL_AUX_ENTRY("base_addr1_lo", pci_config.base_addr1_lo, "0x%08X"); + __HAL_AUX_ENTRY("base_addr1_hi", pci_config.base_addr1_hi, "0x%08X"); + __HAL_AUX_ENTRY("not_Implemented1", + pci_config.not_Implemented1, "0x%08X"); + __HAL_AUX_ENTRY("not_Implemented2", pci_config.not_Implemented2, + "0x%08X"); + __HAL_AUX_ENTRY("cardbus_cis_pointer", pci_config.cardbus_cis_pointer, + "0x%08X"); + __HAL_AUX_ENTRY("subsystem_vendor_id", pci_config.subsystem_vendor_id, + "0x%04X"); + __HAL_AUX_ENTRY("subsystem_id", pci_config.subsystem_id, "0x%04X"); + __HAL_AUX_ENTRY("rom_base", pci_config.rom_base, "0x%08X"); + __HAL_AUX_ENTRY("capabilities_pointer", + pci_config.capabilities_pointer, "0x%02X"); + __HAL_AUX_ENTRY("interrupt_line", pci_config.interrupt_line, "0x%02X"); + __HAL_AUX_ENTRY("interrupt_pin", pci_config.interrupt_pin, "0x%02X"); + __HAL_AUX_ENTRY("min_grant", pci_config.min_grant, "0x%02X"); + __HAL_AUX_ENTRY("max_latency", pci_config.max_latency, "0x%02X"); + __HAL_AUX_ENTRY("msi_cap_id", pci_config.msi_cap_id, "0x%02X"); + __HAL_AUX_ENTRY("msi_next_ptr", pci_config.msi_next_ptr, "0x%02X"); + __HAL_AUX_ENTRY("msi_control", pci_config.msi_control, "0x%04X"); + __HAL_AUX_ENTRY("msi_lower_address", pci_config.msi_lower_address, + "0x%08X"); + __HAL_AUX_ENTRY("msi_higher_address", pci_config.msi_higher_address, + "0x%08X"); + __HAL_AUX_ENTRY("msi_data", pci_config.msi_data, "0x%04X"); + __HAL_AUX_ENTRY("msi_unused", pci_config.msi_unused, "0x%04X"); + __HAL_AUX_ENTRY("vpd_cap_id", pci_config.vpd_cap_id, "0x%02X"); + __HAL_AUX_ENTRY("vpd_next_cap", pci_config.vpd_next_cap, "0x%02X"); + __HAL_AUX_ENTRY("vpd_addr", pci_config.vpd_addr, "0x%04X"); + __HAL_AUX_ENTRY("vpd_data", pci_config.vpd_data, "0x%08X"); + __HAL_AUX_ENTRY("pcix_cap", pci_config.pcix_cap, "0x%02X"); + __HAL_AUX_ENTRY("pcix_next_cap", pci_config.pcix_next_cap, "0x%02X"); + __HAL_AUX_ENTRY("pcix_command", pci_config.pcix_command, "0x%04X"); + __HAL_AUX_ENTRY("pcix_status", pci_config.pcix_status, "0x%08X"); + + if (xge_hal_device_check_id(devh) == XGE_HAL_CARD_HERC) { + char key[XGE_OS_SPRINTF_STRLEN]; + int i; + + for (i = 0; + i < (XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE - 0x68)/4; + i++) { + (void) xge_os_sprintf(key, "%03x:", 4*i + 0x68); + __HAL_AUX_ENTRY(key, *((int *)pci_config.rsvd_b1 + i), + "0x%08X"); + } + } + + __HAL_AUX_ENTRY_END(bufsize, retsize); + + return XGE_HAL_OK; +} + + +/** + * xge_hal_aux_channel_read - Read channels information. + * @devh: HAL device handle. + * @bufsize: Buffer size. + * @retbuf: Buffer pointer. + * @retsize: Size of the result. Cannot be greater than @bufsize. + * + * Read HAL statistics. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_OUT_OF_SPACE - Buffer size is very small. + * See also: xge_hal_aux_device_dump(). + */ +xge_hal_status_e xge_hal_aux_channel_read(xge_hal_device_h devh, + int bufsize, char *retbuf, int *retsize) +{ + xge_list_t *item; + xge_hal_channel_t *channel; + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf); + + if (hldev->magic != XGE_HAL_MAGIC) { + return XGE_HAL_ERR_INVALID_DEVICE; + } + + /* for each opened rx channel */ + xge_list_for_each(item, &hldev->ring_channels) { + char key[XGE_OS_SPRINTF_STRLEN]; + channel = xge_container_of(item, xge_hal_channel_t, item); + + if (channel->is_open != 1) + continue; + + (void) xge_os_sprintf(key, "ring%d_", channel->post_qid); + xge_os_strcpy(key+6, "type"); + __HAL_AUX_ENTRY(key, channel->type, "%u"); + xge_os_strcpy(key+6, "length"); + __HAL_AUX_ENTRY(key, channel->length, "%u"); + xge_os_strcpy(key+6, "is_open"); + __HAL_AUX_ENTRY(key, channel->is_open, "%u"); + xge_os_strcpy(key+6, "reserve_initial"); + __HAL_AUX_ENTRY(key, channel->reserve_initial, "%u"); + xge_os_strcpy(key+6, "reserve_max"); + __HAL_AUX_ENTRY(key, channel->reserve_max, "%u"); + xge_os_strcpy(key+6, "reserve_length"); + __HAL_AUX_ENTRY(key, channel->reserve_length, "%u"); + xge_os_strcpy(key+6, "reserve_top"); + __HAL_AUX_ENTRY(key, channel->reserve_top, "%u"); + xge_os_strcpy(key+6, "reserve_threshold"); + __HAL_AUX_ENTRY(key, channel->reserve_threshold, "%u"); + xge_os_strcpy(key+6, "free_length"); + __HAL_AUX_ENTRY(key, channel->free_length, "%u"); + xge_os_strcpy(key+6, "post_index"); + __HAL_AUX_ENTRY(key, channel->post_index, "%u"); + xge_os_strcpy(key+6, "compl_index"); + __HAL_AUX_ENTRY(key, channel->compl_index, "%u"); + xge_os_strcpy(key+6, "per_dtr_space"); + __HAL_AUX_ENTRY(key, channel->per_dtr_space, "%u"); + xge_os_strcpy(key+6, "usage_cnt"); + __HAL_AUX_ENTRY(key, channel->usage_cnt, "%u"); + } + + /* for each opened tx channel */ + xge_list_for_each(item, &hldev->fifo_channels) { + char key[XGE_OS_SPRINTF_STRLEN]; + channel = xge_container_of(item, xge_hal_channel_t, item); + + if (channel->is_open != 1) + continue; + + (void) xge_os_sprintf(key, "fifo%d_", channel->post_qid); + xge_os_strcpy(key+6, "type"); + __HAL_AUX_ENTRY(key, channel->type, "%u"); + xge_os_strcpy(key+6, "length"); + __HAL_AUX_ENTRY(key, channel->length, "%u"); + xge_os_strcpy(key+6, "is_open"); + __HAL_AUX_ENTRY(key, channel->is_open, "%u"); + xge_os_strcpy(key+6, "reserve_initial"); + __HAL_AUX_ENTRY(key, channel->reserve_initial, "%u"); + xge_os_strcpy(key+6, "reserve_max"); + __HAL_AUX_ENTRY(key, channel->reserve_max, "%u"); + xge_os_strcpy(key+6, "reserve_length"); + __HAL_AUX_ENTRY(key, channel->reserve_length, "%u"); + xge_os_strcpy(key+6, "reserve_top"); + __HAL_AUX_ENTRY(key, channel->reserve_top, "%u"); + xge_os_strcpy(key+6, "reserve_threshold"); + __HAL_AUX_ENTRY(key, channel->reserve_threshold, "%u"); + xge_os_strcpy(key+6, "free_length"); + __HAL_AUX_ENTRY(key, channel->free_length, "%u"); + xge_os_strcpy(key+6, "post_index"); + __HAL_AUX_ENTRY(key, channel->post_index, "%u"); + xge_os_strcpy(key+6, "compl_index"); + __HAL_AUX_ENTRY(key, channel->compl_index, "%u"); + xge_os_strcpy(key+6, "per_dtr_space"); + __HAL_AUX_ENTRY(key, channel->per_dtr_space, "%u"); + xge_os_strcpy(key+6, "usage_cnt"); + __HAL_AUX_ENTRY(key, channel->usage_cnt, "%u"); + } + + __HAL_AUX_ENTRY_END(bufsize, retsize); + + return XGE_HAL_OK; +} + +/** + * xge_hal_aux_device_dump - Dump driver "about" info and device state. + * @devh: HAL device handle. + * + * Dump driver & device "about" info and device state, + * including all BAR0 registers, hardware and software statistics, PCI + * configuration space. + * See also: xge_hal_aux_about_read(), xge_hal_mgmt_reg_read(), + * xge_hal_aux_pci_config_read(), xge_hal_aux_stats_sw_dev_read(), + * xge_hal_aux_stats_tmac_read(), xge_hal_aux_stats_rmac_read(), + * xge_hal_aux_channel_read(), xge_hal_aux_stats_hal_read(). + * Returns: + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_OUT_OF_SPACE - Buffer size is very small. + */ +xge_hal_status_e +xge_hal_aux_device_dump(xge_hal_device_h devh) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + xge_hal_status_e status; + int retsize; + int offset; + u64 retval; + + xge_assert(hldev->dump_buf != NULL); + + xge_os_println("********* xge DEVICE DUMP BEGIN **********"); + + status = xge_hal_aux_about_read(hldev, XGE_HAL_DUMP_BUF_SIZE, + hldev->dump_buf, + &retsize); + if (status != XGE_HAL_OK) { + goto error; + } + xge_os_println(hldev->dump_buf); + + + for (offset = 0; offset < 1574; offset++) { + + status = xge_hal_mgmt_reg_read(hldev, 0, offset*8, &retval); + if (status != XGE_HAL_OK) { + goto error; + } + + if (!retval) continue; + + xge_os_printf("0x%04x 0x%08x%08x", offset*8, + (u32)(retval>>32), (u32)retval); + } + xge_os_println("\n"); + + status = xge_hal_aux_pci_config_read(hldev, XGE_HAL_DUMP_BUF_SIZE, + hldev->dump_buf, + &retsize); + if (status != XGE_HAL_OK) { + goto error; + } + xge_os_println(hldev->dump_buf); + + status = xge_hal_aux_stats_tmac_read(hldev, XGE_HAL_DUMP_BUF_SIZE, + hldev->dump_buf, + &retsize); + if (status != XGE_HAL_OK) { + goto error; + } + xge_os_println(hldev->dump_buf); + + status = xge_hal_aux_stats_rmac_read(hldev, XGE_HAL_DUMP_BUF_SIZE, + hldev->dump_buf, + &retsize); + if (status != XGE_HAL_OK) { + goto error; + } + xge_os_println(hldev->dump_buf); + + status = xge_hal_aux_stats_pci_read(hldev, XGE_HAL_DUMP_BUF_SIZE, + hldev->dump_buf, + &retsize); + if (status != XGE_HAL_OK) { + goto error; + } + xge_os_println(hldev->dump_buf); + + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) { + status = xge_hal_aux_stats_herc_enchanced(hldev, + XGE_HAL_DUMP_BUF_SIZE, hldev->dump_buf, &retsize); + if (status != XGE_HAL_OK) { + goto error; + } + xge_os_println(hldev->dump_buf); + } + + status = xge_hal_aux_stats_sw_dev_read(hldev, XGE_HAL_DUMP_BUF_SIZE, + hldev->dump_buf, &retsize); + if (status != XGE_HAL_OK) { + goto error; + } + xge_os_println(hldev->dump_buf); + + status = xge_hal_aux_channel_read(hldev, XGE_HAL_DUMP_BUF_SIZE, + hldev->dump_buf, + &retsize); + if (status != XGE_HAL_OK) { + goto error; + } + xge_os_println(hldev->dump_buf); + + status = xge_hal_aux_stats_hal_read(hldev, XGE_HAL_DUMP_BUF_SIZE, + hldev->dump_buf, + &retsize); + if (status != XGE_HAL_OK) { + goto error; + } + xge_os_println(hldev->dump_buf); + + xge_os_println("********* XFRAME DEVICE DUMP END **********"); + +error: + return status; +} + + +/** + * xge_hal_aux_driver_config_read - Read Driver configuration. + * @bufsize: Buffer size. + * @retbuf: Buffer pointer. + * @retsize: Size of the result. Cannot be greater than @bufsize. + * + * Read driver configuration, + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. + * + * See also: xge_hal_aux_device_config_read(). + */ +xge_hal_status_e +xge_hal_aux_driver_config_read(int bufsize, char *retbuf, int *retsize) +{ + xge_hal_status_e status; + xge_hal_driver_config_t drv_config; + __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf); + + status = xge_hal_mgmt_driver_config(&drv_config, + sizeof(xge_hal_driver_config_t)); + if (status != XGE_HAL_OK) { + return status; + } + + __HAL_AUX_ENTRY("queue size initial", + drv_config.queue_size_initial, "%u"); + __HAL_AUX_ENTRY("queue size max", drv_config.queue_size_max, "%u"); + __HAL_AUX_ENTRY_END(bufsize, retsize); + + return XGE_HAL_OK; +} + + +/** + * xge_hal_aux_device_config_read - Read device configuration. + * @devh: HAL device handle. + * @bufsize: Buffer size. + * @retbuf: Buffer pointer. + * @retsize: Size of the result. Cannot be greater than @bufsize. + * + * Read device configuration, + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_ERR_INVALID_DEVICE - Device is not valid. + * XGE_HAL_ERR_VERSION_CONFLICT - Version it not maching. + * + * See also: xge_hal_aux_driver_config_read(). + */ +xge_hal_status_e xge_hal_aux_device_config_read(xge_hal_device_h devh, + int bufsize, char *retbuf, int *retsize) +{ + int i; + xge_hal_status_e status; + xge_hal_device_config_t *dev_config; + xge_hal_device_t *hldev = (xge_hal_device_t *) devh; + char key[XGE_OS_SPRINTF_STRLEN]; + __HAL_AUX_ENTRY_DECLARE(bufsize, retbuf); + + dev_config = (xge_hal_device_config_t *) xge_os_malloc(hldev->pdev, + sizeof(xge_hal_device_config_t)); + if (dev_config == NULL) { + return XGE_HAL_FAIL; + } + + status = xge_hal_mgmt_device_config(devh, dev_config, + sizeof(xge_hal_device_config_t)); + if (status != XGE_HAL_OK) { + xge_os_free(hldev->pdev, dev_config, + sizeof(xge_hal_device_config_t)); + return status; + } + + __HAL_AUX_ENTRY("mtu", dev_config->mtu, "%u"); + __HAL_AUX_ENTRY("isr_polling_count", dev_config->isr_polling_cnt, "%u"); + __HAL_AUX_ENTRY("latency_timer", dev_config->latency_timer, "%u"); + __HAL_AUX_ENTRY("max_splits_trans", + dev_config->max_splits_trans, "%u"); + __HAL_AUX_ENTRY("mmrb_count", dev_config->mmrb_count, "%d"); + __HAL_AUX_ENTRY("shared_splits", dev_config->shared_splits, "%u"); + __HAL_AUX_ENTRY("stats_refresh_time_sec", + dev_config->stats_refresh_time_sec, "%u"); + __HAL_AUX_ENTRY("pci_freq_mherz", dev_config->pci_freq_mherz, "%u"); + __HAL_AUX_ENTRY("intr_mode", dev_config->intr_mode, "%u"); + __HAL_AUX_ENTRY("ring_memblock_size", + dev_config->ring.memblock_size, "%u"); + + __HAL_AUX_ENTRY("sched_timer_us", dev_config->sched_timer_us, "%u"); + __HAL_AUX_ENTRY("sched_timer_one_shot", + dev_config->sched_timer_one_shot, "%u"); + __HAL_AUX_ENTRY("rxufca_intr_thres", dev_config->rxufca_intr_thres, "%u"); + __HAL_AUX_ENTRY("rxufca_lo_lim", dev_config->rxufca_lo_lim, "%u"); + __HAL_AUX_ENTRY("rxufca_hi_lim", dev_config->rxufca_hi_lim, "%u"); + __HAL_AUX_ENTRY("rxufca_lbolt_period", dev_config->rxufca_lbolt_period, "%u"); + + for(i = 0; i < XGE_HAL_MAX_RING_NUM; i++) + { + xge_hal_ring_queue_t *ring = &dev_config->ring.queue[i]; + xge_hal_rti_config_t *rti = &ring->rti; + + if (!ring->configured) + continue; + + (void) xge_os_sprintf(key, "ring%d_", i); + xge_os_strcpy(key+6, "inital"); + __HAL_AUX_ENTRY(key, ring->initial, "%u"); + xge_os_strcpy(key+6, "max"); + __HAL_AUX_ENTRY(key, ring->max, "%u"); + xge_os_strcpy(key+6, "buffer_mode"); + __HAL_AUX_ENTRY(key, ring->buffer_mode, "%u"); + xge_os_strcpy(key+6, "dram_size_mb"); + __HAL_AUX_ENTRY(key, ring->dram_size_mb, "%u"); + xge_os_strcpy(key+6, "backoff_interval_us"); + __HAL_AUX_ENTRY(key, ring->backoff_interval_us, "%u"); + xge_os_strcpy(key+6, "max_frame_len"); + __HAL_AUX_ENTRY(key, ring->max_frm_len, "%d"); + xge_os_strcpy(key+6, "priority"); + __HAL_AUX_ENTRY(key, ring->priority, "%u"); + xge_os_strcpy(key+6, "rth_en"); + __HAL_AUX_ENTRY(key, ring->rth_en, "%u"); + xge_os_strcpy(key+6, "no_snoop_bits"); + __HAL_AUX_ENTRY(key, ring->no_snoop_bits, "%u"); + xge_os_strcpy(key+6, "indicate_max_pkts"); + __HAL_AUX_ENTRY(key, ring->indicate_max_pkts, "%u"); + + xge_os_strcpy(key+6, "urange_a"); + __HAL_AUX_ENTRY(key, rti->urange_a, "%u"); + xge_os_strcpy(key+6, "ufc_a"); + __HAL_AUX_ENTRY(key, rti->ufc_a, "%u"); + xge_os_strcpy(key+6, "urange_b"); + __HAL_AUX_ENTRY(key, rti->urange_b, "%u"); + xge_os_strcpy(key+6, "ufc_b"); + __HAL_AUX_ENTRY(key, rti->ufc_b, "%u"); + xge_os_strcpy(key+6, "urange_c"); + __HAL_AUX_ENTRY(key, rti->urange_c, "%u"); + xge_os_strcpy(key+6, "ufc_c"); + __HAL_AUX_ENTRY(key, rti->ufc_c, "%u"); + xge_os_strcpy(key+6, "ufc_d"); + __HAL_AUX_ENTRY(key, rti->ufc_d, "%u"); + xge_os_strcpy(key+6, "timer_val_us"); + __HAL_AUX_ENTRY(key, rti->timer_val_us, "%u"); + } + + + { + xge_hal_mac_config_t *mac= &dev_config->mac; + + __HAL_AUX_ENTRY("tmac_util_period", + mac->tmac_util_period, "%u"); + __HAL_AUX_ENTRY("rmac_util_period", + mac->rmac_util_period, "%u"); + __HAL_AUX_ENTRY("rmac_bcast_en", + mac->rmac_bcast_en, "%u"); + __HAL_AUX_ENTRY("rmac_pause_gen_en", + mac->rmac_pause_gen_en, "%d"); + __HAL_AUX_ENTRY("rmac_pause_rcv_en", + mac->rmac_pause_rcv_en, "%d"); + __HAL_AUX_ENTRY("rmac_pause_time", + mac->rmac_pause_time, "%u"); + __HAL_AUX_ENTRY("mc_pause_threshold_q0q3", + mac->mc_pause_threshold_q0q3, "%u"); + __HAL_AUX_ENTRY("mc_pause_threshold_q4q7", + mac->mc_pause_threshold_q4q7, "%u"); + } + + + __HAL_AUX_ENTRY("fifo_max_frags", dev_config->fifo.max_frags, "%u"); + __HAL_AUX_ENTRY("fifo_reserve_threshold", + dev_config->fifo.reserve_threshold, "%u"); + __HAL_AUX_ENTRY("fifo_memblock_size", + dev_config->fifo.memblock_size, "%u"); +#ifdef XGE_HAL_ALIGN_XMIT + __HAL_AUX_ENTRY("fifo_alignment_size", + dev_config->fifo.alignment_size, "%u"); +#endif + + for (i = 0; i < XGE_HAL_MAX_FIFO_NUM; i++) { + int j; + xge_hal_fifo_queue_t *fifo = &dev_config->fifo.queue[i]; + + if (!fifo->configured) + continue; + + (void) xge_os_sprintf(key, "fifo%d_", i); + xge_os_strcpy(key+6, "initial"); + __HAL_AUX_ENTRY(key, fifo->initial, "%u"); + xge_os_strcpy(key+6, "max"); + __HAL_AUX_ENTRY(key, fifo->max, "%u"); + xge_os_strcpy(key+6, "intr"); + __HAL_AUX_ENTRY(key, fifo->intr, "%u"); + xge_os_strcpy(key+6, "no_snoop_bits"); + __HAL_AUX_ENTRY(key, fifo->no_snoop_bits, "%u"); + + for (j = 0; j < XGE_HAL_MAX_FIFO_TTI_NUM; j++) { + xge_hal_tti_config_t *tti = + &dev_config->fifo.queue[i].tti[j]; + + if (!tti->enabled) + continue; + + (void) xge_os_sprintf(key, "fifo%d_tti%02d_", i, + i * XGE_HAL_MAX_FIFO_TTI_NUM + j); + xge_os_strcpy(key+12, "urange_a"); + __HAL_AUX_ENTRY(key, tti->urange_a, "%u"); + xge_os_strcpy(key+12, "ufc_a"); + __HAL_AUX_ENTRY(key, tti->ufc_a, "%u"); + xge_os_strcpy(key+12, "urange_b"); + __HAL_AUX_ENTRY(key, tti->urange_b, "%u"); + xge_os_strcpy(key+12, "ufc_b"); + __HAL_AUX_ENTRY(key, tti->ufc_b, "%u"); + xge_os_strcpy(key+12, "urange_c"); + __HAL_AUX_ENTRY(key, tti->urange_c, "%u"); + xge_os_strcpy(key+12, "ufc_c"); + __HAL_AUX_ENTRY(key, tti->ufc_c, "%u"); + xge_os_strcpy(key+12, "ufc_d"); + __HAL_AUX_ENTRY(key, tti->ufc_d, "%u"); + xge_os_strcpy(key+12, "timer_val_us"); + __HAL_AUX_ENTRY(key, tti->timer_val_us, "%u"); + xge_os_strcpy(key+12, "timer_ci_en"); + __HAL_AUX_ENTRY(key, tti->timer_ci_en, "%u"); + } + } + + /* and bimodal TTIs */ + for (i=0; ibimodal_tti[i]; + + if (!tti->enabled) + continue; + + (void) xge_os_sprintf(key, "tti%02d_", + XGE_HAL_MAX_FIFO_TTI_RING_0 + i); + + xge_os_strcpy(key+6, "urange_a"); + __HAL_AUX_ENTRY(key, tti->urange_a, "%u"); + xge_os_strcpy(key+6, "ufc_a"); + __HAL_AUX_ENTRY(key, tti->ufc_a, "%u"); + xge_os_strcpy(key+6, "urange_b"); + __HAL_AUX_ENTRY(key, tti->urange_b, "%u"); + xge_os_strcpy(key+6, "ufc_b"); + __HAL_AUX_ENTRY(key, tti->ufc_b, "%u"); + xge_os_strcpy(key+6, "urange_c"); + __HAL_AUX_ENTRY(key, tti->urange_c, "%u"); + xge_os_strcpy(key+6, "ufc_c"); + __HAL_AUX_ENTRY(key, tti->ufc_c, "%u"); + xge_os_strcpy(key+6, "ufc_d"); + __HAL_AUX_ENTRY(key, tti->ufc_d, "%u"); + xge_os_strcpy(key+6, "timer_val_us"); + __HAL_AUX_ENTRY(key, tti->timer_val_us, "%u"); + xge_os_strcpy(key+6, "timer_ac_en"); + __HAL_AUX_ENTRY(key, tti->timer_ac_en, "%u"); + xge_os_strcpy(key+6, "timer_ci_en"); + __HAL_AUX_ENTRY(key, tti->timer_ci_en, "%u"); + } + __HAL_AUX_ENTRY("dump_on_serr", dev_config->dump_on_serr, "%u"); + __HAL_AUX_ENTRY("dump_on_eccerr", + dev_config->dump_on_eccerr, "%u"); + __HAL_AUX_ENTRY("dump_on_parityerr", + dev_config->dump_on_parityerr, "%u"); + __HAL_AUX_ENTRY("rth_en", dev_config->rth_en, "%u"); + __HAL_AUX_ENTRY("rth_bucket_size", dev_config->rth_bucket_size, "%u"); + + __HAL_AUX_ENTRY_END(bufsize, retsize); + + xge_os_free(hldev->pdev, dev_config, + sizeof(xge_hal_device_config_t)); + + return XGE_HAL_OK; +} + diff --git a/sys/dev/nxge/xgehal/xgehal-mm.c b/sys/dev/nxge/xgehal/xgehal-mm.c new file mode 100644 index 0000000..d23f88a --- /dev/null +++ b/sys/dev/nxge/xgehal/xgehal-mm.c @@ -0,0 +1,436 @@ +/*- + * Copyright (c) 2002-2007 Neterion, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * FileName : hal-mm.c + * + * Description: chipset memory pool object implementation + * + * Created: 10 May 2004 + */ + +#include +#include +#include + +/* + * __hal_mempool_grow + * + * Will resize mempool up to %num_allocate value. + */ +xge_hal_status_e +__hal_mempool_grow(xge_hal_mempool_t *mempool, int num_allocate, + int *num_allocated) +{ + int i, first_time = mempool->memblocks_allocated == 0 ? 1 : 0; + int n_items = mempool->items_per_memblock; + + *num_allocated = 0; + + if ((mempool->memblocks_allocated + num_allocate) > + mempool->memblocks_max) { + xge_debug_mm(XGE_ERR, "%s", + "__hal_mempool_grow: can grow anymore"); + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + + for (i = mempool->memblocks_allocated; + i < mempool->memblocks_allocated + num_allocate; i++) { + int j; + int is_last = + ((mempool->memblocks_allocated+num_allocate-1) == i); + xge_hal_mempool_dma_t *dma_object = + mempool->memblocks_dma_arr + i; + void *the_memblock; + int dma_flags; + + dma_flags = XGE_OS_DMA_CACHELINE_ALIGNED; +#ifdef XGE_HAL_DMA_DTR_CONSISTENT + dma_flags |= XGE_OS_DMA_CONSISTENT; +#else + dma_flags |= XGE_OS_DMA_STREAMING; +#endif + + /* allocate DMA-capable memblock */ + mempool->memblocks_arr[i] = xge_os_dma_malloc(mempool->pdev, + mempool->memblock_size, + dma_flags, + &dma_object->handle, + &dma_object->acc_handle); + if (mempool->memblocks_arr[i] == NULL) { + xge_debug_mm(XGE_ERR, + "memblock[%d]: out of DMA memory", i); + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + xge_os_memzero(mempool->memblocks_arr[i], + mempool->memblock_size); + the_memblock = mempool->memblocks_arr[i]; + + /* allocate memblock's private part. Each DMA memblock + * has a space allocated for item's private usage upon + * mempool's user request. Each time mempool grows, it will + * allocate new memblock and its private part at once. + * This helps to minimize memory usage a lot. */ + mempool->memblocks_priv_arr[i] = xge_os_malloc(mempool->pdev, + mempool->items_priv_size * n_items); + if (mempool->memblocks_priv_arr[i] == NULL) { + xge_os_dma_free(mempool->pdev, + the_memblock, + mempool->memblock_size, + &dma_object->acc_handle, + &dma_object->handle); + xge_debug_mm(XGE_ERR, + "memblock_priv[%d]: out of virtual memory, " + "requested %d(%d:%d) bytes", i, + mempool->items_priv_size * n_items, + mempool->items_priv_size, n_items); + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + xge_os_memzero(mempool->memblocks_priv_arr[i], + mempool->items_priv_size * n_items); + + /* map memblock to physical memory */ + dma_object->addr = xge_os_dma_map(mempool->pdev, + dma_object->handle, + the_memblock, + mempool->memblock_size, + XGE_OS_DMA_DIR_BIDIRECTIONAL, +#ifdef XGE_HAL_DMA_DTR_CONSISTENT + XGE_OS_DMA_CONSISTENT +#else + XGE_OS_DMA_STREAMING +#endif + ); + if (dma_object->addr == XGE_OS_INVALID_DMA_ADDR) { + xge_os_free(mempool->pdev, mempool->memblocks_priv_arr[i], + mempool->items_priv_size * + n_items); + xge_os_dma_free(mempool->pdev, + the_memblock, + mempool->memblock_size, + &dma_object->acc_handle, + &dma_object->handle); + return XGE_HAL_ERR_OUT_OF_MAPPING; + } + + /* fill the items hash array */ + for (j=0; j= mempool->items_initial) { + break; + } + + mempool->items_arr[index] = + ((char *)the_memblock + j*mempool->item_size); + + /* let caller to do more job on each item */ + if (mempool->item_func_alloc != NULL) { + xge_hal_status_e status; + + if ((status = mempool->item_func_alloc( + mempool, + the_memblock, + i, + dma_object, + mempool->items_arr[index], + index, + is_last, + mempool->userdata)) != XGE_HAL_OK) { + + if (mempool->item_func_free != NULL) { + int k; + + for (k=0; kitem_func_free( + mempool, the_memblock, + i, dma_object, + mempool->items_arr[index], + index, is_last, + mempool->userdata); + } + } + + xge_os_free(mempool->pdev, + mempool->memblocks_priv_arr[i], + mempool->items_priv_size * + n_items); + xge_os_dma_unmap(mempool->pdev, + dma_object->handle, + dma_object->addr, + mempool->memblock_size, + XGE_OS_DMA_DIR_BIDIRECTIONAL); + xge_os_dma_free(mempool->pdev, + the_memblock, + mempool->memblock_size, + &dma_object->acc_handle, + &dma_object->handle); + return status; + } + } + + mempool->items_current = index + 1; + } + + xge_debug_mm(XGE_TRACE, + "memblock%d: allocated %dk, vaddr 0x"XGE_OS_LLXFMT", " + "dma_addr 0x"XGE_OS_LLXFMT, i, mempool->memblock_size / 1024, + (unsigned long long)(ulong_t)mempool->memblocks_arr[i], + (unsigned long long)dma_object->addr); + + (*num_allocated)++; + + if (first_time && mempool->items_current == + mempool->items_initial) { + break; + } + } + + /* increment actual number of allocated memblocks */ + mempool->memblocks_allocated += *num_allocated; + + return XGE_HAL_OK; +} + +/* + * xge_hal_mempool_create + * @memblock_size: + * @items_initial: + * @items_max: + * @item_size: + * @item_func: + * + * This function will create memory pool object. Pool may grow but will + * never shrink. Pool consists of number of dynamically allocated blocks + * with size enough to hold %items_initial number of items. Memory is + * DMA-able but client must map/unmap before interoperating with the device. + * See also: xge_os_dma_map(), xge_hal_dma_unmap(), xge_hal_status_e{}. + */ +xge_hal_mempool_t* +__hal_mempool_create(pci_dev_h pdev, int memblock_size, int item_size, + int items_priv_size, int items_initial, int items_max, + xge_hal_mempool_item_f item_func_alloc, + xge_hal_mempool_item_f item_func_free, void *userdata) +{ + xge_hal_status_e status; + int memblocks_to_allocate; + xge_hal_mempool_t *mempool; + int allocated; + + if (memblock_size < item_size) { + xge_debug_mm(XGE_ERR, + "memblock_size %d < item_size %d: misconfiguration", + memblock_size, item_size); + return NULL; + } + + mempool = (xge_hal_mempool_t *) \ + xge_os_malloc(pdev, sizeof(xge_hal_mempool_t)); + if (mempool == NULL) { + xge_debug_mm(XGE_ERR, "mempool allocation failure"); + return NULL; + } + xge_os_memzero(mempool, sizeof(xge_hal_mempool_t)); + + mempool->pdev = pdev; + mempool->memblock_size = memblock_size; + mempool->items_max = items_max; + mempool->items_initial = items_initial; + mempool->item_size = item_size; + mempool->items_priv_size = items_priv_size; + mempool->item_func_alloc = item_func_alloc; + mempool->item_func_free = item_func_free; + mempool->userdata = userdata; + + mempool->memblocks_allocated = 0; + + mempool->items_per_memblock = memblock_size / item_size; + + mempool->memblocks_max = (items_max + mempool->items_per_memblock - 1) / + mempool->items_per_memblock; + + /* allocate array of memblocks */ + mempool->memblocks_arr = (void ** ) xge_os_malloc(mempool->pdev, + sizeof(void*) * mempool->memblocks_max); + if (mempool->memblocks_arr == NULL) { + xge_debug_mm(XGE_ERR, "memblocks_arr allocation failure"); + __hal_mempool_destroy(mempool); + return NULL; + } + xge_os_memzero(mempool->memblocks_arr, + sizeof(void*) * mempool->memblocks_max); + + /* allocate array of private parts of items per memblocks */ + mempool->memblocks_priv_arr = (void **) xge_os_malloc(mempool->pdev, + sizeof(void*) * mempool->memblocks_max); + if (mempool->memblocks_priv_arr == NULL) { + xge_debug_mm(XGE_ERR, "memblocks_priv_arr allocation failure"); + __hal_mempool_destroy(mempool); + return NULL; + } + xge_os_memzero(mempool->memblocks_priv_arr, + sizeof(void*) * mempool->memblocks_max); + + /* allocate array of memblocks DMA objects */ + mempool->memblocks_dma_arr = + (xge_hal_mempool_dma_t *) xge_os_malloc(mempool->pdev, + sizeof(xge_hal_mempool_dma_t) * mempool->memblocks_max); + + if (mempool->memblocks_dma_arr == NULL) { + xge_debug_mm(XGE_ERR, "memblocks_dma_arr allocation failure"); + __hal_mempool_destroy(mempool); + return NULL; + } + xge_os_memzero(mempool->memblocks_dma_arr, + sizeof(xge_hal_mempool_dma_t) * mempool->memblocks_max); + + /* allocate hash array of items */ + mempool->items_arr = (void **) xge_os_malloc(mempool->pdev, + sizeof(void*) * mempool->items_max); + if (mempool->items_arr == NULL) { + xge_debug_mm(XGE_ERR, "items_arr allocation failure"); + __hal_mempool_destroy(mempool); + return NULL; + } + xge_os_memzero(mempool->items_arr, sizeof(void *) * mempool->items_max); + + mempool->shadow_items_arr = (void **) xge_os_malloc(mempool->pdev, + sizeof(void*) * mempool->items_max); + if (mempool->shadow_items_arr == NULL) { + xge_debug_mm(XGE_ERR, "shadow_items_arr allocation failure"); + __hal_mempool_destroy(mempool); + return NULL; + } + xge_os_memzero(mempool->shadow_items_arr, + sizeof(void *) * mempool->items_max); + + /* calculate initial number of memblocks */ + memblocks_to_allocate = (mempool->items_initial + + mempool->items_per_memblock - 1) / + mempool->items_per_memblock; + + xge_debug_mm(XGE_TRACE, "allocating %d memblocks, " + "%d items per memblock", memblocks_to_allocate, + mempool->items_per_memblock); + + /* pre-allocate the mempool */ + status = __hal_mempool_grow(mempool, memblocks_to_allocate, &allocated); + xge_os_memcpy(mempool->shadow_items_arr, mempool->items_arr, + sizeof(void*) * mempool->items_max); + if (status != XGE_HAL_OK) { + xge_debug_mm(XGE_ERR, "mempool_grow failure"); + __hal_mempool_destroy(mempool); + return NULL; + } + + xge_debug_mm(XGE_TRACE, + "total: allocated %dk of DMA-capable memory", + mempool->memblock_size * allocated / 1024); + + return mempool; +} + +/* + * xge_hal_mempool_destroy + */ +void +__hal_mempool_destroy(xge_hal_mempool_t *mempool) +{ + int i, j; + + for (i=0; imemblocks_allocated; i++) { + xge_hal_mempool_dma_t *dma_object; + + xge_assert(mempool->memblocks_arr[i]); + xge_assert(mempool->memblocks_dma_arr + i); + + dma_object = mempool->memblocks_dma_arr + i; + + for (j=0; jitems_per_memblock; j++) { + int index = i*mempool->items_per_memblock + j; + + /* to skip last partially filled(if any) memblock */ + if (index >= mempool->items_current) { + break; + } + + /* let caller to do more job on each item */ + if (mempool->item_func_free != NULL) { + + mempool->item_func_free(mempool, + mempool->memblocks_arr[i], + i, dma_object, + mempool->shadow_items_arr[index], + index, /* unused */ -1, + mempool->userdata); + } + } + + xge_os_dma_unmap(mempool->pdev, + dma_object->handle, dma_object->addr, + mempool->memblock_size, XGE_OS_DMA_DIR_BIDIRECTIONAL); + + xge_os_free(mempool->pdev, mempool->memblocks_priv_arr[i], + mempool->items_priv_size * mempool->items_per_memblock); + + xge_os_dma_free(mempool->pdev, mempool->memblocks_arr[i], + mempool->memblock_size, &dma_object->acc_handle, + &dma_object->handle); + } + + if (mempool->items_arr) { + xge_os_free(mempool->pdev, mempool->items_arr, sizeof(void*) * + mempool->items_max); + } + + if (mempool->shadow_items_arr) { + xge_os_free(mempool->pdev, mempool->shadow_items_arr, + sizeof(void*) * mempool->items_max); + } + + if (mempool->memblocks_dma_arr) { + xge_os_free(mempool->pdev, mempool->memblocks_dma_arr, + sizeof(xge_hal_mempool_dma_t) * + mempool->memblocks_max); + } + + if (mempool->memblocks_priv_arr) { + xge_os_free(mempool->pdev, mempool->memblocks_priv_arr, + sizeof(void*) * mempool->memblocks_max); + } + + if (mempool->memblocks_arr) { + xge_os_free(mempool->pdev, mempool->memblocks_arr, + sizeof(void*) * mempool->memblocks_max); + } + + xge_os_free(mempool->pdev, mempool, sizeof(xge_hal_mempool_t)); +} diff --git a/sys/dev/nxge/xgehal/xgehal-ring-fp.c b/sys/dev/nxge/xgehal/xgehal-ring-fp.c new file mode 100644 index 0000000..9d5a09e --- /dev/null +++ b/sys/dev/nxge/xgehal/xgehal-ring-fp.c @@ -0,0 +1,852 @@ +/*- + * Copyright (c) 2002-2007 Neterion, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * FileName : xgehal-ring-fp.c + * + * Description: HAL Rx ring object functionality (fast path) + * + * Created: 10 June 2004 + */ + +#ifdef XGE_DEBUG_FP +#include +#endif + +__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_ring_rxd_priv_t* +__hal_ring_rxd_priv(xge_hal_ring_t *ring, xge_hal_dtr_h dtrh) +{ + + xge_hal_ring_rxd_1_t *rxdp = (xge_hal_ring_rxd_1_t *)dtrh; + xge_hal_ring_rxd_priv_t *rxd_priv; + + xge_assert(rxdp); + +#if defined(XGE_HAL_USE_5B_MODE) + xge_assert(ring); + if (ring->buffer_mode == XGE_HAL_RING_QUEUE_BUFFER_MODE_5) { + xge_hal_ring_rxd_5_t *rxdp_5 = (xge_hal_ring_rxd_5_t *)dtrh; +#if defined (XGE_OS_PLATFORM_64BIT) + int memblock_idx = rxdp_5->host_control >> 16; + int i = rxdp_5->host_control & 0xFFFF; + rxd_priv = (xge_hal_ring_rxd_priv_t *) + ((char*)ring->mempool->memblocks_priv_arr[memblock_idx] + ring->rxd_priv_size * i); +#else + /* 32-bit case */ + rxd_priv = (xge_hal_ring_rxd_priv_t *)rxdp_5->host_control; +#endif + } else +#endif + { + rxd_priv = (xge_hal_ring_rxd_priv_t *) + (ulong_t)rxdp->host_control; + } + + xge_assert(rxd_priv); + xge_assert(rxd_priv->dma_object); + + xge_assert(rxd_priv->dma_object->handle == rxd_priv->dma_handle); + + xge_assert(rxd_priv->dma_object->addr + rxd_priv->dma_offset == + rxd_priv->dma_addr); + + return rxd_priv; +} + +__HAL_STATIC_RING __HAL_INLINE_RING int +__hal_ring_block_memblock_idx(xge_hal_ring_block_t *block) +{ + return (int)*((u64 *)(void *)((char *)block + + XGE_HAL_RING_MEMBLOCK_IDX_OFFSET)); +} + +__HAL_STATIC_RING __HAL_INLINE_RING void +__hal_ring_block_memblock_idx_set(xge_hal_ring_block_t*block, int memblock_idx) +{ + *((u64 *)(void *)((char *)block + + XGE_HAL_RING_MEMBLOCK_IDX_OFFSET)) = + memblock_idx; +} + + +__HAL_STATIC_RING __HAL_INLINE_RING dma_addr_t +__hal_ring_block_next_pointer(xge_hal_ring_block_t *block) +{ + return (dma_addr_t)*((u64 *)(void *)((char *)block + + XGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET)); +} + +__HAL_STATIC_RING __HAL_INLINE_RING void +__hal_ring_block_next_pointer_set(xge_hal_ring_block_t *block, + dma_addr_t dma_next) +{ + *((u64 *)(void *)((char *)block + + XGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET)) = dma_next; +} + +/** + * xge_hal_ring_dtr_private - Get ULD private per-descriptor data. + * @channelh: Channel handle. + * @dtrh: Descriptor handle. + * + * Returns: private ULD info associated with the descriptor. + * ULD requests per-descriptor space via xge_hal_channel_open(). + * + * See also: xge_hal_fifo_dtr_private(). + * Usage: See ex_rx_compl{}. + */ +__HAL_STATIC_RING __HAL_INLINE_RING void* +xge_hal_ring_dtr_private(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh) +{ + return (char *)__hal_ring_rxd_priv((xge_hal_ring_t *) channelh, dtrh) + + sizeof(xge_hal_ring_rxd_priv_t); +} + +/** + * xge_hal_ring_dtr_reserve - Reserve ring descriptor. + * @channelh: Channel handle. + * @dtrh: Reserved descriptor. On success HAL fills this "out" parameter + * with a valid handle. + * + * Reserve Rx descriptor for the subsequent filling-in (by upper layer + * driver (ULD)) and posting on the corresponding channel (@channelh) + * via xge_hal_ring_dtr_post(). + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available. + * + * See also: xge_hal_fifo_dtr_reserve(), xge_hal_ring_dtr_free(), + * xge_hal_fifo_dtr_reserve_sp(), xge_hal_status_e{}. + * Usage: See ex_post_all_rx{}. + */ +__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e +xge_hal_ring_dtr_reserve(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh) +{ + xge_hal_status_e status; +#if defined(XGE_HAL_RX_MULTI_RESERVE_IRQ) + unsigned long flags; +#endif + +#if defined(XGE_HAL_RX_MULTI_RESERVE) + xge_os_spin_lock(&((xge_hal_channel_t*)channelh)->reserve_lock); +#elif defined(XGE_HAL_RX_MULTI_RESERVE_IRQ) + xge_os_spin_lock_irq(&((xge_hal_channel_t*)channelh)->reserve_lock, + flags); +#endif + + status = __hal_channel_dtr_alloc(channelh, dtrh); + +#if defined(XGE_HAL_RX_MULTI_RESERVE) + xge_os_spin_unlock(&((xge_hal_channel_t*)channelh)->reserve_lock); +#elif defined(XGE_HAL_RX_MULTI_RESERVE_IRQ) + xge_os_spin_unlock_irq(&((xge_hal_channel_t*)channelh)->reserve_lock, + flags); +#endif + + if (status == XGE_HAL_OK) { + xge_hal_ring_rxd_1_t *rxdp = (xge_hal_ring_rxd_1_t *)*dtrh; + + /* instead of memset: reset this RxD */ + rxdp->control_1 = rxdp->control_2 = 0; + +#if defined(XGE_OS_MEMORY_CHECK) + __hal_ring_rxd_priv((xge_hal_ring_t *) channelh, rxdp)->allocated = 1; +#endif + } + + return status; +} + +/** + * xge_hal_ring_dtr_info_get - Get extended information associated with + * a completed receive descriptor for 1b mode. + * @channelh: Channel handle. + * @dtrh: Descriptor handle. + * @ext_info: See xge_hal_dtr_info_t{}. Returned by HAL. + * + * Retrieve extended information associated with a completed receive descriptor. + * + * See also: xge_hal_dtr_info_t{}, xge_hal_ring_dtr_1b_get(), + * xge_hal_ring_dtr_5b_get(). + */ +__HAL_STATIC_RING __HAL_INLINE_RING void +xge_hal_ring_dtr_info_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, + xge_hal_dtr_info_t *ext_info) +{ + /* cast to 1-buffer mode RxD: the code below relies on the fact + * that control_1 and control_2 are formatted the same way.. */ + xge_hal_ring_rxd_1_t *rxdp = (xge_hal_ring_rxd_1_t *)dtrh; + + ext_info->l3_cksum = XGE_HAL_RXD_GET_L3_CKSUM(rxdp->control_1); + ext_info->l4_cksum = XGE_HAL_RXD_GET_L4_CKSUM(rxdp->control_1); + ext_info->frame = XGE_HAL_RXD_GET_FRAME_TYPE(rxdp->control_1); + ext_info->proto = XGE_HAL_RXD_GET_FRAME_PROTO(rxdp->control_1); + ext_info->vlan = XGE_HAL_RXD_GET_VLAN_TAG(rxdp->control_2); + + /* Herc only, a few extra cycles imposed on Xena and/or + * when RTH is not enabled. + * Alternatively, could check + * xge_hal_device_check_id(), hldev->config.rth_en, queue->rth_en */ + ext_info->rth_it_hit = XGE_HAL_RXD_GET_RTH_IT_HIT(rxdp->control_1); + ext_info->rth_spdm_hit = + XGE_HAL_RXD_GET_RTH_SPDM_HIT(rxdp->control_1); + ext_info->rth_hash_type = + XGE_HAL_RXD_GET_RTH_HASH_TYPE(rxdp->control_1); + ext_info->rth_value = XGE_HAL_RXD_1_GET_RTH_VALUE(rxdp->control_2); +} + +/** + * xge_hal_ring_dtr_info_nb_get - Get extended information associated + * with a completed receive descriptor for 3b or 5b + * modes. + * @channelh: Channel handle. + * @dtrh: Descriptor handle. + * @ext_info: See xge_hal_dtr_info_t{}. Returned by HAL. + * + * Retrieve extended information associated with a completed receive descriptor. + * + * See also: xge_hal_dtr_info_t{}, xge_hal_ring_dtr_1b_get(), + * xge_hal_ring_dtr_5b_get(). + */ +__HAL_STATIC_RING __HAL_INLINE_RING void +xge_hal_ring_dtr_info_nb_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, + xge_hal_dtr_info_t *ext_info) +{ + /* cast to 1-buffer mode RxD: the code below relies on the fact + * that control_1 and control_2 are formatted the same way.. */ + xge_hal_ring_rxd_1_t *rxdp = (xge_hal_ring_rxd_1_t *)dtrh; + + ext_info->l3_cksum = XGE_HAL_RXD_GET_L3_CKSUM(rxdp->control_1); + ext_info->l4_cksum = XGE_HAL_RXD_GET_L4_CKSUM(rxdp->control_1); + ext_info->frame = XGE_HAL_RXD_GET_FRAME_TYPE(rxdp->control_1); + ext_info->proto = XGE_HAL_RXD_GET_FRAME_PROTO(rxdp->control_1); + ext_info->vlan = XGE_HAL_RXD_GET_VLAN_TAG(rxdp->control_2); + /* Herc only, a few extra cycles imposed on Xena and/or + * when RTH is not enabled. Same comment as above. */ + ext_info->rth_it_hit = XGE_HAL_RXD_GET_RTH_IT_HIT(rxdp->control_1); + ext_info->rth_spdm_hit = + XGE_HAL_RXD_GET_RTH_SPDM_HIT(rxdp->control_1); + ext_info->rth_hash_type = + XGE_HAL_RXD_GET_RTH_HASH_TYPE(rxdp->control_1); + ext_info->rth_value = (u32)rxdp->buffer0_ptr; +} + +/** + * xge_hal_ring_dtr_1b_set - Prepare 1-buffer-mode descriptor. + * @dtrh: Descriptor handle. + * @dma_pointer: DMA address of a single receive buffer this descriptor + * should carry. Note that by the time + * xge_hal_ring_dtr_1b_set + * is called, the receive buffer should be already mapped + * to the corresponding Xframe device. + * @size: Size of the receive @dma_pointer buffer. + * + * Prepare 1-buffer-mode Rx descriptor for posting + * (via xge_hal_ring_dtr_post()). + * + * This inline helper-function does not return any parameters and always + * succeeds. + * + * See also: xge_hal_ring_dtr_3b_set(), xge_hal_ring_dtr_5b_set(). + * Usage: See ex_post_all_rx{}. + */ +__HAL_STATIC_RING __HAL_INLINE_RING void +xge_hal_ring_dtr_1b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointer, int size) +{ + xge_hal_ring_rxd_1_t *rxdp = (xge_hal_ring_rxd_1_t *)dtrh; + rxdp->buffer0_ptr = dma_pointer; + rxdp->control_2 &= (~XGE_HAL_RXD_1_MASK_BUFFER0_SIZE); + rxdp->control_2 |= XGE_HAL_RXD_1_SET_BUFFER0_SIZE(size); + + xge_debug_ring(XGE_TRACE, "xge_hal_ring_dtr_1b_set: rxdp %p control_2 %p buffer0_ptr %p", + (xge_hal_ring_rxd_1_t *)dtrh, + rxdp->control_2, + rxdp->buffer0_ptr); +} + +/** + * xge_hal_ring_dtr_1b_get - Get data from the completed 1-buf + * descriptor. + * @channelh: Channel handle. + * @dtrh: Descriptor handle. + * @dma_pointer: DMA address of a single receive buffer _this_ descriptor + * carries. Returned by HAL. + * @pkt_length: Length (in bytes) of the data in the buffer pointed by + * @dma_pointer. Returned by HAL. + * + * Retrieve protocol data from the completed 1-buffer-mode Rx descriptor. + * This inline helper-function uses completed descriptor to populate receive + * buffer pointer and other "out" parameters. The function always succeeds. + * + * See also: xge_hal_ring_dtr_3b_get(), xge_hal_ring_dtr_5b_get(). + * Usage: See ex_rx_compl{}. + */ +__HAL_STATIC_RING __HAL_INLINE_RING void +xge_hal_ring_dtr_1b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, + dma_addr_t *dma_pointer, int *pkt_length) +{ + xge_hal_ring_rxd_1_t *rxdp = (xge_hal_ring_rxd_1_t *)dtrh; + + *pkt_length = XGE_HAL_RXD_1_GET_BUFFER0_SIZE(rxdp->control_2); + *dma_pointer = rxdp->buffer0_ptr; + + ((xge_hal_channel_t *)channelh)->poll_bytes += *pkt_length; +} + +/** + * xge_hal_ring_dtr_3b_set - Prepare 3-buffer-mode descriptor. + * @dtrh: Descriptor handle. + * @dma_pointers: Array of DMA addresses. Contains exactly 3 receive buffers + * _this_ descriptor should carry. + * Note that by the time xge_hal_ring_dtr_3b_set + * is called, the receive buffers should be mapped + * to the corresponding Xframe device. + * @sizes: Array of receive buffer sizes. Contains 3 sizes: one size per + * buffer from @dma_pointers. + * + * Prepare 3-buffer-mode Rx descriptor for posting (via + * xge_hal_ring_dtr_post()). + * This inline helper-function does not return any parameters and always + * succeeds. + * + * See also: xge_hal_ring_dtr_1b_set(), xge_hal_ring_dtr_5b_set(). + */ +__HAL_STATIC_RING __HAL_INLINE_RING void +xge_hal_ring_dtr_3b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointers[], + int sizes[]) +{ + xge_hal_ring_rxd_3_t *rxdp = (xge_hal_ring_rxd_3_t *)dtrh; + rxdp->buffer0_ptr = dma_pointers[0]; + rxdp->control_2 &= (~XGE_HAL_RXD_3_MASK_BUFFER0_SIZE); + rxdp->control_2 |= XGE_HAL_RXD_3_SET_BUFFER0_SIZE(sizes[0]); + rxdp->buffer1_ptr = dma_pointers[1]; + rxdp->control_2 &= (~XGE_HAL_RXD_3_MASK_BUFFER1_SIZE); + rxdp->control_2 |= XGE_HAL_RXD_3_SET_BUFFER1_SIZE(sizes[1]); + rxdp->buffer2_ptr = dma_pointers[2]; + rxdp->control_2 &= (~XGE_HAL_RXD_3_MASK_BUFFER2_SIZE); + rxdp->control_2 |= XGE_HAL_RXD_3_SET_BUFFER2_SIZE(sizes[2]); +} + +/** + * xge_hal_ring_dtr_3b_get - Get data from the completed 3-buf + * descriptor. + * @channelh: Channel handle. + * @dtrh: Descriptor handle. + * @dma_pointers: DMA addresses of the 3 receive buffers _this_ descriptor + * carries. The first two buffers contain ethernet and + * (IP + transport) headers. The 3rd buffer contains packet + * data. + * Returned by HAL. + * @sizes: Array of receive buffer sizes. Contains 3 sizes: one size per + * buffer from @dma_pointers. Returned by HAL. + * + * Retrieve protocol data from the completed 3-buffer-mode Rx descriptor. + * This inline helper-function uses completed descriptor to populate receive + * buffer pointer and other "out" parameters. The function always succeeds. + * + * See also: xge_hal_ring_dtr_3b_get(), xge_hal_ring_dtr_5b_get(). + */ +__HAL_STATIC_RING __HAL_INLINE_RING void +xge_hal_ring_dtr_3b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, + dma_addr_t dma_pointers[], int sizes[]) +{ + xge_hal_ring_rxd_3_t *rxdp = (xge_hal_ring_rxd_3_t *)dtrh; + + dma_pointers[0] = rxdp->buffer0_ptr; + sizes[0] = XGE_HAL_RXD_3_GET_BUFFER0_SIZE(rxdp->control_2); + + dma_pointers[1] = rxdp->buffer1_ptr; + sizes[1] = XGE_HAL_RXD_3_GET_BUFFER1_SIZE(rxdp->control_2); + + dma_pointers[2] = rxdp->buffer2_ptr; + sizes[2] = XGE_HAL_RXD_3_GET_BUFFER2_SIZE(rxdp->control_2); + + ((xge_hal_channel_t *)channelh)->poll_bytes += sizes[0] + sizes[1] + + sizes[2]; +} + +/** + * xge_hal_ring_dtr_5b_set - Prepare 5-buffer-mode descriptor. + * @dtrh: Descriptor handle. + * @dma_pointers: Array of DMA addresses. Contains exactly 5 receive buffers + * _this_ descriptor should carry. + * Note that by the time xge_hal_ring_dtr_5b_set + * is called, the receive buffers should be mapped + * to the corresponding Xframe device. + * @sizes: Array of receive buffer sizes. Contains 5 sizes: one size per + * buffer from @dma_pointers. + * + * Prepare 3-buffer-mode Rx descriptor for posting (via + * xge_hal_ring_dtr_post()). + * This inline helper-function does not return any parameters and always + * succeeds. + * + * See also: xge_hal_ring_dtr_1b_set(), xge_hal_ring_dtr_3b_set(). + */ +__HAL_STATIC_RING __HAL_INLINE_RING void +xge_hal_ring_dtr_5b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointers[], + int sizes[]) +{ + xge_hal_ring_rxd_5_t *rxdp = (xge_hal_ring_rxd_5_t *)dtrh; + rxdp->buffer0_ptr = dma_pointers[0]; + rxdp->control_2 &= (~XGE_HAL_RXD_5_MASK_BUFFER0_SIZE); + rxdp->control_2 |= XGE_HAL_RXD_5_SET_BUFFER0_SIZE(sizes[0]); + rxdp->buffer1_ptr = dma_pointers[1]; + rxdp->control_2 &= (~XGE_HAL_RXD_5_MASK_BUFFER1_SIZE); + rxdp->control_2 |= XGE_HAL_RXD_5_SET_BUFFER1_SIZE(sizes[1]); + rxdp->buffer2_ptr = dma_pointers[2]; + rxdp->control_2 &= (~XGE_HAL_RXD_5_MASK_BUFFER2_SIZE); + rxdp->control_2 |= XGE_HAL_RXD_5_SET_BUFFER2_SIZE(sizes[2]); + rxdp->buffer3_ptr = dma_pointers[3]; + rxdp->control_3 &= (~XGE_HAL_RXD_5_MASK_BUFFER3_SIZE); + rxdp->control_3 |= XGE_HAL_RXD_5_SET_BUFFER3_SIZE(sizes[3]); + rxdp->buffer4_ptr = dma_pointers[4]; + rxdp->control_3 &= (~XGE_HAL_RXD_5_MASK_BUFFER4_SIZE); + rxdp->control_3 |= XGE_HAL_RXD_5_SET_BUFFER4_SIZE(sizes[4]); +} + +/** + * xge_hal_ring_dtr_5b_get - Get data from the completed 5-buf + * descriptor. + * @channelh: Channel handle. + * @dtrh: Descriptor handle. + * @dma_pointers: DMA addresses of the 5 receive buffers _this_ descriptor + * carries. The first 4 buffers contains L2 (ethernet) through + * L5 headers. The 5th buffer contain received (applicaion) + * data. Returned by HAL. + * @sizes: Array of receive buffer sizes. Contains 5 sizes: one size per + * buffer from @dma_pointers. Returned by HAL. + * + * Retrieve protocol data from the completed 5-buffer-mode Rx descriptor. + * This inline helper-function uses completed descriptor to populate receive + * buffer pointer and other "out" parameters. The function always succeeds. + * + * See also: xge_hal_ring_dtr_3b_get(), xge_hal_ring_dtr_5b_get(). + */ +__HAL_STATIC_RING __HAL_INLINE_RING void +xge_hal_ring_dtr_5b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, + dma_addr_t dma_pointers[], int sizes[]) +{ + xge_hal_ring_rxd_5_t *rxdp = (xge_hal_ring_rxd_5_t *)dtrh; + + dma_pointers[0] = rxdp->buffer0_ptr; + sizes[0] = XGE_HAL_RXD_5_GET_BUFFER0_SIZE(rxdp->control_2); + + dma_pointers[1] = rxdp->buffer1_ptr; + sizes[1] = XGE_HAL_RXD_5_GET_BUFFER1_SIZE(rxdp->control_2); + + dma_pointers[2] = rxdp->buffer2_ptr; + sizes[2] = XGE_HAL_RXD_5_GET_BUFFER2_SIZE(rxdp->control_2); + + dma_pointers[3] = rxdp->buffer3_ptr; + sizes[3] = XGE_HAL_RXD_5_GET_BUFFER3_SIZE(rxdp->control_3); + + dma_pointers[4] = rxdp->buffer4_ptr; + sizes[4] = XGE_HAL_RXD_5_GET_BUFFER4_SIZE(rxdp->control_3); + + ((xge_hal_channel_t *)channelh)->poll_bytes += sizes[0] + sizes[1] + + sizes[2] + sizes[3] + sizes[4]; +} + + +/** + * xge_hal_ring_dtr_pre_post - FIXME. + * @channelh: Channel handle. + * @dtrh: Descriptor handle. + * + * TBD + */ +__HAL_STATIC_RING __HAL_INLINE_RING void +xge_hal_ring_dtr_pre_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh) +{ + xge_hal_ring_rxd_1_t *rxdp = (xge_hal_ring_rxd_1_t *)dtrh; +#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_DTR_STREAMING) + xge_hal_ring_rxd_priv_t *priv; + xge_hal_ring_t *ring = (xge_hal_ring_t *)channelh; +#endif +#if defined(XGE_HAL_RX_MULTI_POST_IRQ) + unsigned long flags; +#endif + + rxdp->control_2 |= XGE_HAL_RXD_NOT_COMPLETED; + +#ifdef XGE_DEBUG_ASSERT + /* make sure Xena overwrites the (illegal) t_code on completion */ + XGE_HAL_RXD_SET_T_CODE(rxdp->control_1, XGE_HAL_RXD_T_CODE_UNUSED_C); +#endif + + xge_debug_ring(XGE_TRACE, "xge_hal_ring_dtr_pre_post: rxd 0x"XGE_OS_LLXFMT" posted %d post_qid %d", + (unsigned long long)(ulong_t)dtrh, + ((xge_hal_ring_t *)channelh)->channel.post_index, + ((xge_hal_ring_t *)channelh)->channel.post_qid); + +#if defined(XGE_HAL_RX_MULTI_POST) + xge_os_spin_lock(&((xge_hal_channel_t*)channelh)->post_lock); +#elif defined(XGE_HAL_RX_MULTI_POST_IRQ) + xge_os_spin_lock_irq(&((xge_hal_channel_t*)channelh)->post_lock, + flags); +#endif + +#if defined(XGE_DEBUG_ASSERT) && defined(XGE_HAL_RING_ENFORCE_ORDER) + { + xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; + + if (channel->post_index != 0) { + xge_hal_dtr_h prev_dtrh; + xge_hal_ring_rxd_priv_t *rxdp_priv; + + rxdp_priv = __hal_ring_rxd_priv(channelh, rxdp); + prev_dtrh = channel->work_arr[channel->post_index - 1]; + + if (prev_dtrh != NULL && + (rxdp_priv->dma_offset & (~0xFFF)) != + rxdp_priv->dma_offset) { + xge_assert((char *)prev_dtrh + + ((xge_hal_ring_t*)channel)->rxd_size == dtrh); + } + } + } +#endif + + __hal_channel_dtr_post(channelh, dtrh); + +#if defined(XGE_HAL_RX_MULTI_POST) + xge_os_spin_unlock(&((xge_hal_channel_t*)channelh)->post_lock); +#elif defined(XGE_HAL_RX_MULTI_POST_IRQ) + xge_os_spin_unlock_irq(&((xge_hal_channel_t*)channelh)->post_lock, + flags); +#endif +} + + +/** + * xge_hal_ring_dtr_post_post - FIXME. + * @channelh: Channel handle. + * @dtrh: Descriptor handle. + * + * TBD + */ +__HAL_STATIC_RING __HAL_INLINE_RING void +xge_hal_ring_dtr_post_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh) +{ + xge_hal_ring_rxd_1_t *rxdp = (xge_hal_ring_rxd_1_t *)dtrh; + xge_hal_ring_t *ring = (xge_hal_ring_t *)channelh; +#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_DTR_STREAMING) + xge_hal_ring_rxd_priv_t *priv; +#endif + /* do POST */ + rxdp->control_1 |= XGE_HAL_RXD_POSTED_4_XFRAME; + +#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_DTR_STREAMING) + priv = __hal_ring_rxd_priv(ring, rxdp); + xge_os_dma_sync(ring->channel.pdev, + priv->dma_handle, priv->dma_addr, + priv->dma_offset, ring->rxd_size, + XGE_OS_DMA_DIR_TODEVICE); +#endif + + xge_debug_ring(XGE_TRACE, "xge_hal_ring_dtr_post_post: rxdp %p control_1 %p", + (xge_hal_ring_rxd_1_t *)dtrh, + rxdp->control_1); + + if (ring->channel.usage_cnt > 0) + ring->channel.usage_cnt--; +} + +/** + * xge_hal_ring_dtr_post_post_wmb. + * @channelh: Channel handle. + * @dtrh: Descriptor handle. + * + * Similar as xge_hal_ring_dtr_post_post, but in addition it does memory barrier. + */ +__HAL_STATIC_RING __HAL_INLINE_RING void +xge_hal_ring_dtr_post_post_wmb(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh) +{ + xge_hal_ring_rxd_1_t *rxdp = (xge_hal_ring_rxd_1_t *)dtrh; + xge_hal_ring_t *ring = (xge_hal_ring_t *)channelh; +#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_DTR_STREAMING) + xge_hal_ring_rxd_priv_t *priv; +#endif + /* Do memory barrier before changing the ownership */ + xge_os_wmb(); + + /* do POST */ + rxdp->control_1 |= XGE_HAL_RXD_POSTED_4_XFRAME; + +#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_DTR_STREAMING) + priv = __hal_ring_rxd_priv(ring, rxdp); + xge_os_dma_sync(ring->channel.pdev, + priv->dma_handle, priv->dma_addr, + priv->dma_offset, ring->rxd_size, + XGE_OS_DMA_DIR_TODEVICE); +#endif + + if (ring->channel.usage_cnt > 0) + ring->channel.usage_cnt--; + + xge_debug_ring(XGE_TRACE, "xge_hal_ring_dtr_post_post_wmb: rxdp %p control_1 %p rxds_with_host %d", + (xge_hal_ring_rxd_1_t *)dtrh, + rxdp->control_1, ring->channel.usage_cnt); + +} + +/** + * xge_hal_ring_dtr_post - Post descriptor on the ring channel. + * @channelh: Channel handle. + * @dtrh: Descriptor obtained via xge_hal_ring_dtr_reserve(). + * + * Post descriptor on the 'ring' type channel. + * Prior to posting the descriptor should be filled in accordance with + * Host/Xframe interface specification for a given service (LL, etc.). + * + * See also: xge_hal_fifo_dtr_post_many(), xge_hal_fifo_dtr_post(). + * Usage: See ex_post_all_rx{}. + */ +__HAL_STATIC_RING __HAL_INLINE_RING void +xge_hal_ring_dtr_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh) +{ + xge_hal_ring_dtr_pre_post(channelh, dtrh); + xge_hal_ring_dtr_post_post(channelh, dtrh); +} + +/** + * xge_hal_ring_dtr_next_completed - Get the _next_ completed + * descriptor. + * @channelh: Channel handle. + * @dtrh: Descriptor handle. Returned by HAL. + * @t_code: Transfer code, as per Xframe User Guide, + * Receive Descriptor Format. Returned by HAL. + * + * Retrieve the _next_ completed descriptor. + * HAL uses channel callback (*xge_hal_channel_callback_f) to notifiy + * upper-layer driver (ULD) of new completed descriptors. After that + * the ULD can use xge_hal_ring_dtr_next_completed to retrieve the rest + * completions (the very first completion is passed by HAL via + * xge_hal_channel_callback_f). + * + * Implementation-wise, the upper-layer driver is free to call + * xge_hal_ring_dtr_next_completed either immediately from inside the + * channel callback, or in a deferred fashion and separate (from HAL) + * context. + * + * Non-zero @t_code means failure to fill-in receive buffer(s) + * of the descriptor. + * For instance, parity error detected during the data transfer. + * In this case Xframe will complete the descriptor and indicate + * for the host that the received data is not to be used. + * For details please refer to Xframe User Guide. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors + * are currently available for processing. + * + * See also: xge_hal_channel_callback_f{}, + * xge_hal_fifo_dtr_next_completed(), xge_hal_status_e{}. + * Usage: See ex_rx_compl{}. + */ +__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e +xge_hal_ring_dtr_next_completed(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh, + u8 *t_code) +{ + xge_hal_ring_rxd_1_t *rxdp; /* doesn't matter 1, 3 or 5... */ + xge_hal_ring_t *ring = (xge_hal_ring_t *)channelh; +#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_DTR_STREAMING) + xge_hal_ring_rxd_priv_t *priv; +#endif + + __hal_channel_dtr_try_complete(ring, dtrh); + rxdp = (xge_hal_ring_rxd_1_t *)*dtrh; + if (rxdp == NULL) { + return XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS; + } + +#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_DTR_STREAMING) + /* Note: 24 bytes at most means: + * - Control_3 in case of 5-buffer mode + * - Control_1 and Control_2 + * + * This is the only length needs to be invalidated + * type of channels.*/ + priv = __hal_ring_rxd_priv(ring, rxdp); + xge_os_dma_sync(ring->channel.pdev, + priv->dma_handle, priv->dma_addr, + priv->dma_offset, 24, + XGE_OS_DMA_DIR_FROMDEVICE); +#endif + + /* check whether it is not the end */ + if (!(rxdp->control_2 & XGE_HAL_RXD_NOT_COMPLETED) && + !(rxdp->control_1 & XGE_HAL_RXD_POSTED_4_XFRAME)) { +#ifndef XGE_HAL_IRQ_POLLING + if (++ring->cmpl_cnt > ring->indicate_max_pkts) { + /* reset it. since we don't want to return + * garbage to the ULD */ + *dtrh = 0; + return XGE_HAL_COMPLETIONS_REMAIN; + } +#endif + +#ifdef XGE_DEBUG_ASSERT +#if defined(XGE_HAL_USE_5B_MODE) +#if !defined(XGE_OS_PLATFORM_64BIT) + if (ring->buffer_mode == XGE_HAL_RING_QUEUE_BUFFER_MODE_5) { + xge_assert(((xge_hal_ring_rxd_5_t *) + rxdp)->host_control!=0); + } +#endif + +#else + xge_assert(rxdp->host_control!=0); +#endif +#endif + + __hal_channel_dtr_complete(ring); + + *t_code = (u8)XGE_HAL_RXD_GET_T_CODE(rxdp->control_1); + + /* see XGE_HAL_SET_RXD_T_CODE() above.. */ + xge_assert(*t_code != XGE_HAL_RXD_T_CODE_UNUSED_C); + + xge_debug_ring(XGE_TRACE, + "compl_index %d post_qid %d t_code %d rxd 0x"XGE_OS_LLXFMT, + ((xge_hal_channel_t*)ring)->compl_index, + ((xge_hal_channel_t*)ring)->post_qid, *t_code, + (unsigned long long)(ulong_t)rxdp); + + ring->channel.usage_cnt++; + if (ring->channel.stats.usage_max < ring->channel.usage_cnt) + ring->channel.stats.usage_max = ring->channel.usage_cnt; + + return XGE_HAL_OK; + } + + /* reset it. since we don't want to return + * garbage to the ULD */ + *dtrh = 0; + return XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS; +} + +/** + * xge_hal_ring_dtr_free - Free descriptor. + * @channelh: Channel handle. + * @dtrh: Descriptor handle. + * + * Free the reserved descriptor. This operation is "symmetrical" to + * xge_hal_ring_dtr_reserve. The "free-ing" completes the descriptor's + * lifecycle. + * + * After free-ing (see xge_hal_ring_dtr_free()) the descriptor again can + * be: + * + * - reserved (xge_hal_ring_dtr_reserve); + * + * - posted (xge_hal_ring_dtr_post); + * + * - completed (xge_hal_ring_dtr_next_completed); + * + * - and recycled again (xge_hal_ring_dtr_free). + * + * For alternative state transitions and more details please refer to + * the design doc. + * + * See also: xge_hal_ring_dtr_reserve(), xge_hal_fifo_dtr_free(). + * Usage: See ex_rx_compl{}. + */ +__HAL_STATIC_RING __HAL_INLINE_RING void +xge_hal_ring_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh) +{ +#if defined(XGE_HAL_RX_MULTI_FREE_IRQ) + unsigned long flags; +#endif + +#if defined(XGE_HAL_RX_MULTI_FREE) + xge_os_spin_lock(&((xge_hal_channel_t*)channelh)->free_lock); +#elif defined(XGE_HAL_RX_MULTI_FREE_IRQ) + xge_os_spin_lock_irq(&((xge_hal_channel_t*)channelh)->free_lock, + flags); +#endif + + __hal_channel_dtr_free(channelh, dtrh); +#if defined(XGE_OS_MEMORY_CHECK) + __hal_ring_rxd_priv((xge_hal_ring_t * ) channelh, dtrh)->allocated = 0; +#endif + +#if defined(XGE_HAL_RX_MULTI_FREE) + xge_os_spin_unlock(&((xge_hal_channel_t*)channelh)->free_lock); +#elif defined(XGE_HAL_RX_MULTI_FREE_IRQ) + xge_os_spin_unlock_irq(&((xge_hal_channel_t*)channelh)->free_lock, + flags); +#endif +} + +/** + * xge_hal_ring_is_next_dtr_completed - Check if the next dtr is completed + * @channelh: Channel handle. + * + * Checks if the the _next_ completed descriptor is in host memory + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors + * are currently available for processing. + */ +__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e +xge_hal_ring_is_next_dtr_completed(xge_hal_channel_h channelh) +{ + xge_hal_ring_rxd_1_t *rxdp; /* doesn't matter 1, 3 or 5... */ + xge_hal_ring_t *ring = (xge_hal_ring_t *)channelh; + xge_hal_dtr_h dtrh; + + __hal_channel_dtr_try_complete(ring, &dtrh); + rxdp = (xge_hal_ring_rxd_1_t *)dtrh; + if (rxdp == NULL) { + return XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS; + } + + /* check whether it is not the end */ + if (!(rxdp->control_2 & XGE_HAL_RXD_NOT_COMPLETED) && + !(rxdp->control_1 & XGE_HAL_RXD_POSTED_4_XFRAME)) { + +#ifdef XGE_DEBUG_ASSERT +#if defined(XGE_HAL_USE_5B_MODE) +#if !defined(XGE_OS_PLATFORM_64BIT) + if (ring->buffer_mode == XGE_HAL_RING_QUEUE_BUFFER_MODE_5) { + xge_assert(((xge_hal_ring_rxd_5_t *) + rxdp)->host_control!=0); + } +#endif + +#else + xge_assert(rxdp->host_control!=0); +#endif +#endif + return XGE_HAL_OK; + } + + return XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS; +} diff --git a/sys/dev/nxge/xgehal/xgehal-ring.c b/sys/dev/nxge/xgehal/xgehal-ring.c new file mode 100644 index 0000000..84e8f9b --- /dev/null +++ b/sys/dev/nxge/xgehal/xgehal-ring.c @@ -0,0 +1,669 @@ +/*- + * Copyright (c) 2002-2007 Neterion, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * FileName : hal-ring.c + * + * Description: Rx ring object implementation + * + * Created: 10 May 2004 + */ + +#include +#include + +#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_DTR_STREAMING) +static ptrdiff_t +__hal_ring_item_dma_offset(xge_hal_mempool_h mempoolh, + void *item) +{ + int memblock_idx; + void *memblock; + + /* get owner memblock index */ + memblock_idx = __hal_ring_block_memblock_idx(item); + + /* get owner memblock by memblock index */ + memblock = __hal_mempool_memblock(mempoolh, memblock_idx); + + return (char*)item - (char*)memblock; +} +#endif + +static dma_addr_t +__hal_ring_item_dma_addr(xge_hal_mempool_h mempoolh, void *item, + pci_dma_h *dma_handle) +{ + int memblock_idx; + void *memblock; + xge_hal_mempool_dma_t *memblock_dma_object; + ptrdiff_t dma_item_offset; + + /* get owner memblock index */ + memblock_idx = __hal_ring_block_memblock_idx((xge_hal_ring_block_t *) item); + + /* get owner memblock by memblock index */ + memblock = __hal_mempool_memblock((xge_hal_mempool_t *) mempoolh, + memblock_idx); + + /* get memblock DMA object by memblock index */ + memblock_dma_object = + __hal_mempool_memblock_dma((xge_hal_mempool_t *) mempoolh, + memblock_idx); + + /* calculate offset in the memblock of this item */ + dma_item_offset = (char*)item - (char*)memblock; + + *dma_handle = memblock_dma_object->handle; + + return memblock_dma_object->addr + dma_item_offset; +} + +static void +__hal_ring_rxdblock_link(xge_hal_mempool_h mempoolh, + xge_hal_ring_t *ring, int from, int to) +{ + xge_hal_ring_block_t *to_item, *from_item; + dma_addr_t to_dma, from_dma; + pci_dma_h to_dma_handle, from_dma_handle; + + /* get "from" RxD block */ + from_item = (xge_hal_ring_block_t *) + __hal_mempool_item((xge_hal_mempool_t *) mempoolh, from); + xge_assert(from_item); + + /* get "to" RxD block */ + to_item = (xge_hal_ring_block_t *) + __hal_mempool_item((xge_hal_mempool_t *) mempoolh, to); + xge_assert(to_item); + + /* return address of the beginning of previous RxD block */ + to_dma = __hal_ring_item_dma_addr(mempoolh, to_item, &to_dma_handle); + + /* set next pointer for this RxD block to point on + * previous item's DMA start address */ + __hal_ring_block_next_pointer_set(from_item, to_dma); + + /* return "from" RxD block's DMA start address */ + from_dma = + __hal_ring_item_dma_addr(mempoolh, from_item, &from_dma_handle); + +#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_DTR_STREAMING) + /* we must sync "from" RxD block, so hardware will see it */ + xge_os_dma_sync(ring->channel.pdev, + from_dma_handle, + from_dma + XGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET, + __hal_ring_item_dma_offset(mempoolh, from_item) + + XGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET, + sizeof(u64), + XGE_OS_DMA_DIR_TODEVICE); +#endif + + xge_debug_ring(XGE_TRACE, "block%d:0x"XGE_OS_LLXFMT" => block%d:0x"XGE_OS_LLXFMT, + from, (unsigned long long)from_dma, to, + (unsigned long long)to_dma); +} + +static xge_hal_status_e +__hal_ring_mempool_item_alloc(xge_hal_mempool_h mempoolh, + void *memblock, + int memblock_index, + xge_hal_mempool_dma_t *dma_object, + void *item, + int index, + int is_last, + void *userdata) +{ + int i; + xge_hal_ring_t *ring = (xge_hal_ring_t *)userdata; + + xge_assert(item); + xge_assert(ring); + + + /* format rxds array */ + for (i=ring->rxds_per_block-1; i>=0; i--) { + void *rxdblock_priv; + xge_hal_ring_rxd_priv_t *rxd_priv; + xge_hal_ring_rxd_1_t *rxdp; + int reserve_index = index * ring->rxds_per_block + i; + int memblock_item_idx; + + ring->reserved_rxds_arr[reserve_index] = (char *)item + + (ring->rxds_per_block - 1 - i) * ring->rxd_size; + + /* Note: memblock_item_idx is index of the item within + * the memblock. For instance, in case of three RxD-blocks + * per memblock this value can be 0,1 or 2. */ + rxdblock_priv = + __hal_mempool_item_priv((xge_hal_mempool_t *) mempoolh, + memblock_index, item, + &memblock_item_idx); + rxdp = (xge_hal_ring_rxd_1_t *) + ring->reserved_rxds_arr[reserve_index]; + rxd_priv = (xge_hal_ring_rxd_priv_t *) (void *) + ((char*)rxdblock_priv + ring->rxd_priv_size * i); + + /* pre-format per-RxD Ring's private */ + rxd_priv->dma_offset = (char*)rxdp - (char*)memblock; + rxd_priv->dma_addr = dma_object->addr + rxd_priv->dma_offset; + rxd_priv->dma_handle = dma_object->handle; +#ifdef XGE_DEBUG_ASSERT + rxd_priv->dma_object = dma_object; +#endif + + /* pre-format Host_Control */ +#if defined(XGE_HAL_USE_5B_MODE) + if (ring->buffer_mode == XGE_HAL_RING_QUEUE_BUFFER_MODE_5) { + xge_hal_ring_rxd_5_t *rxdp_5 = (xge_hal_ring_rxd_5_t *)rxdp; +#if defined(XGE_OS_PLATFORM_64BIT) + xge_assert(memblock_index <= 0xFFFF); + xge_assert(i <= 0xFFFF); + /* store memblock's index */ + rxdp_5->host_control = (u32)memblock_index << 16; + /* store index of memblock's private */ + rxdp_5->host_control |= (u32)(memblock_item_idx * + ring->rxds_per_block + i); +#else + /* 32-bit case */ + rxdp_5->host_control = (u32)rxd_priv; +#endif + } else { + /* 1b and 3b modes */ + rxdp->host_control = (u64)(ulong_t)rxd_priv; + } +#else + /* 1b and 3b modes */ + rxdp->host_control = (u64)(ulong_t)rxd_priv; +#endif + } + + __hal_ring_block_memblock_idx_set((xge_hal_ring_block_t *) item, memblock_index); + + if (is_last) { + /* link last one with first one */ + __hal_ring_rxdblock_link(mempoolh, ring, 0, index); + } + + if (index > 0 ) { + /* link this RxD block with previous one */ + __hal_ring_rxdblock_link(mempoolh, ring, index, index-1); + } + + return XGE_HAL_OK; +} + + xge_hal_status_e +__hal_ring_initial_replenish(xge_hal_channel_t *channel, + xge_hal_channel_reopen_e reopen) +{ + xge_hal_dtr_h dtr; + + while (xge_hal_channel_dtr_count(channel) > 0) { + xge_hal_status_e status; + + status = xge_hal_ring_dtr_reserve(channel, &dtr); + xge_assert(status == XGE_HAL_OK); + + if (channel->dtr_init) { + status = channel->dtr_init(channel, + dtr, channel->reserve_length, + channel->userdata, + reopen); + if (status != XGE_HAL_OK) { + xge_hal_ring_dtr_free(channel, dtr); + xge_hal_channel_abort(channel, + XGE_HAL_CHANNEL_OC_NORMAL); + return status; + } + } + + xge_hal_ring_dtr_post(channel, dtr); + } + + return XGE_HAL_OK; +} + +xge_hal_status_e +__hal_ring_open(xge_hal_channel_h channelh, xge_hal_channel_attr_t *attr) +{ + xge_hal_status_e status; + xge_hal_device_t *hldev; + xge_hal_ring_t *ring = (xge_hal_ring_t *)channelh; + xge_hal_ring_queue_t *queue; + + + /* Note: at this point we have channel.devh and channel.pdev + * pre-set only! */ + + hldev = (xge_hal_device_t *)ring->channel.devh; + ring->config = &hldev->config.ring; + queue = &ring->config->queue[attr->post_qid]; + ring->indicate_max_pkts = queue->indicate_max_pkts; + ring->buffer_mode = queue->buffer_mode; + + xge_assert(queue->configured); + +#if defined(XGE_HAL_RX_MULTI_RESERVE) + xge_os_spin_lock_init(&ring->channel.reserve_lock, hldev->pdev); +#elif defined(XGE_HAL_RX_MULTI_RESERVE_IRQ) + xge_os_spin_lock_init_irq(&ring->channel.reserve_lock, hldev->irqh); +#endif +#if defined(XGE_HAL_RX_MULTI_POST) + xge_os_spin_lock_init(&ring->channel.post_lock, hldev->pdev); +#elif defined(XGE_HAL_RX_MULTI_POST_IRQ) + xge_os_spin_lock_init_irq(&ring->channel.post_lock, hldev->irqh); +#endif + + ring->rxd_size = XGE_HAL_RING_RXD_SIZEOF(queue->buffer_mode); + ring->rxd_priv_size = + sizeof(xge_hal_ring_rxd_priv_t) + attr->per_dtr_space; + + /* how many RxDs can fit into one block. Depends on configured + * buffer_mode. */ + ring->rxds_per_block = XGE_HAL_RING_RXDS_PER_BLOCK(queue->buffer_mode); + + /* calculate actual RxD block private size */ + ring->rxdblock_priv_size = ring->rxd_priv_size * ring->rxds_per_block; + + ring->reserved_rxds_arr = (void **) xge_os_malloc(ring->channel.pdev, + sizeof(void*) * queue->max * ring->rxds_per_block); + + if (ring->reserved_rxds_arr == NULL) { + __hal_ring_close(channelh); + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + + ring->mempool = __hal_mempool_create( + hldev->pdev, + ring->config->memblock_size, + XGE_HAL_RING_RXDBLOCK_SIZE, + ring->rxdblock_priv_size, + queue->initial, queue->max, + __hal_ring_mempool_item_alloc, + NULL, /* nothing to free */ + ring); + if (ring->mempool == NULL) { + __hal_ring_close(channelh); + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + + status = __hal_channel_initialize(channelh, + attr, + ring->reserved_rxds_arr, + queue->initial * ring->rxds_per_block, + queue->max * ring->rxds_per_block, + 0 /* no threshold for ring! */); + if (status != XGE_HAL_OK) { + __hal_ring_close(channelh); + return status; + } + + /* sanity check that everything formatted ok */ + xge_assert(ring->reserved_rxds_arr[0] == + (char *)ring->mempool->items_arr[0] + + (ring->rxds_per_block * ring->rxd_size - ring->rxd_size)); + + /* Note: + * Specifying dtr_init callback means two things: + * 1) dtrs need to be initialized by ULD at channel-open time; + * 2) dtrs need to be posted at channel-open time + * (that's what the initial_replenish() below does) + * Currently we don't have a case when the 1) is done without the 2). + */ + if (ring->channel.dtr_init) { + if ((status = __hal_ring_initial_replenish ( + (xge_hal_channel_t *) channelh, + XGE_HAL_CHANNEL_OC_NORMAL) ) + != XGE_HAL_OK) { + __hal_ring_close(channelh); + return status; + } + } + + /* initial replenish will increment the counter in its post() routine, + * we have to reset it */ + ring->channel.usage_cnt = 0; + + return XGE_HAL_OK; +} + +void +__hal_ring_close(xge_hal_channel_h channelh) +{ + xge_hal_ring_t *ring = (xge_hal_ring_t *)channelh; + xge_hal_ring_queue_t *queue; +#if defined(XGE_HAL_RX_MULTI_RESERVE)||defined(XGE_HAL_RX_MULTI_RESERVE_IRQ)||\ + defined(XGE_HAL_RX_MULTI_POST) || defined(XGE_HAL_RX_MULTI_POST_IRQ) + xge_hal_device_t *hldev = (xge_hal_device_t *)ring->channel.devh; +#endif + + xge_assert(ring->channel.pdev); + + queue = &ring->config->queue[ring->channel.post_qid]; + + if (ring->mempool) { + __hal_mempool_destroy(ring->mempool); + } + + if (ring->reserved_rxds_arr) { + xge_os_free(ring->channel.pdev, + ring->reserved_rxds_arr, + sizeof(void*) * queue->max * ring->rxds_per_block); + } + + __hal_channel_terminate(channelh); + +#if defined(XGE_HAL_RX_MULTI_RESERVE) + xge_os_spin_lock_destroy(&ring->channel.reserve_lock, hldev->pdev); +#elif defined(XGE_HAL_RX_MULTI_RESERVE_IRQ) + xge_os_spin_lock_destroy_irq(&ring->channel.reserve_lock, hldev->pdev); +#endif +#if defined(XGE_HAL_RX_MULTI_POST) + xge_os_spin_lock_destroy(&ring->channel.post_lock, hldev->pdev); +#elif defined(XGE_HAL_RX_MULTI_POST_IRQ) + xge_os_spin_lock_destroy_irq(&ring->channel.post_lock, hldev->pdev); +#endif +} + +void +__hal_ring_prc_enable(xge_hal_channel_h channelh) +{ + xge_hal_ring_t *ring = (xge_hal_ring_t *)channelh; + xge_hal_device_t *hldev = (xge_hal_device_t *)ring->channel.devh; + xge_hal_pci_bar0_t *bar0; + u64 val64; + void *first_block; + int block_num; + xge_hal_ring_queue_t *queue; + pci_dma_h dma_handle; + + xge_assert(ring); + xge_assert(ring->channel.pdev); + bar0 = (xge_hal_pci_bar0_t *) (void *) + ((xge_hal_device_t *)ring->channel.devh)->bar0; + + queue = &ring->config->queue[ring->channel.post_qid]; + xge_assert(queue->buffer_mode == 1 || + queue->buffer_mode == 3 || + queue->buffer_mode == 5); + + /* last block in fact becomes first. This is just the way it + * is filled up and linked by item_alloc() */ + + block_num = queue->initial; + first_block = __hal_mempool_item(ring->mempool, block_num - 1); + val64 = __hal_ring_item_dma_addr(ring->mempool, + first_block, &dma_handle); + xge_os_pio_mem_write64(ring->channel.pdev, ring->channel.regh0, + val64, &bar0->prc_rxd0_n[ring->channel.post_qid]); + + xge_debug_ring(XGE_TRACE, "ring%d PRC DMA addr 0x"XGE_OS_LLXFMT" initialized", + ring->channel.post_qid, (unsigned long long)val64); + + val64 = xge_os_pio_mem_read64(ring->channel.pdev, + ring->channel.regh0, &bar0->prc_ctrl_n[ring->channel.post_qid]); + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC && + !queue->rth_en) { + val64 |= XGE_HAL_PRC_CTRL_RTH_DISABLE; + } + val64 |= XGE_HAL_PRC_CTRL_RC_ENABLED; + + val64 |= vBIT((queue->buffer_mode >> 1),14,2);/* 1,3 or 5 => 0,1 or 2 */ + val64 &= ~XGE_HAL_PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF); + val64 |= XGE_HAL_PRC_CTRL_RXD_BACKOFF_INTERVAL( + (hldev->config.pci_freq_mherz * queue->backoff_interval_us)); + + /* Beware: no snoop by the bridge if (no_snoop_bits) */ + val64 |= XGE_HAL_PRC_CTRL_NO_SNOOP(queue->no_snoop_bits); + + /* Herc: always use group_reads */ + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) + val64 |= XGE_HAL_PRC_CTRL_GROUP_READS; + + if (hldev->config.bimodal_interrupts) + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) + val64 |= XGE_HAL_PRC_CTRL_BIMODAL_INTERRUPT; + + xge_os_pio_mem_write64(ring->channel.pdev, ring->channel.regh0, + val64, &bar0->prc_ctrl_n[ring->channel.post_qid]); + + /* Configure Receive Protocol Assist */ + val64 = xge_os_pio_mem_read64(ring->channel.pdev, + ring->channel.regh0, &bar0->rx_pa_cfg); + val64 |= XGE_HAL_RX_PA_CFG_SCATTER_MODE(ring->config->scatter_mode); + val64 |= (XGE_HAL_RX_PA_CFG_IGNORE_SNAP_OUI | XGE_HAL_RX_PA_CFG_IGNORE_LLC_CTRL); + /* Clean STRIP_VLAN_TAG bit and set as config from upper layer */ + val64 &= ~XGE_HAL_RX_PA_CFG_STRIP_VLAN_TAG_MODE(1); + val64 |= XGE_HAL_RX_PA_CFG_STRIP_VLAN_TAG_MODE(ring->config->strip_vlan_tag); + + xge_os_pio_mem_write64(ring->channel.pdev, ring->channel.regh0, + val64, &bar0->rx_pa_cfg); + + xge_debug_ring(XGE_TRACE, "ring%d enabled in buffer_mode %d", + ring->channel.post_qid, queue->buffer_mode); +} + +void +__hal_ring_prc_disable(xge_hal_channel_h channelh) +{ + xge_hal_ring_t *ring = (xge_hal_ring_t *)channelh; + xge_hal_pci_bar0_t *bar0; + u64 val64; + + xge_assert(ring); + xge_assert(ring->channel.pdev); + bar0 = (xge_hal_pci_bar0_t *) (void *) + ((xge_hal_device_t *)ring->channel.devh)->bar0; + + val64 = xge_os_pio_mem_read64(ring->channel.pdev, + ring->channel.regh0, + &bar0->prc_ctrl_n[ring->channel.post_qid]); + val64 &= ~((u64) XGE_HAL_PRC_CTRL_RC_ENABLED); + xge_os_pio_mem_write64(ring->channel.pdev, ring->channel.regh0, + val64, &bar0->prc_ctrl_n[ring->channel.post_qid]); +} + +void +__hal_ring_hw_initialize(xge_hal_device_h devh) +{ + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + u64 val64; + int i, j; + + /* Rx DMA intialization. */ + + val64 = 0; + for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) { + if (!hldev->config.ring.queue[i].configured) + continue; + val64 |= vBIT(hldev->config.ring.queue[i].priority, + (5 + (i * 8)), 3); + } + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rx_queue_priority); + xge_debug_ring(XGE_TRACE, "Rings priority configured to 0x"XGE_OS_LLXFMT, + (unsigned long long)val64); + + /* Configuring ring queues according to per-ring configuration */ + val64 = 0; + for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) { + if (!hldev->config.ring.queue[i].configured) + continue; + val64 |= vBIT(hldev->config.ring.queue[i].dram_size_mb,(i*8),8); + } + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rx_queue_cfg); + xge_debug_ring(XGE_TRACE, "DRAM configured to 0x"XGE_OS_LLXFMT, + (unsigned long long)val64); + + if (!hldev->config.rts_qos_en && + !hldev->config.rts_port_en && + !hldev->config.rts_mac_en) { + + /* + * Activate default (QoS-based) Rx steering + */ + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->rts_qos_steering); + for (j = 0; j < 8 /* QoS max */; j++) + { + for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) + { + if (!hldev->config.ring.queue[i].configured) + continue; + if (!hldev->config.ring.queue[i].rth_en) + val64 |= (BIT(i) >> (j*8)); + } + } + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->rts_qos_steering); + xge_debug_ring(XGE_TRACE, "QoS steering configured to 0x"XGE_OS_LLXFMT, + (unsigned long long)val64); + + } + + /* Note: If a queue does not exist, it should be assigned a maximum + * length of zero. Otherwise, packet loss could occur. + * P. 4-4 User guide. + * + * All configured rings will be properly set at device open time + * by utilizing device_mtu_set() API call. */ + for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) { + if (hldev->config.ring.queue[i].configured) + continue; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, 0ULL, + &bar0->rts_frm_len_n[i]); + } + +#ifdef XGE_HAL_HERC_EMULATION + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + ((u8 *)bar0 + 0x2e60)); /* mc_rldram_mrs_herc */ + val64 |= 0x0000000000010000; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + ((u8 *)bar0 + 0x2e60)); + + val64 |= 0x003a000000000000; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + ((u8 *)bar0 + 0x2e40)); /* mc_rldram_ref_herc */ + xge_os_mdelay(2000); +#endif + + /* now enabling MC-RLDRAM after setting MC_QUEUE sizes */ + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->mc_rldram_mrs); + val64 |= XGE_HAL_MC_RLDRAM_QUEUE_SIZE_ENABLE | + XGE_HAL_MC_RLDRAM_MRS_ENABLE; + __hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0, (u32)(val64>>32), + &bar0->mc_rldram_mrs); + xge_os_wmb(); + __hal_pio_mem_write32_lower(hldev->pdev, hldev->regh0, (u32)val64, + &bar0->mc_rldram_mrs); + + /* RLDRAM initialization procedure require 500us to complete */ + xge_os_mdelay(1); + + /* Temporary fixes for Herc RLDRAM */ + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) { + val64 = XGE_HAL_MC_RLDRAM_SET_REF_PERIOD(0x0279); + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->mc_rldram_ref_per_herc); + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->mc_rldram_mrs_herc); + xge_debug_ring(XGE_TRACE, "default mc_rldram_mrs_herc 0x"XGE_OS_LLXFMT, + (unsigned long long)val64); + + val64 = 0x0003570003010300ULL; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->mc_rldram_mrs_herc); + + xge_os_mdelay(1); + } + + /* + * Assign MSI-X vectors + */ + for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) { + xge_list_t *item; + xge_hal_channel_t *channel = NULL; + + if (!hldev->config.ring.queue[i].configured || + !hldev->config.ring.queue[i].intr_vector || + !hldev->config.intr_mode != XGE_HAL_INTR_MODE_MSIX) + continue; + + /* find channel */ + xge_list_for_each(item, &hldev->free_channels) { + xge_hal_channel_t *tmp; + tmp = xge_container_of(item, xge_hal_channel_t, + item); + if (tmp->type == XGE_HAL_CHANNEL_TYPE_RING && + tmp->post_qid == i) { + channel = tmp; + break; + } + } + + if (channel) { + xge_hal_channel_msix_set(channel, + hldev->config.ring.queue[i].intr_vector); + } + } + + xge_debug_ring(XGE_TRACE, "%s", "ring channels initialized"); +} + +void +__hal_ring_mtu_set(xge_hal_device_h devh, int new_frmlen) +{ + int i; + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + + for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) { + if (!hldev->config.ring.queue[i].configured) + continue; + if (hldev->config.ring.queue[i].max_frm_len != + XGE_HAL_RING_USE_MTU) { + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_MAC_RTS_FRM_LEN_SET( + hldev->config.ring.queue[i].max_frm_len), + &bar0->rts_frm_len_n[i]); + } else { + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_MAC_RTS_FRM_LEN_SET(new_frmlen), + &bar0->rts_frm_len_n[i]); + } + } + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + XGE_HAL_RMAC_MAX_PYLD_LEN(new_frmlen), + &bar0->rmac_max_pyld_len); +} diff --git a/sys/dev/nxge/xgehal/xgehal-stats.c b/sys/dev/nxge/xgehal/xgehal-stats.c new file mode 100644 index 0000000..2755ebb --- /dev/null +++ b/sys/dev/nxge/xgehal/xgehal-stats.c @@ -0,0 +1,1019 @@ +/*- + * Copyright (c) 2002-2007 Neterion, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * FileName : xgehal-stats.c + * + * Description: statistics object implementation + * + * Created: 2 June 2004 + */ + +#include +#include + +/* + * __hal_stats_initialize + * @stats: xge_hal_stats_t structure that contains, in particular, + * Xframe hw stat counters. + * @devh: HAL device handle. + * + * Initialize per-device statistics object. + * See also: xge_hal_stats_getinfo(), xge_hal_status_e{}. + */ +xge_hal_status_e +__hal_stats_initialize (xge_hal_stats_t *stats, xge_hal_device_h devh) +{ + int dma_flags; + xge_hal_device_t *hldev = (xge_hal_device_t*)devh; + + xge_assert(!stats->is_initialized); + + dma_flags = XGE_OS_DMA_CACHELINE_ALIGNED; +#ifdef XGE_HAL_DMA_STATS_CONSISTENT + dma_flags |= XGE_OS_DMA_CONSISTENT; +#else + dma_flags |= XGE_OS_DMA_STREAMING; +#endif + if (xge_hal_device_check_id(hldev) != XGE_HAL_CARD_TITAN) { + stats->hw_info = + (xge_hal_stats_hw_info_t *) xge_os_dma_malloc( + hldev->pdev, + sizeof(xge_hal_stats_hw_info_t), + dma_flags, + &stats->hw_info_dmah, + &stats->hw_info_dma_acch); + + if (stats->hw_info == NULL) { + xge_debug_stats(XGE_ERR, "%s", "can not DMA alloc"); + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + xge_os_memzero(stats->hw_info, + sizeof(xge_hal_stats_hw_info_t)); + xge_os_memzero(&stats->hw_info_saved, + sizeof(xge_hal_stats_hw_info_t)); + xge_os_memzero(&stats->hw_info_latest, + sizeof(xge_hal_stats_hw_info_t)); + + + + stats->dma_addr = xge_os_dma_map(hldev->pdev, + stats->hw_info_dmah, + stats->hw_info, + sizeof(xge_hal_stats_hw_info_t), + XGE_OS_DMA_DIR_FROMDEVICE, + XGE_OS_DMA_CACHELINE_ALIGNED | +#ifdef XGE_HAL_DMA_STATS_CONSISTENT + XGE_OS_DMA_CONSISTENT +#else + XGE_OS_DMA_STREAMING +#endif + ); + if (stats->dma_addr == XGE_OS_INVALID_DMA_ADDR) { + xge_debug_stats(XGE_ERR, + "can not map vaddr 0x"XGE_OS_LLXFMT" to DMA", + (unsigned long long)(ulong_t)stats->hw_info); + xge_os_dma_free(hldev->pdev, + stats->hw_info, + sizeof(xge_hal_stats_hw_info_t), + &stats->hw_info_dma_acch, + &stats->hw_info_dmah); + return XGE_HAL_ERR_OUT_OF_MAPPING; + } + } + else { + stats->pcim_info_saved = + (xge_hal_stats_pcim_info_t *)xge_os_malloc( + hldev->pdev, sizeof(xge_hal_stats_pcim_info_t)); + if (stats->pcim_info_saved == NULL) { + xge_debug_stats(XGE_ERR, "%s", "can not alloc"); + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + + stats->pcim_info_latest = + (xge_hal_stats_pcim_info_t *)xge_os_malloc( + hldev->pdev, sizeof(xge_hal_stats_pcim_info_t)); + if (stats->pcim_info_latest == NULL) { + xge_os_free(hldev->pdev, stats->pcim_info_saved, + sizeof(xge_hal_stats_pcim_info_t)); + xge_debug_stats(XGE_ERR, "%s", "can not alloc"); + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + + stats->pcim_info = + (xge_hal_stats_pcim_info_t *) xge_os_dma_malloc( + hldev->pdev, + sizeof(xge_hal_stats_pcim_info_t), + dma_flags, + &stats->hw_info_dmah, + &stats->hw_info_dma_acch); + + if (stats->pcim_info == NULL) { + xge_os_free(hldev->pdev, stats->pcim_info_saved, + sizeof(xge_hal_stats_pcim_info_t)); + xge_os_free(hldev->pdev, stats->pcim_info_latest, + sizeof(xge_hal_stats_pcim_info_t)); + xge_debug_stats(XGE_ERR, "%s", "can not DMA alloc"); + return XGE_HAL_ERR_OUT_OF_MEMORY; + } + + + xge_os_memzero(stats->pcim_info, + sizeof(xge_hal_stats_pcim_info_t)); + xge_os_memzero(stats->pcim_info_saved, + sizeof(xge_hal_stats_pcim_info_t)); + xge_os_memzero(stats->pcim_info_latest, + sizeof(xge_hal_stats_pcim_info_t)); + + + + stats->dma_addr = xge_os_dma_map(hldev->pdev, + stats->hw_info_dmah, + stats->pcim_info, + sizeof(xge_hal_stats_pcim_info_t), + XGE_OS_DMA_DIR_FROMDEVICE, + XGE_OS_DMA_CACHELINE_ALIGNED | +#ifdef XGE_HAL_DMA_STATS_CONSISTENT + XGE_OS_DMA_CONSISTENT +#else + XGE_OS_DMA_STREAMING +#endif + ); + if (stats->dma_addr == XGE_OS_INVALID_DMA_ADDR) { + xge_debug_stats(XGE_ERR, + "can not map vaddr 0x"XGE_OS_LLXFMT" to DMA", + (unsigned long long)(ulong_t)stats->hw_info); + + xge_os_dma_free(hldev->pdev, + stats->pcim_info, + sizeof(xge_hal_stats_pcim_info_t), + &stats->hw_info_dma_acch, + &stats->hw_info_dmah); + + xge_os_free(hldev->pdev, stats->pcim_info_saved, + sizeof(xge_hal_stats_pcim_info_t)); + + xge_os_free(hldev->pdev, stats->pcim_info_latest, + sizeof(xge_hal_stats_pcim_info_t)); + + return XGE_HAL_ERR_OUT_OF_MAPPING; + } + } + stats->devh = devh; + xge_os_memzero(&stats->sw_dev_info_stats, + sizeof(xge_hal_stats_device_info_t)); + + stats->is_initialized = 1; + + return XGE_HAL_OK; +} + +static void +__hal_stats_save (xge_hal_stats_t *stats) +{ + xge_hal_device_t *hldev = (xge_hal_device_t*)stats->devh; + + if (xge_hal_device_check_id(hldev) != XGE_HAL_CARD_TITAN) { + xge_hal_stats_hw_info_t *latest; + + (void) xge_hal_stats_hw(stats->devh, &latest); + + xge_os_memcpy(&stats->hw_info_saved, stats->hw_info, + sizeof(xge_hal_stats_hw_info_t)); + } else { + xge_hal_stats_pcim_info_t *latest; + + (void) xge_hal_stats_pcim(stats->devh, &latest); + + xge_os_memcpy(stats->pcim_info_saved, stats->pcim_info, + sizeof(xge_hal_stats_pcim_info_t)); + } +} + +/* + * __hal_stats_disable + * @stats: xge_hal_stats_t structure that contains, in particular, + * Xframe hw stat counters. + * + * Ask device to stop collecting stats. + * See also: xge_hal_stats_getinfo(). + */ +void +__hal_stats_disable (xge_hal_stats_t *stats) +{ + xge_hal_device_t *hldev; + xge_hal_pci_bar0_t *bar0; + u64 val64; + + xge_assert(stats->hw_info); + + hldev = (xge_hal_device_t*)stats->devh; + xge_assert(hldev); + bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + + val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->stat_cfg); + val64 &= ~XGE_HAL_STAT_CFG_STAT_EN; + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64, + &bar0->stat_cfg); + /* flush the write */ + (void)xge_os_pio_mem_read64(hldev->pdev, hldev->regh0, + &bar0->stat_cfg); + + xge_debug_stats(XGE_TRACE, "stats disabled at 0x"XGE_OS_LLXFMT, + (unsigned long long)stats->dma_addr); + + stats->is_enabled = 0; +} + +/* + * __hal_stats_terminate + * @stats: xge_hal_stats_t structure that contains, in particular, + * Xframe hw stat counters. + * Terminate per-device statistics object. + */ +void +__hal_stats_terminate (xge_hal_stats_t *stats) +{ + xge_hal_device_t *hldev; + + xge_assert(stats->hw_info); + + hldev = (xge_hal_device_t*)stats->devh; + xge_assert(hldev); + xge_assert(stats->is_initialized); + if (xge_hal_device_check_id(hldev) != XGE_HAL_CARD_TITAN) { + xge_os_dma_unmap(hldev->pdev, + stats->hw_info_dmah, + stats->dma_addr, + sizeof(xge_hal_stats_hw_info_t), + XGE_OS_DMA_DIR_FROMDEVICE); + + xge_os_dma_free(hldev->pdev, + stats->hw_info, + sizeof(xge_hal_stats_hw_info_t), + &stats->hw_info_dma_acch, + &stats->hw_info_dmah); + } else { + xge_os_dma_unmap(hldev->pdev, + stats->hw_info_dmah, + stats->dma_addr, + sizeof(xge_hal_stats_pcim_info_t), + XGE_OS_DMA_DIR_FROMDEVICE); + + xge_os_dma_free(hldev->pdev, + stats->pcim_info, + sizeof(xge_hal_stats_pcim_info_t), + &stats->hw_info_dma_acch, + &stats->hw_info_dmah); + + xge_os_free(hldev->pdev, stats->pcim_info_saved, + sizeof(xge_hal_stats_pcim_info_t)); + + xge_os_free(hldev->pdev, stats->pcim_info_latest, + sizeof(xge_hal_stats_pcim_info_t)); + + } + + stats->is_initialized = 0; + stats->is_enabled = 0; +} + + + +/* + * __hal_stats_enable + * @stats: xge_hal_stats_t structure that contains, in particular, + * Xframe hw stat counters. + * + * Ask device to start collecting stats. + * See also: xge_hal_stats_getinfo(). + */ +void +__hal_stats_enable (xge_hal_stats_t *stats) +{ + xge_hal_device_t *hldev; + xge_hal_pci_bar0_t *bar0; + u64 val64; + unsigned int refresh_time_pci_clocks; + + xge_assert(stats->hw_info); + + hldev = (xge_hal_device_t*)stats->devh; + xge_assert(hldev); + + bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0; + + /* enable statistics + * For Titan stat_addr offset == 0x09d8, and stat_cfg offset == 0x09d0 + */ + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + stats->dma_addr, &bar0->stat_addr); + + refresh_time_pci_clocks = XGE_HAL_XENA_PER_SEC * + hldev->config.stats_refresh_time_sec; + refresh_time_pci_clocks = + __hal_fix_time_ival_herc(hldev, + refresh_time_pci_clocks); + +#ifdef XGE_HAL_HERC_EMULATION + /* + * The clocks in the emulator are running ~1000 times slower + * than real world, so the stats transfer will occur ~1000 + * times less frequent. STAT_CFG.STAT_TRSF_PERIOD should be + * set to 0x20C for Hercules emulation (stats transferred + * every 0.5 sec). + */ + + val64 = (0x20C | XGE_HAL_STAT_CFG_STAT_RO | + XGE_HAL_STAT_CFG_STAT_EN); +#else + val64 = XGE_HAL_SET_UPDT_PERIOD(refresh_time_pci_clocks) | + XGE_HAL_STAT_CFG_STAT_RO | + XGE_HAL_STAT_CFG_STAT_EN; +#endif + + xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, + val64, &bar0->stat_cfg); + + xge_debug_stats(XGE_TRACE, "stats enabled at 0x"XGE_OS_LLXFMT, + (unsigned long long)stats->dma_addr); + + stats->is_enabled = 1; +} + +/* + * __hal_stats_pcim_update_latest - Update hw ER stats counters, based on the + * real hardware maintained counters and the stored "reset" values. + */ +static void +__hal_stats_pcim_update_latest(xge_hal_device_h devh) +{ + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + int i; + +#define set_latest_stat_link_cnt(_link, _p) \ + hldev->stats.pcim_info_latest->link_info[_link]._p = \ + ((hldev->stats.pcim_info->link_info[_link]._p >= \ + hldev->stats.pcim_info_saved->link_info[_link]._p) ? \ + hldev->stats.pcim_info->link_info[_link]._p - \ + hldev->stats.pcim_info_saved->link_info[_link]._p : \ + ((-1) - hldev->stats.pcim_info_saved->link_info[_link]._p) + \ + hldev->stats.pcim_info->link_info[_link]._p) + + +#define set_latest_stat_aggr_cnt(_aggr, _p) \ + hldev->stats.pcim_info_latest->aggr_info[_aggr]._p = \ + ((hldev->stats.pcim_info->aggr_info[_aggr]._p >= \ + hldev->stats.pcim_info_saved->aggr_info[_aggr]._p) ? \ + hldev->stats.pcim_info->aggr_info[_aggr]._p - \ + hldev->stats.pcim_info_saved->aggr_info[_aggr]._p : \ + ((-1) - hldev->stats.pcim_info_saved->aggr_info[_aggr]._p) + \ + hldev->stats.pcim_info->aggr_info[_aggr]._p) + + + for (i = 0; i < XGE_HAL_MAC_LINKS; i++) { + set_latest_stat_link_cnt(i, tx_frms); + set_latest_stat_link_cnt(i, tx_ttl_eth_octets); + set_latest_stat_link_cnt(i, tx_data_octets); + set_latest_stat_link_cnt(i, tx_mcst_frms); + set_latest_stat_link_cnt(i, tx_bcst_frms); + set_latest_stat_link_cnt(i, tx_ucst_frms); + set_latest_stat_link_cnt(i, tx_tagged_frms); + set_latest_stat_link_cnt(i, tx_vld_ip); + set_latest_stat_link_cnt(i, tx_vld_ip_octets); + set_latest_stat_link_cnt(i, tx_icmp); + set_latest_stat_link_cnt(i, tx_tcp); + set_latest_stat_link_cnt(i, tx_rst_tcp); + set_latest_stat_link_cnt(i, tx_udp); + set_latest_stat_link_cnt(i, tx_unknown_protocol); + set_latest_stat_link_cnt(i, tx_parse_error); + set_latest_stat_link_cnt(i, tx_pause_ctrl_frms); + set_latest_stat_link_cnt(i, tx_lacpdu_frms); + set_latest_stat_link_cnt(i, tx_marker_pdu_frms); + set_latest_stat_link_cnt(i, tx_marker_resp_pdu_frms); + set_latest_stat_link_cnt(i, tx_drop_ip); + set_latest_stat_link_cnt(i, tx_xgmii_char1_match); + set_latest_stat_link_cnt(i, tx_xgmii_char2_match); + set_latest_stat_link_cnt(i, tx_xgmii_column1_match); + set_latest_stat_link_cnt(i, tx_xgmii_column2_match); + set_latest_stat_link_cnt(i, tx_drop_frms); + set_latest_stat_link_cnt(i, tx_any_err_frms); + set_latest_stat_link_cnt(i, rx_ttl_frms); + set_latest_stat_link_cnt(i, rx_vld_frms); + set_latest_stat_link_cnt(i, rx_offld_frms); + set_latest_stat_link_cnt(i, rx_ttl_eth_octets); + set_latest_stat_link_cnt(i, rx_data_octets); + set_latest_stat_link_cnt(i, rx_offld_octets); + set_latest_stat_link_cnt(i, rx_vld_mcst_frms); + set_latest_stat_link_cnt(i, rx_vld_bcst_frms); + set_latest_stat_link_cnt(i, rx_accepted_ucst_frms); + set_latest_stat_link_cnt(i, rx_accepted_nucst_frms); + set_latest_stat_link_cnt(i, rx_tagged_frms); + set_latest_stat_link_cnt(i, rx_long_frms); + set_latest_stat_link_cnt(i, rx_usized_frms); + set_latest_stat_link_cnt(i, rx_osized_frms); + set_latest_stat_link_cnt(i, rx_frag_frms); + set_latest_stat_link_cnt(i, rx_jabber_frms); + set_latest_stat_link_cnt(i, rx_ttl_64_frms); + set_latest_stat_link_cnt(i, rx_ttl_65_127_frms); + set_latest_stat_link_cnt(i, rx_ttl_128_255_frms); + set_latest_stat_link_cnt(i, rx_ttl_256_511_frms); + set_latest_stat_link_cnt(i, rx_ttl_512_1023_frms); + set_latest_stat_link_cnt(i, rx_ttl_1024_1518_frms); + set_latest_stat_link_cnt(i, rx_ttl_1519_4095_frms); + set_latest_stat_link_cnt(i, rx_ttl_40956_8191_frms); + set_latest_stat_link_cnt(i, rx_ttl_8192_max_frms); + set_latest_stat_link_cnt(i, rx_ttl_gt_max_frms); + set_latest_stat_link_cnt(i, rx_ip); + set_latest_stat_link_cnt(i, rx_ip_octets); + set_latest_stat_link_cnt(i, rx_hdr_err_ip); + set_latest_stat_link_cnt(i, rx_icmp); + set_latest_stat_link_cnt(i, rx_tcp); + set_latest_stat_link_cnt(i, rx_udp); + set_latest_stat_link_cnt(i, rx_err_tcp); + set_latest_stat_link_cnt(i, rx_pause_cnt); + set_latest_stat_link_cnt(i, rx_pause_ctrl_frms); + set_latest_stat_link_cnt(i, rx_unsup_ctrl_frms); + set_latest_stat_link_cnt(i, rx_in_rng_len_err_frms); + set_latest_stat_link_cnt(i, rx_out_rng_len_err_frms); + set_latest_stat_link_cnt(i, rx_drop_frms); + set_latest_stat_link_cnt(i, rx_discarded_frms); + set_latest_stat_link_cnt(i, rx_drop_ip); + set_latest_stat_link_cnt(i, rx_err_drp_udp); + set_latest_stat_link_cnt(i, rx_lacpdu_frms); + set_latest_stat_link_cnt(i, rx_marker_pdu_frms); + set_latest_stat_link_cnt(i, rx_marker_resp_pdu_frms); + set_latest_stat_link_cnt(i, rx_unknown_pdu_frms); + set_latest_stat_link_cnt(i, rx_illegal_pdu_frms); + set_latest_stat_link_cnt(i, rx_fcs_discard); + set_latest_stat_link_cnt(i, rx_len_discard); + set_latest_stat_link_cnt(i, rx_pf_discard); + set_latest_stat_link_cnt(i, rx_trash_discard); + set_latest_stat_link_cnt(i, rx_rts_discard); + set_latest_stat_link_cnt(i, rx_wol_discard); + set_latest_stat_link_cnt(i, rx_red_discard); + set_latest_stat_link_cnt(i, rx_ingm_full_discard); + set_latest_stat_link_cnt(i, rx_xgmii_data_err_cnt); + set_latest_stat_link_cnt(i, rx_xgmii_ctrl_err_cnt); + set_latest_stat_link_cnt(i, rx_xgmii_err_sym); + set_latest_stat_link_cnt(i, rx_xgmii_char1_match); + set_latest_stat_link_cnt(i, rx_xgmii_char2_match); + set_latest_stat_link_cnt(i, rx_xgmii_column1_match); + set_latest_stat_link_cnt(i, rx_xgmii_column2_match); + set_latest_stat_link_cnt(i, rx_local_fault); + set_latest_stat_link_cnt(i, rx_remote_fault); + set_latest_stat_link_cnt(i, rx_queue_full); + } + + for (i = 0; i < XGE_HAL_MAC_AGGREGATORS; i++) { + set_latest_stat_aggr_cnt(i, tx_frms); + set_latest_stat_aggr_cnt(i, tx_mcst_frms); + set_latest_stat_aggr_cnt(i, tx_bcst_frms); + set_latest_stat_aggr_cnt(i, tx_discarded_frms); + set_latest_stat_aggr_cnt(i, tx_errored_frms); + set_latest_stat_aggr_cnt(i, rx_frms); + set_latest_stat_aggr_cnt(i, rx_data_octets); + set_latest_stat_aggr_cnt(i, rx_mcst_frms); + set_latest_stat_aggr_cnt(i, rx_bcst_frms); + set_latest_stat_aggr_cnt(i, rx_discarded_frms); + set_latest_stat_aggr_cnt(i, rx_errored_frms); + set_latest_stat_aggr_cnt(i, rx_unknown_protocol_frms); + } + return; +} + +/* + * __hal_stats_update_latest - Update hw stats counters, based on the real + * hardware maintained counters and the stored "reset" values. + */ +static void +__hal_stats_update_latest(xge_hal_device_h devh) +{ + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + +#define set_latest_stat_cnt(_dev, _p) \ + hldev->stats.hw_info_latest._p = \ + ((hldev->stats.hw_info->_p >= hldev->stats.hw_info_saved._p) ? \ + hldev->stats.hw_info->_p - hldev->stats.hw_info_saved._p : \ + ((-1) - hldev->stats.hw_info_saved._p) + hldev->stats.hw_info->_p) + + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_TITAN) { + __hal_stats_pcim_update_latest(devh); + return; + } + + /* Tx MAC statistics counters. */ + set_latest_stat_cnt(hldev, tmac_frms); + set_latest_stat_cnt(hldev, tmac_data_octets); + set_latest_stat_cnt(hldev, tmac_drop_frms); + set_latest_stat_cnt(hldev, tmac_mcst_frms); + set_latest_stat_cnt(hldev, tmac_bcst_frms); + set_latest_stat_cnt(hldev, tmac_pause_ctrl_frms); + set_latest_stat_cnt(hldev, tmac_ttl_octets); + set_latest_stat_cnt(hldev, tmac_ucst_frms); + set_latest_stat_cnt(hldev, tmac_nucst_frms); + set_latest_stat_cnt(hldev, tmac_any_err_frms); + set_latest_stat_cnt(hldev, tmac_ttl_less_fb_octets); + set_latest_stat_cnt(hldev, tmac_vld_ip_octets); + set_latest_stat_cnt(hldev, tmac_vld_ip); + set_latest_stat_cnt(hldev, tmac_drop_ip); + set_latest_stat_cnt(hldev, tmac_icmp); + set_latest_stat_cnt(hldev, tmac_rst_tcp); + set_latest_stat_cnt(hldev, tmac_tcp); + set_latest_stat_cnt(hldev, tmac_udp); + set_latest_stat_cnt(hldev, reserved_0); + + /* Rx MAC Statistics counters. */ + set_latest_stat_cnt(hldev, rmac_vld_frms); + set_latest_stat_cnt(hldev, rmac_data_octets); + set_latest_stat_cnt(hldev, rmac_fcs_err_frms); + set_latest_stat_cnt(hldev, rmac_drop_frms); + set_latest_stat_cnt(hldev, rmac_vld_mcst_frms); + set_latest_stat_cnt(hldev, rmac_vld_bcst_frms); + set_latest_stat_cnt(hldev, rmac_in_rng_len_err_frms); + set_latest_stat_cnt(hldev, rmac_out_rng_len_err_frms); + set_latest_stat_cnt(hldev, rmac_long_frms); + set_latest_stat_cnt(hldev, rmac_pause_ctrl_frms); + set_latest_stat_cnt(hldev, rmac_unsup_ctrl_frms); + set_latest_stat_cnt(hldev, rmac_ttl_octets); + set_latest_stat_cnt(hldev, rmac_accepted_ucst_frms); + set_latest_stat_cnt(hldev, rmac_accepted_nucst_frms); + set_latest_stat_cnt(hldev, rmac_discarded_frms); + set_latest_stat_cnt(hldev, rmac_drop_events); + set_latest_stat_cnt(hldev, reserved_1); + set_latest_stat_cnt(hldev, rmac_ttl_less_fb_octets); + set_latest_stat_cnt(hldev, rmac_ttl_frms); + set_latest_stat_cnt(hldev, reserved_2); + set_latest_stat_cnt(hldev, reserved_3); + set_latest_stat_cnt(hldev, rmac_usized_frms); + set_latest_stat_cnt(hldev, rmac_osized_frms); + set_latest_stat_cnt(hldev, rmac_frag_frms); + set_latest_stat_cnt(hldev, rmac_jabber_frms); + set_latest_stat_cnt(hldev, reserved_4); + set_latest_stat_cnt(hldev, rmac_ttl_64_frms); + set_latest_stat_cnt(hldev, rmac_ttl_65_127_frms); + set_latest_stat_cnt(hldev, reserved_5); + set_latest_stat_cnt(hldev, rmac_ttl_128_255_frms); + set_latest_stat_cnt(hldev, rmac_ttl_256_511_frms); + set_latest_stat_cnt(hldev, reserved_6); + set_latest_stat_cnt(hldev, rmac_ttl_512_1023_frms); + set_latest_stat_cnt(hldev, rmac_ttl_1024_1518_frms); + set_latest_stat_cnt(hldev, reserved_7); + set_latest_stat_cnt(hldev, rmac_ip); + set_latest_stat_cnt(hldev, rmac_ip_octets); + set_latest_stat_cnt(hldev, rmac_hdr_err_ip); + set_latest_stat_cnt(hldev, rmac_drop_ip); + set_latest_stat_cnt(hldev, rmac_icmp); + set_latest_stat_cnt(hldev, reserved_8); + set_latest_stat_cnt(hldev, rmac_tcp); + set_latest_stat_cnt(hldev, rmac_udp); + set_latest_stat_cnt(hldev, rmac_err_drp_udp); + set_latest_stat_cnt(hldev, rmac_xgmii_err_sym); + set_latest_stat_cnt(hldev, rmac_frms_q0); + set_latest_stat_cnt(hldev, rmac_frms_q1); + set_latest_stat_cnt(hldev, rmac_frms_q2); + set_latest_stat_cnt(hldev, rmac_frms_q3); + set_latest_stat_cnt(hldev, rmac_frms_q4); + set_latest_stat_cnt(hldev, rmac_frms_q5); + set_latest_stat_cnt(hldev, rmac_frms_q6); + set_latest_stat_cnt(hldev, rmac_frms_q7); + set_latest_stat_cnt(hldev, rmac_full_q0); + set_latest_stat_cnt(hldev, rmac_full_q1); + set_latest_stat_cnt(hldev, rmac_full_q2); + set_latest_stat_cnt(hldev, rmac_full_q3); + set_latest_stat_cnt(hldev, rmac_full_q4); + set_latest_stat_cnt(hldev, rmac_full_q5); + set_latest_stat_cnt(hldev, rmac_full_q6); + set_latest_stat_cnt(hldev, rmac_full_q7); + set_latest_stat_cnt(hldev, rmac_pause_cnt); + set_latest_stat_cnt(hldev, reserved_9); + set_latest_stat_cnt(hldev, rmac_xgmii_data_err_cnt); + set_latest_stat_cnt(hldev, rmac_xgmii_ctrl_err_cnt); + set_latest_stat_cnt(hldev, rmac_accepted_ip); + set_latest_stat_cnt(hldev, rmac_err_tcp); + + /* PCI/PCI-X Read transaction statistics. */ + set_latest_stat_cnt(hldev, rd_req_cnt); + set_latest_stat_cnt(hldev, new_rd_req_cnt); + set_latest_stat_cnt(hldev, new_rd_req_rtry_cnt); + set_latest_stat_cnt(hldev, rd_rtry_cnt); + set_latest_stat_cnt(hldev, wr_rtry_rd_ack_cnt); + + /* PCI/PCI-X write transaction statistics. */ + set_latest_stat_cnt(hldev, wr_req_cnt); + set_latest_stat_cnt(hldev, new_wr_req_cnt); + set_latest_stat_cnt(hldev, new_wr_req_rtry_cnt); + set_latest_stat_cnt(hldev, wr_rtry_cnt); + set_latest_stat_cnt(hldev, wr_disc_cnt); + set_latest_stat_cnt(hldev, rd_rtry_wr_ack_cnt); + + /* DMA Transaction statistics. */ + set_latest_stat_cnt(hldev, txp_wr_cnt); + set_latest_stat_cnt(hldev, txd_rd_cnt); + set_latest_stat_cnt(hldev, txd_wr_cnt); + set_latest_stat_cnt(hldev, rxd_rd_cnt); + set_latest_stat_cnt(hldev, rxd_wr_cnt); + set_latest_stat_cnt(hldev, txf_rd_cnt); + set_latest_stat_cnt(hldev, rxf_wr_cnt); + + /* Enhanced Herc statistics */ + set_latest_stat_cnt(hldev, tmac_frms_oflow); + set_latest_stat_cnt(hldev, tmac_data_octets_oflow); + set_latest_stat_cnt(hldev, tmac_mcst_frms_oflow); + set_latest_stat_cnt(hldev, tmac_bcst_frms_oflow); + set_latest_stat_cnt(hldev, tmac_ttl_octets_oflow); + set_latest_stat_cnt(hldev, tmac_ucst_frms_oflow); + set_latest_stat_cnt(hldev, tmac_nucst_frms_oflow); + set_latest_stat_cnt(hldev, tmac_any_err_frms_oflow); + set_latest_stat_cnt(hldev, tmac_vlan_frms); + set_latest_stat_cnt(hldev, tmac_vld_ip_oflow); + set_latest_stat_cnt(hldev, tmac_drop_ip_oflow); + set_latest_stat_cnt(hldev, tmac_icmp_oflow); + set_latest_stat_cnt(hldev, tmac_rst_tcp_oflow); + set_latest_stat_cnt(hldev, tmac_udp_oflow); + set_latest_stat_cnt(hldev, tpa_unknown_protocol); + set_latest_stat_cnt(hldev, tpa_parse_failure); + set_latest_stat_cnt(hldev, rmac_vld_frms_oflow); + set_latest_stat_cnt(hldev, rmac_data_octets_oflow); + set_latest_stat_cnt(hldev, rmac_vld_mcst_frms_oflow); + set_latest_stat_cnt(hldev, rmac_vld_bcst_frms_oflow); + set_latest_stat_cnt(hldev, rmac_ttl_octets_oflow); + set_latest_stat_cnt(hldev, rmac_accepted_ucst_frms_oflow); + set_latest_stat_cnt(hldev, rmac_accepted_nucst_frms_oflow); + set_latest_stat_cnt(hldev, rmac_discarded_frms_oflow); + set_latest_stat_cnt(hldev, rmac_drop_events_oflow); + set_latest_stat_cnt(hldev, rmac_usized_frms_oflow); + set_latest_stat_cnt(hldev, rmac_osized_frms_oflow); + set_latest_stat_cnt(hldev, rmac_frag_frms_oflow); + set_latest_stat_cnt(hldev, rmac_jabber_frms_oflow); + set_latest_stat_cnt(hldev, rmac_ip_oflow); + set_latest_stat_cnt(hldev, rmac_drop_ip_oflow); + set_latest_stat_cnt(hldev, rmac_icmp_oflow); + set_latest_stat_cnt(hldev, rmac_udp_oflow); + set_latest_stat_cnt(hldev, rmac_err_drp_udp_oflow); + set_latest_stat_cnt(hldev, rmac_pause_cnt_oflow); + set_latest_stat_cnt(hldev, rmac_ttl_1519_4095_frms); + set_latest_stat_cnt(hldev, rmac_ttl_4096_8191_frms); + set_latest_stat_cnt(hldev, rmac_ttl_8192_max_frms); + set_latest_stat_cnt(hldev, rmac_ttl_gt_max_frms); + set_latest_stat_cnt(hldev, rmac_osized_alt_frms); + set_latest_stat_cnt(hldev, rmac_jabber_alt_frms); + set_latest_stat_cnt(hldev, rmac_gt_max_alt_frms); + set_latest_stat_cnt(hldev, rmac_vlan_frms); + set_latest_stat_cnt(hldev, rmac_fcs_discard); + set_latest_stat_cnt(hldev, rmac_len_discard); + set_latest_stat_cnt(hldev, rmac_da_discard); + set_latest_stat_cnt(hldev, rmac_pf_discard); + set_latest_stat_cnt(hldev, rmac_rts_discard); + set_latest_stat_cnt(hldev, rmac_red_discard); + set_latest_stat_cnt(hldev, rmac_ingm_full_discard); + set_latest_stat_cnt(hldev, rmac_accepted_ip_oflow); + set_latest_stat_cnt(hldev, link_fault_cnt); +} + +/** + * xge_hal_stats_hw - Get HW device statistics. + * @devh: HAL device handle. + * @hw_info: Xframe statistic counters. See xge_hal_stats_hw_info_t. + * Returned by HAL. + * + * Get device and HAL statistics. The latter is part of the in-host statistics + * that HAL maintains for _that_ device. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_INF_STATS_IS_NOT_READY - Statistics information is not + * currently available. + * + * See also: xge_hal_status_e{}. + */ +xge_hal_status_e +xge_hal_stats_hw(xge_hal_device_h devh, xge_hal_stats_hw_info_t **hw_info) +{ + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + + xge_assert(xge_hal_device_check_id(hldev) != XGE_HAL_CARD_TITAN) + + if (!hldev->stats.is_initialized || + !hldev->stats.is_enabled) { + *hw_info = NULL; + return XGE_HAL_INF_STATS_IS_NOT_READY; + } + +#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_STATS_STREAMING) + xge_os_dma_sync(hldev->pdev, + hldev->stats.hw_info_dmah, + hldev->stats.dma_addr, + 0, + sizeof(xge_hal_stats_hw_info_t), + XGE_OS_DMA_DIR_FROMDEVICE); +#endif + + /* + * update hw counters, taking into account + * the "reset" or "saved" + * values + */ + __hal_stats_update_latest(devh); + + /* + * statistics HW bug fixups for Xena and Herc + */ + if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA || + xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) { + u64 mcst, bcst; + xge_hal_stats_hw_info_t *hwsta = &hldev->stats.hw_info_latest; + + mcst = ((u64)hwsta->rmac_vld_mcst_frms_oflow << 32) | + hwsta->rmac_vld_mcst_frms; + + bcst = ((u64)hwsta->rmac_vld_bcst_frms_oflow << 32) | + hwsta->rmac_vld_bcst_frms; + + mcst -= bcst; + + hwsta->rmac_vld_mcst_frms_oflow = (u32)(mcst >> 32); + hwsta->rmac_vld_mcst_frms = (u32)mcst; + } + + *hw_info = &hldev->stats.hw_info_latest; + + return XGE_HAL_OK; +} + +/** + * xge_hal_stats_pcim - Get HW device statistics. + * @devh: HAL device handle. + * @hw_info: Xframe statistic counters. See xge_hal_stats_pcim_info_t. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_INF_STATS_IS_NOT_READY - Statistics information is not + * currently available. + * + * See also: xge_hal_status_e{}. + */ +xge_hal_status_e +xge_hal_stats_pcim(xge_hal_device_h devh, xge_hal_stats_pcim_info_t **hw_info) +{ + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + + xge_assert(xge_hal_device_check_id(hldev) == XGE_HAL_CARD_TITAN) + + if (!hldev->stats.is_initialized || + !hldev->stats.is_enabled) { + *hw_info = NULL; + return XGE_HAL_INF_STATS_IS_NOT_READY; + } + +#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_STATS_STREAMING) + xge_os_dma_sync(hldev->pdev, + hldev->stats.hw_info_dmah, + hldev->stats.dma_addr, + 0, + sizeof(xge_hal_stats_pcim_info_t), + XGE_OS_DMA_DIR_FROMDEVICE); +#endif + + /* + * update hw counters, taking into account + * the "reset" or "saved" + * values + */ + __hal_stats_pcim_update_latest(devh); + + *hw_info = hldev->stats.pcim_info_latest; + + return XGE_HAL_OK; +} + +/** + * xge_hal_stats_device - Get HAL statistics. + * @devh: HAL device handle. + * @hw_info: Xframe statistic counters. See xge_hal_stats_hw_info_t. + * Returned by HAL. + * @device_info: HAL statistics. See xge_hal_stats_device_info_t. + * Returned by HAL. + * + * Get device and HAL statistics. The latter is part of the in-host statistics + * that HAL maintains for _that_ device. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_INF_STATS_IS_NOT_READY - Statistics information is not + * currently available. + * + * See also: xge_hal_status_e{}. + */ +xge_hal_status_e +xge_hal_stats_device(xge_hal_device_h devh, + xge_hal_stats_device_info_t **device_info) +{ + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + + if (!hldev->stats.is_initialized || + !hldev->stats.is_enabled) { + *device_info = NULL; + return XGE_HAL_INF_STATS_IS_NOT_READY; + } + + hldev->stats.sw_dev_info_stats.traffic_intr_cnt = + hldev->stats.sw_dev_info_stats.total_intr_cnt - + hldev->stats.sw_dev_info_stats.not_traffic_intr_cnt; + + *device_info = &hldev->stats.sw_dev_info_stats; + + return XGE_HAL_OK; +} + +/** + * xge_hal_stats_channel - Get channel statistics. + * @channelh: Channel handle. + * @channel_info: HAL channel statistic counters. + * See xge_hal_stats_channel_info_t{}. Returned by HAL. + * + * Retrieve statistics of a particular HAL channel. This includes, for instance, + * number of completions per interrupt, number of traffic interrupts, etc. + * + * Returns: XGE_HAL_OK - success. + * XGE_HAL_INF_STATS_IS_NOT_READY - Statistics information is not + * currently available. + * + * See also: xge_hal_status_e{}. + */ +xge_hal_status_e +xge_hal_stats_channel(xge_hal_channel_h channelh, + xge_hal_stats_channel_info_t **channel_info) +{ + xge_hal_stats_hw_info_t *latest; + xge_hal_channel_t *channel; + xge_hal_device_t *hldev; + + channel = (xge_hal_channel_t *)channelh; + hldev = (xge_hal_device_t *)channel->devh; + if ((hldev == NULL) || (hldev->magic != XGE_HAL_MAGIC)) { + return XGE_HAL_ERR_INVALID_DEVICE; + } + if ((channel == NULL) || (channel->magic != XGE_HAL_MAGIC)) { + return XGE_HAL_ERR_INVALID_DEVICE; + } + + if (!hldev->stats.is_initialized || + !hldev->stats.is_enabled || + !channel->is_open) { + *channel_info = NULL; + return XGE_HAL_INF_STATS_IS_NOT_READY; + } + + hldev->stats.sw_dev_info_stats.traffic_intr_cnt = + hldev->stats.sw_dev_info_stats.total_intr_cnt - + hldev->stats.sw_dev_info_stats.not_traffic_intr_cnt; + + if (hldev->stats.sw_dev_info_stats.traffic_intr_cnt) { + int rxcnt = hldev->stats.sw_dev_info_stats.rx_traffic_intr_cnt; + int txcnt = hldev->stats.sw_dev_info_stats.tx_traffic_intr_cnt; + if (channel->type == XGE_HAL_CHANNEL_TYPE_FIFO) { + if (!txcnt) + txcnt = 1; + channel->stats.avg_compl_per_intr_cnt = + channel->stats.total_compl_cnt / txcnt; + } else if (channel->type == XGE_HAL_CHANNEL_TYPE_RING && + !hldev->config.bimodal_interrupts) { + if (!rxcnt) + rxcnt = 1; + channel->stats.avg_compl_per_intr_cnt = + channel->stats.total_compl_cnt / rxcnt; + } + if (channel->stats.avg_compl_per_intr_cnt == 0) { + /* to not confuse user */ + channel->stats.avg_compl_per_intr_cnt = 1; + } + } + + (void) xge_hal_stats_hw(hldev, &latest); + + if (channel->stats.total_posts) { + channel->stats.avg_buffers_per_post = + channel->stats.total_buffers / + channel->stats.total_posts; +#ifdef XGE_OS_PLATFORM_64BIT + if (channel->type == XGE_HAL_CHANNEL_TYPE_FIFO) { + channel->stats.avg_post_size = + (u32)(latest->tmac_ttl_less_fb_octets / + channel->stats.total_posts); + } +#endif + } + +#ifdef XGE_OS_PLATFORM_64BIT + if (channel->stats.total_buffers && + channel->type == XGE_HAL_CHANNEL_TYPE_FIFO) { + channel->stats.avg_buffer_size = + (u32)(latest->tmac_ttl_less_fb_octets / + channel->stats.total_buffers); + } +#endif + + *channel_info = &channel->stats; + return XGE_HAL_OK; +} + +/** + * xge_hal_stats_reset - Reset (zero-out) device statistics + * @devh: HAL device handle. + * + * Reset all device statistics. + * Returns: XGE_HAL_OK - success. + * XGE_HAL_INF_STATS_IS_NOT_READY - Statistics information is not + * currently available. + * + * See also: xge_hal_status_e{}, xge_hal_stats_channel_info_t{}, + * xge_hal_stats_sw_err_t{}, xge_hal_stats_device_info_t{}. + */ +xge_hal_status_e +xge_hal_stats_reset(xge_hal_device_h devh) +{ + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + + if (!hldev->stats.is_initialized || + !hldev->stats.is_enabled) { + return XGE_HAL_INF_STATS_IS_NOT_READY; + } + + /* save hw stats to calculate the after-reset values */ + __hal_stats_save(&hldev->stats); + + /* zero-out driver-maintained stats, don't reset the saved */ + __hal_stats_soft_reset(hldev, 0); + + return XGE_HAL_OK; +} + +/* + * __hal_stats_soft_reset - Reset software-maintained statistics. + */ +void +__hal_stats_soft_reset (xge_hal_device_h devh, int reset_all) +{ + xge_list_t *item; + xge_hal_channel_t *channel; + xge_hal_device_t *hldev = (xge_hal_device_t *)devh; + + if (reset_all) { + if (xge_hal_device_check_id(hldev) != XGE_HAL_CARD_TITAN) { + xge_os_memzero(&hldev->stats.hw_info_saved, + sizeof(xge_hal_stats_hw_info_t)); + xge_os_memzero(&hldev->stats.hw_info_latest, + sizeof(xge_hal_stats_hw_info_t)); + } else { + xge_os_memzero(&hldev->stats.pcim_info_saved, + sizeof(xge_hal_stats_pcim_info_t)); + xge_os_memzero(&hldev->stats.pcim_info_latest, + sizeof(xge_hal_stats_pcim_info_t)); + } + } + + /* Reset the "soft" error and informational statistics */ + xge_os_memzero(&hldev->stats.sw_dev_err_stats, + sizeof(xge_hal_stats_sw_err_t)); + xge_os_memzero(&hldev->stats.sw_dev_info_stats, + sizeof(xge_hal_stats_device_info_t)); + + /* for each Rx channel */ + xge_list_for_each(item, &hldev->ring_channels) { + channel = xge_container_of(item, xge_hal_channel_t, item); + xge_os_memzero(&channel->stats, + sizeof(xge_hal_stats_channel_info_t)); + } + + /* for each Tx channel */ + xge_list_for_each(item, &hldev->fifo_channels) { + channel = xge_container_of(item, xge_hal_channel_t, item); + xge_os_memzero(&channel->stats, + sizeof(xge_hal_stats_channel_info_t)); + } +} + -- cgit v1.1